Revision 62a46c61 hw/fdc.c
b/hw/fdc.c | ||
---|---|---|
95 | 95 |
} fdrive_t; |
96 | 96 |
|
97 | 97 |
#ifdef TARGET_SPARC |
98 |
/* XXX: suppress those hacks */ |
|
98 | 99 |
#define DMA_read_memory(a,b,c,d) |
99 | 100 |
#define DMA_write_memory(a,b,c,d) |
100 |
#define DMA_register_channel(a,b,c) |
|
101 |
void DMA_register_channel (int nchan, |
|
102 |
DMA_transfer_handler transfer_handler, |
|
103 |
void *opaque) |
|
104 |
{ |
|
105 |
} |
|
101 | 106 |
#define DMA_hold_DREQ(a) |
102 | 107 |
#define DMA_release_DREQ(a) |
103 | 108 |
#define DMA_get_channel_mode(a) (0) |
... | ... | |
469 | 474 |
} |
470 | 475 |
} |
471 | 476 |
|
477 |
static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg) |
|
478 |
{ |
|
479 |
return fdctrl_read(opaque, reg); |
|
480 |
} |
|
481 |
|
|
482 |
static void fdctrl_write_mem (void *opaque, |
|
483 |
target_phys_addr_t reg, uint32_t value) |
|
484 |
{ |
|
485 |
fdctrl_write(opaque, reg, value); |
|
486 |
} |
|
487 |
|
|
472 | 488 |
static CPUReadMemoryFunc *fdctrl_mem_read[3] = { |
473 |
fdctrl_read, |
|
474 |
fdctrl_read, |
|
475 |
fdctrl_read, |
|
489 |
fdctrl_read_mem,
|
|
490 |
fdctrl_read_mem,
|
|
491 |
fdctrl_read_mem,
|
|
476 | 492 |
}; |
477 | 493 |
|
478 | 494 |
static CPUWriteMemoryFunc *fdctrl_mem_write[3] = { |
479 |
fdctrl_write, |
|
480 |
fdctrl_write, |
|
481 |
fdctrl_write, |
|
495 |
fdctrl_write_mem,
|
|
496 |
fdctrl_write_mem,
|
|
497 |
fdctrl_write_mem,
|
|
482 | 498 |
}; |
483 | 499 |
|
484 | 500 |
static void fd_change_cb (void *opaque) |
Also available in: Unified diff