root / hw / esp.c @ 636aa70a
History | View | Annotate | Download (18.6 kB)
1 |
/*
|
---|---|
2 |
* QEMU ESP/NCR53C9x emulation
|
3 |
*
|
4 |
* Copyright (c) 2005-2006 Fabrice Bellard
|
5 |
*
|
6 |
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 |
* of this software and associated documentation files (the "Software"), to deal
|
8 |
* in the Software without restriction, including without limitation the rights
|
9 |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 |
* copies of the Software, and to permit persons to whom the Software is
|
11 |
* furnished to do so, subject to the following conditions:
|
12 |
*
|
13 |
* The above copyright notice and this permission notice shall be included in
|
14 |
* all copies or substantial portions of the Software.
|
15 |
*
|
16 |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 |
* THE SOFTWARE.
|
23 |
*/
|
24 |
|
25 |
#include "sysbus.h" |
26 |
#include "scsi-disk.h" |
27 |
#include "scsi.h" |
28 |
|
29 |
/* debug ESP card */
|
30 |
//#define DEBUG_ESP
|
31 |
|
32 |
/*
|
33 |
* On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
|
34 |
* also produced as NCR89C100. See
|
35 |
* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
|
36 |
* and
|
37 |
* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
|
38 |
*/
|
39 |
|
40 |
#ifdef DEBUG_ESP
|
41 |
#define DPRINTF(fmt, ...) \
|
42 |
do { printf("ESP: " fmt , ## __VA_ARGS__); } while (0) |
43 |
#else
|
44 |
#define DPRINTF(fmt, ...) do {} while (0) |
45 |
#endif
|
46 |
|
47 |
#define ESP_ERROR(fmt, ...) \
|
48 |
do { printf("ESP ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0) |
49 |
|
50 |
#define ESP_REGS 16 |
51 |
#define TI_BUFSZ 16 |
52 |
|
53 |
typedef struct ESPState ESPState; |
54 |
|
55 |
struct ESPState {
|
56 |
SysBusDevice busdev; |
57 |
uint32_t it_shift; |
58 |
qemu_irq irq; |
59 |
uint8_t rregs[ESP_REGS]; |
60 |
uint8_t wregs[ESP_REGS]; |
61 |
int32_t ti_size; |
62 |
uint32_t ti_rptr, ti_wptr; |
63 |
uint8_t ti_buf[TI_BUFSZ]; |
64 |
uint32_t sense; |
65 |
uint32_t dma; |
66 |
SCSIDevice *scsi_dev[ESP_MAX_DEVS]; |
67 |
SCSIDevice *current_dev; |
68 |
uint8_t cmdbuf[TI_BUFSZ]; |
69 |
uint32_t cmdlen; |
70 |
uint32_t do_cmd; |
71 |
|
72 |
/* The amount of data left in the current DMA transfer. */
|
73 |
uint32_t dma_left; |
74 |
/* The size of the current DMA transfer. Zero if no transfer is in
|
75 |
progress. */
|
76 |
uint32_t dma_counter; |
77 |
uint8_t *async_buf; |
78 |
uint32_t async_len; |
79 |
|
80 |
espdma_memory_read_write dma_memory_read; |
81 |
espdma_memory_read_write dma_memory_write; |
82 |
void *dma_opaque;
|
83 |
}; |
84 |
|
85 |
#define ESP_TCLO 0x0 |
86 |
#define ESP_TCMID 0x1 |
87 |
#define ESP_FIFO 0x2 |
88 |
#define ESP_CMD 0x3 |
89 |
#define ESP_RSTAT 0x4 |
90 |
#define ESP_WBUSID 0x4 |
91 |
#define ESP_RINTR 0x5 |
92 |
#define ESP_WSEL 0x5 |
93 |
#define ESP_RSEQ 0x6 |
94 |
#define ESP_WSYNTP 0x6 |
95 |
#define ESP_RFLAGS 0x7 |
96 |
#define ESP_WSYNO 0x7 |
97 |
#define ESP_CFG1 0x8 |
98 |
#define ESP_RRES1 0x9 |
99 |
#define ESP_WCCF 0x9 |
100 |
#define ESP_RRES2 0xa |
101 |
#define ESP_WTEST 0xa |
102 |
#define ESP_CFG2 0xb |
103 |
#define ESP_CFG3 0xc |
104 |
#define ESP_RES3 0xd |
105 |
#define ESP_TCHI 0xe |
106 |
#define ESP_RES4 0xf |
107 |
|
108 |
#define CMD_DMA 0x80 |
109 |
#define CMD_CMD 0x7f |
110 |
|
111 |
#define CMD_NOP 0x00 |
112 |
#define CMD_FLUSH 0x01 |
113 |
#define CMD_RESET 0x02 |
114 |
#define CMD_BUSRESET 0x03 |
115 |
#define CMD_TI 0x10 |
116 |
#define CMD_ICCS 0x11 |
117 |
#define CMD_MSGACC 0x12 |
118 |
#define CMD_SATN 0x1a |
119 |
#define CMD_SELATN 0x42 |
120 |
#define CMD_SELATNS 0x43 |
121 |
#define CMD_ENSEL 0x44 |
122 |
|
123 |
#define STAT_DO 0x00 |
124 |
#define STAT_DI 0x01 |
125 |
#define STAT_CD 0x02 |
126 |
#define STAT_ST 0x03 |
127 |
#define STAT_MO 0x06 |
128 |
#define STAT_MI 0x07 |
129 |
#define STAT_PIO_MASK 0x06 |
130 |
|
131 |
#define STAT_TC 0x10 |
132 |
#define STAT_PE 0x20 |
133 |
#define STAT_GE 0x40 |
134 |
#define STAT_INT 0x80 |
135 |
|
136 |
#define BUSID_DID 0x07 |
137 |
|
138 |
#define INTR_FC 0x08 |
139 |
#define INTR_BS 0x10 |
140 |
#define INTR_DC 0x20 |
141 |
#define INTR_RST 0x80 |
142 |
|
143 |
#define SEQ_0 0x0 |
144 |
#define SEQ_CD 0x4 |
145 |
|
146 |
#define CFG1_RESREPT 0x40 |
147 |
|
148 |
#define TCHI_FAS100A 0x4 |
149 |
|
150 |
static void esp_raise_irq(ESPState *s) |
151 |
{ |
152 |
if (!(s->rregs[ESP_RSTAT] & STAT_INT)) {
|
153 |
s->rregs[ESP_RSTAT] |= STAT_INT; |
154 |
qemu_irq_raise(s->irq); |
155 |
} |
156 |
} |
157 |
|
158 |
static void esp_lower_irq(ESPState *s) |
159 |
{ |
160 |
if (s->rregs[ESP_RSTAT] & STAT_INT) {
|
161 |
s->rregs[ESP_RSTAT] &= ~STAT_INT; |
162 |
qemu_irq_lower(s->irq); |
163 |
} |
164 |
} |
165 |
|
166 |
static uint32_t get_cmd(ESPState *s, uint8_t *buf)
|
167 |
{ |
168 |
uint32_t dmalen; |
169 |
int target;
|
170 |
|
171 |
target = s->wregs[ESP_WBUSID] & BUSID_DID; |
172 |
if (s->dma) {
|
173 |
dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
|
174 |
s->dma_memory_read(s->dma_opaque, buf, dmalen); |
175 |
} else {
|
176 |
dmalen = s->ti_size; |
177 |
memcpy(buf, s->ti_buf, dmalen); |
178 |
buf[0] = 0; |
179 |
} |
180 |
DPRINTF("get_cmd: len %d target %d\n", dmalen, target);
|
181 |
|
182 |
s->ti_size = 0;
|
183 |
s->ti_rptr = 0;
|
184 |
s->ti_wptr = 0;
|
185 |
|
186 |
if (s->current_dev) {
|
187 |
/* Started a new command before the old one finished. Cancel it. */
|
188 |
s->current_dev->cancel_io(s->current_dev, 0);
|
189 |
s->async_len = 0;
|
190 |
} |
191 |
|
192 |
if (target >= ESP_MAX_DEVS || !s->scsi_dev[target]) {
|
193 |
// No such drive
|
194 |
s->rregs[ESP_RSTAT] = 0;
|
195 |
s->rregs[ESP_RINTR] = INTR_DC; |
196 |
s->rregs[ESP_RSEQ] = SEQ_0; |
197 |
esp_raise_irq(s); |
198 |
return 0; |
199 |
} |
200 |
s->current_dev = s->scsi_dev[target]; |
201 |
return dmalen;
|
202 |
} |
203 |
|
204 |
static void do_cmd(ESPState *s, uint8_t *buf) |
205 |
{ |
206 |
int32_t datalen; |
207 |
int lun;
|
208 |
|
209 |
DPRINTF("do_cmd: busid 0x%x\n", buf[0]); |
210 |
lun = buf[0] & 7; |
211 |
datalen = s->current_dev->send_command(s->current_dev, 0, &buf[1], lun); |
212 |
s->ti_size = datalen; |
213 |
if (datalen != 0) { |
214 |
s->rregs[ESP_RSTAT] = STAT_TC; |
215 |
s->dma_left = 0;
|
216 |
s->dma_counter = 0;
|
217 |
if (datalen > 0) { |
218 |
s->rregs[ESP_RSTAT] |= STAT_DI; |
219 |
s->current_dev->read_data(s->current_dev, 0);
|
220 |
} else {
|
221 |
s->rregs[ESP_RSTAT] |= STAT_DO; |
222 |
s->current_dev->write_data(s->current_dev, 0);
|
223 |
} |
224 |
} |
225 |
s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
226 |
s->rregs[ESP_RSEQ] = SEQ_CD; |
227 |
esp_raise_irq(s); |
228 |
} |
229 |
|
230 |
static void handle_satn(ESPState *s) |
231 |
{ |
232 |
uint8_t buf[32];
|
233 |
int len;
|
234 |
|
235 |
len = get_cmd(s, buf); |
236 |
if (len)
|
237 |
do_cmd(s, buf); |
238 |
} |
239 |
|
240 |
static void handle_satn_stop(ESPState *s) |
241 |
{ |
242 |
s->cmdlen = get_cmd(s, s->cmdbuf); |
243 |
if (s->cmdlen) {
|
244 |
DPRINTF("Set ATN & Stop: cmdlen %d\n", s->cmdlen);
|
245 |
s->do_cmd = 1;
|
246 |
s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; |
247 |
s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
248 |
s->rregs[ESP_RSEQ] = SEQ_CD; |
249 |
esp_raise_irq(s); |
250 |
} |
251 |
} |
252 |
|
253 |
static void write_response(ESPState *s) |
254 |
{ |
255 |
DPRINTF("Transfer status (sense=%d)\n", s->sense);
|
256 |
s->ti_buf[0] = s->sense;
|
257 |
s->ti_buf[1] = 0; |
258 |
if (s->dma) {
|
259 |
s->dma_memory_write(s->dma_opaque, s->ti_buf, 2);
|
260 |
s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; |
261 |
s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
262 |
s->rregs[ESP_RSEQ] = SEQ_CD; |
263 |
} else {
|
264 |
s->ti_size = 2;
|
265 |
s->ti_rptr = 0;
|
266 |
s->ti_wptr = 0;
|
267 |
s->rregs[ESP_RFLAGS] = 2;
|
268 |
} |
269 |
esp_raise_irq(s); |
270 |
} |
271 |
|
272 |
static void esp_dma_done(ESPState *s) |
273 |
{ |
274 |
s->rregs[ESP_RSTAT] |= STAT_TC; |
275 |
s->rregs[ESP_RINTR] = INTR_BS; |
276 |
s->rregs[ESP_RSEQ] = 0;
|
277 |
s->rregs[ESP_RFLAGS] = 0;
|
278 |
s->rregs[ESP_TCLO] = 0;
|
279 |
s->rregs[ESP_TCMID] = 0;
|
280 |
esp_raise_irq(s); |
281 |
} |
282 |
|
283 |
static void esp_do_dma(ESPState *s) |
284 |
{ |
285 |
uint32_t len; |
286 |
int to_device;
|
287 |
|
288 |
to_device = (s->ti_size < 0);
|
289 |
len = s->dma_left; |
290 |
if (s->do_cmd) {
|
291 |
DPRINTF("command len %d + %d\n", s->cmdlen, len);
|
292 |
s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len); |
293 |
s->ti_size = 0;
|
294 |
s->cmdlen = 0;
|
295 |
s->do_cmd = 0;
|
296 |
do_cmd(s, s->cmdbuf); |
297 |
return;
|
298 |
} |
299 |
if (s->async_len == 0) { |
300 |
/* Defer until data is available. */
|
301 |
return;
|
302 |
} |
303 |
if (len > s->async_len) {
|
304 |
len = s->async_len; |
305 |
} |
306 |
if (to_device) {
|
307 |
s->dma_memory_read(s->dma_opaque, s->async_buf, len); |
308 |
} else {
|
309 |
s->dma_memory_write(s->dma_opaque, s->async_buf, len); |
310 |
} |
311 |
s->dma_left -= len; |
312 |
s->async_buf += len; |
313 |
s->async_len -= len; |
314 |
if (to_device)
|
315 |
s->ti_size += len; |
316 |
else
|
317 |
s->ti_size -= len; |
318 |
if (s->async_len == 0) { |
319 |
if (to_device) {
|
320 |
// ti_size is negative
|
321 |
s->current_dev->write_data(s->current_dev, 0);
|
322 |
} else {
|
323 |
s->current_dev->read_data(s->current_dev, 0);
|
324 |
/* If there is still data to be read from the device then
|
325 |
complete the DMA operation immediately. Otherwise defer
|
326 |
until the scsi layer has completed. */
|
327 |
if (s->dma_left == 0 && s->ti_size > 0) { |
328 |
esp_dma_done(s); |
329 |
} |
330 |
} |
331 |
} else {
|
332 |
/* Partially filled a scsi buffer. Complete immediately. */
|
333 |
esp_dma_done(s); |
334 |
} |
335 |
} |
336 |
|
337 |
static void esp_command_complete(void *opaque, int reason, uint32_t tag, |
338 |
uint32_t arg) |
339 |
{ |
340 |
ESPState *s = (ESPState *)opaque; |
341 |
|
342 |
if (reason == SCSI_REASON_DONE) {
|
343 |
DPRINTF("SCSI Command complete\n");
|
344 |
if (s->ti_size != 0) |
345 |
DPRINTF("SCSI command completed unexpectedly\n");
|
346 |
s->ti_size = 0;
|
347 |
s->dma_left = 0;
|
348 |
s->async_len = 0;
|
349 |
if (arg)
|
350 |
DPRINTF("Command failed\n");
|
351 |
s->sense = arg; |
352 |
s->rregs[ESP_RSTAT] = STAT_ST; |
353 |
esp_dma_done(s); |
354 |
s->current_dev = NULL;
|
355 |
} else {
|
356 |
DPRINTF("transfer %d/%d\n", s->dma_left, s->ti_size);
|
357 |
s->async_len = arg; |
358 |
s->async_buf = s->current_dev->get_buf(s->current_dev, 0);
|
359 |
if (s->dma_left) {
|
360 |
esp_do_dma(s); |
361 |
} else if (s->dma_counter != 0 && s->ti_size <= 0) { |
362 |
/* If this was the last part of a DMA transfer then the
|
363 |
completion interrupt is deferred to here. */
|
364 |
esp_dma_done(s); |
365 |
} |
366 |
} |
367 |
} |
368 |
|
369 |
static void handle_ti(ESPState *s) |
370 |
{ |
371 |
uint32_t dmalen, minlen; |
372 |
|
373 |
dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
|
374 |
if (dmalen==0) { |
375 |
dmalen=0x10000;
|
376 |
} |
377 |
s->dma_counter = dmalen; |
378 |
|
379 |
if (s->do_cmd)
|
380 |
minlen = (dmalen < 32) ? dmalen : 32; |
381 |
else if (s->ti_size < 0) |
382 |
minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size; |
383 |
else
|
384 |
minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size; |
385 |
DPRINTF("Transfer Information len %d\n", minlen);
|
386 |
if (s->dma) {
|
387 |
s->dma_left = minlen; |
388 |
s->rregs[ESP_RSTAT] &= ~STAT_TC; |
389 |
esp_do_dma(s); |
390 |
} else if (s->do_cmd) { |
391 |
DPRINTF("command len %d\n", s->cmdlen);
|
392 |
s->ti_size = 0;
|
393 |
s->cmdlen = 0;
|
394 |
s->do_cmd = 0;
|
395 |
do_cmd(s, s->cmdbuf); |
396 |
return;
|
397 |
} |
398 |
} |
399 |
|
400 |
static void esp_reset(void *opaque) |
401 |
{ |
402 |
ESPState *s = opaque; |
403 |
|
404 |
memset(s->rregs, 0, ESP_REGS);
|
405 |
memset(s->wregs, 0, ESP_REGS);
|
406 |
s->rregs[ESP_TCHI] = TCHI_FAS100A; // Indicate fas100a
|
407 |
s->ti_size = 0;
|
408 |
s->ti_rptr = 0;
|
409 |
s->ti_wptr = 0;
|
410 |
s->dma = 0;
|
411 |
s->do_cmd = 0;
|
412 |
|
413 |
s->rregs[ESP_CFG1] = 7;
|
414 |
} |
415 |
|
416 |
static void parent_esp_reset(void *opaque, int irq, int level) |
417 |
{ |
418 |
if (level)
|
419 |
esp_reset(opaque); |
420 |
} |
421 |
|
422 |
static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr) |
423 |
{ |
424 |
ESPState *s = opaque; |
425 |
uint32_t saddr; |
426 |
|
427 |
saddr = addr >> s->it_shift; |
428 |
DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);
|
429 |
switch (saddr) {
|
430 |
case ESP_FIFO:
|
431 |
if (s->ti_size > 0) { |
432 |
s->ti_size--; |
433 |
if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { |
434 |
/* Data out. */
|
435 |
ESP_ERROR("PIO data read not implemented\n");
|
436 |
s->rregs[ESP_FIFO] = 0;
|
437 |
} else {
|
438 |
s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++]; |
439 |
} |
440 |
esp_raise_irq(s); |
441 |
} |
442 |
if (s->ti_size == 0) { |
443 |
s->ti_rptr = 0;
|
444 |
s->ti_wptr = 0;
|
445 |
} |
446 |
break;
|
447 |
case ESP_RINTR:
|
448 |
// Clear interrupt/error status bits
|
449 |
s->rregs[ESP_RSTAT] &= ~(STAT_GE | STAT_PE); |
450 |
esp_lower_irq(s); |
451 |
break;
|
452 |
default:
|
453 |
break;
|
454 |
} |
455 |
return s->rregs[saddr];
|
456 |
} |
457 |
|
458 |
static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
459 |
{ |
460 |
ESPState *s = opaque; |
461 |
uint32_t saddr; |
462 |
|
463 |
saddr = addr >> s->it_shift; |
464 |
DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr],
|
465 |
val); |
466 |
switch (saddr) {
|
467 |
case ESP_TCLO:
|
468 |
case ESP_TCMID:
|
469 |
s->rregs[ESP_RSTAT] &= ~STAT_TC; |
470 |
break;
|
471 |
case ESP_FIFO:
|
472 |
if (s->do_cmd) {
|
473 |
s->cmdbuf[s->cmdlen++] = val & 0xff;
|
474 |
} else if (s->ti_size == TI_BUFSZ - 1) { |
475 |
ESP_ERROR("fifo overrun\n");
|
476 |
} else {
|
477 |
s->ti_size++; |
478 |
s->ti_buf[s->ti_wptr++] = val & 0xff;
|
479 |
} |
480 |
break;
|
481 |
case ESP_CMD:
|
482 |
s->rregs[saddr] = val; |
483 |
if (val & CMD_DMA) {
|
484 |
s->dma = 1;
|
485 |
/* Reload DMA counter. */
|
486 |
s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO]; |
487 |
s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID]; |
488 |
} else {
|
489 |
s->dma = 0;
|
490 |
} |
491 |
switch(val & CMD_CMD) {
|
492 |
case CMD_NOP:
|
493 |
DPRINTF("NOP (%2.2x)\n", val);
|
494 |
break;
|
495 |
case CMD_FLUSH:
|
496 |
DPRINTF("Flush FIFO (%2.2x)\n", val);
|
497 |
//s->ti_size = 0;
|
498 |
s->rregs[ESP_RINTR] = INTR_FC; |
499 |
s->rregs[ESP_RSEQ] = 0;
|
500 |
s->rregs[ESP_RFLAGS] = 0;
|
501 |
break;
|
502 |
case CMD_RESET:
|
503 |
DPRINTF("Chip reset (%2.2x)\n", val);
|
504 |
esp_reset(s); |
505 |
break;
|
506 |
case CMD_BUSRESET:
|
507 |
DPRINTF("Bus reset (%2.2x)\n", val);
|
508 |
s->rregs[ESP_RINTR] = INTR_RST; |
509 |
if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {
|
510 |
esp_raise_irq(s); |
511 |
} |
512 |
break;
|
513 |
case CMD_TI:
|
514 |
handle_ti(s); |
515 |
break;
|
516 |
case CMD_ICCS:
|
517 |
DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val);
|
518 |
write_response(s); |
519 |
s->rregs[ESP_RINTR] = INTR_FC; |
520 |
s->rregs[ESP_RSTAT] |= STAT_MI; |
521 |
break;
|
522 |
case CMD_MSGACC:
|
523 |
DPRINTF("Message Accepted (%2.2x)\n", val);
|
524 |
write_response(s); |
525 |
s->rregs[ESP_RINTR] = INTR_DC; |
526 |
s->rregs[ESP_RSEQ] = 0;
|
527 |
break;
|
528 |
case CMD_SATN:
|
529 |
DPRINTF("Set ATN (%2.2x)\n", val);
|
530 |
break;
|
531 |
case CMD_SELATN:
|
532 |
DPRINTF("Set ATN (%2.2x)\n", val);
|
533 |
handle_satn(s); |
534 |
break;
|
535 |
case CMD_SELATNS:
|
536 |
DPRINTF("Set ATN & stop (%2.2x)\n", val);
|
537 |
handle_satn_stop(s); |
538 |
break;
|
539 |
case CMD_ENSEL:
|
540 |
DPRINTF("Enable selection (%2.2x)\n", val);
|
541 |
s->rregs[ESP_RINTR] = 0;
|
542 |
break;
|
543 |
default:
|
544 |
ESP_ERROR("Unhandled ESP command (%2.2x)\n", val);
|
545 |
break;
|
546 |
} |
547 |
break;
|
548 |
case ESP_WBUSID ... ESP_WSYNO:
|
549 |
break;
|
550 |
case ESP_CFG1:
|
551 |
s->rregs[saddr] = val; |
552 |
break;
|
553 |
case ESP_WCCF ... ESP_WTEST:
|
554 |
break;
|
555 |
case ESP_CFG2 ... ESP_RES4:
|
556 |
s->rregs[saddr] = val; |
557 |
break;
|
558 |
default:
|
559 |
ESP_ERROR("invalid write of 0x%02x at [0x%x]\n", val, saddr);
|
560 |
return;
|
561 |
} |
562 |
s->wregs[saddr] = val; |
563 |
} |
564 |
|
565 |
static CPUReadMemoryFunc *esp_mem_read[3] = { |
566 |
esp_mem_readb, |
567 |
NULL,
|
568 |
NULL,
|
569 |
}; |
570 |
|
571 |
static CPUWriteMemoryFunc *esp_mem_write[3] = { |
572 |
esp_mem_writeb, |
573 |
NULL,
|
574 |
esp_mem_writeb, |
575 |
}; |
576 |
|
577 |
static void esp_save(QEMUFile *f, void *opaque) |
578 |
{ |
579 |
ESPState *s = opaque; |
580 |
|
581 |
qemu_put_buffer(f, s->rregs, ESP_REGS); |
582 |
qemu_put_buffer(f, s->wregs, ESP_REGS); |
583 |
qemu_put_sbe32s(f, &s->ti_size); |
584 |
qemu_put_be32s(f, &s->ti_rptr); |
585 |
qemu_put_be32s(f, &s->ti_wptr); |
586 |
qemu_put_buffer(f, s->ti_buf, TI_BUFSZ); |
587 |
qemu_put_be32s(f, &s->sense); |
588 |
qemu_put_be32s(f, &s->dma); |
589 |
qemu_put_buffer(f, s->cmdbuf, TI_BUFSZ); |
590 |
qemu_put_be32s(f, &s->cmdlen); |
591 |
qemu_put_be32s(f, &s->do_cmd); |
592 |
qemu_put_be32s(f, &s->dma_left); |
593 |
// There should be no transfers in progress, so dma_counter is not saved
|
594 |
} |
595 |
|
596 |
static int esp_load(QEMUFile *f, void *opaque, int version_id) |
597 |
{ |
598 |
ESPState *s = opaque; |
599 |
|
600 |
if (version_id != 3) |
601 |
return -EINVAL; // Cannot emulate 2 |
602 |
|
603 |
qemu_get_buffer(f, s->rregs, ESP_REGS); |
604 |
qemu_get_buffer(f, s->wregs, ESP_REGS); |
605 |
qemu_get_sbe32s(f, &s->ti_size); |
606 |
qemu_get_be32s(f, &s->ti_rptr); |
607 |
qemu_get_be32s(f, &s->ti_wptr); |
608 |
qemu_get_buffer(f, s->ti_buf, TI_BUFSZ); |
609 |
qemu_get_be32s(f, &s->sense); |
610 |
qemu_get_be32s(f, &s->dma); |
611 |
qemu_get_buffer(f, s->cmdbuf, TI_BUFSZ); |
612 |
qemu_get_be32s(f, &s->cmdlen); |
613 |
qemu_get_be32s(f, &s->do_cmd); |
614 |
qemu_get_be32s(f, &s->dma_left); |
615 |
|
616 |
return 0; |
617 |
} |
618 |
|
619 |
static void esp_scsi_attach(DeviceState *host, BlockDriverState *bd, int id) |
620 |
{ |
621 |
ESPState *s = FROM_SYSBUS(ESPState, sysbus_from_qdev(host)); |
622 |
|
623 |
if (id < 0) { |
624 |
for (id = 0; id < ESP_MAX_DEVS; id++) { |
625 |
if (id == (s->rregs[ESP_CFG1] & 0x7)) |
626 |
continue;
|
627 |
if (s->scsi_dev[id] == NULL) |
628 |
break;
|
629 |
} |
630 |
} |
631 |
if (id >= ESP_MAX_DEVS) {
|
632 |
DPRINTF("Bad Device ID %d\n", id);
|
633 |
return;
|
634 |
} |
635 |
if (s->scsi_dev[id]) {
|
636 |
DPRINTF("Destroying device %d\n", id);
|
637 |
s->scsi_dev[id]->destroy(s->scsi_dev[id]); |
638 |
} |
639 |
DPRINTF("Attaching block device %d\n", id);
|
640 |
/* Command queueing is not implemented. */
|
641 |
s->scsi_dev[id] = scsi_generic_init(bd, 0, esp_command_complete, s);
|
642 |
if (s->scsi_dev[id] == NULL) |
643 |
s->scsi_dev[id] = scsi_disk_init(bd, 0, esp_command_complete, s);
|
644 |
} |
645 |
|
646 |
void esp_init(target_phys_addr_t espaddr, int it_shift, |
647 |
espdma_memory_read_write dma_memory_read, |
648 |
espdma_memory_read_write dma_memory_write, |
649 |
void *dma_opaque, qemu_irq irq, qemu_irq *reset)
|
650 |
{ |
651 |
DeviceState *dev; |
652 |
SysBusDevice *s; |
653 |
ESPState *esp; |
654 |
|
655 |
dev = qdev_create(NULL, "esp"); |
656 |
esp = DO_UPCAST(ESPState, busdev.qdev, dev); |
657 |
esp->dma_memory_read = dma_memory_read; |
658 |
esp->dma_memory_write = dma_memory_write; |
659 |
esp->dma_opaque = dma_opaque; |
660 |
esp->it_shift = it_shift; |
661 |
qdev_init(dev); |
662 |
s = sysbus_from_qdev(dev); |
663 |
sysbus_connect_irq(s, 0, irq);
|
664 |
sysbus_mmio_map(s, 0, espaddr);
|
665 |
} |
666 |
|
667 |
static void esp_init1(SysBusDevice *dev) |
668 |
{ |
669 |
ESPState *s = FROM_SYSBUS(ESPState, dev); |
670 |
int esp_io_memory;
|
671 |
|
672 |
sysbus_init_irq(dev, &s->irq); |
673 |
assert(s->it_shift != -1);
|
674 |
|
675 |
esp_io_memory = cpu_register_io_memory(esp_mem_read, esp_mem_write, s); |
676 |
sysbus_init_mmio(dev, ESP_REGS << s->it_shift, esp_io_memory); |
677 |
|
678 |
esp_reset(s); |
679 |
|
680 |
register_savevm("esp", -1, 3, esp_save, esp_load, s); |
681 |
qemu_register_reset(esp_reset, s); |
682 |
|
683 |
qdev_init_gpio_in(&dev->qdev, parent_esp_reset, 1);
|
684 |
|
685 |
scsi_bus_new(&dev->qdev, esp_scsi_attach); |
686 |
} |
687 |
|
688 |
static void esp_register_devices(void) |
689 |
{ |
690 |
sysbus_register_dev("esp", sizeof(ESPState), esp_init1); |
691 |
} |
692 |
|
693 |
device_init(esp_register_devices) |