Revision 638737ad
| b/target-sparc/translate.c | ||
|---|---|---|
| 1558 | 1558 |
return 0; |
| 1559 | 1559 |
} |
| 1560 | 1560 |
|
| 1561 |
static inline void gen_update_fprs_dirty(int rd) |
|
| 1562 |
{
|
|
| 1563 |
#if defined(TARGET_SPARC64) |
|
| 1564 |
tcg_gen_ori_i32(cpu_fprs, cpu_fprs, (rd < 32) ? 1 : 2); |
|
| 1565 |
#endif |
|
| 1566 |
} |
|
| 1567 |
|
|
| 1561 | 1568 |
static inline void gen_op_clear_ieee_excp_and_FTT(void) |
| 1562 | 1569 |
{
|
| 1563 | 1570 |
tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK); |
| ... | ... | |
| 2351 | 2358 |
switch (xop) {
|
| 2352 | 2359 |
case 0x1: /* fmovs */ |
| 2353 | 2360 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); |
| 2361 |
gen_update_fprs_dirty(rd); |
|
| 2354 | 2362 |
break; |
| 2355 | 2363 |
case 0x5: /* fnegs */ |
| 2356 | 2364 |
gen_helper_fnegs(cpu_fpr[rd], cpu_fpr[rs2]); |
| 2365 |
gen_update_fprs_dirty(rd); |
|
| 2357 | 2366 |
break; |
| 2358 | 2367 |
case 0x9: /* fabss */ |
| 2359 | 2368 |
gen_helper_fabss(cpu_fpr[rd], cpu_fpr[rs2]); |
| 2369 |
gen_update_fprs_dirty(rd); |
|
| 2360 | 2370 |
break; |
| 2361 | 2371 |
case 0x29: /* fsqrts */ |
| 2362 | 2372 |
CHECK_FPU_FEATURE(dc, FSQRT); |
| ... | ... | |
| 2364 | 2374 |
gen_helper_fsqrts(cpu_tmp32, cpu_fpr[rs2]); |
| 2365 | 2375 |
gen_helper_check_ieee_exceptions(); |
| 2366 | 2376 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2377 |
gen_update_fprs_dirty(rd); |
|
| 2367 | 2378 |
break; |
| 2368 | 2379 |
case 0x2a: /* fsqrtd */ |
| 2369 | 2380 |
CHECK_FPU_FEATURE(dc, FSQRT); |
| ... | ... | |
| 2372 | 2383 |
gen_helper_fsqrtd(); |
| 2373 | 2384 |
gen_helper_check_ieee_exceptions(); |
| 2374 | 2385 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2386 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 2375 | 2387 |
break; |
| 2376 | 2388 |
case 0x2b: /* fsqrtq */ |
| 2377 | 2389 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| ... | ... | |
| 2380 | 2392 |
gen_helper_fsqrtq(); |
| 2381 | 2393 |
gen_helper_check_ieee_exceptions(); |
| 2382 | 2394 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
| 2395 |
gen_update_fprs_dirty(QFPREG(rd)); |
|
| 2383 | 2396 |
break; |
| 2384 | 2397 |
case 0x41: /* fadds */ |
| 2385 | 2398 |
gen_clear_float_exceptions(); |
| 2386 | 2399 |
gen_helper_fadds(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
| 2387 | 2400 |
gen_helper_check_ieee_exceptions(); |
| 2388 | 2401 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2402 |
gen_update_fprs_dirty(rd); |
|
| 2389 | 2403 |
break; |
| 2390 | 2404 |
case 0x42: /* faddd */ |
| 2391 | 2405 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| ... | ... | |
| 2394 | 2408 |
gen_helper_faddd(); |
| 2395 | 2409 |
gen_helper_check_ieee_exceptions(); |
| 2396 | 2410 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2411 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 2397 | 2412 |
break; |
| 2398 | 2413 |
case 0x43: /* faddq */ |
| 2399 | 2414 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| ... | ... | |
| 2403 | 2418 |
gen_helper_faddq(); |
| 2404 | 2419 |
gen_helper_check_ieee_exceptions(); |
| 2405 | 2420 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
| 2421 |
gen_update_fprs_dirty(QFPREG(rd)); |
|
| 2406 | 2422 |
break; |
| 2407 | 2423 |
case 0x45: /* fsubs */ |
| 2408 | 2424 |
gen_clear_float_exceptions(); |
| 2409 | 2425 |
gen_helper_fsubs(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
| 2410 | 2426 |
gen_helper_check_ieee_exceptions(); |
| 2411 | 2427 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2428 |
gen_update_fprs_dirty(rd); |
|
| 2412 | 2429 |
break; |
| 2413 | 2430 |
case 0x46: /* fsubd */ |
| 2414 | 2431 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| ... | ... | |
| 2417 | 2434 |
gen_helper_fsubd(); |
| 2418 | 2435 |
gen_helper_check_ieee_exceptions(); |
| 2419 | 2436 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2437 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 2420 | 2438 |
break; |
| 2421 | 2439 |
case 0x47: /* fsubq */ |
| 2422 | 2440 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| ... | ... | |
| 2426 | 2444 |
gen_helper_fsubq(); |
| 2427 | 2445 |
gen_helper_check_ieee_exceptions(); |
| 2428 | 2446 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
| 2447 |
gen_update_fprs_dirty(QFPREG(rd)); |
|
| 2429 | 2448 |
break; |
| 2430 | 2449 |
case 0x49: /* fmuls */ |
| 2431 | 2450 |
CHECK_FPU_FEATURE(dc, FMUL); |
| ... | ... | |
| 2433 | 2452 |
gen_helper_fmuls(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
| 2434 | 2453 |
gen_helper_check_ieee_exceptions(); |
| 2435 | 2454 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2455 |
gen_update_fprs_dirty(rd); |
|
| 2436 | 2456 |
break; |
| 2437 | 2457 |
case 0x4a: /* fmuld */ |
| 2438 | 2458 |
CHECK_FPU_FEATURE(dc, FMUL); |
| ... | ... | |
| 2442 | 2462 |
gen_helper_fmuld(); |
| 2443 | 2463 |
gen_helper_check_ieee_exceptions(); |
| 2444 | 2464 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2465 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 2445 | 2466 |
break; |
| 2446 | 2467 |
case 0x4b: /* fmulq */ |
| 2447 | 2468 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| ... | ... | |
| 2452 | 2473 |
gen_helper_fmulq(); |
| 2453 | 2474 |
gen_helper_check_ieee_exceptions(); |
| 2454 | 2475 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
| 2476 |
gen_update_fprs_dirty(QFPREG(rd)); |
|
| 2455 | 2477 |
break; |
| 2456 | 2478 |
case 0x4d: /* fdivs */ |
| 2457 | 2479 |
gen_clear_float_exceptions(); |
| 2458 | 2480 |
gen_helper_fdivs(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
| 2459 | 2481 |
gen_helper_check_ieee_exceptions(); |
| 2460 | 2482 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2483 |
gen_update_fprs_dirty(rd); |
|
| 2461 | 2484 |
break; |
| 2462 | 2485 |
case 0x4e: /* fdivd */ |
| 2463 | 2486 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| ... | ... | |
| 2466 | 2489 |
gen_helper_fdivd(); |
| 2467 | 2490 |
gen_helper_check_ieee_exceptions(); |
| 2468 | 2491 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2492 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 2469 | 2493 |
break; |
| 2470 | 2494 |
case 0x4f: /* fdivq */ |
| 2471 | 2495 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| ... | ... | |
| 2475 | 2499 |
gen_helper_fdivq(); |
| 2476 | 2500 |
gen_helper_check_ieee_exceptions(); |
| 2477 | 2501 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
| 2502 |
gen_update_fprs_dirty(QFPREG(rd)); |
|
| 2478 | 2503 |
break; |
| 2479 | 2504 |
case 0x69: /* fsmuld */ |
| 2480 | 2505 |
CHECK_FPU_FEATURE(dc, FSMULD); |
| ... | ... | |
| 2482 | 2507 |
gen_helper_fsmuld(cpu_fpr[rs1], cpu_fpr[rs2]); |
| 2483 | 2508 |
gen_helper_check_ieee_exceptions(); |
| 2484 | 2509 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2510 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 2485 | 2511 |
break; |
| 2486 | 2512 |
case 0x6e: /* fdmulq */ |
| 2487 | 2513 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| ... | ... | |
| 2491 | 2517 |
gen_helper_fdmulq(); |
| 2492 | 2518 |
gen_helper_check_ieee_exceptions(); |
| 2493 | 2519 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
| 2520 |
gen_update_fprs_dirty(QFPREG(rd)); |
|
| 2494 | 2521 |
break; |
| 2495 | 2522 |
case 0xc4: /* fitos */ |
| 2496 | 2523 |
gen_clear_float_exceptions(); |
| 2497 | 2524 |
gen_helper_fitos(cpu_tmp32, cpu_fpr[rs2]); |
| 2498 | 2525 |
gen_helper_check_ieee_exceptions(); |
| 2499 | 2526 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2527 |
gen_update_fprs_dirty(rd); |
|
| 2500 | 2528 |
break; |
| 2501 | 2529 |
case 0xc6: /* fdtos */ |
| 2502 | 2530 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| ... | ... | |
| 2504 | 2532 |
gen_helper_fdtos(cpu_tmp32); |
| 2505 | 2533 |
gen_helper_check_ieee_exceptions(); |
| 2506 | 2534 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2535 |
gen_update_fprs_dirty(rd); |
|
| 2507 | 2536 |
break; |
| 2508 | 2537 |
case 0xc7: /* fqtos */ |
| 2509 | 2538 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| ... | ... | |
| 2512 | 2541 |
gen_helper_fqtos(cpu_tmp32); |
| 2513 | 2542 |
gen_helper_check_ieee_exceptions(); |
| 2514 | 2543 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2544 |
gen_update_fprs_dirty(rd); |
|
| 2515 | 2545 |
break; |
| 2516 | 2546 |
case 0xc8: /* fitod */ |
| 2517 | 2547 |
gen_helper_fitod(cpu_fpr[rs2]); |
| 2518 | 2548 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2549 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 2519 | 2550 |
break; |
| 2520 | 2551 |
case 0xc9: /* fstod */ |
| 2521 | 2552 |
gen_helper_fstod(cpu_fpr[rs2]); |
| 2522 | 2553 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2554 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 2523 | 2555 |
break; |
| 2524 | 2556 |
case 0xcb: /* fqtod */ |
| 2525 | 2557 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| ... | ... | |
| 2528 | 2560 |
gen_helper_fqtod(); |
| 2529 | 2561 |
gen_helper_check_ieee_exceptions(); |
| 2530 | 2562 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2563 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 2531 | 2564 |
break; |
| 2532 | 2565 |
case 0xcc: /* fitoq */ |
| 2533 | 2566 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| 2534 | 2567 |
gen_helper_fitoq(cpu_fpr[rs2]); |
| 2535 | 2568 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
| 2569 |
gen_update_fprs_dirty(QFPREG(rd)); |
|
| 2536 | 2570 |
break; |
| 2537 | 2571 |
case 0xcd: /* fstoq */ |
| 2538 | 2572 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| 2539 | 2573 |
gen_helper_fstoq(cpu_fpr[rs2]); |
| 2540 | 2574 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
| 2575 |
gen_update_fprs_dirty(QFPREG(rd)); |
|
| 2541 | 2576 |
break; |
| 2542 | 2577 |
case 0xce: /* fdtoq */ |
| 2543 | 2578 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| 2544 | 2579 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 2545 | 2580 |
gen_helper_fdtoq(); |
| 2546 | 2581 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
| 2582 |
gen_update_fprs_dirty(QFPREG(rd)); |
|
| 2547 | 2583 |
break; |
| 2548 | 2584 |
case 0xd1: /* fstoi */ |
| 2549 | 2585 |
gen_clear_float_exceptions(); |
| 2550 | 2586 |
gen_helper_fstoi(cpu_tmp32, cpu_fpr[rs2]); |
| 2551 | 2587 |
gen_helper_check_ieee_exceptions(); |
| 2552 | 2588 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2589 |
gen_update_fprs_dirty(rd); |
|
| 2553 | 2590 |
break; |
| 2554 | 2591 |
case 0xd2: /* fdtoi */ |
| 2555 | 2592 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| ... | ... | |
| 2557 | 2594 |
gen_helper_fdtoi(cpu_tmp32); |
| 2558 | 2595 |
gen_helper_check_ieee_exceptions(); |
| 2559 | 2596 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2597 |
gen_update_fprs_dirty(rd); |
|
| 2560 | 2598 |
break; |
| 2561 | 2599 |
case 0xd3: /* fqtoi */ |
| 2562 | 2600 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| ... | ... | |
| 2565 | 2603 |
gen_helper_fqtoi(cpu_tmp32); |
| 2566 | 2604 |
gen_helper_check_ieee_exceptions(); |
| 2567 | 2605 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2606 |
gen_update_fprs_dirty(rd); |
|
| 2568 | 2607 |
break; |
| 2569 | 2608 |
#ifdef TARGET_SPARC64 |
| 2570 | 2609 |
case 0x2: /* V9 fmovd */ |
| 2571 | 2610 |
tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)]); |
| 2572 | 2611 |
tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], |
| 2573 | 2612 |
cpu_fpr[DFPREG(rs2) + 1]); |
| 2613 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 2574 | 2614 |
break; |
| 2575 | 2615 |
case 0x3: /* V9 fmovq */ |
| 2576 | 2616 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| ... | ... | |
| 2581 | 2621 |
cpu_fpr[QFPREG(rs2) + 2]); |
| 2582 | 2622 |
tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3], |
| 2583 | 2623 |
cpu_fpr[QFPREG(rs2) + 3]); |
| 2624 |
gen_update_fprs_dirty(QFPREG(rd)); |
|
| 2584 | 2625 |
break; |
| 2585 | 2626 |
case 0x6: /* V9 fnegd */ |
| 2586 | 2627 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 2587 | 2628 |
gen_helper_fnegd(); |
| 2588 | 2629 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2630 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 2589 | 2631 |
break; |
| 2590 | 2632 |
case 0x7: /* V9 fnegq */ |
| 2591 | 2633 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| 2592 | 2634 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
| 2593 | 2635 |
gen_helper_fnegq(); |
| 2594 | 2636 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
| 2637 |
gen_update_fprs_dirty(QFPREG(rd)); |
|
| 2595 | 2638 |
break; |
| 2596 | 2639 |
case 0xa: /* V9 fabsd */ |
| 2597 | 2640 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 2598 | 2641 |
gen_helper_fabsd(); |
| 2599 | 2642 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2643 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 2600 | 2644 |
break; |
| 2601 | 2645 |
case 0xb: /* V9 fabsq */ |
| 2602 | 2646 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| 2603 | 2647 |
gen_op_load_fpr_QT1(QFPREG(rs2)); |
| 2604 | 2648 |
gen_helper_fabsq(); |
| 2605 | 2649 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
| 2650 |
gen_update_fprs_dirty(QFPREG(rd)); |
|
| 2606 | 2651 |
break; |
| 2607 | 2652 |
case 0x81: /* V9 fstox */ |
| 2608 | 2653 |
gen_clear_float_exceptions(); |
| 2609 | 2654 |
gen_helper_fstox(cpu_fpr[rs2]); |
| 2610 | 2655 |
gen_helper_check_ieee_exceptions(); |
| 2611 | 2656 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2657 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 2612 | 2658 |
break; |
| 2613 | 2659 |
case 0x82: /* V9 fdtox */ |
| 2614 | 2660 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| ... | ... | |
| 2616 | 2662 |
gen_helper_fdtox(); |
| 2617 | 2663 |
gen_helper_check_ieee_exceptions(); |
| 2618 | 2664 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2665 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 2619 | 2666 |
break; |
| 2620 | 2667 |
case 0x83: /* V9 fqtox */ |
| 2621 | 2668 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| ... | ... | |
| 2624 | 2671 |
gen_helper_fqtox(); |
| 2625 | 2672 |
gen_helper_check_ieee_exceptions(); |
| 2626 | 2673 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2674 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 2627 | 2675 |
break; |
| 2628 | 2676 |
case 0x84: /* V9 fxtos */ |
| 2629 | 2677 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| ... | ... | |
| 2631 | 2679 |
gen_helper_fxtos(cpu_tmp32); |
| 2632 | 2680 |
gen_helper_check_ieee_exceptions(); |
| 2633 | 2681 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2682 |
gen_update_fprs_dirty(rd); |
|
| 2634 | 2683 |
break; |
| 2635 | 2684 |
case 0x88: /* V9 fxtod */ |
| 2636 | 2685 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| ... | ... | |
| 2638 | 2687 |
gen_helper_fxtod(); |
| 2639 | 2688 |
gen_helper_check_ieee_exceptions(); |
| 2640 | 2689 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 2690 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 2641 | 2691 |
break; |
| 2642 | 2692 |
case 0x8c: /* V9 fxtoq */ |
| 2643 | 2693 |
CHECK_FPU_FEATURE(dc, FLOAT128); |
| ... | ... | |
| 2646 | 2696 |
gen_helper_fxtoq(); |
| 2647 | 2697 |
gen_helper_check_ieee_exceptions(); |
| 2648 | 2698 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
| 2699 |
gen_update_fprs_dirty(QFPREG(rd)); |
|
| 2649 | 2700 |
break; |
| 2650 | 2701 |
#endif |
| 2651 | 2702 |
default: |
| ... | ... | |
| 2672 | 2723 |
tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1, |
| 2673 | 2724 |
0, l1); |
| 2674 | 2725 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); |
| 2726 |
gen_update_fprs_dirty(rd); |
|
| 2675 | 2727 |
gen_set_label(l1); |
| 2676 | 2728 |
break; |
| 2677 | 2729 |
} else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
|
| ... | ... | |
| 2684 | 2736 |
0, l1); |
| 2685 | 2737 |
tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)]); |
| 2686 | 2738 |
tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], cpu_fpr[DFPREG(rs2) + 1]); |
| 2739 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 2687 | 2740 |
gen_set_label(l1); |
| 2688 | 2741 |
break; |
| 2689 | 2742 |
} else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
|
| ... | ... | |
| 2699 | 2752 |
tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1], cpu_fpr[QFPREG(rs2) + 1]); |
| 2700 | 2753 |
tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2], cpu_fpr[QFPREG(rs2) + 2]); |
| 2701 | 2754 |
tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3], cpu_fpr[QFPREG(rs2) + 3]); |
| 2755 |
gen_update_fprs_dirty(QFPREG(rd)); |
|
| 2702 | 2756 |
gen_set_label(l1); |
| 2703 | 2757 |
break; |
| 2704 | 2758 |
} |
| ... | ... | |
| 2717 | 2771 |
tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
| 2718 | 2772 |
0, l1); \ |
| 2719 | 2773 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); \ |
| 2774 |
gen_update_fprs_dirty(rd); \ |
|
| 2720 | 2775 |
gen_set_label(l1); \ |
| 2721 | 2776 |
tcg_temp_free(r_cond); \ |
| 2722 | 2777 |
} |
| ... | ... | |
| 2735 | 2790 |
cpu_fpr[DFPREG(rs2)]); \ |
| 2736 | 2791 |
tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], \ |
| 2737 | 2792 |
cpu_fpr[DFPREG(rs2) + 1]); \ |
| 2793 |
gen_update_fprs_dirty(DFPREG(rd)); \ |
|
| 2738 | 2794 |
gen_set_label(l1); \ |
| 2739 | 2795 |
tcg_temp_free(r_cond); \ |
| 2740 | 2796 |
} |
| ... | ... | |
| 2757 | 2813 |
cpu_fpr[QFPREG(rs2) + 2]); \ |
| 2758 | 2814 |
tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3], \ |
| 2759 | 2815 |
cpu_fpr[QFPREG(rs2) + 3]); \ |
| 2816 |
gen_update_fprs_dirty(QFPREG(rd)); \ |
|
| 2760 | 2817 |
gen_set_label(l1); \ |
| 2761 | 2818 |
tcg_temp_free(r_cond); \ |
| 2762 | 2819 |
} |
| ... | ... | |
| 2815 | 2872 |
tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
| 2816 | 2873 |
0, l1); \ |
| 2817 | 2874 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); \ |
| 2875 |
gen_update_fprs_dirty(rd); \ |
|
| 2818 | 2876 |
gen_set_label(l1); \ |
| 2819 | 2877 |
tcg_temp_free(r_cond); \ |
| 2820 | 2878 |
} |
| ... | ... | |
| 2833 | 2891 |
cpu_fpr[DFPREG(rs2)]); \ |
| 2834 | 2892 |
tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], \ |
| 2835 | 2893 |
cpu_fpr[DFPREG(rs2) + 1]); \ |
| 2894 |
gen_update_fprs_dirty(DFPREG(rd)); \ |
|
| 2836 | 2895 |
gen_set_label(l1); \ |
| 2837 | 2896 |
tcg_temp_free(r_cond); \ |
| 2838 | 2897 |
} |
| ... | ... | |
| 2855 | 2914 |
cpu_fpr[QFPREG(rs2) + 2]); \ |
| 2856 | 2915 |
tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3], \ |
| 2857 | 2916 |
cpu_fpr[QFPREG(rs2) + 3]); \ |
| 2917 |
gen_update_fprs_dirty(QFPREG(rd)); \ |
|
| 2858 | 2918 |
gen_set_label(l1); \ |
| 2859 | 2919 |
tcg_temp_free(r_cond); \ |
| 2860 | 2920 |
} |
| ... | ... | |
| 3848 | 3908 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3849 | 3909 |
gen_helper_fmul8x16(); |
| 3850 | 3910 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 3911 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 3851 | 3912 |
break; |
| 3852 | 3913 |
case 0x033: /* VIS I fmul8x16au */ |
| 3853 | 3914 |
CHECK_FPU_FEATURE(dc, VIS1); |
| ... | ... | |
| 3855 | 3916 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3856 | 3917 |
gen_helper_fmul8x16au(); |
| 3857 | 3918 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 3919 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 3858 | 3920 |
break; |
| 3859 | 3921 |
case 0x035: /* VIS I fmul8x16al */ |
| 3860 | 3922 |
CHECK_FPU_FEATURE(dc, VIS1); |
| ... | ... | |
| 3862 | 3924 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3863 | 3925 |
gen_helper_fmul8x16al(); |
| 3864 | 3926 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 3927 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 3865 | 3928 |
break; |
| 3866 | 3929 |
case 0x036: /* VIS I fmul8sux16 */ |
| 3867 | 3930 |
CHECK_FPU_FEATURE(dc, VIS1); |
| ... | ... | |
| 3869 | 3932 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3870 | 3933 |
gen_helper_fmul8sux16(); |
| 3871 | 3934 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 3935 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 3872 | 3936 |
break; |
| 3873 | 3937 |
case 0x037: /* VIS I fmul8ulx16 */ |
| 3874 | 3938 |
CHECK_FPU_FEATURE(dc, VIS1); |
| ... | ... | |
| 3876 | 3940 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3877 | 3941 |
gen_helper_fmul8ulx16(); |
| 3878 | 3942 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 3943 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 3879 | 3944 |
break; |
| 3880 | 3945 |
case 0x038: /* VIS I fmuld8sux16 */ |
| 3881 | 3946 |
CHECK_FPU_FEATURE(dc, VIS1); |
| ... | ... | |
| 3883 | 3948 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3884 | 3949 |
gen_helper_fmuld8sux16(); |
| 3885 | 3950 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 3951 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 3886 | 3952 |
break; |
| 3887 | 3953 |
case 0x039: /* VIS I fmuld8ulx16 */ |
| 3888 | 3954 |
CHECK_FPU_FEATURE(dc, VIS1); |
| ... | ... | |
| 3890 | 3956 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3891 | 3957 |
gen_helper_fmuld8ulx16(); |
| 3892 | 3958 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 3959 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 3893 | 3960 |
break; |
| 3894 | 3961 |
case 0x03a: /* VIS I fpack32 */ |
| 3895 | 3962 |
case 0x03b: /* VIS I fpack16 */ |
| ... | ... | |
| 3903 | 3970 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3904 | 3971 |
gen_helper_faligndata(); |
| 3905 | 3972 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 3973 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 3906 | 3974 |
break; |
| 3907 | 3975 |
case 0x04b: /* VIS I fpmerge */ |
| 3908 | 3976 |
CHECK_FPU_FEATURE(dc, VIS1); |
| ... | ... | |
| 3910 | 3978 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3911 | 3979 |
gen_helper_fpmerge(); |
| 3912 | 3980 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 3981 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 3913 | 3982 |
break; |
| 3914 | 3983 |
case 0x04c: /* VIS II bshuffle */ |
| 3915 | 3984 |
// XXX |
| ... | ... | |
| 3920 | 3989 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3921 | 3990 |
gen_helper_fexpand(); |
| 3922 | 3991 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 3992 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 3923 | 3993 |
break; |
| 3924 | 3994 |
case 0x050: /* VIS I fpadd16 */ |
| 3925 | 3995 |
CHECK_FPU_FEATURE(dc, VIS1); |
| ... | ... | |
| 3927 | 3997 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3928 | 3998 |
gen_helper_fpadd16(); |
| 3929 | 3999 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 4000 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 3930 | 4001 |
break; |
| 3931 | 4002 |
case 0x051: /* VIS I fpadd16s */ |
| 3932 | 4003 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3933 | 4004 |
gen_helper_fpadd16s(cpu_fpr[rd], |
| 3934 | 4005 |
cpu_fpr[rs1], cpu_fpr[rs2]); |
| 4006 |
gen_update_fprs_dirty(rd); |
|
| 3935 | 4007 |
break; |
| 3936 | 4008 |
case 0x052: /* VIS I fpadd32 */ |
| 3937 | 4009 |
CHECK_FPU_FEATURE(dc, VIS1); |
| ... | ... | |
| 3939 | 4011 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3940 | 4012 |
gen_helper_fpadd32(); |
| 3941 | 4013 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 4014 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 3942 | 4015 |
break; |
| 3943 | 4016 |
case 0x053: /* VIS I fpadd32s */ |
| 3944 | 4017 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3945 | 4018 |
gen_helper_fpadd32s(cpu_fpr[rd], |
| 3946 | 4019 |
cpu_fpr[rs1], cpu_fpr[rs2]); |
| 4020 |
gen_update_fprs_dirty(rd); |
|
| 3947 | 4021 |
break; |
| 3948 | 4022 |
case 0x054: /* VIS I fpsub16 */ |
| 3949 | 4023 |
CHECK_FPU_FEATURE(dc, VIS1); |
| ... | ... | |
| 3951 | 4025 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3952 | 4026 |
gen_helper_fpsub16(); |
| 3953 | 4027 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 4028 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 3954 | 4029 |
break; |
| 3955 | 4030 |
case 0x055: /* VIS I fpsub16s */ |
| 3956 | 4031 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3957 | 4032 |
gen_helper_fpsub16s(cpu_fpr[rd], |
| 3958 | 4033 |
cpu_fpr[rs1], cpu_fpr[rs2]); |
| 4034 |
gen_update_fprs_dirty(rd); |
|
| 3959 | 4035 |
break; |
| 3960 | 4036 |
case 0x056: /* VIS I fpsub32 */ |
| 3961 | 4037 |
CHECK_FPU_FEATURE(dc, VIS1); |
| ... | ... | |
| 3963 | 4039 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 3964 | 4040 |
gen_helper_fpsub32(); |
| 3965 | 4041 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 4042 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 3966 | 4043 |
break; |
| 3967 | 4044 |
case 0x057: /* VIS I fpsub32s */ |
| 3968 | 4045 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3969 | 4046 |
gen_helper_fpsub32s(cpu_fpr[rd], |
| 3970 | 4047 |
cpu_fpr[rs1], cpu_fpr[rs2]); |
| 4048 |
gen_update_fprs_dirty(rd); |
|
| 3971 | 4049 |
break; |
| 3972 | 4050 |
case 0x060: /* VIS I fzero */ |
| 3973 | 4051 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3974 | 4052 |
tcg_gen_movi_i32(cpu_fpr[DFPREG(rd)], 0); |
| 3975 | 4053 |
tcg_gen_movi_i32(cpu_fpr[DFPREG(rd) + 1], 0); |
| 4054 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 3976 | 4055 |
break; |
| 3977 | 4056 |
case 0x061: /* VIS I fzeros */ |
| 3978 | 4057 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3979 | 4058 |
tcg_gen_movi_i32(cpu_fpr[rd], 0); |
| 4059 |
gen_update_fprs_dirty(rd); |
|
| 3980 | 4060 |
break; |
| 3981 | 4061 |
case 0x062: /* VIS I fnor */ |
| 3982 | 4062 |
CHECK_FPU_FEATURE(dc, VIS1); |
| ... | ... | |
| 3985 | 4065 |
tcg_gen_nor_i32(cpu_fpr[DFPREG(rd) + 1], |
| 3986 | 4066 |
cpu_fpr[DFPREG(rs1) + 1], |
| 3987 | 4067 |
cpu_fpr[DFPREG(rs2) + 1]); |
| 4068 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 3988 | 4069 |
break; |
| 3989 | 4070 |
case 0x063: /* VIS I fnors */ |
| 3990 | 4071 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3991 | 4072 |
tcg_gen_nor_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
| 4073 |
gen_update_fprs_dirty(rd); |
|
| 3992 | 4074 |
break; |
| 3993 | 4075 |
case 0x064: /* VIS I fandnot2 */ |
| 3994 | 4076 |
CHECK_FPU_FEATURE(dc, VIS1); |
| ... | ... | |
| 3997 | 4079 |
tcg_gen_andc_i32(cpu_fpr[DFPREG(rd) + 1], |
| 3998 | 4080 |
cpu_fpr[DFPREG(rs1) + 1], |
| 3999 | 4081 |
cpu_fpr[DFPREG(rs2) + 1]); |
| 4082 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 4000 | 4083 |
break; |
| 4001 | 4084 |
case 0x065: /* VIS I fandnot2s */ |
| 4002 | 4085 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4003 | 4086 |
tcg_gen_andc_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
| 4087 |
gen_update_fprs_dirty(rd); |
|
| 4004 | 4088 |
break; |
| 4005 | 4089 |
case 0x066: /* VIS I fnot2 */ |
| 4006 | 4090 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4007 | 4091 |
tcg_gen_not_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)]); |
| 4008 | 4092 |
tcg_gen_not_i32(cpu_fpr[DFPREG(rd) + 1], |
| 4009 | 4093 |
cpu_fpr[DFPREG(rs2) + 1]); |
| 4094 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 4010 | 4095 |
break; |
| 4011 | 4096 |
case 0x067: /* VIS I fnot2s */ |
| 4012 | 4097 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4013 | 4098 |
tcg_gen_not_i32(cpu_fpr[rd], cpu_fpr[rs2]); |
| 4099 |
gen_update_fprs_dirty(rd); |
|
| 4014 | 4100 |
break; |
| 4015 | 4101 |
case 0x068: /* VIS I fandnot1 */ |
| 4016 | 4102 |
CHECK_FPU_FEATURE(dc, VIS1); |
| ... | ... | |
| 4019 | 4105 |
tcg_gen_andc_i32(cpu_fpr[DFPREG(rd) + 1], |
| 4020 | 4106 |
cpu_fpr[DFPREG(rs2) + 1], |
| 4021 | 4107 |
cpu_fpr[DFPREG(rs1) + 1]); |
| 4108 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 4022 | 4109 |
break; |
| 4023 | 4110 |
case 0x069: /* VIS I fandnot1s */ |
| 4024 | 4111 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4025 | 4112 |
tcg_gen_andc_i32(cpu_fpr[rd], cpu_fpr[rs2], cpu_fpr[rs1]); |
| 4113 |
gen_update_fprs_dirty(rd); |
|
| 4026 | 4114 |
break; |
| 4027 | 4115 |
case 0x06a: /* VIS I fnot1 */ |
| 4028 | 4116 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4029 | 4117 |
tcg_gen_not_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)]); |
| 4030 | 4118 |
tcg_gen_not_i32(cpu_fpr[DFPREG(rd) + 1], |
| 4031 | 4119 |
cpu_fpr[DFPREG(rs1) + 1]); |
| 4120 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 4032 | 4121 |
break; |
| 4033 | 4122 |
case 0x06b: /* VIS I fnot1s */ |
| 4034 | 4123 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4035 | 4124 |
tcg_gen_not_i32(cpu_fpr[rd], cpu_fpr[rs1]); |
| 4125 |
gen_update_fprs_dirty(rd); |
|
| 4036 | 4126 |
break; |
| 4037 | 4127 |
case 0x06c: /* VIS I fxor */ |
| 4038 | 4128 |
CHECK_FPU_FEATURE(dc, VIS1); |
| ... | ... | |
| 4041 | 4131 |
tcg_gen_xor_i32(cpu_fpr[DFPREG(rd) + 1], |
| 4042 | 4132 |
cpu_fpr[DFPREG(rs1) + 1], |
| 4043 | 4133 |
cpu_fpr[DFPREG(rs2) + 1]); |
| 4134 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 4044 | 4135 |
break; |
| 4045 | 4136 |
case 0x06d: /* VIS I fxors */ |
| 4046 | 4137 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4047 | 4138 |
tcg_gen_xor_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
| 4139 |
gen_update_fprs_dirty(rd); |
|
| 4048 | 4140 |
break; |
| 4049 | 4141 |
case 0x06e: /* VIS I fnand */ |
| 4050 | 4142 |
CHECK_FPU_FEATURE(dc, VIS1); |
| ... | ... | |
| 4053 | 4145 |
tcg_gen_nand_i32(cpu_fpr[DFPREG(rd) + 1], |
| 4054 | 4146 |
cpu_fpr[DFPREG(rs1) + 1], |
| 4055 | 4147 |
cpu_fpr[DFPREG(rs2) + 1]); |
| 4148 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 4056 | 4149 |
break; |
| 4057 | 4150 |
case 0x06f: /* VIS I fnands */ |
| 4058 | 4151 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4059 | 4152 |
tcg_gen_nand_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
| 4153 |
gen_update_fprs_dirty(rd); |
|
| 4060 | 4154 |
break; |
| 4061 | 4155 |
case 0x070: /* VIS I fand */ |
| 4062 | 4156 |
CHECK_FPU_FEATURE(dc, VIS1); |
| ... | ... | |
| 4065 | 4159 |
tcg_gen_and_i32(cpu_fpr[DFPREG(rd) + 1], |
| 4066 | 4160 |
cpu_fpr[DFPREG(rs1) + 1], |
| 4067 | 4161 |
cpu_fpr[DFPREG(rs2) + 1]); |
| 4162 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 4068 | 4163 |
break; |
| 4069 | 4164 |
case 0x071: /* VIS I fands */ |
| 4070 | 4165 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4071 | 4166 |
tcg_gen_and_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
| 4167 |
gen_update_fprs_dirty(rd); |
|
| 4072 | 4168 |
break; |
| 4073 | 4169 |
case 0x072: /* VIS I fxnor */ |
| 4074 | 4170 |
CHECK_FPU_FEATURE(dc, VIS1); |
| ... | ... | |
| 4078 | 4174 |
tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2) + 1], -1); |
| 4079 | 4175 |
tcg_gen_xor_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, |
| 4080 | 4176 |
cpu_fpr[DFPREG(rs1) + 1]); |
| 4177 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 4081 | 4178 |
break; |
| 4082 | 4179 |
case 0x073: /* VIS I fxnors */ |
| 4083 | 4180 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4084 | 4181 |
tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs2], -1); |
| 4085 | 4182 |
tcg_gen_xor_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs1]); |
| 4183 |
gen_update_fprs_dirty(rd); |
|
| 4086 | 4184 |
break; |
| 4087 | 4185 |
case 0x074: /* VIS I fsrc1 */ |
| 4088 | 4186 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4089 | 4187 |
tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)]); |
| 4090 | 4188 |
tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], |
| 4091 | 4189 |
cpu_fpr[DFPREG(rs1) + 1]); |
| 4190 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 4092 | 4191 |
break; |
| 4093 | 4192 |
case 0x075: /* VIS I fsrc1s */ |
| 4094 | 4193 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4095 | 4194 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs1]); |
| 4195 |
gen_update_fprs_dirty(rd); |
|
| 4096 | 4196 |
break; |
| 4097 | 4197 |
case 0x076: /* VIS I fornot2 */ |
| 4098 | 4198 |
CHECK_FPU_FEATURE(dc, VIS1); |
| ... | ... | |
| 4101 | 4201 |
tcg_gen_orc_i32(cpu_fpr[DFPREG(rd) + 1], |
| 4102 | 4202 |
cpu_fpr[DFPREG(rs1) + 1], |
| 4103 | 4203 |
cpu_fpr[DFPREG(rs2) + 1]); |
| 4204 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 4104 | 4205 |
break; |
| 4105 | 4206 |
case 0x077: /* VIS I fornot2s */ |
| 4106 | 4207 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4107 | 4208 |
tcg_gen_orc_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
| 4209 |
gen_update_fprs_dirty(rd); |
|
| 4108 | 4210 |
break; |
| 4109 | 4211 |
case 0x078: /* VIS I fsrc2 */ |
| 4110 | 4212 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4111 | 4213 |
gen_op_load_fpr_DT0(DFPREG(rs2)); |
| 4112 | 4214 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 4215 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 4113 | 4216 |
break; |
| 4114 | 4217 |
case 0x079: /* VIS I fsrc2s */ |
| 4115 | 4218 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4116 | 4219 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); |
| 4220 |
gen_update_fprs_dirty(rd); |
|
| 4117 | 4221 |
break; |
| 4118 | 4222 |
case 0x07a: /* VIS I fornot1 */ |
| 4119 | 4223 |
CHECK_FPU_FEATURE(dc, VIS1); |
| ... | ... | |
| 4122 | 4226 |
tcg_gen_orc_i32(cpu_fpr[DFPREG(rd) + 1], |
| 4123 | 4227 |
cpu_fpr[DFPREG(rs2) + 1], |
| 4124 | 4228 |
cpu_fpr[DFPREG(rs1) + 1]); |
| 4229 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 4125 | 4230 |
break; |
| 4126 | 4231 |
case 0x07b: /* VIS I fornot1s */ |
| 4127 | 4232 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4128 | 4233 |
tcg_gen_orc_i32(cpu_fpr[rd], cpu_fpr[rs2], cpu_fpr[rs1]); |
| 4234 |
gen_update_fprs_dirty(rd); |
|
| 4129 | 4235 |
break; |
| 4130 | 4236 |
case 0x07c: /* VIS I for */ |
| 4131 | 4237 |
CHECK_FPU_FEATURE(dc, VIS1); |
| ... | ... | |
| 4134 | 4240 |
tcg_gen_or_i32(cpu_fpr[DFPREG(rd) + 1], |
| 4135 | 4241 |
cpu_fpr[DFPREG(rs1) + 1], |
| 4136 | 4242 |
cpu_fpr[DFPREG(rs2) + 1]); |
| 4243 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 4137 | 4244 |
break; |
| 4138 | 4245 |
case 0x07d: /* VIS I fors */ |
| 4139 | 4246 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4140 | 4247 |
tcg_gen_or_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
| 4248 |
gen_update_fprs_dirty(rd); |
|
| 4141 | 4249 |
break; |
| 4142 | 4250 |
case 0x07e: /* VIS I fone */ |
| 4143 | 4251 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4144 | 4252 |
tcg_gen_movi_i32(cpu_fpr[DFPREG(rd)], -1); |
| 4145 | 4253 |
tcg_gen_movi_i32(cpu_fpr[DFPREG(rd) + 1], -1); |
| 4254 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 4146 | 4255 |
break; |
| 4147 | 4256 |
case 0x07f: /* VIS I fones */ |
| 4148 | 4257 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 4149 | 4258 |
tcg_gen_movi_i32(cpu_fpr[rd], -1); |
| 4259 |
gen_update_fprs_dirty(rd); |
|
| 4150 | 4260 |
break; |
| 4151 | 4261 |
case 0x080: /* VIS I shutdown */ |
| 4152 | 4262 |
case 0x081: /* VIS II siam */ |
| ... | ... | |
| 4492 | 4602 |
} |
| 4493 | 4603 |
save_state(dc, cpu_cond); |
| 4494 | 4604 |
gen_ldf_asi(cpu_addr, insn, 4, rd); |
| 4605 |
gen_update_fprs_dirty(rd); |
|
| 4495 | 4606 |
goto skip_move; |
| 4496 | 4607 |
case 0x33: /* V9 lddfa */ |
| 4497 | 4608 |
if (gen_trap_ifnofpu(dc, cpu_cond)) {
|
| ... | ... | |
| 4499 | 4610 |
} |
| 4500 | 4611 |
save_state(dc, cpu_cond); |
| 4501 | 4612 |
gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd)); |
| 4613 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 4502 | 4614 |
goto skip_move; |
| 4503 | 4615 |
case 0x3d: /* V9 prefetcha, no effect */ |
| 4504 | 4616 |
goto skip_move; |
| ... | ... | |
| 4509 | 4621 |
} |
| 4510 | 4622 |
save_state(dc, cpu_cond); |
| 4511 | 4623 |
gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd)); |
| 4624 |
gen_update_fprs_dirty(QFPREG(rd)); |
|
| 4512 | 4625 |
goto skip_move; |
| 4513 | 4626 |
#endif |
| 4514 | 4627 |
default: |
| ... | ... | |
| 4527 | 4640 |
gen_address_mask(dc, cpu_addr); |
| 4528 | 4641 |
tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx); |
| 4529 | 4642 |
tcg_gen_trunc_tl_i32(cpu_fpr[rd], cpu_tmp0); |
| 4643 |
gen_update_fprs_dirty(rd); |
|
| 4530 | 4644 |
break; |
| 4531 | 4645 |
case 0x21: /* ldfsr, V9 ldxfsr */ |
| 4532 | 4646 |
#ifdef TARGET_SPARC64 |
| ... | ... | |
| 4556 | 4670 |
gen_helper_ldqf(cpu_addr, r_const); |
| 4557 | 4671 |
tcg_temp_free_i32(r_const); |
| 4558 | 4672 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
| 4673 |
gen_update_fprs_dirty(QFPREG(rd)); |
|
| 4559 | 4674 |
} |
| 4560 | 4675 |
break; |
| 4561 | 4676 |
case 0x23: /* lddf, load double fpreg */ |
| ... | ... | |
| 4567 | 4682 |
gen_helper_lddf(cpu_addr, r_const); |
| 4568 | 4683 |
tcg_temp_free_i32(r_const); |
| 4569 | 4684 |
gen_op_store_DT0_fpr(DFPREG(rd)); |
| 4685 |
gen_update_fprs_dirty(DFPREG(rd)); |
|
| 4570 | 4686 |
} |
| 4571 | 4687 |
break; |
| 4572 | 4688 |
default: |
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