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1
/*
2
 * Copyright (C) 2010 Red Hat, Inc.
3
 *
4
 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
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 * maintained by Gerd Hoffmann <kraxel@redhat.com>
6
 *
7
 * This program is free software; you can redistribute it and/or
8
 * modify it under the terms of the GNU General Public License as
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 * published by the Free Software Foundation; either version 2 or
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 * (at your option) version 3 of the License.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License
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 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19
 */
20

    
21
#include <pthread.h>
22

    
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#include "qemu-common.h"
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#include "qemu-timer.h"
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#include "qemu-queue.h"
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#include "monitor.h"
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#include "sysemu.h"
28

    
29
#include "qxl.h"
30

    
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#undef SPICE_RING_PROD_ITEM
32
#define SPICE_RING_PROD_ITEM(r, ret) {                                  \
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        typeof(r) start = r;                                            \
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        typeof(r) end = r + 1;                                          \
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        uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r);           \
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        typeof(&(r)->items[prod]) m_item = &(r)->items[prod];           \
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        if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
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            abort();                                                    \
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        }                                                               \
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        ret = &m_item->el;                                              \
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    }
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#undef SPICE_RING_CONS_ITEM
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#define SPICE_RING_CONS_ITEM(r, ret) {                                  \
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        typeof(r) start = r;                                            \
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        typeof(r) end = r + 1;                                          \
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        uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r);           \
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        typeof(&(r)->items[cons]) m_item = &(r)->items[cons];           \
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        if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
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            abort();                                                    \
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        }                                                               \
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        ret = &m_item->el;                                              \
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    }
54

    
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#undef ALIGN
56
#define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
57

    
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#define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9" 
59

    
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#define QXL_MODE(_x, _y, _b, _o)                  \
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    {   .x_res = _x,                              \
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        .y_res = _y,                              \
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        .bits  = _b,                              \
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        .stride = (_x) * (_b) / 8,                \
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        .x_mili = PIXEL_SIZE * (_x),              \
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        .y_mili = PIXEL_SIZE * (_y),              \
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        .orientation = _o,                        \
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    }
69

    
70
#define QXL_MODE_16_32(x_res, y_res, orientation) \
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    QXL_MODE(x_res, y_res, 16, orientation),      \
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    QXL_MODE(x_res, y_res, 32, orientation)
73

    
74
#define QXL_MODE_EX(x_res, y_res)                 \
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    QXL_MODE_16_32(x_res, y_res, 0),              \
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    QXL_MODE_16_32(y_res, x_res, 1),              \
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    QXL_MODE_16_32(x_res, y_res, 2),              \
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    QXL_MODE_16_32(y_res, x_res, 3)
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80
static QXLMode qxl_modes[] = {
81
    QXL_MODE_EX(640, 480),
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    QXL_MODE_EX(800, 480),
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    QXL_MODE_EX(800, 600),
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    QXL_MODE_EX(832, 624),
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    QXL_MODE_EX(960, 640),
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    QXL_MODE_EX(1024, 600),
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    QXL_MODE_EX(1024, 768),
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    QXL_MODE_EX(1152, 864),
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    QXL_MODE_EX(1152, 870),
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    QXL_MODE_EX(1280, 720),
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    QXL_MODE_EX(1280, 760),
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    QXL_MODE_EX(1280, 768),
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    QXL_MODE_EX(1280, 800),
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    QXL_MODE_EX(1280, 960),
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    QXL_MODE_EX(1280, 1024),
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    QXL_MODE_EX(1360, 768),
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    QXL_MODE_EX(1366, 768),
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    QXL_MODE_EX(1400, 1050),
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    QXL_MODE_EX(1440, 900),
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    QXL_MODE_EX(1600, 900),
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    QXL_MODE_EX(1600, 1200),
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    QXL_MODE_EX(1680, 1050),
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    QXL_MODE_EX(1920, 1080),
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#if VGA_RAM_SIZE >= (16 * 1024 * 1024)
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    /* these modes need more than 8 MB video memory */
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    QXL_MODE_EX(1920, 1200),
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    QXL_MODE_EX(1920, 1440),
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    QXL_MODE_EX(2048, 1536),
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    QXL_MODE_EX(2560, 1440),
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    QXL_MODE_EX(2560, 1600),
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#endif
112
#if VGA_RAM_SIZE >= (32 * 1024 * 1024)
113
    /* these modes need more than 16 MB video memory */
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    QXL_MODE_EX(2560, 2048),
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    QXL_MODE_EX(2800, 2100),
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    QXL_MODE_EX(3200, 2400),
117
#endif
118
};
119

    
120
static PCIQXLDevice *qxl0;
121

    
122
static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
123
static void qxl_destroy_primary(PCIQXLDevice *d);
124
static void qxl_reset_memslots(PCIQXLDevice *d);
125
static void qxl_reset_surfaces(PCIQXLDevice *d);
126
static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
127

    
128
static inline uint32_t msb_mask(uint32_t val)
129
{
130
    uint32_t mask;
131

    
132
    do {
133
        mask = ~(val - 1) & val;
134
        val &= ~mask;
135
    } while (mask < val);
136

    
137
    return mask;
138
}
139

    
140
static ram_addr_t qxl_rom_size(void)
141
{
142
    uint32_t rom_size = sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes);
143
    rom_size = MAX(rom_size, TARGET_PAGE_SIZE);
144
    rom_size = msb_mask(rom_size * 2 - 1);
145
    return rom_size;
146
}
147

    
148
static void init_qxl_rom(PCIQXLDevice *d)
149
{
150
    QXLRom *rom = qemu_get_ram_ptr(d->rom_offset);
151
    QXLModes *modes = (QXLModes *)(rom + 1);
152
    uint32_t ram_header_size;
153
    uint32_t surface0_area_size;
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    uint32_t num_pages;
155
    uint32_t fb, maxfb = 0;
156
    int i;
157

    
158
    memset(rom, 0, d->rom_size);
159

    
160
    rom->magic         = cpu_to_le32(QXL_ROM_MAGIC);
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    rom->id            = cpu_to_le32(d->id);
162
    rom->log_level     = cpu_to_le32(d->guestdebug);
163
    rom->modes_offset  = cpu_to_le32(sizeof(QXLRom));
164

    
165
    rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
166
    rom->slot_id_bits  = MEMSLOT_SLOT_BITS;
167
    rom->slots_start   = 1;
168
    rom->slots_end     = NUM_MEMSLOTS - 1;
169
    rom->n_surfaces    = cpu_to_le32(NUM_SURFACES);
170

    
171
    modes->n_modes     = cpu_to_le32(ARRAY_SIZE(qxl_modes));
172
    for (i = 0; i < modes->n_modes; i++) {
173
        fb = qxl_modes[i].y_res * qxl_modes[i].stride;
174
        if (maxfb < fb) {
175
            maxfb = fb;
176
        }
177
        modes->modes[i].id          = cpu_to_le32(i);
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        modes->modes[i].x_res       = cpu_to_le32(qxl_modes[i].x_res);
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        modes->modes[i].y_res       = cpu_to_le32(qxl_modes[i].y_res);
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        modes->modes[i].bits        = cpu_to_le32(qxl_modes[i].bits);
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        modes->modes[i].stride      = cpu_to_le32(qxl_modes[i].stride);
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        modes->modes[i].x_mili      = cpu_to_le32(qxl_modes[i].x_mili);
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        modes->modes[i].y_mili      = cpu_to_le32(qxl_modes[i].y_mili);
184
        modes->modes[i].orientation = cpu_to_le32(qxl_modes[i].orientation);
185
    }
186
    if (maxfb < VGA_RAM_SIZE && d->id == 0)
187
        maxfb = VGA_RAM_SIZE;
188

    
189
    ram_header_size    = ALIGN(sizeof(QXLRam), 4096);
190
    surface0_area_size = ALIGN(maxfb, 4096);
191
    num_pages          = d->vga.vram_size;
192
    num_pages         -= ram_header_size;
193
    num_pages         -= surface0_area_size;
194
    num_pages          = num_pages / TARGET_PAGE_SIZE;
195

    
196
    rom->draw_area_offset   = cpu_to_le32(0);
197
    rom->surface0_area_size = cpu_to_le32(surface0_area_size);
198
    rom->pages_offset       = cpu_to_le32(surface0_area_size);
199
    rom->num_pages          = cpu_to_le32(num_pages);
200
    rom->ram_header_offset  = cpu_to_le32(d->vga.vram_size - ram_header_size);
201

    
202
    d->shadow_rom = *rom;
203
    d->rom        = rom;
204
    d->modes      = modes;
205
}
206

    
207
static void init_qxl_ram(PCIQXLDevice *d)
208
{
209
    uint8_t *buf;
210
    uint64_t *item;
211

    
212
    buf = d->vga.vram_ptr;
213
    d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
214
    d->ram->magic       = cpu_to_le32(QXL_RAM_MAGIC);
215
    d->ram->int_pending = cpu_to_le32(0);
216
    d->ram->int_mask    = cpu_to_le32(0);
217
    SPICE_RING_INIT(&d->ram->cmd_ring);
218
    SPICE_RING_INIT(&d->ram->cursor_ring);
219
    SPICE_RING_INIT(&d->ram->release_ring);
220
    SPICE_RING_PROD_ITEM(&d->ram->release_ring, item);
221
    *item = 0;
222
    qxl_ring_set_dirty(d);
223
}
224

    
225
/* can be called from spice server thread context */
226
static void qxl_set_dirty(ram_addr_t addr, ram_addr_t end)
227
{
228
    while (addr < end) {
229
        cpu_physical_memory_set_dirty(addr);
230
        addr += TARGET_PAGE_SIZE;
231
    }
232
}
233

    
234
static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
235
{
236
    ram_addr_t addr = qxl->rom_offset;
237
    qxl_set_dirty(addr, addr + qxl->rom_size);
238
}
239

    
240
/* called from spice server thread context only */
241
static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
242
{
243
    ram_addr_t addr = qxl->vga.vram_offset;
244
    void *base = qxl->vga.vram_ptr;
245
    intptr_t offset;
246

    
247
    offset = ptr - base;
248
    offset &= ~(TARGET_PAGE_SIZE-1);
249
    assert(offset < qxl->vga.vram_size);
250
    qxl_set_dirty(addr + offset, addr + offset + TARGET_PAGE_SIZE);
251
}
252

    
253
/* can be called from spice server thread context */
254
static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
255
{
256
    ram_addr_t addr = qxl->vga.vram_offset + qxl->shadow_rom.ram_header_offset;
257
    ram_addr_t end  = qxl->vga.vram_offset + qxl->vga.vram_size;
258
    qxl_set_dirty(addr, end);
259
}
260

    
261
/*
262
 * keep track of some command state, for savevm/loadvm.
263
 * called from spice server thread context only
264
 */
265
static void qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
266
{
267
    switch (le32_to_cpu(ext->cmd.type)) {
268
    case QXL_CMD_SURFACE:
269
    {
270
        QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
271
        uint32_t id = le32_to_cpu(cmd->surface_id);
272
        PANIC_ON(id >= NUM_SURFACES);
273
        if (cmd->type == QXL_SURFACE_CMD_CREATE) {
274
            qxl->guest_surfaces.cmds[id] = ext->cmd.data;
275
            qxl->guest_surfaces.count++;
276
            if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
277
                qxl->guest_surfaces.max = qxl->guest_surfaces.count;
278
        }
279
        if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
280
            qxl->guest_surfaces.cmds[id] = 0;
281
            qxl->guest_surfaces.count--;
282
        }
283
        break;
284
    }
285
    case QXL_CMD_CURSOR:
286
    {
287
        QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
288
        if (cmd->type == QXL_CURSOR_SET) {
289
            qxl->guest_cursor = ext->cmd.data;
290
        }
291
        break;
292
    }
293
    }
294
}
295

    
296
/* spice display interface callbacks */
297

    
298
static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
299
{
300
    PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
301

    
302
    dprint(qxl, 1, "%s:\n", __FUNCTION__);
303
    qxl->ssd.worker = qxl_worker;
304
}
305

    
306
static void interface_set_compression_level(QXLInstance *sin, int level)
307
{
308
    PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
309

    
310
    dprint(qxl, 1, "%s: %d\n", __FUNCTION__, level);
311
    qxl->shadow_rom.compression_level = cpu_to_le32(level);
312
    qxl->rom->compression_level = cpu_to_le32(level);
313
    qxl_rom_set_dirty(qxl);
314
}
315

    
316
static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
317
{
318
    PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
319

    
320
    qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
321
    qxl->rom->mm_clock = cpu_to_le32(mm_time);
322
    qxl_rom_set_dirty(qxl);
323
}
324

    
325
static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
326
{
327
    PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
328

    
329
    dprint(qxl, 1, "%s:\n", __FUNCTION__);
330
    info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
331
    info->memslot_id_bits = MEMSLOT_SLOT_BITS;
332
    info->num_memslots = NUM_MEMSLOTS;
333
    info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
334
    info->internal_groupslot_id = 0;
335
    info->qxl_ram_size = le32_to_cpu(qxl->shadow_rom.num_pages) << TARGET_PAGE_BITS;
336
    info->n_surfaces = NUM_SURFACES;
337
}
338

    
339
/* called from spice server thread context only */
340
static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
341
{
342
    PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
343
    SimpleSpiceUpdate *update;
344
    QXLCommandRing *ring;
345
    QXLCommand *cmd;
346
    int notify, ret;
347

    
348
    switch (qxl->mode) {
349
    case QXL_MODE_VGA:
350
        dprint(qxl, 2, "%s: vga\n", __FUNCTION__);
351
        ret = false;
352
        qemu_mutex_lock(&qxl->ssd.lock);
353
        if (qxl->ssd.update != NULL) {
354
            update = qxl->ssd.update;
355
            qxl->ssd.update = NULL;
356
            *ext = update->ext;
357
            ret = true;
358
        }
359
        qemu_mutex_unlock(&qxl->ssd.lock);
360
        if (ret) {
361
            qxl_log_command(qxl, "vga", ext);
362
        }
363
        return ret;
364
    case QXL_MODE_COMPAT:
365
    case QXL_MODE_NATIVE:
366
    case QXL_MODE_UNDEFINED:
367
        dprint(qxl, 2, "%s: %s\n", __FUNCTION__,
368
               qxl->cmdflags ? "compat" : "native");
369
        ring = &qxl->ram->cmd_ring;
370
        if (SPICE_RING_IS_EMPTY(ring)) {
371
            return false;
372
        }
373
        SPICE_RING_CONS_ITEM(ring, cmd);
374
        ext->cmd      = *cmd;
375
        ext->group_id = MEMSLOT_GROUP_GUEST;
376
        ext->flags    = qxl->cmdflags;
377
        SPICE_RING_POP(ring, notify);
378
        qxl_ring_set_dirty(qxl);
379
        if (notify) {
380
            qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
381
        }
382
        qxl->guest_primary.commands++;
383
        qxl_track_command(qxl, ext);
384
        qxl_log_command(qxl, "cmd", ext);
385
        return true;
386
    default:
387
        return false;
388
    }
389
}
390

    
391
/* called from spice server thread context only */
392
static int interface_req_cmd_notification(QXLInstance *sin)
393
{
394
    PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
395
    int wait = 1;
396

    
397
    switch (qxl->mode) {
398
    case QXL_MODE_COMPAT:
399
    case QXL_MODE_NATIVE:
400
    case QXL_MODE_UNDEFINED:
401
        SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
402
        qxl_ring_set_dirty(qxl);
403
        break;
404
    default:
405
        /* nothing */
406
        break;
407
    }
408
    return wait;
409
}
410

    
411
/* called from spice server thread context only */
412
static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
413
{
414
    QXLReleaseRing *ring = &d->ram->release_ring;
415
    uint64_t *item;
416
    int notify;
417

    
418
#define QXL_FREE_BUNCH_SIZE 32
419

    
420
    if (ring->prod - ring->cons + 1 == ring->num_items) {
421
        /* ring full -- can't push */
422
        return;
423
    }
424
    if (!flush && d->oom_running) {
425
        /* collect everything from oom handler before pushing */
426
        return;
427
    }
428
    if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
429
        /* collect a bit more before pushing */
430
        return;
431
    }
432

    
433
    SPICE_RING_PUSH(ring, notify);
434
    dprint(d, 2, "free: push %d items, notify %s, ring %d/%d [%d,%d]\n",
435
           d->num_free_res, notify ? "yes" : "no",
436
           ring->prod - ring->cons, ring->num_items,
437
           ring->prod, ring->cons);
438
    if (notify) {
439
        qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
440
    }
441
    SPICE_RING_PROD_ITEM(ring, item);
442
    *item = 0;
443
    d->num_free_res = 0;
444
    d->last_release = NULL;
445
    qxl_ring_set_dirty(d);
446
}
447

    
448
/* called from spice server thread context only */
449
static void interface_release_resource(QXLInstance *sin,
450
                                       struct QXLReleaseInfoExt ext)
451
{
452
    PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
453
    QXLReleaseRing *ring;
454
    uint64_t *item, id;
455

    
456
    if (ext.group_id == MEMSLOT_GROUP_HOST) {
457
        /* host group -> vga mode update request */
458
        qemu_spice_destroy_update(&qxl->ssd, (void*)ext.info->id);
459
        return;
460
    }
461

    
462
    /*
463
     * ext->info points into guest-visible memory
464
     * pci bar 0, $command.release_info
465
     */
466
    ring = &qxl->ram->release_ring;
467
    SPICE_RING_PROD_ITEM(ring, item);
468
    if (*item == 0) {
469
        /* stick head into the ring */
470
        id = ext.info->id;
471
        ext.info->next = 0;
472
        qxl_ram_set_dirty(qxl, &ext.info->next);
473
        *item = id;
474
        qxl_ring_set_dirty(qxl);
475
    } else {
476
        /* append item to the list */
477
        qxl->last_release->next = ext.info->id;
478
        qxl_ram_set_dirty(qxl, &qxl->last_release->next);
479
        ext.info->next = 0;
480
        qxl_ram_set_dirty(qxl, &ext.info->next);
481
    }
482
    qxl->last_release = ext.info;
483
    qxl->num_free_res++;
484
    dprint(qxl, 3, "%4d\r", qxl->num_free_res);
485
    qxl_push_free_res(qxl, 0);
486
}
487

    
488
/* called from spice server thread context only */
489
static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
490
{
491
    PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
492
    QXLCursorRing *ring;
493
    QXLCommand *cmd;
494
    int notify;
495

    
496
    switch (qxl->mode) {
497
    case QXL_MODE_COMPAT:
498
    case QXL_MODE_NATIVE:
499
    case QXL_MODE_UNDEFINED:
500
        ring = &qxl->ram->cursor_ring;
501
        if (SPICE_RING_IS_EMPTY(ring)) {
502
            return false;
503
        }
504
        SPICE_RING_CONS_ITEM(ring, cmd);
505
        ext->cmd      = *cmd;
506
        ext->group_id = MEMSLOT_GROUP_GUEST;
507
        ext->flags    = qxl->cmdflags;
508
        SPICE_RING_POP(ring, notify);
509
        qxl_ring_set_dirty(qxl);
510
        if (notify) {
511
            qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
512
        }
513
        qxl->guest_primary.commands++;
514
        qxl_track_command(qxl, ext);
515
        qxl_log_command(qxl, "csr", ext);
516
        if (qxl->id == 0) {
517
            qxl_render_cursor(qxl, ext);
518
        }
519
        return true;
520
    default:
521
        return false;
522
    }
523
}
524

    
525
/* called from spice server thread context only */
526
static int interface_req_cursor_notification(QXLInstance *sin)
527
{
528
    PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
529
    int wait = 1;
530

    
531
    switch (qxl->mode) {
532
    case QXL_MODE_COMPAT:
533
    case QXL_MODE_NATIVE:
534
    case QXL_MODE_UNDEFINED:
535
        SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
536
        qxl_ring_set_dirty(qxl);
537
        break;
538
    default:
539
        /* nothing */
540
        break;
541
    }
542
    return wait;
543
}
544

    
545
/* called from spice server thread context */
546
static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
547
{
548
    fprintf(stderr, "%s: abort()\n", __FUNCTION__);
549
    abort();
550
}
551

    
552
/* called from spice server thread context only */
553
static int interface_flush_resources(QXLInstance *sin)
554
{
555
    PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
556
    int ret;
557

    
558
    dprint(qxl, 1, "free: guest flush (have %d)\n", qxl->num_free_res);
559
    ret = qxl->num_free_res;
560
    if (ret) {
561
        qxl_push_free_res(qxl, 1);
562
    }
563
    return ret;
564
}
565

    
566
static const QXLInterface qxl_interface = {
567
    .base.type               = SPICE_INTERFACE_QXL,
568
    .base.description        = "qxl gpu",
569
    .base.major_version      = SPICE_INTERFACE_QXL_MAJOR,
570
    .base.minor_version      = SPICE_INTERFACE_QXL_MINOR,
571

    
572
    .attache_worker          = interface_attach_worker,
573
    .set_compression_level   = interface_set_compression_level,
574
    .set_mm_time             = interface_set_mm_time,
575
    .get_init_info           = interface_get_init_info,
576

    
577
    /* the callbacks below are called from spice server thread context */
578
    .get_command             = interface_get_command,
579
    .req_cmd_notification    = interface_req_cmd_notification,
580
    .release_resource        = interface_release_resource,
581
    .get_cursor_command      = interface_get_cursor_command,
582
    .req_cursor_notification = interface_req_cursor_notification,
583
    .notify_update           = interface_notify_update,
584
    .flush_resources         = interface_flush_resources,
585
};
586

    
587
static void qxl_enter_vga_mode(PCIQXLDevice *d)
588
{
589
    if (d->mode == QXL_MODE_VGA) {
590
        return;
591
    }
592
    dprint(d, 1, "%s\n", __FUNCTION__);
593
    qemu_spice_create_host_primary(&d->ssd);
594
    d->mode = QXL_MODE_VGA;
595
    memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
596
}
597

    
598
static void qxl_exit_vga_mode(PCIQXLDevice *d)
599
{
600
    if (d->mode != QXL_MODE_VGA) {
601
        return;
602
    }
603
    dprint(d, 1, "%s\n", __FUNCTION__);
604
    qxl_destroy_primary(d);
605
}
606

    
607
static void qxl_set_irq(PCIQXLDevice *d)
608
{
609
    uint32_t pending = le32_to_cpu(d->ram->int_pending);
610
    uint32_t mask    = le32_to_cpu(d->ram->int_mask);
611
    int level = !!(pending & mask);
612
    qemu_set_irq(d->pci.irq[0], level);
613
    qxl_ring_set_dirty(d);
614
}
615

    
616
static void qxl_write_config(PCIDevice *d, uint32_t address,
617
                             uint32_t val, int len)
618
{
619
    PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, d);
620
    VGACommonState *vga = &qxl->vga;
621

    
622
    vga_dirty_log_stop(vga);
623
    pci_default_write_config(d, address, val, len);
624
    if (vga->map_addr && qxl->pci.io_regions[0].addr == -1) {
625
        vga->map_addr = 0;
626
    }
627
    vga_dirty_log_start(vga);
628
}
629

    
630
static void qxl_check_state(PCIQXLDevice *d)
631
{
632
    QXLRam *ram = d->ram;
633

    
634
    assert(SPICE_RING_IS_EMPTY(&ram->cmd_ring));
635
    assert(SPICE_RING_IS_EMPTY(&ram->cursor_ring));
636
}
637

    
638
static void qxl_reset_state(PCIQXLDevice *d)
639
{
640
    QXLRam *ram = d->ram;
641
    QXLRom *rom = d->rom;
642

    
643
    assert(SPICE_RING_IS_EMPTY(&ram->cmd_ring));
644
    assert(SPICE_RING_IS_EMPTY(&ram->cursor_ring));
645
    d->shadow_rom.update_id = cpu_to_le32(0);
646
    *rom = d->shadow_rom;
647
    qxl_rom_set_dirty(d);
648
    init_qxl_ram(d);
649
    d->num_free_res = 0;
650
    d->last_release = NULL;
651
    memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
652
}
653

    
654
static void qxl_soft_reset(PCIQXLDevice *d)
655
{
656
    dprint(d, 1, "%s:\n", __FUNCTION__);
657
    qxl_check_state(d);
658

    
659
    if (d->id == 0) {
660
        qxl_enter_vga_mode(d);
661
    } else {
662
        d->mode = QXL_MODE_UNDEFINED;
663
    }
664
}
665

    
666
static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
667
{
668
    dprint(d, 1, "%s: start%s\n", __FUNCTION__,
669
           loadvm ? " (loadvm)" : "");
670

    
671
    d->ssd.worker->reset_cursor(d->ssd.worker);
672
    d->ssd.worker->reset_image_cache(d->ssd.worker);
673
    qxl_reset_surfaces(d);
674
    qxl_reset_memslots(d);
675

    
676
    /* pre loadvm reset must not touch QXLRam.  This lives in
677
     * device memory, is migrated together with RAM and thus
678
     * already loaded at this point */
679
    if (!loadvm) {
680
        qxl_reset_state(d);
681
    }
682
    qemu_spice_create_host_memslot(&d->ssd);
683
    qxl_soft_reset(d);
684

    
685
    dprint(d, 1, "%s: done\n", __FUNCTION__);
686
}
687

    
688
static void qxl_reset_handler(DeviceState *dev)
689
{
690
    PCIQXLDevice *d = DO_UPCAST(PCIQXLDevice, pci.qdev, dev);
691
    qxl_hard_reset(d, 0);
692
}
693

    
694
static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
695
{
696
    VGACommonState *vga = opaque;
697
    PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
698

    
699
    if (qxl->mode != QXL_MODE_VGA) {
700
        dprint(qxl, 1, "%s\n", __FUNCTION__);
701
        qxl_destroy_primary(qxl);
702
        qxl_soft_reset(qxl);
703
    }
704
    vga_ioport_write(opaque, addr, val);
705
}
706

    
707
static void qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta)
708
{
709
    static const int regions[] = {
710
        QXL_RAM_RANGE_INDEX,
711
        QXL_VRAM_RANGE_INDEX,
712
    };
713
    uint64_t guest_start;
714
    uint64_t guest_end;
715
    int pci_region;
716
    pcibus_t pci_start;
717
    pcibus_t pci_end;
718
    intptr_t virt_start;
719
    QXLDevMemSlot memslot;
720
    int i;
721

    
722
    guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
723
    guest_end   = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
724

    
725
    dprint(d, 1, "%s: slot %d: guest phys 0x%" PRIx64 " - 0x%" PRIx64 "\n",
726
           __FUNCTION__, slot_id,
727
           guest_start, guest_end);
728

    
729
    PANIC_ON(slot_id >= NUM_MEMSLOTS);
730
    PANIC_ON(guest_start > guest_end);
731

    
732
    for (i = 0; i < ARRAY_SIZE(regions); i++) {
733
        pci_region = regions[i];
734
        pci_start = d->pci.io_regions[pci_region].addr;
735
        pci_end = pci_start + d->pci.io_regions[pci_region].size;
736
        /* mapped? */
737
        if (pci_start == -1) {
738
            continue;
739
        }
740
        /* start address in range ? */
741
        if (guest_start < pci_start || guest_start > pci_end) {
742
            continue;
743
        }
744
        /* end address in range ? */
745
        if (guest_end > pci_end) {
746
            continue;
747
        }
748
        /* passed */
749
        break;
750
    }
751
    PANIC_ON(i == ARRAY_SIZE(regions)); /* finished loop without match */
752

    
753
    switch (pci_region) {
754
    case QXL_RAM_RANGE_INDEX:
755
        virt_start = (intptr_t)qemu_get_ram_ptr(d->vga.vram_offset);
756
        break;
757
    case QXL_VRAM_RANGE_INDEX:
758
        virt_start = (intptr_t)qemu_get_ram_ptr(d->vram_offset);
759
        break;
760
    default:
761
        /* should not happen */
762
        abort();
763
    }
764

    
765
    memslot.slot_id = slot_id;
766
    memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
767
    memslot.virt_start = virt_start + (guest_start - pci_start);
768
    memslot.virt_end   = virt_start + (guest_end   - pci_start);
769
    memslot.addr_delta = memslot.virt_start - delta;
770
    memslot.generation = d->rom->slot_generation = 0;
771
    qxl_rom_set_dirty(d);
772

    
773
    dprint(d, 1, "%s: slot %d: host virt 0x%" PRIx64 " - 0x%" PRIx64 "\n",
774
           __FUNCTION__, memslot.slot_id,
775
           memslot.virt_start, memslot.virt_end);
776

    
777
    d->ssd.worker->add_memslot(d->ssd.worker, &memslot);
778
    d->guest_slots[slot_id].ptr = (void*)memslot.virt_start;
779
    d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
780
    d->guest_slots[slot_id].delta = delta;
781
    d->guest_slots[slot_id].active = 1;
782
}
783

    
784
static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
785
{
786
    dprint(d, 1, "%s: slot %d\n", __FUNCTION__, slot_id);
787
    d->ssd.worker->del_memslot(d->ssd.worker, MEMSLOT_GROUP_HOST, slot_id);
788
    d->guest_slots[slot_id].active = 0;
789
}
790

    
791
static void qxl_reset_memslots(PCIQXLDevice *d)
792
{
793
    dprint(d, 1, "%s:\n", __FUNCTION__);
794
    d->ssd.worker->reset_memslots(d->ssd.worker);
795
    memset(&d->guest_slots, 0, sizeof(d->guest_slots));
796
}
797

    
798
static void qxl_reset_surfaces(PCIQXLDevice *d)
799
{
800
    dprint(d, 1, "%s:\n", __FUNCTION__);
801
    d->mode = QXL_MODE_UNDEFINED;
802
    d->ssd.worker->destroy_surfaces(d->ssd.worker);
803
    memset(&d->guest_surfaces.cmds, 0, sizeof(d->guest_surfaces.cmds));
804
}
805

    
806
/* called from spice server thread context only */
807
void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
808
{
809
    uint64_t phys   = le64_to_cpu(pqxl);
810
    uint32_t slot   = (phys >> (64 -  8)) & 0xff;
811
    uint64_t offset = phys & 0xffffffffffff;
812

    
813
    switch (group_id) {
814
    case MEMSLOT_GROUP_HOST:
815
        return (void*)offset;
816
    case MEMSLOT_GROUP_GUEST:
817
        PANIC_ON(slot > NUM_MEMSLOTS);
818
        PANIC_ON(!qxl->guest_slots[slot].active);
819
        PANIC_ON(offset < qxl->guest_slots[slot].delta);
820
        offset -= qxl->guest_slots[slot].delta;
821
        PANIC_ON(offset > qxl->guest_slots[slot].size)
822
        return qxl->guest_slots[slot].ptr + offset;
823
    default:
824
        PANIC_ON(1);
825
    }
826
}
827

    
828
static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm)
829
{
830
    QXLDevSurfaceCreate surface;
831
    QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
832

    
833
    assert(qxl->mode != QXL_MODE_NATIVE);
834
    qxl_exit_vga_mode(qxl);
835

    
836
    dprint(qxl, 1, "%s: %dx%d\n", __FUNCTION__,
837
           le32_to_cpu(sc->width), le32_to_cpu(sc->height));
838

    
839
    surface.format     = le32_to_cpu(sc->format);
840
    surface.height     = le32_to_cpu(sc->height);
841
    surface.mem        = le64_to_cpu(sc->mem);
842
    surface.position   = le32_to_cpu(sc->position);
843
    surface.stride     = le32_to_cpu(sc->stride);
844
    surface.width      = le32_to_cpu(sc->width);
845
    surface.type       = le32_to_cpu(sc->type);
846
    surface.flags      = le32_to_cpu(sc->flags);
847

    
848
    surface.mouse_mode = true;
849
    surface.group_id   = MEMSLOT_GROUP_GUEST;
850
    if (loadvm) {
851
        surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
852
    }
853

    
854
    qxl->mode = QXL_MODE_NATIVE;
855
    qxl->cmdflags = 0;
856
    qxl->ssd.worker->create_primary_surface(qxl->ssd.worker, 0, &surface);
857

    
858
    /* for local rendering */
859
    qxl_render_resize(qxl);
860
}
861

    
862
static void qxl_destroy_primary(PCIQXLDevice *d)
863
{
864
    if (d->mode == QXL_MODE_UNDEFINED) {
865
        return;
866
    }
867

    
868
    dprint(d, 1, "%s\n", __FUNCTION__);
869

    
870
    d->mode = QXL_MODE_UNDEFINED;
871
    d->ssd.worker->destroy_primary_surface(d->ssd.worker, 0);
872
}
873

    
874
static void qxl_set_mode(PCIQXLDevice *d, int modenr, int loadvm)
875
{
876
    pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
877
    pcibus_t end   = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
878
    QXLMode *mode = d->modes->modes + modenr;
879
    uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
880
    QXLMemSlot slot = {
881
        .mem_start = start,
882
        .mem_end = end
883
    };
884
    QXLSurfaceCreate surface = {
885
        .width      = mode->x_res,
886
        .height     = mode->y_res,
887
        .stride     = -mode->x_res * 4,
888
        .format     = SPICE_SURFACE_FMT_32_xRGB,
889
        .flags      = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
890
        .mouse_mode = true,
891
        .mem        = devmem + d->shadow_rom.draw_area_offset,
892
    };
893

    
894
    dprint(d, 1, "%s: mode %d  [ %d x %d @ %d bpp devmem 0x%lx ]\n", __FUNCTION__,
895
           modenr, mode->x_res, mode->y_res, mode->bits, devmem);
896
    if (!loadvm) {
897
        qxl_hard_reset(d, 0);
898
    }
899

    
900
    d->guest_slots[0].slot = slot;
901
    qxl_add_memslot(d, 0, devmem);
902

    
903
    d->guest_primary.surface = surface;
904
    qxl_create_guest_primary(d, 0);
905

    
906
    d->mode = QXL_MODE_COMPAT;
907
    d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
908
#ifdef QXL_COMMAND_FLAG_COMPAT_16BPP /* new in spice 0.6.1 */
909
    if (mode->bits == 16) {
910
        d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
911
    }
912
#endif
913
    d->shadow_rom.mode = cpu_to_le32(modenr);
914
    d->rom->mode = cpu_to_le32(modenr);
915
    qxl_rom_set_dirty(d);
916
}
917

    
918
static void ioport_write(void *opaque, uint32_t addr, uint32_t val)
919
{
920
    PCIQXLDevice *d = opaque;
921
    uint32_t io_port = addr - d->io_base;
922

    
923
    switch (io_port) {
924
    case QXL_IO_RESET:
925
    case QXL_IO_SET_MODE:
926
    case QXL_IO_MEMSLOT_ADD:
927
    case QXL_IO_MEMSLOT_DEL:
928
    case QXL_IO_CREATE_PRIMARY:
929
        break;
930
    default:
931
        if (d->mode == QXL_MODE_NATIVE || d->mode == QXL_MODE_COMPAT)
932
            break;
933
        dprint(d, 1, "%s: unexpected port 0x%x in vga mode\n", __FUNCTION__, io_port);
934
        return;
935
    }
936

    
937
    switch (io_port) {
938
    case QXL_IO_UPDATE_AREA:
939
    {
940
        QXLRect update = d->ram->update_area;
941
        d->ssd.worker->update_area(d->ssd.worker, d->ram->update_surface,
942
                                   &update, NULL, 0, 0);
943
        break;
944
    }
945
    case QXL_IO_NOTIFY_CMD:
946
        d->ssd.worker->wakeup(d->ssd.worker);
947
        break;
948
    case QXL_IO_NOTIFY_CURSOR:
949
        d->ssd.worker->wakeup(d->ssd.worker);
950
        break;
951
    case QXL_IO_UPDATE_IRQ:
952
        qxl_set_irq(d);
953
        break;
954
    case QXL_IO_NOTIFY_OOM:
955
        if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
956
            break;
957
        }
958
        pthread_yield();
959
        if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
960
            break;
961
        }
962
        d->oom_running = 1;
963
        d->ssd.worker->oom(d->ssd.worker);
964
        d->oom_running = 0;
965
        break;
966
    case QXL_IO_SET_MODE:
967
        dprint(d, 1, "QXL_SET_MODE %d\n", val);
968
        qxl_set_mode(d, val, 0);
969
        break;
970
    case QXL_IO_LOG:
971
        if (d->guestdebug) {
972
            fprintf(stderr, "qxl/guest: %s", d->ram->log_buf);
973
        }
974
        break;
975
    case QXL_IO_RESET:
976
        dprint(d, 1, "QXL_IO_RESET\n");
977
        qxl_hard_reset(d, 0);
978
        break;
979
    case QXL_IO_MEMSLOT_ADD:
980
        PANIC_ON(val >= NUM_MEMSLOTS);
981
        PANIC_ON(d->guest_slots[val].active);
982
        d->guest_slots[val].slot = d->ram->mem_slot;
983
        qxl_add_memslot(d, val, 0);
984
        break;
985
    case QXL_IO_MEMSLOT_DEL:
986
        qxl_del_memslot(d, val);
987
        break;
988
    case QXL_IO_CREATE_PRIMARY:
989
        PANIC_ON(val != 0);
990
        dprint(d, 1, "QXL_IO_CREATE_PRIMARY\n");
991
        d->guest_primary.surface = d->ram->create_surface;
992
        qxl_create_guest_primary(d, 0);
993
        break;
994
    case QXL_IO_DESTROY_PRIMARY:
995
        PANIC_ON(val != 0);
996
        dprint(d, 1, "QXL_IO_DESTROY_PRIMARY\n");
997
        qxl_destroy_primary(d);
998
        break;
999
    case QXL_IO_DESTROY_SURFACE_WAIT:
1000
        d->ssd.worker->destroy_surface_wait(d->ssd.worker, val);
1001
        break;
1002
    case QXL_IO_DESTROY_ALL_SURFACES:
1003
        d->ssd.worker->destroy_surfaces(d->ssd.worker);
1004
        break;
1005
    default:
1006
        fprintf(stderr, "%s: ioport=0x%x, abort()\n", __FUNCTION__, io_port);
1007
        abort();
1008
    }
1009
}
1010

    
1011
static uint32_t ioport_read(void *opaque, uint32_t addr)
1012
{
1013
    PCIQXLDevice *d = opaque;
1014

    
1015
    dprint(d, 1, "%s: unexpected\n", __FUNCTION__);
1016
    return 0xff;
1017
}
1018

    
1019
static void qxl_map(PCIDevice *pci, int region_num,
1020
                    pcibus_t addr, pcibus_t size, int type)
1021
{
1022
    static const char *names[] = {
1023
        [ QXL_IO_RANGE_INDEX ]   = "ioports",
1024
        [ QXL_RAM_RANGE_INDEX ]  = "devram",
1025
        [ QXL_ROM_RANGE_INDEX ]  = "rom",
1026
        [ QXL_VRAM_RANGE_INDEX ] = "vram",
1027
    };
1028
    PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, pci);
1029

    
1030
    dprint(qxl, 1, "%s: bar %d [%s] addr 0x%lx size 0x%lx\n", __FUNCTION__,
1031
            region_num, names[region_num], addr, size);
1032

    
1033
    switch (region_num) {
1034
    case QXL_IO_RANGE_INDEX:
1035
        register_ioport_write(addr, size, 1, ioport_write, pci);
1036
        register_ioport_read(addr, size, 1, ioport_read, pci);
1037
        qxl->io_base = addr;
1038
        break;
1039
    case QXL_RAM_RANGE_INDEX:
1040
        cpu_register_physical_memory(addr, size, qxl->vga.vram_offset | IO_MEM_RAM);
1041
        qxl->vga.map_addr = addr;
1042
        qxl->vga.map_end = addr + size;
1043
        if (qxl->id == 0) {
1044
            vga_dirty_log_start(&qxl->vga);
1045
        }
1046
        break;
1047
    case QXL_ROM_RANGE_INDEX:
1048
        cpu_register_physical_memory(addr, size, qxl->rom_offset | IO_MEM_ROM);
1049
        break;
1050
    case QXL_VRAM_RANGE_INDEX:
1051
        cpu_register_physical_memory(addr, size, qxl->vram_offset | IO_MEM_RAM);
1052
        break;
1053
    }
1054
}
1055

    
1056
static void pipe_read(void *opaque)
1057
{
1058
    PCIQXLDevice *d = opaque;
1059
    char dummy;
1060
    int len;
1061

    
1062
    do {
1063
        len = read(d->pipe[0], &dummy, sizeof(dummy));
1064
    } while (len == sizeof(dummy));
1065
    qxl_set_irq(d);
1066
}
1067

    
1068
/* called from spice server thread context only */
1069
static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1070
{
1071
    uint32_t old_pending;
1072
    uint32_t le_events = cpu_to_le32(events);
1073

    
1074
    assert(d->ssd.running);
1075
    old_pending = __sync_fetch_and_or(&d->ram->int_pending, le_events);
1076
    if ((old_pending & le_events) == le_events) {
1077
        return;
1078
    }
1079
    if (pthread_self() == d->main) {
1080
        qxl_set_irq(d);
1081
    } else {
1082
        if (write(d->pipe[1], d, 1) != 1) {
1083
            dprint(d, 1, "%s: write to pipe failed\n", __FUNCTION__);
1084
        }
1085
    }
1086
}
1087

    
1088
static void init_pipe_signaling(PCIQXLDevice *d)
1089
{
1090
   if (pipe(d->pipe) < 0) {
1091
       dprint(d, 1, "%s: pipe creation failed\n", __FUNCTION__);
1092
       return;
1093
   }
1094
#ifdef CONFIG_IOTHREAD
1095
   fcntl(d->pipe[0], F_SETFL, O_NONBLOCK);
1096
#else
1097
   fcntl(d->pipe[0], F_SETFL, O_NONBLOCK /* | O_ASYNC */);
1098
#endif
1099
   fcntl(d->pipe[1], F_SETFL, O_NONBLOCK);
1100
   fcntl(d->pipe[0], F_SETOWN, getpid());
1101

    
1102
   d->main = pthread_self();
1103
   qemu_set_fd_handler(d->pipe[0], pipe_read, NULL, d);
1104
}
1105

    
1106
/* graphics console */
1107

    
1108
static void qxl_hw_update(void *opaque)
1109
{
1110
    PCIQXLDevice *qxl = opaque;
1111
    VGACommonState *vga = &qxl->vga;
1112

    
1113
    switch (qxl->mode) {
1114
    case QXL_MODE_VGA:
1115
        vga->update(vga);
1116
        break;
1117
    case QXL_MODE_COMPAT:
1118
    case QXL_MODE_NATIVE:
1119
        qxl_render_update(qxl);
1120
        break;
1121
    default:
1122
        break;
1123
    }
1124
}
1125

    
1126
static void qxl_hw_invalidate(void *opaque)
1127
{
1128
    PCIQXLDevice *qxl = opaque;
1129
    VGACommonState *vga = &qxl->vga;
1130

    
1131
    vga->invalidate(vga);
1132
}
1133

    
1134
static void qxl_hw_screen_dump(void *opaque, const char *filename)
1135
{
1136
    PCIQXLDevice *qxl = opaque;
1137
    VGACommonState *vga = &qxl->vga;
1138

    
1139
    switch (qxl->mode) {
1140
    case QXL_MODE_COMPAT:
1141
    case QXL_MODE_NATIVE:
1142
        qxl_render_update(qxl);
1143
        ppm_save(filename, qxl->ssd.ds->surface);
1144
        break;
1145
    case QXL_MODE_VGA:
1146
        vga->screen_dump(vga, filename);
1147
        break;
1148
    default:
1149
        break;
1150
    }
1151
}
1152

    
1153
static void qxl_hw_text_update(void *opaque, console_ch_t *chardata)
1154
{
1155
    PCIQXLDevice *qxl = opaque;
1156
    VGACommonState *vga = &qxl->vga;
1157

    
1158
    if (qxl->mode == QXL_MODE_VGA) {
1159
        vga->text_update(vga, chardata);
1160
        return;
1161
    }
1162
}
1163

    
1164
static void qxl_vm_change_state_handler(void *opaque, int running, int reason)
1165
{
1166
    PCIQXLDevice *qxl = opaque;
1167
    qemu_spice_vm_change_state_handler(&qxl->ssd, running, reason);
1168

    
1169
    if (!running && qxl->mode == QXL_MODE_NATIVE) {
1170
        /* dirty all vram (which holds surfaces) to make sure it is saved */
1171
        /* FIXME #1: should go out during "live" stage */
1172
        /* FIXME #2: we only need to save the areas which are actually used */
1173
        ram_addr_t addr = qxl->vram_offset;
1174
        qxl_set_dirty(addr, addr + qxl->vram_size);
1175
    }
1176
}
1177

    
1178
/* display change listener */
1179

    
1180
static void display_update(struct DisplayState *ds, int x, int y, int w, int h)
1181
{
1182
    if (qxl0->mode == QXL_MODE_VGA) {
1183
        qemu_spice_display_update(&qxl0->ssd, x, y, w, h);
1184
    }
1185
}
1186

    
1187
static void display_resize(struct DisplayState *ds)
1188
{
1189
    if (qxl0->mode == QXL_MODE_VGA) {
1190
        qemu_spice_display_resize(&qxl0->ssd);
1191
    }
1192
}
1193

    
1194
static void display_refresh(struct DisplayState *ds)
1195
{
1196
    if (qxl0->mode == QXL_MODE_VGA) {
1197
        qemu_spice_display_refresh(&qxl0->ssd);
1198
    }
1199
}
1200

    
1201
static DisplayChangeListener display_listener = {
1202
    .dpy_update  = display_update,
1203
    .dpy_resize  = display_resize,
1204
    .dpy_refresh = display_refresh,
1205
};
1206

    
1207
static int qxl_init_common(PCIQXLDevice *qxl)
1208
{
1209
    uint8_t* config = qxl->pci.config;
1210
    uint32_t pci_device_rev;
1211
    uint32_t io_size;
1212

    
1213
    qxl->mode = QXL_MODE_UNDEFINED;
1214
    qxl->generation = 1;
1215
    qxl->num_memslots = NUM_MEMSLOTS;
1216
    qxl->num_surfaces = NUM_SURFACES;
1217

    
1218
    switch (qxl->revision) {
1219
    case 1: /* spice 0.4 -- qxl-1 */
1220
        pci_device_rev = QXL_REVISION_STABLE_V04;
1221
        break;
1222
    case 2: /* spice 0.6 -- qxl-2 */
1223
    default:
1224
        pci_device_rev = QXL_REVISION_STABLE_V06;
1225
        break;
1226
    }
1227

    
1228
    pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
1229
    pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
1230

    
1231
    qxl->rom_size = qxl_rom_size();
1232
    qxl->rom_offset = qemu_ram_alloc(&qxl->pci.qdev, "qxl.vrom", qxl->rom_size);
1233
    init_qxl_rom(qxl);
1234
    init_qxl_ram(qxl);
1235

    
1236
    if (qxl->vram_size < 16 * 1024 * 1024) {
1237
        qxl->vram_size = 16 * 1024 * 1024;
1238
    }
1239
    if (qxl->revision == 1) {
1240
        qxl->vram_size = 4096;
1241
    }
1242
    qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1);
1243
    qxl->vram_offset = qemu_ram_alloc(&qxl->pci.qdev, "qxl.vram", qxl->vram_size);
1244

    
1245
    io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1);
1246
    if (qxl->revision == 1) {
1247
        io_size = 8;
1248
    }
1249

    
1250
    pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
1251
                     io_size, PCI_BASE_ADDRESS_SPACE_IO, qxl_map);
1252

    
1253
    pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
1254
                     qxl->rom_size, PCI_BASE_ADDRESS_SPACE_MEMORY,
1255
                     qxl_map);
1256

    
1257
    pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
1258
                     qxl->vga.vram_size, PCI_BASE_ADDRESS_SPACE_MEMORY,
1259
                     qxl_map);
1260

    
1261
    pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX, qxl->vram_size,
1262
                     PCI_BASE_ADDRESS_SPACE_MEMORY, qxl_map);
1263

    
1264
    qxl->ssd.qxl.base.sif = &qxl_interface.base;
1265
    qxl->ssd.qxl.id = qxl->id;
1266
    qemu_spice_add_interface(&qxl->ssd.qxl.base);
1267
    qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
1268

    
1269
    init_pipe_signaling(qxl);
1270
    qxl_reset_state(qxl);
1271

    
1272
    return 0;
1273
}
1274

    
1275
static int qxl_init_primary(PCIDevice *dev)
1276
{
1277
    PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
1278
    VGACommonState *vga = &qxl->vga;
1279
    ram_addr_t ram_size = msb_mask(qxl->vga.vram_size * 2 - 1);
1280

    
1281
    qxl->id = 0;
1282

    
1283
    if (ram_size < 32 * 1024 * 1024) {
1284
        ram_size = 32 * 1024 * 1024;
1285
    }
1286
    vga_common_init(vga, ram_size);
1287
    vga_init(vga);
1288
    register_ioport_write(0x3c0, 16, 1, qxl_vga_ioport_write, vga);
1289
    register_ioport_write(0x3b4,  2, 1, qxl_vga_ioport_write, vga);
1290
    register_ioport_write(0x3d4,  2, 1, qxl_vga_ioport_write, vga);
1291
    register_ioport_write(0x3ba,  1, 1, qxl_vga_ioport_write, vga);
1292
    register_ioport_write(0x3da,  1, 1, qxl_vga_ioport_write, vga);
1293

    
1294
    vga->ds = graphic_console_init(qxl_hw_update, qxl_hw_invalidate,
1295
                                   qxl_hw_screen_dump, qxl_hw_text_update, qxl);
1296
    qxl->ssd.ds = vga->ds;
1297
    qemu_mutex_init(&qxl->ssd.lock);
1298
    qxl->ssd.mouse_x = -1;
1299
    qxl->ssd.mouse_y = -1;
1300
    qxl->ssd.bufsize = (16 * 1024 * 1024);
1301
    qxl->ssd.buf = qemu_malloc(qxl->ssd.bufsize);
1302

    
1303
    qxl0 = qxl;
1304
    register_displaychangelistener(vga->ds, &display_listener);
1305

    
1306
    return qxl_init_common(qxl);
1307
}
1308

    
1309
static int qxl_init_secondary(PCIDevice *dev)
1310
{
1311
    static int device_id = 1;
1312
    PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
1313
    ram_addr_t ram_size = msb_mask(qxl->vga.vram_size * 2 - 1);
1314

    
1315
    qxl->id = device_id++;
1316

    
1317
    if (ram_size < 16 * 1024 * 1024) {
1318
        ram_size = 16 * 1024 * 1024;
1319
    }
1320
    qxl->vga.vram_size = ram_size;
1321
    qxl->vga.vram_offset = qemu_ram_alloc(&qxl->pci.qdev, "qxl.vgavram",
1322
                                          qxl->vga.vram_size);
1323
    qxl->vga.vram_ptr = qemu_get_ram_ptr(qxl->vga.vram_offset);
1324

    
1325
    return qxl_init_common(qxl);
1326
}
1327

    
1328
static void qxl_pre_save(void *opaque)
1329
{
1330
    PCIQXLDevice* d = opaque;
1331
    uint8_t *ram_start = d->vga.vram_ptr;
1332

    
1333
    dprint(d, 1, "%s:\n", __FUNCTION__);
1334
    if (d->last_release == NULL) {
1335
        d->last_release_offset = 0;
1336
    } else {
1337
        d->last_release_offset = (uint8_t *)d->last_release - ram_start;
1338
    }
1339
    assert(d->last_release_offset < d->vga.vram_size);
1340
}
1341

    
1342
static int qxl_pre_load(void *opaque)
1343
{
1344
    PCIQXLDevice* d = opaque;
1345

    
1346
    dprint(d, 1, "%s: start\n", __FUNCTION__);
1347
    qxl_hard_reset(d, 1);
1348
    qxl_exit_vga_mode(d);
1349
    dprint(d, 1, "%s: done\n", __FUNCTION__);
1350
    return 0;
1351
}
1352

    
1353
static int qxl_post_load(void *opaque, int version)
1354
{
1355
    PCIQXLDevice* d = opaque;
1356
    uint8_t *ram_start = d->vga.vram_ptr;
1357
    QXLCommandExt *cmds;
1358
    int in, out, i, newmode;
1359

    
1360
    dprint(d, 1, "%s: start\n", __FUNCTION__);
1361

    
1362
    assert(d->last_release_offset < d->vga.vram_size);
1363
    if (d->last_release_offset == 0) {
1364
        d->last_release = NULL;
1365
    } else {
1366
        d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
1367
    }
1368

    
1369
    d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
1370

    
1371
    dprint(d, 1, "%s: restore mode\n", __FUNCTION__);
1372
    newmode = d->mode;
1373
    d->mode = QXL_MODE_UNDEFINED;
1374
    switch (newmode) {
1375
    case QXL_MODE_UNDEFINED:
1376
        break;
1377
    case QXL_MODE_VGA:
1378
        qxl_enter_vga_mode(d);
1379
        break;
1380
    case QXL_MODE_NATIVE:
1381
        for (i = 0; i < NUM_MEMSLOTS; i++) {
1382
            if (!d->guest_slots[i].active) {
1383
                continue;
1384
            }
1385
            qxl_add_memslot(d, i, 0);
1386
        }
1387
        qxl_create_guest_primary(d, 1);
1388

    
1389
        /* replay surface-create and cursor-set commands */
1390
        cmds = qemu_mallocz(sizeof(QXLCommandExt) * (NUM_SURFACES + 1));
1391
        for (in = 0, out = 0; in < NUM_SURFACES; in++) {
1392
            if (d->guest_surfaces.cmds[in] == 0) {
1393
                continue;
1394
            }
1395
            cmds[out].cmd.data = d->guest_surfaces.cmds[in];
1396
            cmds[out].cmd.type = QXL_CMD_SURFACE;
1397
            cmds[out].group_id = MEMSLOT_GROUP_GUEST;
1398
            out++;
1399
        }
1400
        cmds[out].cmd.data = d->guest_cursor;
1401
        cmds[out].cmd.type = QXL_CMD_CURSOR;
1402
        cmds[out].group_id = MEMSLOT_GROUP_GUEST;
1403
        out++;
1404
        d->ssd.worker->loadvm_commands(d->ssd.worker, cmds, out);
1405
        qemu_free(cmds);
1406

    
1407
        break;
1408
    case QXL_MODE_COMPAT:
1409
        qxl_set_mode(d, d->shadow_rom.mode, 1);
1410
        break;
1411
    }
1412
    dprint(d, 1, "%s: done\n", __FUNCTION__);
1413

    
1414
    return 0;
1415
}
1416

    
1417
#define QXL_SAVE_VERSION 21
1418

    
1419
static VMStateDescription qxl_memslot = {
1420
    .name               = "qxl-memslot",
1421
    .version_id         = QXL_SAVE_VERSION,
1422
    .minimum_version_id = QXL_SAVE_VERSION,
1423
    .fields = (VMStateField[]) {
1424
        VMSTATE_UINT64(slot.mem_start, struct guest_slots),
1425
        VMSTATE_UINT64(slot.mem_end,   struct guest_slots),
1426
        VMSTATE_UINT32(active,         struct guest_slots),
1427
        VMSTATE_END_OF_LIST()
1428
    }
1429
};
1430

    
1431
static VMStateDescription qxl_surface = {
1432
    .name               = "qxl-surface",
1433
    .version_id         = QXL_SAVE_VERSION,
1434
    .minimum_version_id = QXL_SAVE_VERSION,
1435
    .fields = (VMStateField[]) {
1436
        VMSTATE_UINT32(width,      QXLSurfaceCreate),
1437
        VMSTATE_UINT32(height,     QXLSurfaceCreate),
1438
        VMSTATE_INT32(stride,      QXLSurfaceCreate),
1439
        VMSTATE_UINT32(format,     QXLSurfaceCreate),
1440
        VMSTATE_UINT32(position,   QXLSurfaceCreate),
1441
        VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
1442
        VMSTATE_UINT32(flags,      QXLSurfaceCreate),
1443
        VMSTATE_UINT32(type,       QXLSurfaceCreate),
1444
        VMSTATE_UINT64(mem,        QXLSurfaceCreate),
1445
        VMSTATE_END_OF_LIST()
1446
    }
1447
};
1448

    
1449
static VMStateDescription qxl_vmstate = {
1450
    .name               = "qxl",
1451
    .version_id         = QXL_SAVE_VERSION,
1452
    .minimum_version_id = QXL_SAVE_VERSION,
1453
    .pre_save           = qxl_pre_save,
1454
    .pre_load           = qxl_pre_load,
1455
    .post_load          = qxl_post_load,
1456
    .fields = (VMStateField []) {
1457
        VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
1458
        VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
1459
        VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
1460
        VMSTATE_UINT32(num_free_res, PCIQXLDevice),
1461
        VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
1462
        VMSTATE_UINT32(mode, PCIQXLDevice),
1463
        VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
1464
        VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice),
1465
        VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
1466
                             qxl_memslot, struct guest_slots),
1467
        VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
1468
                       qxl_surface, QXLSurfaceCreate),
1469
        VMSTATE_INT32_EQUAL(num_surfaces, PCIQXLDevice),
1470
        VMSTATE_ARRAY(guest_surfaces.cmds, PCIQXLDevice, NUM_SURFACES, 0,
1471
                      vmstate_info_uint64, uint64_t),
1472
        VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
1473
        VMSTATE_END_OF_LIST()
1474
    },
1475
};
1476

    
1477
static PCIDeviceInfo qxl_info_primary = {
1478
    .qdev.name    = "qxl-vga",
1479
    .qdev.desc    = "Spice QXL GPU (primary, vga compatible)",
1480
    .qdev.size    = sizeof(PCIQXLDevice),
1481
    .qdev.reset   = qxl_reset_handler,
1482
    .qdev.vmsd    = &qxl_vmstate,
1483
    .no_hotplug   = 1,
1484
    .init         = qxl_init_primary,
1485
    .config_write = qxl_write_config,
1486
    .romfile      = "vgabios-qxl.bin",
1487
    .vendor_id    = REDHAT_PCI_VENDOR_ID,
1488
    .device_id    = QXL_DEVICE_ID_STABLE,
1489
    .class_id     = PCI_CLASS_DISPLAY_VGA,
1490
    .qdev.props = (Property[]) {
1491
        DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 64 * 1024 * 1024),
1492
        DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram_size, 64 * 1024 * 1024),
1493
        DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision, 2),
1494
        DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
1495
        DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
1496
        DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
1497
        DEFINE_PROP_END_OF_LIST(),
1498
    }
1499
};
1500

    
1501
static PCIDeviceInfo qxl_info_secondary = {
1502
    .qdev.name    = "qxl",
1503
    .qdev.desc    = "Spice QXL GPU (secondary)",
1504
    .qdev.size    = sizeof(PCIQXLDevice),
1505
    .qdev.reset   = qxl_reset_handler,
1506
    .qdev.vmsd    = &qxl_vmstate,
1507
    .init         = qxl_init_secondary,
1508
    .vendor_id    = REDHAT_PCI_VENDOR_ID,
1509
    .device_id    = QXL_DEVICE_ID_STABLE,
1510
    .class_id     = PCI_CLASS_DISPLAY_OTHER,
1511
    .qdev.props = (Property[]) {
1512
        DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 64 * 1024 * 1024),
1513
        DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram_size, 64 * 1024 * 1024),
1514
        DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision, 2),
1515
        DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
1516
        DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
1517
        DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
1518
        DEFINE_PROP_END_OF_LIST(),
1519
    }
1520
};
1521

    
1522
static void qxl_register(void)
1523
{
1524
    pci_qdev_register(&qxl_info_primary);
1525
    pci_qdev_register(&qxl_info_secondary);
1526
}
1527

    
1528
device_init(qxl_register);