root / hw / acpi.c @ 6407f373
History | View | Annotate | Download (22.2 kB)
1 | 6515b203 | bellard | /*
|
---|---|---|---|
2 | 6515b203 | bellard | * ACPI implementation
|
3 | 5fafdf24 | ths | *
|
4 | 6515b203 | bellard | * Copyright (c) 2006 Fabrice Bellard
|
5 | 5fafdf24 | ths | *
|
6 | 6515b203 | bellard | * This library is free software; you can redistribute it and/or
|
7 | 6515b203 | bellard | * modify it under the terms of the GNU Lesser General Public
|
8 | 6515b203 | bellard | * License version 2 as published by the Free Software Foundation.
|
9 | 6515b203 | bellard | *
|
10 | 6515b203 | bellard | * This library is distributed in the hope that it will be useful,
|
11 | 6515b203 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
12 | 6515b203 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
13 | 6515b203 | bellard | * Lesser General Public License for more details.
|
14 | 6515b203 | bellard | *
|
15 | 6515b203 | bellard | * You should have received a copy of the GNU Lesser General Public
|
16 | 6515b203 | bellard | * License along with this library; if not, write to the Free Software
|
17 | fad6cb1a | aurel32 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
|
18 | 6515b203 | bellard | */
|
19 | 87ecb68b | pbrook | #include "hw.h" |
20 | 87ecb68b | pbrook | #include "pc.h" |
21 | 87ecb68b | pbrook | #include "pci.h" |
22 | 87ecb68b | pbrook | #include "qemu-timer.h" |
23 | 87ecb68b | pbrook | #include "sysemu.h" |
24 | 87ecb68b | pbrook | #include "i2c.h" |
25 | 87ecb68b | pbrook | #include "smbus.h" |
26 | 7ba1e619 | aliguori | #include "kvm.h" |
27 | 6515b203 | bellard | |
28 | 6515b203 | bellard | //#define DEBUG
|
29 | 6515b203 | bellard | |
30 | 6515b203 | bellard | /* i82731AB (PIIX4) compatible power management function */
|
31 | 6515b203 | bellard | #define PM_FREQ 3579545 |
32 | 6515b203 | bellard | |
33 | 6515b203 | bellard | #define ACPI_DBG_IO_ADDR 0xb044 |
34 | 6515b203 | bellard | |
35 | 6515b203 | bellard | typedef struct PIIX4PMState { |
36 | 6515b203 | bellard | PCIDevice dev; |
37 | 6515b203 | bellard | uint16_t pmsts; |
38 | 6515b203 | bellard | uint16_t pmen; |
39 | 6515b203 | bellard | uint16_t pmcntrl; |
40 | ab1e34ad | bellard | uint8_t apmc; |
41 | ab1e34ad | bellard | uint8_t apms; |
42 | 6515b203 | bellard | QEMUTimer *tmr_timer; |
43 | 6515b203 | bellard | int64_t tmr_overflow_time; |
44 | 0ff596d0 | pbrook | i2c_bus *smbus; |
45 | 3fffc223 | ths | uint8_t smb_stat; |
46 | 3fffc223 | ths | uint8_t smb_ctl; |
47 | 3fffc223 | ths | uint8_t smb_cmd; |
48 | 3fffc223 | ths | uint8_t smb_addr; |
49 | 3fffc223 | ths | uint8_t smb_data0; |
50 | 3fffc223 | ths | uint8_t smb_data1; |
51 | 3fffc223 | ths | uint8_t smb_data[32];
|
52 | 3fffc223 | ths | uint8_t smb_index; |
53 | cf7a2fe2 | aurel32 | qemu_irq irq; |
54 | 6515b203 | bellard | } PIIX4PMState; |
55 | 6515b203 | bellard | |
56 | 0bacd130 | aliguori | #define RSM_STS (1 << 15) |
57 | 0bacd130 | aliguori | #define PWRBTN_STS (1 << 8) |
58 | 6515b203 | bellard | #define RTC_EN (1 << 10) |
59 | 6515b203 | bellard | #define PWRBTN_EN (1 << 8) |
60 | 6515b203 | bellard | #define GBL_EN (1 << 5) |
61 | 6515b203 | bellard | #define TMROF_EN (1 << 0) |
62 | 6515b203 | bellard | |
63 | 6515b203 | bellard | #define SCI_EN (1 << 0) |
64 | 6515b203 | bellard | |
65 | 6515b203 | bellard | #define SUS_EN (1 << 13) |
66 | 6515b203 | bellard | |
67 | 24bc1cbc | ths | #define ACPI_ENABLE 0xf1 |
68 | 24bc1cbc | ths | #define ACPI_DISABLE 0xf0 |
69 | 24bc1cbc | ths | |
70 | 3fffc223 | ths | #define SMBHSTSTS 0x00 |
71 | 3fffc223 | ths | #define SMBHSTCNT 0x02 |
72 | 3fffc223 | ths | #define SMBHSTCMD 0x03 |
73 | 3fffc223 | ths | #define SMBHSTADD 0x04 |
74 | 3fffc223 | ths | #define SMBHSTDAT0 0x05 |
75 | 3fffc223 | ths | #define SMBHSTDAT1 0x06 |
76 | 3fffc223 | ths | #define SMBBLKDAT 0x07 |
77 | 3fffc223 | ths | |
78 | 9669d3c5 | aurel32 | static PIIX4PMState *pm_state;
|
79 | cf7a2fe2 | aurel32 | |
80 | 6515b203 | bellard | static uint32_t get_pmtmr(PIIX4PMState *s)
|
81 | 6515b203 | bellard | { |
82 | 7546c016 | balrog | uint32_t d; |
83 | 7546c016 | balrog | d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec); |
84 | 7546c016 | balrog | return d & 0xffffff; |
85 | 6515b203 | bellard | } |
86 | 6515b203 | bellard | |
87 | 6515b203 | bellard | static int get_pmsts(PIIX4PMState *s) |
88 | 6515b203 | bellard | { |
89 | 7546c016 | balrog | int64_t d; |
90 | 7546c016 | balrog | int pmsts;
|
91 | 7546c016 | balrog | pmsts = s->pmsts; |
92 | 7546c016 | balrog | d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec); |
93 | 7546c016 | balrog | if (d >= s->tmr_overflow_time)
|
94 | 7546c016 | balrog | s->pmsts |= TMROF_EN; |
95 | 055479fe | aliguori | return s->pmsts;
|
96 | 6515b203 | bellard | } |
97 | 6515b203 | bellard | |
98 | 6515b203 | bellard | static void pm_update_sci(PIIX4PMState *s) |
99 | 6515b203 | bellard | { |
100 | 7546c016 | balrog | int sci_level, pmsts;
|
101 | 7546c016 | balrog | int64_t expire_time; |
102 | 7546c016 | balrog | |
103 | 7546c016 | balrog | pmsts = get_pmsts(s); |
104 | 7546c016 | balrog | sci_level = (((pmsts & s->pmen) & |
105 | 7546c016 | balrog | (RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
|
106 | 7546c016 | balrog | qemu_set_irq(s->irq, sci_level); |
107 | 7546c016 | balrog | /* schedule a timer interruption if needed */
|
108 | 7546c016 | balrog | if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
|
109 | 7546c016 | balrog | expire_time = muldiv64(s->tmr_overflow_time, ticks_per_sec, PM_FREQ); |
110 | 7546c016 | balrog | qemu_mod_timer(s->tmr_timer, expire_time); |
111 | 7546c016 | balrog | } else {
|
112 | 7546c016 | balrog | qemu_del_timer(s->tmr_timer); |
113 | 7546c016 | balrog | } |
114 | 6515b203 | bellard | } |
115 | 6515b203 | bellard | |
116 | 6515b203 | bellard | static void pm_tmr_timer(void *opaque) |
117 | 6515b203 | bellard | { |
118 | 6515b203 | bellard | PIIX4PMState *s = opaque; |
119 | 7546c016 | balrog | pm_update_sci(s); |
120 | 6515b203 | bellard | } |
121 | 6515b203 | bellard | |
122 | 6515b203 | bellard | static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val) |
123 | 6515b203 | bellard | { |
124 | 6515b203 | bellard | PIIX4PMState *s = opaque; |
125 | 6515b203 | bellard | addr &= 0x3f;
|
126 | 6515b203 | bellard | switch(addr) {
|
127 | 6515b203 | bellard | case 0x00: |
128 | 7546c016 | balrog | { |
129 | 7546c016 | balrog | int64_t d; |
130 | 7546c016 | balrog | int pmsts;
|
131 | 7546c016 | balrog | pmsts = get_pmsts(s); |
132 | 7546c016 | balrog | if (pmsts & val & TMROF_EN) {
|
133 | 7546c016 | balrog | /* if TMRSTS is reset, then compute the new overflow time */
|
134 | 7546c016 | balrog | d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec); |
135 | 7546c016 | balrog | s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL; |
136 | 7546c016 | balrog | } |
137 | 7546c016 | balrog | s->pmsts &= ~val; |
138 | 7546c016 | balrog | pm_update_sci(s); |
139 | 7546c016 | balrog | } |
140 | 6515b203 | bellard | break;
|
141 | 6515b203 | bellard | case 0x02: |
142 | 6515b203 | bellard | s->pmen = val; |
143 | 6515b203 | bellard | pm_update_sci(s); |
144 | 6515b203 | bellard | break;
|
145 | 6515b203 | bellard | case 0x04: |
146 | 6515b203 | bellard | { |
147 | 6515b203 | bellard | int sus_typ;
|
148 | 6515b203 | bellard | s->pmcntrl = val & ~(SUS_EN); |
149 | 6515b203 | bellard | if (val & SUS_EN) {
|
150 | 6515b203 | bellard | /* change suspend type */
|
151 | f99ed40a | aurel32 | sus_typ = (val >> 10) & 7; |
152 | 6515b203 | bellard | switch(sus_typ) {
|
153 | 6515b203 | bellard | case 0: /* soft power off */ |
154 | 6515b203 | bellard | qemu_system_shutdown_request(); |
155 | 6515b203 | bellard | break;
|
156 | 0bacd130 | aliguori | case 1: |
157 | 0bacd130 | aliguori | /* RSM_STS should be set on resume. Pretend that resume
|
158 | 0bacd130 | aliguori | was caused by power button */
|
159 | 0bacd130 | aliguori | s->pmsts |= (RSM_STS | PWRBTN_STS); |
160 | 0bacd130 | aliguori | qemu_system_reset_request(); |
161 | 0bacd130 | aliguori | #if defined(TARGET_I386)
|
162 | 0bacd130 | aliguori | cmos_set_s3_resume(); |
163 | 0bacd130 | aliguori | #endif
|
164 | 6515b203 | bellard | default:
|
165 | 6515b203 | bellard | break;
|
166 | 6515b203 | bellard | } |
167 | 6515b203 | bellard | } |
168 | 6515b203 | bellard | } |
169 | 6515b203 | bellard | break;
|
170 | 6515b203 | bellard | default:
|
171 | 6515b203 | bellard | break;
|
172 | 6515b203 | bellard | } |
173 | 6515b203 | bellard | #ifdef DEBUG
|
174 | 6515b203 | bellard | printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
|
175 | 6515b203 | bellard | #endif
|
176 | 6515b203 | bellard | } |
177 | 6515b203 | bellard | |
178 | 6515b203 | bellard | static uint32_t pm_ioport_readw(void *opaque, uint32_t addr) |
179 | 6515b203 | bellard | { |
180 | 6515b203 | bellard | PIIX4PMState *s = opaque; |
181 | 6515b203 | bellard | uint32_t val; |
182 | 6515b203 | bellard | |
183 | 6515b203 | bellard | addr &= 0x3f;
|
184 | 6515b203 | bellard | switch(addr) {
|
185 | 6515b203 | bellard | case 0x00: |
186 | 6515b203 | bellard | val = get_pmsts(s); |
187 | 6515b203 | bellard | break;
|
188 | 6515b203 | bellard | case 0x02: |
189 | 6515b203 | bellard | val = s->pmen; |
190 | 6515b203 | bellard | break;
|
191 | 6515b203 | bellard | case 0x04: |
192 | 6515b203 | bellard | val = s->pmcntrl; |
193 | 6515b203 | bellard | break;
|
194 | 6515b203 | bellard | default:
|
195 | 6515b203 | bellard | val = 0;
|
196 | 6515b203 | bellard | break;
|
197 | 6515b203 | bellard | } |
198 | 6515b203 | bellard | #ifdef DEBUG
|
199 | 6515b203 | bellard | printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
|
200 | 6515b203 | bellard | #endif
|
201 | 6515b203 | bellard | return val;
|
202 | 6515b203 | bellard | } |
203 | 6515b203 | bellard | |
204 | 6515b203 | bellard | static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
205 | 6515b203 | bellard | { |
206 | 6515b203 | bellard | // PIIX4PMState *s = opaque;
|
207 | 6515b203 | bellard | addr &= 0x3f;
|
208 | 6515b203 | bellard | #ifdef DEBUG
|
209 | 6515b203 | bellard | printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
|
210 | 6515b203 | bellard | #endif
|
211 | 6515b203 | bellard | } |
212 | 6515b203 | bellard | |
213 | 6515b203 | bellard | static uint32_t pm_ioport_readl(void *opaque, uint32_t addr) |
214 | 6515b203 | bellard | { |
215 | 6515b203 | bellard | PIIX4PMState *s = opaque; |
216 | 6515b203 | bellard | uint32_t val; |
217 | 6515b203 | bellard | |
218 | 6515b203 | bellard | addr &= 0x3f;
|
219 | 6515b203 | bellard | switch(addr) {
|
220 | 6515b203 | bellard | case 0x08: |
221 | 6515b203 | bellard | val = get_pmtmr(s); |
222 | 6515b203 | bellard | break;
|
223 | 6515b203 | bellard | default:
|
224 | 6515b203 | bellard | val = 0;
|
225 | 6515b203 | bellard | break;
|
226 | 6515b203 | bellard | } |
227 | 6515b203 | bellard | #ifdef DEBUG
|
228 | 6515b203 | bellard | printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
|
229 | 6515b203 | bellard | #endif
|
230 | 6515b203 | bellard | return val;
|
231 | 6515b203 | bellard | } |
232 | 6515b203 | bellard | |
233 | ab1e34ad | bellard | static void pm_smi_writeb(void *opaque, uint32_t addr, uint32_t val) |
234 | 6515b203 | bellard | { |
235 | 6515b203 | bellard | PIIX4PMState *s = opaque; |
236 | ab1e34ad | bellard | addr &= 1;
|
237 | 6515b203 | bellard | #ifdef DEBUG
|
238 | ab1e34ad | bellard | printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr, val);
|
239 | 6515b203 | bellard | #endif
|
240 | ab1e34ad | bellard | if (addr == 0) { |
241 | ab1e34ad | bellard | s->apmc = val; |
242 | 24bc1cbc | ths | |
243 | 24bc1cbc | ths | /* ACPI specs 3.0, 4.7.2.5 */
|
244 | 24bc1cbc | ths | if (val == ACPI_ENABLE) {
|
245 | 24bc1cbc | ths | s->pmcntrl |= SCI_EN; |
246 | 24bc1cbc | ths | } else if (val == ACPI_DISABLE) { |
247 | 24bc1cbc | ths | s->pmcntrl &= ~SCI_EN; |
248 | 24bc1cbc | ths | } |
249 | 24bc1cbc | ths | |
250 | 47d02f6d | bellard | if (s->dev.config[0x5b] & (1 << 1)) { |
251 | 47d02f6d | bellard | cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI); |
252 | ab1e34ad | bellard | } |
253 | ab1e34ad | bellard | } else {
|
254 | ab1e34ad | bellard | s->apms = val; |
255 | 6515b203 | bellard | } |
256 | 6515b203 | bellard | } |
257 | 6515b203 | bellard | |
258 | ab1e34ad | bellard | static uint32_t pm_smi_readb(void *opaque, uint32_t addr) |
259 | ab1e34ad | bellard | { |
260 | ab1e34ad | bellard | PIIX4PMState *s = opaque; |
261 | ab1e34ad | bellard | uint32_t val; |
262 | 3b46e624 | ths | |
263 | ab1e34ad | bellard | addr &= 1;
|
264 | ab1e34ad | bellard | if (addr == 0) { |
265 | ab1e34ad | bellard | val = s->apmc; |
266 | ab1e34ad | bellard | } else {
|
267 | ab1e34ad | bellard | val = s->apms; |
268 | ab1e34ad | bellard | } |
269 | ab1e34ad | bellard | #ifdef DEBUG
|
270 | ab1e34ad | bellard | printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr, val);
|
271 | ab1e34ad | bellard | #endif
|
272 | ab1e34ad | bellard | return val;
|
273 | ab1e34ad | bellard | } |
274 | ab1e34ad | bellard | |
275 | 6515b203 | bellard | static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val) |
276 | 6515b203 | bellard | { |
277 | 6515b203 | bellard | #if defined(DEBUG)
|
278 | 6515b203 | bellard | printf("ACPI: DBG: 0x%08x\n", val);
|
279 | 6515b203 | bellard | #endif
|
280 | 6515b203 | bellard | } |
281 | 6515b203 | bellard | |
282 | 3fffc223 | ths | static void smb_transaction(PIIX4PMState *s) |
283 | 3fffc223 | ths | { |
284 | 3fffc223 | ths | uint8_t prot = (s->smb_ctl >> 2) & 0x07; |
285 | 3fffc223 | ths | uint8_t read = s->smb_addr & 0x01;
|
286 | 3fffc223 | ths | uint8_t cmd = s->smb_cmd; |
287 | 3fffc223 | ths | uint8_t addr = s->smb_addr >> 1;
|
288 | 0ff596d0 | pbrook | i2c_bus *bus = s->smbus; |
289 | 3fffc223 | ths | |
290 | 3fffc223 | ths | #ifdef DEBUG
|
291 | 3fffc223 | ths | printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
|
292 | 3fffc223 | ths | #endif
|
293 | 3fffc223 | ths | switch(prot) {
|
294 | 3fffc223 | ths | case 0x0: |
295 | 0ff596d0 | pbrook | smbus_quick_command(bus, addr, read); |
296 | 3fffc223 | ths | break;
|
297 | 3fffc223 | ths | case 0x1: |
298 | 3fffc223 | ths | if (read) {
|
299 | 0ff596d0 | pbrook | s->smb_data0 = smbus_receive_byte(bus, addr); |
300 | 0ff596d0 | pbrook | } else {
|
301 | 0ff596d0 | pbrook | smbus_send_byte(bus, addr, cmd); |
302 | 3fffc223 | ths | } |
303 | 3fffc223 | ths | break;
|
304 | 3fffc223 | ths | case 0x2: |
305 | 3fffc223 | ths | if (read) {
|
306 | 0ff596d0 | pbrook | s->smb_data0 = smbus_read_byte(bus, addr, cmd); |
307 | 0ff596d0 | pbrook | } else {
|
308 | 0ff596d0 | pbrook | smbus_write_byte(bus, addr, cmd, s->smb_data0); |
309 | 3fffc223 | ths | } |
310 | 3fffc223 | ths | break;
|
311 | 3fffc223 | ths | case 0x3: |
312 | 3fffc223 | ths | if (read) {
|
313 | 3fffc223 | ths | uint16_t val; |
314 | 0ff596d0 | pbrook | val = smbus_read_word(bus, addr, cmd); |
315 | 3fffc223 | ths | s->smb_data0 = val; |
316 | 3fffc223 | ths | s->smb_data1 = val >> 8;
|
317 | 0ff596d0 | pbrook | } else {
|
318 | 0ff596d0 | pbrook | smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) | s->smb_data0);
|
319 | 3fffc223 | ths | } |
320 | 3fffc223 | ths | break;
|
321 | 3fffc223 | ths | case 0x5: |
322 | 3fffc223 | ths | if (read) {
|
323 | 0ff596d0 | pbrook | s->smb_data0 = smbus_read_block(bus, addr, cmd, s->smb_data); |
324 | 0ff596d0 | pbrook | } else {
|
325 | 0ff596d0 | pbrook | smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0); |
326 | 3fffc223 | ths | } |
327 | 3fffc223 | ths | break;
|
328 | 3fffc223 | ths | default:
|
329 | 3fffc223 | ths | goto error;
|
330 | 3fffc223 | ths | } |
331 | 3fffc223 | ths | return;
|
332 | 3fffc223 | ths | |
333 | 3fffc223 | ths | error:
|
334 | 3fffc223 | ths | s->smb_stat |= 0x04;
|
335 | 3fffc223 | ths | } |
336 | 3fffc223 | ths | |
337 | 3fffc223 | ths | static void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) |
338 | 3fffc223 | ths | { |
339 | 3fffc223 | ths | PIIX4PMState *s = opaque; |
340 | 3fffc223 | ths | addr &= 0x3f;
|
341 | 3fffc223 | ths | #ifdef DEBUG
|
342 | 3fffc223 | ths | printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
|
343 | 3fffc223 | ths | #endif
|
344 | 3fffc223 | ths | switch(addr) {
|
345 | 3fffc223 | ths | case SMBHSTSTS:
|
346 | 3fffc223 | ths | s->smb_stat = 0;
|
347 | 3fffc223 | ths | s->smb_index = 0;
|
348 | 3fffc223 | ths | break;
|
349 | 3fffc223 | ths | case SMBHSTCNT:
|
350 | 3fffc223 | ths | s->smb_ctl = val; |
351 | 3fffc223 | ths | if (val & 0x40) |
352 | 3fffc223 | ths | smb_transaction(s); |
353 | 3fffc223 | ths | break;
|
354 | 3fffc223 | ths | case SMBHSTCMD:
|
355 | 3fffc223 | ths | s->smb_cmd = val; |
356 | 3fffc223 | ths | break;
|
357 | 3fffc223 | ths | case SMBHSTADD:
|
358 | 3fffc223 | ths | s->smb_addr = val; |
359 | 3fffc223 | ths | break;
|
360 | 3fffc223 | ths | case SMBHSTDAT0:
|
361 | 3fffc223 | ths | s->smb_data0 = val; |
362 | 3fffc223 | ths | break;
|
363 | 3fffc223 | ths | case SMBHSTDAT1:
|
364 | 3fffc223 | ths | s->smb_data1 = val; |
365 | 3fffc223 | ths | break;
|
366 | 3fffc223 | ths | case SMBBLKDAT:
|
367 | 3fffc223 | ths | s->smb_data[s->smb_index++] = val; |
368 | 3fffc223 | ths | if (s->smb_index > 31) |
369 | 3fffc223 | ths | s->smb_index = 0;
|
370 | 3fffc223 | ths | break;
|
371 | 3fffc223 | ths | default:
|
372 | 3fffc223 | ths | break;
|
373 | 3fffc223 | ths | } |
374 | 3fffc223 | ths | } |
375 | 3fffc223 | ths | |
376 | 3fffc223 | ths | static uint32_t smb_ioport_readb(void *opaque, uint32_t addr) |
377 | 3fffc223 | ths | { |
378 | 3fffc223 | ths | PIIX4PMState *s = opaque; |
379 | 3fffc223 | ths | uint32_t val; |
380 | 3fffc223 | ths | |
381 | 3fffc223 | ths | addr &= 0x3f;
|
382 | 3fffc223 | ths | switch(addr) {
|
383 | 3fffc223 | ths | case SMBHSTSTS:
|
384 | 3fffc223 | ths | val = s->smb_stat; |
385 | 3fffc223 | ths | break;
|
386 | 3fffc223 | ths | case SMBHSTCNT:
|
387 | 3fffc223 | ths | s->smb_index = 0;
|
388 | 3fffc223 | ths | val = s->smb_ctl & 0x1f;
|
389 | 3fffc223 | ths | break;
|
390 | 3fffc223 | ths | case SMBHSTCMD:
|
391 | 3fffc223 | ths | val = s->smb_cmd; |
392 | 3fffc223 | ths | break;
|
393 | 3fffc223 | ths | case SMBHSTADD:
|
394 | 3fffc223 | ths | val = s->smb_addr; |
395 | 3fffc223 | ths | break;
|
396 | 3fffc223 | ths | case SMBHSTDAT0:
|
397 | 3fffc223 | ths | val = s->smb_data0; |
398 | 3fffc223 | ths | break;
|
399 | 3fffc223 | ths | case SMBHSTDAT1:
|
400 | 3fffc223 | ths | val = s->smb_data1; |
401 | 3fffc223 | ths | break;
|
402 | 3fffc223 | ths | case SMBBLKDAT:
|
403 | 3fffc223 | ths | val = s->smb_data[s->smb_index++]; |
404 | 3fffc223 | ths | if (s->smb_index > 31) |
405 | 3fffc223 | ths | s->smb_index = 0;
|
406 | 3fffc223 | ths | break;
|
407 | 3fffc223 | ths | default:
|
408 | 3fffc223 | ths | val = 0;
|
409 | 3fffc223 | ths | break;
|
410 | 3fffc223 | ths | } |
411 | 3fffc223 | ths | #ifdef DEBUG
|
412 | 3fffc223 | ths | printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
|
413 | 3fffc223 | ths | #endif
|
414 | 3fffc223 | ths | return val;
|
415 | 3fffc223 | ths | } |
416 | 3fffc223 | ths | |
417 | ab1e34ad | bellard | static void pm_io_space_update(PIIX4PMState *s) |
418 | ab1e34ad | bellard | { |
419 | ab1e34ad | bellard | uint32_t pm_io_base; |
420 | ab1e34ad | bellard | |
421 | ab1e34ad | bellard | if (s->dev.config[0x80] & 1) { |
422 | ab1e34ad | bellard | pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
|
423 | bf367b54 | ths | pm_io_base &= 0xffc0;
|
424 | ab1e34ad | bellard | |
425 | ab1e34ad | bellard | /* XXX: need to improve memory and ioport allocation */
|
426 | ab1e34ad | bellard | #if defined(DEBUG)
|
427 | ab1e34ad | bellard | printf("PM: mapping to 0x%x\n", pm_io_base);
|
428 | ab1e34ad | bellard | #endif
|
429 | ab1e34ad | bellard | register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s); |
430 | ab1e34ad | bellard | register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s); |
431 | ab1e34ad | bellard | register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s); |
432 | ab1e34ad | bellard | register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s); |
433 | ab1e34ad | bellard | } |
434 | ab1e34ad | bellard | } |
435 | ab1e34ad | bellard | |
436 | 5fafdf24 | ths | static void pm_write_config(PCIDevice *d, |
437 | ab1e34ad | bellard | uint32_t address, uint32_t val, int len)
|
438 | ab1e34ad | bellard | { |
439 | ab1e34ad | bellard | pci_default_write_config(d, address, val, len); |
440 | ab1e34ad | bellard | if (address == 0x80) |
441 | ab1e34ad | bellard | pm_io_space_update((PIIX4PMState *)d); |
442 | ab1e34ad | bellard | } |
443 | ab1e34ad | bellard | |
444 | ab1e34ad | bellard | static void pm_save(QEMUFile* f,void *opaque) |
445 | ab1e34ad | bellard | { |
446 | ab1e34ad | bellard | PIIX4PMState *s = opaque; |
447 | ab1e34ad | bellard | |
448 | ab1e34ad | bellard | pci_device_save(&s->dev, f); |
449 | ab1e34ad | bellard | |
450 | ab1e34ad | bellard | qemu_put_be16s(f, &s->pmsts); |
451 | ab1e34ad | bellard | qemu_put_be16s(f, &s->pmen); |
452 | ab1e34ad | bellard | qemu_put_be16s(f, &s->pmcntrl); |
453 | ab1e34ad | bellard | qemu_put_8s(f, &s->apmc); |
454 | ab1e34ad | bellard | qemu_put_8s(f, &s->apms); |
455 | ab1e34ad | bellard | qemu_put_timer(f, s->tmr_timer); |
456 | bee8d684 | ths | qemu_put_be64(f, s->tmr_overflow_time); |
457 | ab1e34ad | bellard | } |
458 | ab1e34ad | bellard | |
459 | ab1e34ad | bellard | static int pm_load(QEMUFile* f,void* opaque,int version_id) |
460 | ab1e34ad | bellard | { |
461 | ab1e34ad | bellard | PIIX4PMState *s = opaque; |
462 | ab1e34ad | bellard | int ret;
|
463 | ab1e34ad | bellard | |
464 | ab1e34ad | bellard | if (version_id > 1) |
465 | ab1e34ad | bellard | return -EINVAL;
|
466 | ab1e34ad | bellard | |
467 | ab1e34ad | bellard | ret = pci_device_load(&s->dev, f); |
468 | ab1e34ad | bellard | if (ret < 0) |
469 | ab1e34ad | bellard | return ret;
|
470 | ab1e34ad | bellard | |
471 | ab1e34ad | bellard | qemu_get_be16s(f, &s->pmsts); |
472 | ab1e34ad | bellard | qemu_get_be16s(f, &s->pmen); |
473 | ab1e34ad | bellard | qemu_get_be16s(f, &s->pmcntrl); |
474 | ab1e34ad | bellard | qemu_get_8s(f, &s->apmc); |
475 | ab1e34ad | bellard | qemu_get_8s(f, &s->apms); |
476 | ab1e34ad | bellard | qemu_get_timer(f, s->tmr_timer); |
477 | bee8d684 | ths | s->tmr_overflow_time=qemu_get_be64(f); |
478 | ab1e34ad | bellard | |
479 | ab1e34ad | bellard | pm_io_space_update(s); |
480 | ab1e34ad | bellard | |
481 | ab1e34ad | bellard | return 0; |
482 | ab1e34ad | bellard | } |
483 | ab1e34ad | bellard | |
484 | 0bacd130 | aliguori | static void piix4_reset(void *opaque) |
485 | 0bacd130 | aliguori | { |
486 | 3c892168 | aliguori | PIIX4PMState *s = opaque; |
487 | 3c892168 | aliguori | uint8_t *pci_conf = s->dev.config; |
488 | 3c892168 | aliguori | |
489 | 3c892168 | aliguori | pci_conf[0x58] = 0; |
490 | 3c892168 | aliguori | pci_conf[0x59] = 0; |
491 | 3c892168 | aliguori | pci_conf[0x5a] = 0; |
492 | 3c892168 | aliguori | pci_conf[0x5b] = 0; |
493 | 0bacd130 | aliguori | |
494 | 3c892168 | aliguori | if (kvm_enabled()) {
|
495 | 3c892168 | aliguori | /* Mark SMM as already inited (until KVM supports SMM). */
|
496 | 3c892168 | aliguori | pci_conf[0x5B] = 0x02; |
497 | 3c892168 | aliguori | } |
498 | 0bacd130 | aliguori | } |
499 | 0bacd130 | aliguori | |
500 | cf7a2fe2 | aurel32 | i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
|
501 | cf7a2fe2 | aurel32 | qemu_irq sci_irq) |
502 | 6515b203 | bellard | { |
503 | 6515b203 | bellard | PIIX4PMState *s; |
504 | 6515b203 | bellard | uint8_t *pci_conf; |
505 | 6515b203 | bellard | |
506 | 6515b203 | bellard | s = (PIIX4PMState *)pci_register_device(bus, |
507 | 6515b203 | bellard | "PM", sizeof(PIIX4PMState), |
508 | ab1e34ad | bellard | devfn, NULL, pm_write_config);
|
509 | cf7a2fe2 | aurel32 | pm_state = s; |
510 | 6515b203 | bellard | pci_conf = s->dev.config; |
511 | deb54399 | aliguori | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
512 | deb54399 | aliguori | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3); |
513 | bf367b54 | ths | pci_conf[0x06] = 0x80; |
514 | bf367b54 | ths | pci_conf[0x07] = 0x02; |
515 | a78b03cb | balrog | pci_conf[0x08] = 0x03; // revision number |
516 | 6515b203 | bellard | pci_conf[0x09] = 0x00; |
517 | 173a543b | blueswir1 | pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER); |
518 | 6407f373 | Isaku Yamahata | pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
|
519 | 6515b203 | bellard | pci_conf[0x3d] = 0x01; // interrupt pin 1 |
520 | 3b46e624 | ths | |
521 | ab1e34ad | bellard | pci_conf[0x40] = 0x01; /* PM io base read only bit */ |
522 | 3b46e624 | ths | |
523 | ab1e34ad | bellard | register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s); |
524 | ab1e34ad | bellard | register_ioport_read(0xb2, 2, 1, pm_smi_readb, s); |
525 | ab1e34ad | bellard | |
526 | 6515b203 | bellard | register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s); |
527 | 6515b203 | bellard | |
528 | 7ba1e619 | aliguori | if (kvm_enabled()) {
|
529 | 7ba1e619 | aliguori | /* Mark SMM as already inited to prevent SMM from running. KVM does not
|
530 | 7ba1e619 | aliguori | * support SMM mode. */
|
531 | 7ba1e619 | aliguori | pci_conf[0x5B] = 0x02; |
532 | 7ba1e619 | aliguori | } |
533 | 7ba1e619 | aliguori | |
534 | 1ce549ab | bellard | /* XXX: which specification is used ? The i82731AB has different
|
535 | 1ce549ab | bellard | mappings */
|
536 | 1ce549ab | bellard | pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10; |
537 | 1ce549ab | bellard | pci_conf[0x63] = 0x60; |
538 | 1ce549ab | bellard | pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) | |
539 | 1ce549ab | bellard | (serial_hds[1] != NULL ? 0x90 : 0); |
540 | 1ce549ab | bellard | |
541 | 3fffc223 | ths | pci_conf[0x90] = smb_io_base | 1; |
542 | 3fffc223 | ths | pci_conf[0x91] = smb_io_base >> 8; |
543 | 3fffc223 | ths | pci_conf[0xd2] = 0x09; |
544 | 3fffc223 | ths | register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, s); |
545 | 3fffc223 | ths | register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, s); |
546 | 3fffc223 | ths | |
547 | 6515b203 | bellard | s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s); |
548 | 6515b203 | bellard | |
549 | ab1e34ad | bellard | register_savevm("piix4_pm", 0, 1, pm_save, pm_load, s); |
550 | 3fffc223 | ths | |
551 | 0ff596d0 | pbrook | s->smbus = i2c_init_bus(); |
552 | cf7a2fe2 | aurel32 | s->irq = sci_irq; |
553 | 0bacd130 | aliguori | qemu_register_reset(piix4_reset, s); |
554 | 0bacd130 | aliguori | |
555 | 0ff596d0 | pbrook | return s->smbus;
|
556 | 6515b203 | bellard | } |
557 | cf7a2fe2 | aurel32 | |
558 | cf7a2fe2 | aurel32 | #if defined(TARGET_I386)
|
559 | cf7a2fe2 | aurel32 | void qemu_system_powerdown(void) |
560 | cf7a2fe2 | aurel32 | { |
561 | 9669d3c5 | aurel32 | if (!pm_state) {
|
562 | 9669d3c5 | aurel32 | qemu_system_shutdown_request(); |
563 | 9669d3c5 | aurel32 | } else if (pm_state->pmen & PWRBTN_EN) { |
564 | cf7a2fe2 | aurel32 | pm_state->pmsts |= PWRBTN_EN; |
565 | cf7a2fe2 | aurel32 | pm_update_sci(pm_state); |
566 | cf7a2fe2 | aurel32 | } |
567 | cf7a2fe2 | aurel32 | } |
568 | cf7a2fe2 | aurel32 | #endif
|
569 | 5e3cb534 | aliguori | |
570 | 5e3cb534 | aliguori | #define GPE_BASE 0xafe0 |
571 | ca2c72be | aliguori | #define PCI_BASE 0xae00 |
572 | ca2c72be | aliguori | #define PCI_EJ_BASE 0xae08 |
573 | 5e3cb534 | aliguori | |
574 | 5e3cb534 | aliguori | struct gpe_regs {
|
575 | 5e3cb534 | aliguori | uint16_t sts; /* status */
|
576 | 5e3cb534 | aliguori | uint16_t en; /* enabled */
|
577 | 5e3cb534 | aliguori | }; |
578 | 5e3cb534 | aliguori | |
579 | ca2c72be | aliguori | struct pci_status {
|
580 | ca2c72be | aliguori | uint32_t up; |
581 | ca2c72be | aliguori | uint32_t down; |
582 | ca2c72be | aliguori | }; |
583 | ca2c72be | aliguori | |
584 | 5e3cb534 | aliguori | static struct gpe_regs gpe; |
585 | ca2c72be | aliguori | static struct pci_status pci0_status; |
586 | 5e3cb534 | aliguori | |
587 | 6eb011b0 | aliguori | static uint32_t gpe_read_val(uint16_t val, uint32_t addr)
|
588 | 6eb011b0 | aliguori | { |
589 | 6eb011b0 | aliguori | if (addr & 1) |
590 | 6eb011b0 | aliguori | return (val >> 8) & 0xff; |
591 | 6eb011b0 | aliguori | return val & 0xff; |
592 | 6eb011b0 | aliguori | } |
593 | 6eb011b0 | aliguori | |
594 | 5e3cb534 | aliguori | static uint32_t gpe_readb(void *opaque, uint32_t addr) |
595 | 5e3cb534 | aliguori | { |
596 | 5e3cb534 | aliguori | uint32_t val = 0;
|
597 | 5e3cb534 | aliguori | struct gpe_regs *g = opaque;
|
598 | 5e3cb534 | aliguori | switch (addr) {
|
599 | 5e3cb534 | aliguori | case GPE_BASE:
|
600 | 5e3cb534 | aliguori | case GPE_BASE + 1: |
601 | 6eb011b0 | aliguori | val = gpe_read_val(g->sts, addr); |
602 | 5e3cb534 | aliguori | break;
|
603 | 5e3cb534 | aliguori | case GPE_BASE + 2: |
604 | 5e3cb534 | aliguori | case GPE_BASE + 3: |
605 | 6eb011b0 | aliguori | val = gpe_read_val(g->en, addr); |
606 | 5e3cb534 | aliguori | break;
|
607 | 5e3cb534 | aliguori | default:
|
608 | 5e3cb534 | aliguori | break;
|
609 | 5e3cb534 | aliguori | } |
610 | 5e3cb534 | aliguori | |
611 | 5e3cb534 | aliguori | #if defined(DEBUG)
|
612 | f654d9e2 | Alex Williamson | printf("gpe read %x == %x\n", addr, val);
|
613 | 5e3cb534 | aliguori | #endif
|
614 | 5e3cb534 | aliguori | return val;
|
615 | 5e3cb534 | aliguori | } |
616 | 5e3cb534 | aliguori | |
617 | 6eb011b0 | aliguori | static void gpe_write_val(uint16_t *cur, int addr, uint32_t val) |
618 | 6eb011b0 | aliguori | { |
619 | 6eb011b0 | aliguori | if (addr & 1) |
620 | 6eb011b0 | aliguori | *cur = (*cur & 0xff) | (val << 8); |
621 | 6eb011b0 | aliguori | else
|
622 | 6eb011b0 | aliguori | *cur = (*cur & 0xff00) | (val & 0xff); |
623 | 6eb011b0 | aliguori | } |
624 | 6eb011b0 | aliguori | |
625 | 6eb011b0 | aliguori | static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val) |
626 | 6eb011b0 | aliguori | { |
627 | 6eb011b0 | aliguori | uint16_t x1, x0 = val & 0xff;
|
628 | 6eb011b0 | aliguori | int shift = (addr & 1) ? 8 : 0; |
629 | 6eb011b0 | aliguori | |
630 | 6eb011b0 | aliguori | x1 = (*cur >> shift) & 0xff;
|
631 | 6eb011b0 | aliguori | |
632 | 6eb011b0 | aliguori | x1 = x1 & ~x0; |
633 | 6eb011b0 | aliguori | |
634 | 6eb011b0 | aliguori | *cur = (*cur & (0xff << (8 - shift))) | (x1 << shift); |
635 | 6eb011b0 | aliguori | } |
636 | 6eb011b0 | aliguori | |
637 | 5e3cb534 | aliguori | static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val) |
638 | 5e3cb534 | aliguori | { |
639 | 5e3cb534 | aliguori | struct gpe_regs *g = opaque;
|
640 | 5e3cb534 | aliguori | switch (addr) {
|
641 | 5e3cb534 | aliguori | case GPE_BASE:
|
642 | 5e3cb534 | aliguori | case GPE_BASE + 1: |
643 | 6eb011b0 | aliguori | gpe_reset_val(&g->sts, addr, val); |
644 | 5e3cb534 | aliguori | break;
|
645 | 5e3cb534 | aliguori | case GPE_BASE + 2: |
646 | 5e3cb534 | aliguori | case GPE_BASE + 3: |
647 | 6eb011b0 | aliguori | gpe_write_val(&g->en, addr, val); |
648 | 5e3cb534 | aliguori | break;
|
649 | 5e3cb534 | aliguori | default:
|
650 | 5e3cb534 | aliguori | break;
|
651 | 5e3cb534 | aliguori | } |
652 | 5e3cb534 | aliguori | |
653 | 5e3cb534 | aliguori | #if defined(DEBUG)
|
654 | f654d9e2 | Alex Williamson | printf("gpe write %x <== %d\n", addr, val);
|
655 | 5e3cb534 | aliguori | #endif
|
656 | 5e3cb534 | aliguori | } |
657 | 5e3cb534 | aliguori | |
658 | ca2c72be | aliguori | static uint32_t pcihotplug_read(void *opaque, uint32_t addr) |
659 | ca2c72be | aliguori | { |
660 | ca2c72be | aliguori | uint32_t val = 0;
|
661 | ca2c72be | aliguori | struct pci_status *g = opaque;
|
662 | ca2c72be | aliguori | switch (addr) {
|
663 | ca2c72be | aliguori | case PCI_BASE:
|
664 | ca2c72be | aliguori | val = g->up; |
665 | ca2c72be | aliguori | break;
|
666 | ca2c72be | aliguori | case PCI_BASE + 4: |
667 | ca2c72be | aliguori | val = g->down; |
668 | ca2c72be | aliguori | break;
|
669 | ca2c72be | aliguori | default:
|
670 | ca2c72be | aliguori | break;
|
671 | ca2c72be | aliguori | } |
672 | ca2c72be | aliguori | |
673 | ca2c72be | aliguori | #if defined(DEBUG)
|
674 | f654d9e2 | Alex Williamson | printf("pcihotplug read %x == %x\n", addr, val);
|
675 | ca2c72be | aliguori | #endif
|
676 | ca2c72be | aliguori | return val;
|
677 | ca2c72be | aliguori | } |
678 | ca2c72be | aliguori | |
679 | ca2c72be | aliguori | static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val) |
680 | ca2c72be | aliguori | { |
681 | ca2c72be | aliguori | struct pci_status *g = opaque;
|
682 | ca2c72be | aliguori | switch (addr) {
|
683 | ca2c72be | aliguori | case PCI_BASE:
|
684 | ca2c72be | aliguori | g->up = val; |
685 | ca2c72be | aliguori | break;
|
686 | ca2c72be | aliguori | case PCI_BASE + 4: |
687 | ca2c72be | aliguori | g->down = val; |
688 | ca2c72be | aliguori | break;
|
689 | ca2c72be | aliguori | } |
690 | ca2c72be | aliguori | |
691 | ca2c72be | aliguori | #if defined(DEBUG)
|
692 | f654d9e2 | Alex Williamson | printf("pcihotplug write %x <== %d\n", addr, val);
|
693 | ca2c72be | aliguori | #endif
|
694 | ca2c72be | aliguori | } |
695 | ca2c72be | aliguori | |
696 | ca2c72be | aliguori | static uint32_t pciej_read(void *opaque, uint32_t addr) |
697 | ca2c72be | aliguori | { |
698 | ca2c72be | aliguori | #if defined(DEBUG)
|
699 | f654d9e2 | Alex Williamson | printf("pciej read %x\n", addr);
|
700 | ca2c72be | aliguori | #endif
|
701 | ca2c72be | aliguori | return 0; |
702 | ca2c72be | aliguori | } |
703 | ca2c72be | aliguori | |
704 | ca2c72be | aliguori | static void pciej_write(void *opaque, uint32_t addr, uint32_t val) |
705 | ca2c72be | aliguori | { |
706 | 6f338c34 | aliguori | #if defined (TARGET_I386)
|
707 | ca2c72be | aliguori | int slot = ffs(val) - 1; |
708 | ca2c72be | aliguori | |
709 | 6f338c34 | aliguori | pci_device_hot_remove_success(0, slot);
|
710 | 6f338c34 | aliguori | #endif
|
711 | 6f338c34 | aliguori | |
712 | ca2c72be | aliguori | #if defined(DEBUG)
|
713 | f654d9e2 | Alex Williamson | printf("pciej write %x <== %d\n", addr, val);
|
714 | ca2c72be | aliguori | #endif
|
715 | ca2c72be | aliguori | } |
716 | ca2c72be | aliguori | |
717 | 5e3cb534 | aliguori | void qemu_system_hot_add_init(void) |
718 | 5e3cb534 | aliguori | { |
719 | 5e3cb534 | aliguori | register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, &gpe); |
720 | 5e3cb534 | aliguori | register_ioport_read(GPE_BASE, 4, 1, gpe_readb, &gpe); |
721 | 5e3cb534 | aliguori | |
722 | ca2c72be | aliguori | register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, &pci0_status); |
723 | ca2c72be | aliguori | register_ioport_read(PCI_BASE, 8, 4, pcihotplug_read, &pci0_status); |
724 | ca2c72be | aliguori | |
725 | ca2c72be | aliguori | register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, NULL); |
726 | ca2c72be | aliguori | register_ioport_read(PCI_EJ_BASE, 4, 4, pciej_read, NULL); |
727 | ca2c72be | aliguori | } |
728 | ca2c72be | aliguori | |
729 | ca2c72be | aliguori | static void enable_device(struct pci_status *p, struct gpe_regs *g, int slot) |
730 | ca2c72be | aliguori | { |
731 | ca2c72be | aliguori | g->sts |= 2;
|
732 | ca2c72be | aliguori | p->up |= (1 << slot);
|
733 | ca2c72be | aliguori | } |
734 | ca2c72be | aliguori | |
735 | ca2c72be | aliguori | static void disable_device(struct pci_status *p, struct gpe_regs *g, int slot) |
736 | ca2c72be | aliguori | { |
737 | ca2c72be | aliguori | g->sts |= 2;
|
738 | ca2c72be | aliguori | p->down |= (1 << slot);
|
739 | ca2c72be | aliguori | } |
740 | ca2c72be | aliguori | |
741 | ca2c72be | aliguori | void qemu_system_device_hot_add(int bus, int slot, int state) |
742 | ca2c72be | aliguori | { |
743 | ca2c72be | aliguori | pci0_status.up = 0;
|
744 | ca2c72be | aliguori | pci0_status.down = 0;
|
745 | ca2c72be | aliguori | if (state)
|
746 | ca2c72be | aliguori | enable_device(&pci0_status, &gpe, slot); |
747 | ca2c72be | aliguori | else
|
748 | ca2c72be | aliguori | disable_device(&pci0_status, &gpe, slot); |
749 | 1f0711e2 | aliguori | if (gpe.en & 2) { |
750 | 1f0711e2 | aliguori | qemu_set_irq(pm_state->irq, 1);
|
751 | 1f0711e2 | aliguori | qemu_set_irq(pm_state->irq, 0);
|
752 | 1f0711e2 | aliguori | } |
753 | 5e3cb534 | aliguori | } |
754 | 8a92ea2f | aliguori | |
755 | 8a92ea2f | aliguori | struct acpi_table_header
|
756 | 8a92ea2f | aliguori | { |
757 | 8a92ea2f | aliguori | char signature [4]; /* ACPI signature (4 ASCII characters) */ |
758 | 8a92ea2f | aliguori | uint32_t length; /* Length of table, in bytes, including header */
|
759 | 8a92ea2f | aliguori | uint8_t revision; /* ACPI Specification minor version # */
|
760 | 8a92ea2f | aliguori | uint8_t checksum; /* To make sum of entire table == 0 */
|
761 | 8a92ea2f | aliguori | char oem_id [6]; /* OEM identification */ |
762 | 8a92ea2f | aliguori | char oem_table_id [8]; /* OEM table identification */ |
763 | 8a92ea2f | aliguori | uint32_t oem_revision; /* OEM revision number */
|
764 | 8a92ea2f | aliguori | char asl_compiler_id [4]; /* ASL compiler vendor ID */ |
765 | 8a92ea2f | aliguori | uint32_t asl_compiler_revision; /* ASL compiler revision number */
|
766 | 8a92ea2f | aliguori | } __attribute__((packed)); |
767 | 8a92ea2f | aliguori | |
768 | 8a92ea2f | aliguori | char *acpi_tables;
|
769 | 8a92ea2f | aliguori | size_t acpi_tables_len; |
770 | 8a92ea2f | aliguori | |
771 | 8a92ea2f | aliguori | static int acpi_checksum(const uint8_t *data, int len) |
772 | 8a92ea2f | aliguori | { |
773 | 8a92ea2f | aliguori | int sum, i;
|
774 | 8a92ea2f | aliguori | sum = 0;
|
775 | 8a92ea2f | aliguori | for(i = 0; i < len; i++) |
776 | 8a92ea2f | aliguori | sum += data[i]; |
777 | 8a92ea2f | aliguori | return (-sum) & 0xff; |
778 | 8a92ea2f | aliguori | } |
779 | 8a92ea2f | aliguori | |
780 | 8a92ea2f | aliguori | int acpi_table_add(const char *t) |
781 | 8a92ea2f | aliguori | { |
782 | 8a92ea2f | aliguori | static const char *dfl_id = "QEMUQEMU"; |
783 | 8a92ea2f | aliguori | char buf[1024], *p, *f; |
784 | 8a92ea2f | aliguori | struct acpi_table_header acpi_hdr;
|
785 | 8a92ea2f | aliguori | unsigned long val; |
786 | 8a92ea2f | aliguori | size_t off; |
787 | 8a92ea2f | aliguori | |
788 | 8a92ea2f | aliguori | memset(&acpi_hdr, 0, sizeof(acpi_hdr)); |
789 | 8a92ea2f | aliguori | |
790 | 8a92ea2f | aliguori | if (get_param_value(buf, sizeof(buf), "sig", t)) { |
791 | 8a92ea2f | aliguori | strncpy(acpi_hdr.signature, buf, 4);
|
792 | 8a92ea2f | aliguori | } else {
|
793 | 8a92ea2f | aliguori | strncpy(acpi_hdr.signature, dfl_id, 4);
|
794 | 8a92ea2f | aliguori | } |
795 | 8a92ea2f | aliguori | if (get_param_value(buf, sizeof(buf), "rev", t)) { |
796 | 8a92ea2f | aliguori | val = strtoul(buf, &p, 10);
|
797 | 8a92ea2f | aliguori | if (val > 255 || *p != '\0') |
798 | 8a92ea2f | aliguori | goto out;
|
799 | 8a92ea2f | aliguori | } else {
|
800 | 8a92ea2f | aliguori | val = 1;
|
801 | 8a92ea2f | aliguori | } |
802 | 8a92ea2f | aliguori | acpi_hdr.revision = (int8_t)val; |
803 | 8a92ea2f | aliguori | |
804 | 8a92ea2f | aliguori | if (get_param_value(buf, sizeof(buf), "oem_id", t)) { |
805 | 8a92ea2f | aliguori | strncpy(acpi_hdr.oem_id, buf, 6);
|
806 | 8a92ea2f | aliguori | } else {
|
807 | 8a92ea2f | aliguori | strncpy(acpi_hdr.oem_id, dfl_id, 6);
|
808 | 8a92ea2f | aliguori | } |
809 | 8a92ea2f | aliguori | |
810 | 8a92ea2f | aliguori | if (get_param_value(buf, sizeof(buf), "oem_table_id", t)) { |
811 | 8a92ea2f | aliguori | strncpy(acpi_hdr.oem_table_id, buf, 8);
|
812 | 8a92ea2f | aliguori | } else {
|
813 | 8a92ea2f | aliguori | strncpy(acpi_hdr.oem_table_id, dfl_id, 8);
|
814 | 8a92ea2f | aliguori | } |
815 | 8a92ea2f | aliguori | |
816 | 8a92ea2f | aliguori | if (get_param_value(buf, sizeof(buf), "oem_rev", t)) { |
817 | 8a92ea2f | aliguori | val = strtol(buf, &p, 10);
|
818 | 8a92ea2f | aliguori | if(*p != '\0') |
819 | 8a92ea2f | aliguori | goto out;
|
820 | 8a92ea2f | aliguori | } else {
|
821 | 8a92ea2f | aliguori | val = 1;
|
822 | 8a92ea2f | aliguori | } |
823 | 8a92ea2f | aliguori | acpi_hdr.oem_revision = cpu_to_le32(val); |
824 | 8a92ea2f | aliguori | |
825 | 8a92ea2f | aliguori | if (get_param_value(buf, sizeof(buf), "asl_compiler_id", t)) { |
826 | 8a92ea2f | aliguori | strncpy(acpi_hdr.asl_compiler_id, buf, 4);
|
827 | 8a92ea2f | aliguori | } else {
|
828 | 8a92ea2f | aliguori | strncpy(acpi_hdr.asl_compiler_id, dfl_id, 4);
|
829 | 8a92ea2f | aliguori | } |
830 | 8a92ea2f | aliguori | |
831 | 8a92ea2f | aliguori | if (get_param_value(buf, sizeof(buf), "asl_compiler_rev", t)) { |
832 | 8a92ea2f | aliguori | val = strtol(buf, &p, 10);
|
833 | 8a92ea2f | aliguori | if(*p != '\0') |
834 | 8a92ea2f | aliguori | goto out;
|
835 | 8a92ea2f | aliguori | } else {
|
836 | 8a92ea2f | aliguori | val = 1;
|
837 | 8a92ea2f | aliguori | } |
838 | 8a92ea2f | aliguori | acpi_hdr.asl_compiler_revision = cpu_to_le32(val); |
839 | 8a92ea2f | aliguori | |
840 | 8a92ea2f | aliguori | if (!get_param_value(buf, sizeof(buf), "data", t)) { |
841 | 8a92ea2f | aliguori | buf[0] = '\0'; |
842 | 8a92ea2f | aliguori | } |
843 | 8a92ea2f | aliguori | |
844 | 8a92ea2f | aliguori | acpi_hdr.length = sizeof(acpi_hdr);
|
845 | 8a92ea2f | aliguori | |
846 | 8a92ea2f | aliguori | f = buf; |
847 | 8a92ea2f | aliguori | while (buf[0]) { |
848 | 8a92ea2f | aliguori | struct stat s;
|
849 | 54042bcf | aliguori | char *n = strchr(f, ':'); |
850 | 8a92ea2f | aliguori | if (n)
|
851 | 8a92ea2f | aliguori | *n = '\0';
|
852 | 8a92ea2f | aliguori | if(stat(f, &s) < 0) { |
853 | 8a92ea2f | aliguori | fprintf(stderr, "Can't stat file '%s': %s\n", f, strerror(errno));
|
854 | 8a92ea2f | aliguori | goto out;
|
855 | 8a92ea2f | aliguori | } |
856 | 8a92ea2f | aliguori | acpi_hdr.length += s.st_size; |
857 | 8a92ea2f | aliguori | if (!n)
|
858 | 8a92ea2f | aliguori | break;
|
859 | 8a92ea2f | aliguori | *n = ':';
|
860 | 8a92ea2f | aliguori | f = n + 1;
|
861 | 8a92ea2f | aliguori | } |
862 | 8a92ea2f | aliguori | |
863 | 8a92ea2f | aliguori | if (!acpi_tables) {
|
864 | 8a92ea2f | aliguori | acpi_tables_len = sizeof(uint16_t);
|
865 | 8a92ea2f | aliguori | acpi_tables = qemu_mallocz(acpi_tables_len); |
866 | 8a92ea2f | aliguori | } |
867 | 8a92ea2f | aliguori | p = acpi_tables + acpi_tables_len; |
868 | 8a92ea2f | aliguori | acpi_tables_len += sizeof(uint16_t) + acpi_hdr.length;
|
869 | 8a92ea2f | aliguori | acpi_tables = qemu_realloc(acpi_tables, acpi_tables_len); |
870 | 8a92ea2f | aliguori | |
871 | 8a92ea2f | aliguori | acpi_hdr.length = cpu_to_le32(acpi_hdr.length); |
872 | 8a92ea2f | aliguori | *(uint16_t*)p = acpi_hdr.length; |
873 | 8a92ea2f | aliguori | p += sizeof(uint16_t);
|
874 | 8a92ea2f | aliguori | memcpy(p, &acpi_hdr, sizeof(acpi_hdr));
|
875 | 8a92ea2f | aliguori | off = sizeof(acpi_hdr);
|
876 | 8a92ea2f | aliguori | |
877 | 8a92ea2f | aliguori | f = buf; |
878 | 8a92ea2f | aliguori | while (buf[0]) { |
879 | 8a92ea2f | aliguori | struct stat s;
|
880 | 8a92ea2f | aliguori | int fd;
|
881 | 54042bcf | aliguori | char *n = strchr(f, ':'); |
882 | 8a92ea2f | aliguori | if (n)
|
883 | 8a92ea2f | aliguori | *n = '\0';
|
884 | 8a92ea2f | aliguori | fd = open(f, O_RDONLY); |
885 | 8a92ea2f | aliguori | |
886 | 8a92ea2f | aliguori | if(fd < 0) |
887 | 8a92ea2f | aliguori | goto out;
|
888 | 8a92ea2f | aliguori | if(fstat(fd, &s) < 0) { |
889 | 8a92ea2f | aliguori | close(fd); |
890 | 8a92ea2f | aliguori | goto out;
|
891 | 8a92ea2f | aliguori | } |
892 | 8a92ea2f | aliguori | |
893 | 8a92ea2f | aliguori | do {
|
894 | 8a92ea2f | aliguori | int r;
|
895 | 8a92ea2f | aliguori | r = read(fd, p + off, s.st_size); |
896 | 8a92ea2f | aliguori | if (r > 0) { |
897 | 8a92ea2f | aliguori | off += r; |
898 | 8a92ea2f | aliguori | s.st_size -= r; |
899 | 8a92ea2f | aliguori | } else if ((r < 0 && errno != EINTR) || r == 0) { |
900 | 8a92ea2f | aliguori | close(fd); |
901 | 8a92ea2f | aliguori | goto out;
|
902 | 8a92ea2f | aliguori | } |
903 | 8a92ea2f | aliguori | } while(s.st_size);
|
904 | 8a92ea2f | aliguori | |
905 | 8a92ea2f | aliguori | close(fd); |
906 | 8a92ea2f | aliguori | if (!n)
|
907 | 8a92ea2f | aliguori | break;
|
908 | 8a92ea2f | aliguori | f = n + 1;
|
909 | 8a92ea2f | aliguori | } |
910 | 8a92ea2f | aliguori | |
911 | 8a92ea2f | aliguori | ((struct acpi_table_header*)p)->checksum = acpi_checksum((uint8_t*)p, off);
|
912 | 8a92ea2f | aliguori | /* increase number of tables */
|
913 | 8a92ea2f | aliguori | (*(uint16_t*)acpi_tables) = |
914 | 8a92ea2f | aliguori | cpu_to_le32(le32_to_cpu(*(uint16_t*)acpi_tables) + 1);
|
915 | 8a92ea2f | aliguori | return 0; |
916 | 8a92ea2f | aliguori | out:
|
917 | 8a92ea2f | aliguori | if (acpi_tables) {
|
918 | 8a92ea2f | aliguori | free(acpi_tables); |
919 | 8a92ea2f | aliguori | acpi_tables = NULL;
|
920 | 8a92ea2f | aliguori | } |
921 | 8a92ea2f | aliguori | return -1; |
922 | 8a92ea2f | aliguori | } |