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/*
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* TI OMAP processors emulation.
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*
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* Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include "vl.h" |
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#include "arm_pic.h" |
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/* Should signal the TCMI */
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uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
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{ |
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OMAP_16B_REG(addr); |
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return 0; |
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} |
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void omap_badwidth_write16(void *opaque, target_phys_addr_t addr, |
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uint32_t value) |
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{ |
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OMAP_16B_REG(addr); |
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} |
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uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
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{ |
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OMAP_32B_REG(addr); |
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return 0; |
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} |
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void omap_badwidth_write32(void *opaque, target_phys_addr_t addr, |
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uint32_t value) |
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{ |
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OMAP_32B_REG(addr); |
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} |
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|
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/* Interrupt Handlers */
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struct omap_intr_handler_s {
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qemu_irq *pins; |
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qemu_irq *parent_pic; |
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target_phys_addr_t base; |
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/* state */
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uint32_t irqs; |
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uint32_t mask; |
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uint32_t sens_edge; |
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uint32_t fiq; |
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int priority[32]; |
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uint32_t new_irq_agr; |
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uint32_t new_fiq_agr; |
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int sir_irq;
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int sir_fiq;
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int stats[32]; |
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}; |
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|
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static void omap_inth_update(struct omap_intr_handler_s *s) |
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{ |
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uint32_t irq = s->irqs & ~s->mask & ~s->fiq; |
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uint32_t fiq = s->irqs & ~s->mask & s->fiq; |
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if (s->new_irq_agr || !irq) {
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qemu_set_irq(s->parent_pic[ARM_PIC_CPU_IRQ], irq); |
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if (irq)
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s->new_irq_agr = 0;
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} |
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if (s->new_fiq_agr || !irq) {
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qemu_set_irq(s->parent_pic[ARM_PIC_CPU_FIQ], fiq); |
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if (fiq)
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s->new_fiq_agr = 0;
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} |
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} |
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static void omap_inth_sir_update(struct omap_intr_handler_s *s) |
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{ |
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int i, intr_irq, intr_fiq, p_irq, p_fiq, p, f;
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uint32_t level = s->irqs & ~s->mask; |
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intr_irq = 0;
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intr_fiq = 0;
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p_irq = -1;
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p_fiq = -1;
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/* Find the interrupt line with the highest dynamic priority */
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for (f = ffs(level), i = f - 1, level >>= f - 1; f; i += f, level >>= f) { |
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p = s->priority[i]; |
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if (s->fiq & (1 << i)) { |
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if (p > p_fiq) {
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p_fiq = p; |
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intr_fiq = i; |
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} |
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} else {
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if (p > p_irq) {
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p_irq = p; |
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intr_irq = i; |
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} |
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} |
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f = ffs(level >> 1);
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} |
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s->sir_irq = intr_irq; |
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s->sir_fiq = intr_fiq; |
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} |
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#define INT_FALLING_EDGE 0 |
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#define INT_LOW_LEVEL 1 |
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static void omap_set_intr(void *opaque, int irq, int req) |
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{ |
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struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque; |
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uint32_t rise; |
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if (req) {
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rise = ~ih->irqs & (1 << irq);
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ih->irqs |= rise; |
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ih->stats[irq] += !!rise; |
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} else {
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rise = ih->sens_edge & ih->irqs & (1 << irq);
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ih->irqs &= ~rise; |
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} |
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if (rise & ~ih->mask) {
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omap_inth_sir_update(ih); |
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omap_inth_update(ih); |
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} |
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} |
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static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr) |
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{ |
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struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
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int i, offset = addr - s->base;
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switch (offset) {
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case 0x00: /* ITR */ |
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return s->irqs;
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case 0x04: /* MIR */ |
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return s->mask;
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case 0x10: /* SIR_IRQ_CODE */ |
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i = s->sir_irq; |
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if (((s->sens_edge >> i) & 1) == INT_FALLING_EDGE && i) { |
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s->irqs &= ~(1 << i);
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omap_inth_sir_update(s); |
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omap_inth_update(s); |
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} |
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return i;
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|
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case 0x14: /* SIR_FIQ_CODE */ |
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i = s->sir_fiq; |
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if (((s->sens_edge >> i) & 1) == INT_FALLING_EDGE && i) { |
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s->irqs &= ~(1 << i);
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omap_inth_sir_update(s); |
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omap_inth_update(s); |
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} |
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return i;
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case 0x18: /* CONTROL_REG */ |
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return 0; |
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case 0x1c: /* ILR0 */ |
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case 0x20: /* ILR1 */ |
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case 0x24: /* ILR2 */ |
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case 0x28: /* ILR3 */ |
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case 0x2c: /* ILR4 */ |
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case 0x30: /* ILR5 */ |
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case 0x34: /* ILR6 */ |
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case 0x38: /* ILR7 */ |
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case 0x3c: /* ILR8 */ |
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case 0x40: /* ILR9 */ |
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case 0x44: /* ILR10 */ |
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case 0x48: /* ILR11 */ |
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case 0x4c: /* ILR12 */ |
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case 0x50: /* ILR13 */ |
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case 0x54: /* ILR14 */ |
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case 0x58: /* ILR15 */ |
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case 0x5c: /* ILR16 */ |
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case 0x60: /* ILR17 */ |
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case 0x64: /* ILR18 */ |
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case 0x68: /* ILR19 */ |
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case 0x6c: /* ILR20 */ |
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case 0x70: /* ILR21 */ |
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case 0x74: /* ILR22 */ |
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case 0x78: /* ILR23 */ |
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case 0x7c: /* ILR24 */ |
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case 0x80: /* ILR25 */ |
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case 0x84: /* ILR26 */ |
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case 0x88: /* ILR27 */ |
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case 0x8c: /* ILR28 */ |
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case 0x90: /* ILR29 */ |
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case 0x94: /* ILR30 */ |
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case 0x98: /* ILR31 */ |
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i = (offset - 0x1c) >> 2; |
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return (s->priority[i] << 2) | |
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(((s->sens_edge >> i) & 1) << 1) | |
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((s->fiq >> i) & 1);
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case 0x9c: /* ISR */ |
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return 0x00000000; |
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default:
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OMAP_BAD_REG(addr); |
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break;
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} |
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return 0; |
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} |
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static void omap_inth_write(void *opaque, target_phys_addr_t addr, |
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uint32_t value) |
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{ |
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struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
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int i, offset = addr - s->base;
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switch (offset) {
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case 0x00: /* ITR */ |
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s->irqs &= value; |
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omap_inth_sir_update(s); |
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omap_inth_update(s); |
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return;
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case 0x04: /* MIR */ |
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s->mask = value; |
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omap_inth_sir_update(s); |
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omap_inth_update(s); |
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return;
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case 0x10: /* SIR_IRQ_CODE */ |
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case 0x14: /* SIR_FIQ_CODE */ |
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OMAP_RO_REG(addr); |
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break;
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case 0x18: /* CONTROL_REG */ |
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if (value & 2) |
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s->new_fiq_agr = ~0;
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if (value & 1) |
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s->new_irq_agr = ~0;
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omap_inth_update(s); |
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return;
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|
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case 0x1c: /* ILR0 */ |
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case 0x20: /* ILR1 */ |
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case 0x24: /* ILR2 */ |
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case 0x28: /* ILR3 */ |
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case 0x2c: /* ILR4 */ |
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case 0x30: /* ILR5 */ |
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case 0x34: /* ILR6 */ |
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case 0x38: /* ILR7 */ |
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case 0x3c: /* ILR8 */ |
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case 0x40: /* ILR9 */ |
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case 0x44: /* ILR10 */ |
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case 0x48: /* ILR11 */ |
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case 0x4c: /* ILR12 */ |
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case 0x50: /* ILR13 */ |
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case 0x54: /* ILR14 */ |
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case 0x58: /* ILR15 */ |
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case 0x5c: /* ILR16 */ |
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case 0x60: /* ILR17 */ |
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case 0x64: /* ILR18 */ |
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case 0x68: /* ILR19 */ |
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case 0x6c: /* ILR20 */ |
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case 0x70: /* ILR21 */ |
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case 0x74: /* ILR22 */ |
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case 0x78: /* ILR23 */ |
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case 0x7c: /* ILR24 */ |
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case 0x80: /* ILR25 */ |
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case 0x84: /* ILR26 */ |
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case 0x88: /* ILR27 */ |
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case 0x8c: /* ILR28 */ |
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case 0x90: /* ILR29 */ |
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case 0x94: /* ILR30 */ |
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case 0x98: /* ILR31 */ |
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i = (offset - 0x1c) >> 2; |
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s->priority[i] = (value >> 2) & 0x1f; |
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s->sens_edge &= ~(1 << i);
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s->sens_edge |= ((value >> 1) & 1) << i; |
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s->fiq &= ~(1 << i);
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s->fiq |= (value & 1) << i;
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return;
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|
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case 0x9c: /* ISR */ |
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for (i = 0; i < 32; i ++) |
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if (value & (1 << i)) { |
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omap_set_intr(s, i, 1);
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return;
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} |
299 |
return;
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|
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default:
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OMAP_BAD_REG(addr); |
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} |
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} |
305 |
|
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static CPUReadMemoryFunc *omap_inth_readfn[] = {
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omap_badwidth_read32, |
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omap_badwidth_read32, |
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omap_inth_read, |
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}; |
311 |
|
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static CPUWriteMemoryFunc *omap_inth_writefn[] = {
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omap_inth_write, |
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omap_inth_write, |
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omap_inth_write, |
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}; |
317 |
|
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static void omap_inth_reset(struct omap_intr_handler_s *s) |
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{ |
320 |
s->irqs = 0x00000000;
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s->mask = 0xffffffff;
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s->sens_edge = 0x00000000;
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s->fiq = 0x00000000;
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memset(s->priority, 0, sizeof(s->priority)); |
325 |
s->new_irq_agr = ~0;
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s->new_fiq_agr = ~0;
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s->sir_irq = 0;
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s->sir_fiq = 0;
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|
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omap_inth_update(s); |
331 |
} |
332 |
|
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struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
|
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unsigned long size, qemu_irq parent[2], omap_clk clk) |
335 |
{ |
336 |
int iomemtype;
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struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) |
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qemu_mallocz(sizeof(struct omap_intr_handler_s)); |
339 |
|
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s->parent_pic = parent; |
341 |
s->base = base; |
342 |
s->pins = qemu_allocate_irqs(omap_set_intr, s, 32);
|
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omap_inth_reset(s); |
344 |
|
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iomemtype = cpu_register_io_memory(0, omap_inth_readfn,
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omap_inth_writefn, s); |
347 |
cpu_register_physical_memory(s->base, size, iomemtype); |
348 |
|
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return s;
|
350 |
} |
351 |
|
352 |
/* OMAP1 DMA module */
|
353 |
typedef enum { |
354 |
constant = 0,
|
355 |
post_incremented, |
356 |
single_index, |
357 |
double_index, |
358 |
} omap_dma_addressing_t; |
359 |
|
360 |
struct omap_dma_channel_s {
|
361 |
int burst[2]; |
362 |
int pack[2]; |
363 |
enum omap_dma_port port[2]; |
364 |
target_phys_addr_t addr[2];
|
365 |
omap_dma_addressing_t mode[2];
|
366 |
int data_type;
|
367 |
int end_prog;
|
368 |
int repeat;
|
369 |
int auto_init;
|
370 |
int priority;
|
371 |
int fs;
|
372 |
int sync;
|
373 |
int running;
|
374 |
int interrupts;
|
375 |
int status;
|
376 |
int signalled;
|
377 |
int post_sync;
|
378 |
int transfer;
|
379 |
uint16_t elements; |
380 |
uint16_t frames; |
381 |
uint16_t frame_index; |
382 |
uint16_t element_index; |
383 |
uint16_t cpc; |
384 |
|
385 |
struct omap_dma_reg_set_s {
|
386 |
target_phys_addr_t src, dest; |
387 |
int frame;
|
388 |
int element;
|
389 |
int frame_delta[2]; |
390 |
int elem_delta[2]; |
391 |
int frames;
|
392 |
int elements;
|
393 |
} active_set; |
394 |
}; |
395 |
|
396 |
struct omap_dma_s {
|
397 |
qemu_irq *ih; |
398 |
QEMUTimer *tm; |
399 |
struct omap_mpu_state_s *mpu;
|
400 |
target_phys_addr_t base; |
401 |
omap_clk clk; |
402 |
int64_t delay; |
403 |
uint32_t drq; |
404 |
|
405 |
uint16_t gcr; |
406 |
int run_count;
|
407 |
|
408 |
int chans;
|
409 |
struct omap_dma_channel_s ch[16]; |
410 |
struct omap_dma_lcd_channel_s lcd_ch;
|
411 |
}; |
412 |
|
413 |
static void omap_dma_interrupts_update(struct omap_dma_s *s) |
414 |
{ |
415 |
/* First three interrupts are shared between two channels each. */
|
416 |
qemu_set_irq(s->ih[OMAP_INT_DMA_CH0_6], |
417 |
(s->ch[0].status | s->ch[6].status) & 0x3f); |
418 |
qemu_set_irq(s->ih[OMAP_INT_DMA_CH1_7], |
419 |
(s->ch[1].status | s->ch[7].status) & 0x3f); |
420 |
qemu_set_irq(s->ih[OMAP_INT_DMA_CH2_8], |
421 |
(s->ch[2].status | s->ch[8].status) & 0x3f); |
422 |
qemu_set_irq(s->ih[OMAP_INT_DMA_CH3], |
423 |
(s->ch[3].status) & 0x3f); |
424 |
qemu_set_irq(s->ih[OMAP_INT_DMA_CH4], |
425 |
(s->ch[4].status) & 0x3f); |
426 |
qemu_set_irq(s->ih[OMAP_INT_DMA_CH5], |
427 |
(s->ch[5].status) & 0x3f); |
428 |
} |
429 |
|
430 |
static void omap_dma_channel_load(struct omap_dma_s *s, int ch) |
431 |
{ |
432 |
struct omap_dma_reg_set_s *a = &s->ch[ch].active_set;
|
433 |
int i;
|
434 |
|
435 |
/*
|
436 |
* TODO: verify address ranges and alignment
|
437 |
* TODO: port endianness
|
438 |
*/
|
439 |
|
440 |
a->src = s->ch[ch].addr[0];
|
441 |
a->dest = s->ch[ch].addr[1];
|
442 |
a->frames = s->ch[ch].frames; |
443 |
a->elements = s->ch[ch].elements; |
444 |
a->frame = 0;
|
445 |
a->element = 0;
|
446 |
|
447 |
if (unlikely(!s->ch[ch].elements || !s->ch[ch].frames)) {
|
448 |
printf("%s: bad DMA request\n", __FUNCTION__);
|
449 |
return;
|
450 |
} |
451 |
|
452 |
for (i = 0; i < 2; i ++) |
453 |
switch (s->ch[ch].mode[i]) {
|
454 |
case constant:
|
455 |
a->elem_delta[i] = 0;
|
456 |
a->frame_delta[i] = 0;
|
457 |
break;
|
458 |
case post_incremented:
|
459 |
a->elem_delta[i] = s->ch[ch].data_type; |
460 |
a->frame_delta[i] = 0;
|
461 |
break;
|
462 |
case single_index:
|
463 |
a->elem_delta[i] = s->ch[ch].data_type + |
464 |
s->ch[ch].element_index - 1;
|
465 |
if (s->ch[ch].element_index > 0x7fff) |
466 |
a->elem_delta[i] -= 0x10000;
|
467 |
a->frame_delta[i] = 0;
|
468 |
break;
|
469 |
case double_index:
|
470 |
a->elem_delta[i] = s->ch[ch].data_type + |
471 |
s->ch[ch].element_index - 1;
|
472 |
if (s->ch[ch].element_index > 0x7fff) |
473 |
a->elem_delta[i] -= 0x10000;
|
474 |
a->frame_delta[i] = s->ch[ch].frame_index - |
475 |
s->ch[ch].element_index; |
476 |
if (s->ch[ch].frame_index > 0x7fff) |
477 |
a->frame_delta[i] -= 0x10000;
|
478 |
break;
|
479 |
default:
|
480 |
break;
|
481 |
} |
482 |
} |
483 |
|
484 |
static inline void omap_dma_request_run(struct omap_dma_s *s, |
485 |
int channel, int request) |
486 |
{ |
487 |
next_channel:
|
488 |
if (request > 0) |
489 |
for (; channel < 9; channel ++) |
490 |
if (s->ch[channel].sync == request && s->ch[channel].running)
|
491 |
break;
|
492 |
if (channel >= 9) |
493 |
return;
|
494 |
|
495 |
if (s->ch[channel].transfer) {
|
496 |
if (request > 0) { |
497 |
s->ch[channel ++].post_sync = request; |
498 |
goto next_channel;
|
499 |
} |
500 |
s->ch[channel].status |= 0x02; /* Synchronisation drop */ |
501 |
omap_dma_interrupts_update(s); |
502 |
return;
|
503 |
} |
504 |
|
505 |
if (!s->ch[channel].signalled)
|
506 |
s->run_count ++; |
507 |
s->ch[channel].signalled = 1;
|
508 |
|
509 |
if (request > 0) |
510 |
s->ch[channel].status |= 0x40; /* External request */ |
511 |
|
512 |
if (s->delay && !qemu_timer_pending(s->tm))
|
513 |
qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay); |
514 |
|
515 |
if (request > 0) { |
516 |
channel ++; |
517 |
goto next_channel;
|
518 |
} |
519 |
} |
520 |
|
521 |
static inline void omap_dma_request_stop(struct omap_dma_s *s, int channel) |
522 |
{ |
523 |
if (s->ch[channel].signalled)
|
524 |
s->run_count --; |
525 |
s->ch[channel].signalled = 0;
|
526 |
|
527 |
if (!s->run_count)
|
528 |
qemu_del_timer(s->tm); |
529 |
} |
530 |
|
531 |
static void omap_dma_channel_run(struct omap_dma_s *s) |
532 |
{ |
533 |
int ch;
|
534 |
uint16_t status; |
535 |
uint8_t value[4];
|
536 |
struct omap_dma_port_if_s *src_p, *dest_p;
|
537 |
struct omap_dma_reg_set_s *a;
|
538 |
|
539 |
for (ch = 0; ch < 9; ch ++) { |
540 |
a = &s->ch[ch].active_set; |
541 |
|
542 |
src_p = &s->mpu->port[s->ch[ch].port[0]];
|
543 |
dest_p = &s->mpu->port[s->ch[ch].port[1]];
|
544 |
if (s->ch[ch].signalled && (!src_p->addr_valid(s->mpu, a->src) ||
|
545 |
!dest_p->addr_valid(s->mpu, a->dest))) { |
546 |
#if 0
|
547 |
/* Bus time-out */
|
548 |
if (s->ch[ch].interrupts & 0x01)
|
549 |
s->ch[ch].status |= 0x01;
|
550 |
omap_dma_request_stop(s, ch);
|
551 |
continue;
|
552 |
#endif
|
553 |
printf("%s: Bus time-out in DMA%i operation\n", __FUNCTION__, ch);
|
554 |
} |
555 |
|
556 |
status = s->ch[ch].status; |
557 |
while (status == s->ch[ch].status && s->ch[ch].signalled) {
|
558 |
/* Transfer a single element */
|
559 |
s->ch[ch].transfer = 1;
|
560 |
cpu_physical_memory_read(a->src, value, s->ch[ch].data_type); |
561 |
cpu_physical_memory_write(a->dest, value, s->ch[ch].data_type); |
562 |
s->ch[ch].transfer = 0;
|
563 |
|
564 |
a->src += a->elem_delta[0];
|
565 |
a->dest += a->elem_delta[1];
|
566 |
a->element ++; |
567 |
|
568 |
/* Check interrupt conditions */
|
569 |
if (a->element == a->elements) {
|
570 |
a->element = 0;
|
571 |
a->src += a->frame_delta[0];
|
572 |
a->dest += a->frame_delta[1];
|
573 |
a->frame ++; |
574 |
|
575 |
if (a->frame == a->frames) {
|
576 |
if (!s->ch[ch].repeat || !s->ch[ch].auto_init)
|
577 |
s->ch[ch].running = 0;
|
578 |
|
579 |
if (s->ch[ch].auto_init &&
|
580 |
(s->ch[ch].repeat || |
581 |
s->ch[ch].end_prog)) |
582 |
omap_dma_channel_load(s, ch); |
583 |
|
584 |
if (s->ch[ch].interrupts & 0x20) |
585 |
s->ch[ch].status |= 0x20;
|
586 |
|
587 |
if (!s->ch[ch].sync)
|
588 |
omap_dma_request_stop(s, ch); |
589 |
} |
590 |
|
591 |
if (s->ch[ch].interrupts & 0x08) |
592 |
s->ch[ch].status |= 0x08;
|
593 |
|
594 |
if (s->ch[ch].sync && s->ch[ch].fs &&
|
595 |
!(s->drq & (1 << s->ch[ch].sync))) {
|
596 |
s->ch[ch].status &= ~0x40;
|
597 |
omap_dma_request_stop(s, ch); |
598 |
} |
599 |
} |
600 |
|
601 |
if (a->element == 1 && a->frame == a->frames - 1) |
602 |
if (s->ch[ch].interrupts & 0x10) |
603 |
s->ch[ch].status |= 0x10;
|
604 |
|
605 |
if (a->element == (a->elements >> 1)) |
606 |
if (s->ch[ch].interrupts & 0x04) |
607 |
s->ch[ch].status |= 0x04;
|
608 |
|
609 |
if (s->ch[ch].sync && !s->ch[ch].fs &&
|
610 |
!(s->drq & (1 << s->ch[ch].sync))) {
|
611 |
s->ch[ch].status &= ~0x40;
|
612 |
omap_dma_request_stop(s, ch); |
613 |
} |
614 |
|
615 |
/*
|
616 |
* Process requests made while the element was
|
617 |
* being transferred.
|
618 |
*/
|
619 |
if (s->ch[ch].post_sync) {
|
620 |
omap_dma_request_run(s, 0, s->ch[ch].post_sync);
|
621 |
s->ch[ch].post_sync = 0;
|
622 |
} |
623 |
|
624 |
#if 0
|
625 |
break;
|
626 |
#endif
|
627 |
} |
628 |
|
629 |
s->ch[ch].cpc = a->dest & 0x0000ffff;
|
630 |
} |
631 |
|
632 |
omap_dma_interrupts_update(s); |
633 |
if (s->run_count && s->delay)
|
634 |
qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay); |
635 |
} |
636 |
|
637 |
static int omap_dma_ch_reg_read(struct omap_dma_s *s, |
638 |
int ch, int reg, uint16_t *value) { |
639 |
switch (reg) {
|
640 |
case 0x00: /* SYS_DMA_CSDP_CH0 */ |
641 |
*value = (s->ch[ch].burst[1] << 14) | |
642 |
(s->ch[ch].pack[1] << 13) | |
643 |
(s->ch[ch].port[1] << 9) | |
644 |
(s->ch[ch].burst[0] << 7) | |
645 |
(s->ch[ch].pack[0] << 6) | |
646 |
(s->ch[ch].port[0] << 2) | |
647 |
(s->ch[ch].data_type >> 1);
|
648 |
break;
|
649 |
|
650 |
case 0x02: /* SYS_DMA_CCR_CH0 */ |
651 |
*value = (s->ch[ch].mode[1] << 14) | |
652 |
(s->ch[ch].mode[0] << 12) | |
653 |
(s->ch[ch].end_prog << 11) |
|
654 |
(s->ch[ch].repeat << 9) |
|
655 |
(s->ch[ch].auto_init << 8) |
|
656 |
(s->ch[ch].running << 7) |
|
657 |
(s->ch[ch].priority << 6) |
|
658 |
(s->ch[ch].fs << 5) | s->ch[ch].sync;
|
659 |
break;
|
660 |
|
661 |
case 0x04: /* SYS_DMA_CICR_CH0 */ |
662 |
*value = s->ch[ch].interrupts; |
663 |
break;
|
664 |
|
665 |
case 0x06: /* SYS_DMA_CSR_CH0 */ |
666 |
/* FIXME: shared CSR for channels sharing the interrupts */
|
667 |
*value = s->ch[ch].status; |
668 |
s->ch[ch].status &= 0x40;
|
669 |
omap_dma_interrupts_update(s); |
670 |
break;
|
671 |
|
672 |
case 0x08: /* SYS_DMA_CSSA_L_CH0 */ |
673 |
*value = s->ch[ch].addr[0] & 0x0000ffff; |
674 |
break;
|
675 |
|
676 |
case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ |
677 |
*value = s->ch[ch].addr[0] >> 16; |
678 |
break;
|
679 |
|
680 |
case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ |
681 |
*value = s->ch[ch].addr[1] & 0x0000ffff; |
682 |
break;
|
683 |
|
684 |
case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ |
685 |
*value = s->ch[ch].addr[1] >> 16; |
686 |
break;
|
687 |
|
688 |
case 0x10: /* SYS_DMA_CEN_CH0 */ |
689 |
*value = s->ch[ch].elements; |
690 |
break;
|
691 |
|
692 |
case 0x12: /* SYS_DMA_CFN_CH0 */ |
693 |
*value = s->ch[ch].frames; |
694 |
break;
|
695 |
|
696 |
case 0x14: /* SYS_DMA_CFI_CH0 */ |
697 |
*value = s->ch[ch].frame_index; |
698 |
break;
|
699 |
|
700 |
case 0x16: /* SYS_DMA_CEI_CH0 */ |
701 |
*value = s->ch[ch].element_index; |
702 |
break;
|
703 |
|
704 |
case 0x18: /* SYS_DMA_CPC_CH0 */ |
705 |
*value = s->ch[ch].cpc; |
706 |
break;
|
707 |
|
708 |
default:
|
709 |
return 1; |
710 |
} |
711 |
return 0; |
712 |
} |
713 |
|
714 |
static int omap_dma_ch_reg_write(struct omap_dma_s *s, |
715 |
int ch, int reg, uint16_t value) { |
716 |
switch (reg) {
|
717 |
case 0x00: /* SYS_DMA_CSDP_CH0 */ |
718 |
s->ch[ch].burst[1] = (value & 0xc000) >> 14; |
719 |
s->ch[ch].pack[1] = (value & 0x2000) >> 13; |
720 |
s->ch[ch].port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9); |
721 |
s->ch[ch].burst[0] = (value & 0x0180) >> 7; |
722 |
s->ch[ch].pack[0] = (value & 0x0040) >> 6; |
723 |
s->ch[ch].port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2); |
724 |
s->ch[ch].data_type = (1 << (value & 3)); |
725 |
if (s->ch[ch].port[0] >= omap_dma_port_last) |
726 |
printf("%s: invalid DMA port %i\n", __FUNCTION__,
|
727 |
s->ch[ch].port[0]);
|
728 |
if (s->ch[ch].port[1] >= omap_dma_port_last) |
729 |
printf("%s: invalid DMA port %i\n", __FUNCTION__,
|
730 |
s->ch[ch].port[1]);
|
731 |
if ((value & 3) == 3) |
732 |
printf("%s: bad data_type for DMA channel %i\n", __FUNCTION__, ch);
|
733 |
break;
|
734 |
|
735 |
case 0x02: /* SYS_DMA_CCR_CH0 */ |
736 |
s->ch[ch].mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14); |
737 |
s->ch[ch].mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12); |
738 |
s->ch[ch].end_prog = (value & 0x0800) >> 11; |
739 |
s->ch[ch].repeat = (value & 0x0200) >> 9; |
740 |
s->ch[ch].auto_init = (value & 0x0100) >> 8; |
741 |
s->ch[ch].priority = (value & 0x0040) >> 6; |
742 |
s->ch[ch].fs = (value & 0x0020) >> 5; |
743 |
s->ch[ch].sync = value & 0x001f;
|
744 |
if (value & 0x0080) { |
745 |
if (s->ch[ch].running) {
|
746 |
if (!s->ch[ch].signalled &&
|
747 |
s->ch[ch].auto_init && s->ch[ch].end_prog) |
748 |
omap_dma_channel_load(s, ch); |
749 |
} else {
|
750 |
s->ch[ch].running = 1;
|
751 |
omap_dma_channel_load(s, ch); |
752 |
} |
753 |
if (!s->ch[ch].sync || (s->drq & (1 << s->ch[ch].sync))) |
754 |
omap_dma_request_run(s, ch, 0);
|
755 |
} else {
|
756 |
s->ch[ch].running = 0;
|
757 |
omap_dma_request_stop(s, ch); |
758 |
} |
759 |
break;
|
760 |
|
761 |
case 0x04: /* SYS_DMA_CICR_CH0 */ |
762 |
s->ch[ch].interrupts = value & 0x003f;
|
763 |
break;
|
764 |
|
765 |
case 0x06: /* SYS_DMA_CSR_CH0 */ |
766 |
return 1; |
767 |
|
768 |
case 0x08: /* SYS_DMA_CSSA_L_CH0 */ |
769 |
s->ch[ch].addr[0] &= 0xffff0000; |
770 |
s->ch[ch].addr[0] |= value;
|
771 |
break;
|
772 |
|
773 |
case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ |
774 |
s->ch[ch].addr[0] &= 0x0000ffff; |
775 |
s->ch[ch].addr[0] |= value << 16; |
776 |
break;
|
777 |
|
778 |
case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ |
779 |
s->ch[ch].addr[1] &= 0xffff0000; |
780 |
s->ch[ch].addr[1] |= value;
|
781 |
break;
|
782 |
|
783 |
case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ |
784 |
s->ch[ch].addr[1] &= 0x0000ffff; |
785 |
s->ch[ch].addr[1] |= value << 16; |
786 |
break;
|
787 |
|
788 |
case 0x10: /* SYS_DMA_CEN_CH0 */ |
789 |
s->ch[ch].elements = value & 0xffff;
|
790 |
break;
|
791 |
|
792 |
case 0x12: /* SYS_DMA_CFN_CH0 */ |
793 |
s->ch[ch].frames = value & 0xffff;
|
794 |
break;
|
795 |
|
796 |
case 0x14: /* SYS_DMA_CFI_CH0 */ |
797 |
s->ch[ch].frame_index = value & 0xffff;
|
798 |
break;
|
799 |
|
800 |
case 0x16: /* SYS_DMA_CEI_CH0 */ |
801 |
s->ch[ch].element_index = value & 0xffff;
|
802 |
break;
|
803 |
|
804 |
case 0x18: /* SYS_DMA_CPC_CH0 */ |
805 |
return 1; |
806 |
|
807 |
default:
|
808 |
OMAP_BAD_REG((unsigned long) reg); |
809 |
} |
810 |
return 0; |
811 |
} |
812 |
|
813 |
static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr) |
814 |
{ |
815 |
struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
816 |
int i, reg, ch, offset = addr - s->base;
|
817 |
uint16_t ret; |
818 |
|
819 |
switch (offset) {
|
820 |
case 0x000 ... 0x2fe: |
821 |
reg = offset & 0x3f;
|
822 |
ch = (offset >> 6) & 0x0f; |
823 |
if (omap_dma_ch_reg_read(s, ch, reg, &ret))
|
824 |
break;
|
825 |
return ret;
|
826 |
|
827 |
case 0x300: /* SYS_DMA_LCD_CTRL */ |
828 |
i = s->lcd_ch.condition; |
829 |
s->lcd_ch.condition = 0;
|
830 |
qemu_irq_lower(s->lcd_ch.irq); |
831 |
return ((s->lcd_ch.src == imif) << 6) | (i << 3) | |
832 |
(s->lcd_ch.interrupts << 1) | s->lcd_ch.dual;
|
833 |
|
834 |
case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ |
835 |
return s->lcd_ch.src_f1_top & 0xffff; |
836 |
|
837 |
case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ |
838 |
return s->lcd_ch.src_f1_top >> 16; |
839 |
|
840 |
case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ |
841 |
return s->lcd_ch.src_f1_bottom & 0xffff; |
842 |
|
843 |
case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ |
844 |
return s->lcd_ch.src_f1_bottom >> 16; |
845 |
|
846 |
case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ |
847 |
return s->lcd_ch.src_f2_top & 0xffff; |
848 |
|
849 |
case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ |
850 |
return s->lcd_ch.src_f2_top >> 16; |
851 |
|
852 |
case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ |
853 |
return s->lcd_ch.src_f2_bottom & 0xffff; |
854 |
|
855 |
case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ |
856 |
return s->lcd_ch.src_f2_bottom >> 16; |
857 |
|
858 |
case 0x400: /* SYS_DMA_GCR */ |
859 |
return s->gcr;
|
860 |
} |
861 |
|
862 |
OMAP_BAD_REG(addr); |
863 |
return 0; |
864 |
} |
865 |
|
866 |
static void omap_dma_write(void *opaque, target_phys_addr_t addr, |
867 |
uint32_t value) |
868 |
{ |
869 |
struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
870 |
int reg, ch, offset = addr - s->base;
|
871 |
|
872 |
switch (offset) {
|
873 |
case 0x000 ... 0x2fe: |
874 |
reg = offset & 0x3f;
|
875 |
ch = (offset >> 6) & 0x0f; |
876 |
if (omap_dma_ch_reg_write(s, ch, reg, value))
|
877 |
OMAP_RO_REG(addr); |
878 |
break;
|
879 |
|
880 |
case 0x300: /* SYS_DMA_LCD_CTRL */ |
881 |
s->lcd_ch.src = (value & 0x40) ? imif : emiff;
|
882 |
s->lcd_ch.condition = 0;
|
883 |
/* Assume no bus errors and thus no BUS_ERROR irq bits. */
|
884 |
s->lcd_ch.interrupts = (value >> 1) & 1; |
885 |
s->lcd_ch.dual = value & 1;
|
886 |
break;
|
887 |
|
888 |
case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ |
889 |
s->lcd_ch.src_f1_top &= 0xffff0000;
|
890 |
s->lcd_ch.src_f1_top |= 0x0000ffff & value;
|
891 |
break;
|
892 |
|
893 |
case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ |
894 |
s->lcd_ch.src_f1_top &= 0x0000ffff;
|
895 |
s->lcd_ch.src_f1_top |= value << 16;
|
896 |
break;
|
897 |
|
898 |
case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ |
899 |
s->lcd_ch.src_f1_bottom &= 0xffff0000;
|
900 |
s->lcd_ch.src_f1_bottom |= 0x0000ffff & value;
|
901 |
break;
|
902 |
|
903 |
case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ |
904 |
s->lcd_ch.src_f1_bottom &= 0x0000ffff;
|
905 |
s->lcd_ch.src_f1_bottom |= value << 16;
|
906 |
break;
|
907 |
|
908 |
case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ |
909 |
s->lcd_ch.src_f2_top &= 0xffff0000;
|
910 |
s->lcd_ch.src_f2_top |= 0x0000ffff & value;
|
911 |
break;
|
912 |
|
913 |
case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ |
914 |
s->lcd_ch.src_f2_top &= 0x0000ffff;
|
915 |
s->lcd_ch.src_f2_top |= value << 16;
|
916 |
break;
|
917 |
|
918 |
case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ |
919 |
s->lcd_ch.src_f2_bottom &= 0xffff0000;
|
920 |
s->lcd_ch.src_f2_bottom |= 0x0000ffff & value;
|
921 |
break;
|
922 |
|
923 |
case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ |
924 |
s->lcd_ch.src_f2_bottom &= 0x0000ffff;
|
925 |
s->lcd_ch.src_f2_bottom |= value << 16;
|
926 |
break;
|
927 |
|
928 |
case 0x400: /* SYS_DMA_GCR */ |
929 |
s->gcr = value & 0x000c;
|
930 |
break;
|
931 |
|
932 |
default:
|
933 |
OMAP_BAD_REG(addr); |
934 |
} |
935 |
} |
936 |
|
937 |
static CPUReadMemoryFunc *omap_dma_readfn[] = {
|
938 |
omap_badwidth_read16, |
939 |
omap_dma_read, |
940 |
omap_badwidth_read16, |
941 |
}; |
942 |
|
943 |
static CPUWriteMemoryFunc *omap_dma_writefn[] = {
|
944 |
omap_badwidth_write16, |
945 |
omap_dma_write, |
946 |
omap_badwidth_write16, |
947 |
}; |
948 |
|
949 |
static void omap_dma_request(void *opaque, int drq, int req) |
950 |
{ |
951 |
struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
952 |
/* The request pins are level triggered. */
|
953 |
if (req) {
|
954 |
if (~s->drq & (1 << drq)) { |
955 |
s->drq |= 1 << drq;
|
956 |
omap_dma_request_run(s, 0, drq);
|
957 |
} |
958 |
} else
|
959 |
s->drq &= ~(1 << drq);
|
960 |
} |
961 |
|
962 |
static void omap_dma_clk_update(void *opaque, int line, int on) |
963 |
{ |
964 |
struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
965 |
|
966 |
if (on) {
|
967 |
s->delay = ticks_per_sec >> 5;
|
968 |
if (s->run_count)
|
969 |
qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay); |
970 |
} else {
|
971 |
s->delay = 0;
|
972 |
qemu_del_timer(s->tm); |
973 |
} |
974 |
} |
975 |
|
976 |
static void omap_dma_reset(struct omap_dma_s *s) |
977 |
{ |
978 |
int i;
|
979 |
|
980 |
qemu_del_timer(s->tm); |
981 |
s->gcr = 0x0004;
|
982 |
s->drq = 0x00000000;
|
983 |
s->run_count = 0;
|
984 |
s->lcd_ch.src = emiff; |
985 |
s->lcd_ch.condition = 0;
|
986 |
s->lcd_ch.interrupts = 0;
|
987 |
s->lcd_ch.dual = 0;
|
988 |
memset(s->ch, 0, sizeof(s->ch)); |
989 |
for (i = 0; i < s->chans; i ++) |
990 |
s->ch[i].interrupts = 0x0003;
|
991 |
} |
992 |
|
993 |
struct omap_dma_s *omap_dma_init(target_phys_addr_t base,
|
994 |
qemu_irq pic[], struct omap_mpu_state_s *mpu, omap_clk clk)
|
995 |
{ |
996 |
int iomemtype;
|
997 |
struct omap_dma_s *s = (struct omap_dma_s *) |
998 |
qemu_mallocz(sizeof(struct omap_dma_s)); |
999 |
|
1000 |
s->ih = pic; |
1001 |
s->base = base; |
1002 |
s->chans = 9;
|
1003 |
s->mpu = mpu; |
1004 |
s->clk = clk; |
1005 |
s->lcd_ch.irq = pic[OMAP_INT_DMA_LCD]; |
1006 |
s->lcd_ch.mpu = mpu; |
1007 |
s->tm = qemu_new_timer(vm_clock, (QEMUTimerCB *) omap_dma_channel_run, s); |
1008 |
omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]); |
1009 |
mpu->drq = qemu_allocate_irqs(omap_dma_request, s, 32);
|
1010 |
omap_dma_reset(s); |
1011 |
omap_dma_clk_update(s, 0, 1); |
1012 |
|
1013 |
iomemtype = cpu_register_io_memory(0, omap_dma_readfn,
|
1014 |
omap_dma_writefn, s); |
1015 |
cpu_register_physical_memory(s->base, 0x800, iomemtype);
|
1016 |
|
1017 |
return s;
|
1018 |
} |
1019 |
|
1020 |
/* DMA ports */
|
1021 |
int omap_validate_emiff_addr(struct omap_mpu_state_s *s, |
1022 |
target_phys_addr_t addr) |
1023 |
{ |
1024 |
return addr >= OMAP_EMIFF_BASE && addr < OMAP_EMIFF_BASE + s->sdram_size;
|
1025 |
} |
1026 |
|
1027 |
int omap_validate_emifs_addr(struct omap_mpu_state_s *s, |
1028 |
target_phys_addr_t addr) |
1029 |
{ |
1030 |
return addr >= OMAP_EMIFS_BASE && addr < OMAP_EMIFF_BASE;
|
1031 |
} |
1032 |
|
1033 |
int omap_validate_imif_addr(struct omap_mpu_state_s *s, |
1034 |
target_phys_addr_t addr) |
1035 |
{ |
1036 |
return addr >= OMAP_IMIF_BASE && addr < OMAP_IMIF_BASE + s->sram_size;
|
1037 |
} |
1038 |
|
1039 |
int omap_validate_tipb_addr(struct omap_mpu_state_s *s, |
1040 |
target_phys_addr_t addr) |
1041 |
{ |
1042 |
return addr >= 0xfffb0000 && addr < 0xffff0000; |
1043 |
} |
1044 |
|
1045 |
int omap_validate_local_addr(struct omap_mpu_state_s *s, |
1046 |
target_phys_addr_t addr) |
1047 |
{ |
1048 |
return addr >= OMAP_LOCALBUS_BASE && addr < OMAP_LOCALBUS_BASE + 0x1000000; |
1049 |
} |
1050 |
|
1051 |
int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s, |
1052 |
target_phys_addr_t addr) |
1053 |
{ |
1054 |
return addr >= 0xe1010000 && addr < 0xe1020004; |
1055 |
} |
1056 |
|
1057 |
/* MPU OS timers */
|
1058 |
struct omap_mpu_timer_s {
|
1059 |
qemu_irq irq; |
1060 |
omap_clk clk; |
1061 |
target_phys_addr_t base; |
1062 |
uint32_t val; |
1063 |
int64_t time; |
1064 |
QEMUTimer *timer; |
1065 |
int64_t rate; |
1066 |
int it_ena;
|
1067 |
|
1068 |
int enable;
|
1069 |
int ptv;
|
1070 |
int ar;
|
1071 |
int st;
|
1072 |
uint32_t reset_val; |
1073 |
}; |
1074 |
|
1075 |
static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer) |
1076 |
{ |
1077 |
uint64_t distance = qemu_get_clock(vm_clock) - timer->time; |
1078 |
|
1079 |
if (timer->st && timer->enable && timer->rate)
|
1080 |
return timer->val - muldiv64(distance >> (timer->ptv + 1), |
1081 |
timer->rate, ticks_per_sec); |
1082 |
else
|
1083 |
return timer->val;
|
1084 |
} |
1085 |
|
1086 |
static inline void omap_timer_sync(struct omap_mpu_timer_s *timer) |
1087 |
{ |
1088 |
timer->val = omap_timer_read(timer); |
1089 |
timer->time = qemu_get_clock(vm_clock); |
1090 |
} |
1091 |
|
1092 |
static inline void omap_timer_update(struct omap_mpu_timer_s *timer) |
1093 |
{ |
1094 |
int64_t expires; |
1095 |
|
1096 |
if (timer->enable && timer->st && timer->rate) {
|
1097 |
timer->val = timer->reset_val; /* Should skip this on clk enable */
|
1098 |
expires = timer->time + muldiv64(timer->val << (timer->ptv + 1),
|
1099 |
ticks_per_sec, timer->rate); |
1100 |
qemu_mod_timer(timer->timer, expires); |
1101 |
} else
|
1102 |
qemu_del_timer(timer->timer); |
1103 |
} |
1104 |
|
1105 |
static void omap_timer_tick(void *opaque) |
1106 |
{ |
1107 |
struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque; |
1108 |
omap_timer_sync(timer); |
1109 |
|
1110 |
if (!timer->ar) {
|
1111 |
timer->val = 0;
|
1112 |
timer->st = 0;
|
1113 |
} |
1114 |
|
1115 |
if (timer->it_ena)
|
1116 |
qemu_irq_raise(timer->irq); |
1117 |
omap_timer_update(timer); |
1118 |
} |
1119 |
|
1120 |
static void omap_timer_clk_update(void *opaque, int line, int on) |
1121 |
{ |
1122 |
struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque; |
1123 |
|
1124 |
omap_timer_sync(timer); |
1125 |
timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
|
1126 |
omap_timer_update(timer); |
1127 |
} |
1128 |
|
1129 |
static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer) |
1130 |
{ |
1131 |
omap_clk_adduser(timer->clk, |
1132 |
qemu_allocate_irqs(omap_timer_clk_update, timer, 1)[0]); |
1133 |
timer->rate = omap_clk_getrate(timer->clk); |
1134 |
} |
1135 |
|
1136 |
static uint32_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr) |
1137 |
{ |
1138 |
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; |
1139 |
int offset = addr - s->base;
|
1140 |
|
1141 |
switch (offset) {
|
1142 |
case 0x00: /* CNTL_TIMER */ |
1143 |
return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st; |
1144 |
|
1145 |
case 0x04: /* LOAD_TIM */ |
1146 |
break;
|
1147 |
|
1148 |
case 0x08: /* READ_TIM */ |
1149 |
return omap_timer_read(s);
|
1150 |
} |
1151 |
|
1152 |
OMAP_BAD_REG(addr); |
1153 |
return 0; |
1154 |
} |
1155 |
|
1156 |
static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr, |
1157 |
uint32_t value) |
1158 |
{ |
1159 |
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; |
1160 |
int offset = addr - s->base;
|
1161 |
|
1162 |
switch (offset) {
|
1163 |
case 0x00: /* CNTL_TIMER */ |
1164 |
omap_timer_sync(s); |
1165 |
s->enable = (value >> 5) & 1; |
1166 |
s->ptv = (value >> 2) & 7; |
1167 |
s->ar = (value >> 1) & 1; |
1168 |
s->st = value & 1;
|
1169 |
omap_timer_update(s); |
1170 |
return;
|
1171 |
|
1172 |
case 0x04: /* LOAD_TIM */ |
1173 |
s->reset_val = value; |
1174 |
return;
|
1175 |
|
1176 |
case 0x08: /* READ_TIM */ |
1177 |
OMAP_RO_REG(addr); |
1178 |
break;
|
1179 |
|
1180 |
default:
|
1181 |
OMAP_BAD_REG(addr); |
1182 |
} |
1183 |
} |
1184 |
|
1185 |
static CPUReadMemoryFunc *omap_mpu_timer_readfn[] = {
|
1186 |
omap_badwidth_read32, |
1187 |
omap_badwidth_read32, |
1188 |
omap_mpu_timer_read, |
1189 |
}; |
1190 |
|
1191 |
static CPUWriteMemoryFunc *omap_mpu_timer_writefn[] = {
|
1192 |
omap_badwidth_write32, |
1193 |
omap_badwidth_write32, |
1194 |
omap_mpu_timer_write, |
1195 |
}; |
1196 |
|
1197 |
static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s) |
1198 |
{ |
1199 |
qemu_del_timer(s->timer); |
1200 |
s->enable = 0;
|
1201 |
s->reset_val = 31337;
|
1202 |
s->val = 0;
|
1203 |
s->ptv = 0;
|
1204 |
s->ar = 0;
|
1205 |
s->st = 0;
|
1206 |
s->it_ena = 1;
|
1207 |
} |
1208 |
|
1209 |
struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
|
1210 |
qemu_irq irq, omap_clk clk) |
1211 |
{ |
1212 |
int iomemtype;
|
1213 |
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) |
1214 |
qemu_mallocz(sizeof(struct omap_mpu_timer_s)); |
1215 |
|
1216 |
s->irq = irq; |
1217 |
s->clk = clk; |
1218 |
s->base = base; |
1219 |
s->timer = qemu_new_timer(vm_clock, omap_timer_tick, s); |
1220 |
omap_mpu_timer_reset(s); |
1221 |
omap_timer_clk_setup(s); |
1222 |
|
1223 |
iomemtype = cpu_register_io_memory(0, omap_mpu_timer_readfn,
|
1224 |
omap_mpu_timer_writefn, s); |
1225 |
cpu_register_physical_memory(s->base, 0x100, iomemtype);
|
1226 |
|
1227 |
return s;
|
1228 |
} |
1229 |
|
1230 |
/* Watchdog timer */
|
1231 |
struct omap_watchdog_timer_s {
|
1232 |
struct omap_mpu_timer_s timer;
|
1233 |
uint8_t last_wr; |
1234 |
int mode;
|
1235 |
int free;
|
1236 |
int reset;
|
1237 |
}; |
1238 |
|
1239 |
static uint32_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr) |
1240 |
{ |
1241 |
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; |
1242 |
int offset = addr - s->timer.base;
|
1243 |
|
1244 |
switch (offset) {
|
1245 |
case 0x00: /* CNTL_TIMER */ |
1246 |
return (s->timer.ptv << 9) | (s->timer.ar << 8) | |
1247 |
(s->timer.st << 7) | (s->free << 1); |
1248 |
|
1249 |
case 0x04: /* READ_TIMER */ |
1250 |
return omap_timer_read(&s->timer);
|
1251 |
|
1252 |
case 0x08: /* TIMER_MODE */ |
1253 |
return s->mode << 15; |
1254 |
} |
1255 |
|
1256 |
OMAP_BAD_REG(addr); |
1257 |
return 0; |
1258 |
} |
1259 |
|
1260 |
static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr, |
1261 |
uint32_t value) |
1262 |
{ |
1263 |
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; |
1264 |
int offset = addr - s->timer.base;
|
1265 |
|
1266 |
switch (offset) {
|
1267 |
case 0x00: /* CNTL_TIMER */ |
1268 |
omap_timer_sync(&s->timer); |
1269 |
s->timer.ptv = (value >> 9) & 7; |
1270 |
s->timer.ar = (value >> 8) & 1; |
1271 |
s->timer.st = (value >> 7) & 1; |
1272 |
s->free = (value >> 1) & 1; |
1273 |
omap_timer_update(&s->timer); |
1274 |
break;
|
1275 |
|
1276 |
case 0x04: /* LOAD_TIMER */ |
1277 |
s->timer.reset_val = value & 0xffff;
|
1278 |
break;
|
1279 |
|
1280 |
case 0x08: /* TIMER_MODE */ |
1281 |
if (!s->mode && ((value >> 15) & 1)) |
1282 |
omap_clk_get(s->timer.clk); |
1283 |
s->mode |= (value >> 15) & 1; |
1284 |
if (s->last_wr == 0xf5) { |
1285 |
if ((value & 0xff) == 0xa0) { |
1286 |
s->mode = 0;
|
1287 |
omap_clk_put(s->timer.clk); |
1288 |
} else {
|
1289 |
/* XXX: on T|E hardware somehow this has no effect,
|
1290 |
* on Zire 71 it works as specified. */
|
1291 |
s->reset = 1;
|
1292 |
qemu_system_reset_request(); |
1293 |
} |
1294 |
} |
1295 |
s->last_wr = value & 0xff;
|
1296 |
break;
|
1297 |
|
1298 |
default:
|
1299 |
OMAP_BAD_REG(addr); |
1300 |
} |
1301 |
} |
1302 |
|
1303 |
static CPUReadMemoryFunc *omap_wd_timer_readfn[] = {
|
1304 |
omap_badwidth_read16, |
1305 |
omap_wd_timer_read, |
1306 |
omap_badwidth_read16, |
1307 |
}; |
1308 |
|
1309 |
static CPUWriteMemoryFunc *omap_wd_timer_writefn[] = {
|
1310 |
omap_badwidth_write16, |
1311 |
omap_wd_timer_write, |
1312 |
omap_badwidth_write16, |
1313 |
}; |
1314 |
|
1315 |
static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s) |
1316 |
{ |
1317 |
qemu_del_timer(s->timer.timer); |
1318 |
if (!s->mode)
|
1319 |
omap_clk_get(s->timer.clk); |
1320 |
s->mode = 1;
|
1321 |
s->free = 1;
|
1322 |
s->reset = 0;
|
1323 |
s->timer.enable = 1;
|
1324 |
s->timer.it_ena = 1;
|
1325 |
s->timer.reset_val = 0xffff;
|
1326 |
s->timer.val = 0;
|
1327 |
s->timer.st = 0;
|
1328 |
s->timer.ptv = 0;
|
1329 |
s->timer.ar = 0;
|
1330 |
omap_timer_update(&s->timer); |
1331 |
} |
1332 |
|
1333 |
struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
|
1334 |
qemu_irq irq, omap_clk clk) |
1335 |
{ |
1336 |
int iomemtype;
|
1337 |
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) |
1338 |
qemu_mallocz(sizeof(struct omap_watchdog_timer_s)); |
1339 |
|
1340 |
s->timer.irq = irq; |
1341 |
s->timer.clk = clk; |
1342 |
s->timer.base = base; |
1343 |
s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer); |
1344 |
omap_wd_timer_reset(s); |
1345 |
omap_timer_clk_setup(&s->timer); |
1346 |
|
1347 |
iomemtype = cpu_register_io_memory(0, omap_wd_timer_readfn,
|
1348 |
omap_wd_timer_writefn, s); |
1349 |
cpu_register_physical_memory(s->timer.base, 0x100, iomemtype);
|
1350 |
|
1351 |
return s;
|
1352 |
} |
1353 |
|
1354 |
/* 32-kHz timer */
|
1355 |
struct omap_32khz_timer_s {
|
1356 |
struct omap_mpu_timer_s timer;
|
1357 |
}; |
1358 |
|
1359 |
static uint32_t omap_os_timer_read(void *opaque, target_phys_addr_t addr) |
1360 |
{ |
1361 |
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; |
1362 |
int offset = addr - s->timer.base;
|
1363 |
|
1364 |
switch (offset) {
|
1365 |
case 0x00: /* TVR */ |
1366 |
return s->timer.reset_val;
|
1367 |
|
1368 |
case 0x04: /* TCR */ |
1369 |
return omap_timer_read(&s->timer);
|
1370 |
|
1371 |
case 0x08: /* CR */ |
1372 |
return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st; |
1373 |
|
1374 |
default:
|
1375 |
break;
|
1376 |
} |
1377 |
OMAP_BAD_REG(addr); |
1378 |
return 0; |
1379 |
} |
1380 |
|
1381 |
static void omap_os_timer_write(void *opaque, target_phys_addr_t addr, |
1382 |
uint32_t value) |
1383 |
{ |
1384 |
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; |
1385 |
int offset = addr - s->timer.base;
|
1386 |
|
1387 |
switch (offset) {
|
1388 |
case 0x00: /* TVR */ |
1389 |
s->timer.reset_val = value & 0x00ffffff;
|
1390 |
break;
|
1391 |
|
1392 |
case 0x04: /* TCR */ |
1393 |
OMAP_RO_REG(addr); |
1394 |
break;
|
1395 |
|
1396 |
case 0x08: /* CR */ |
1397 |
s->timer.ar = (value >> 3) & 1; |
1398 |
s->timer.it_ena = (value >> 2) & 1; |
1399 |
if (s->timer.st != (value & 1) || (value & 2)) { |
1400 |
omap_timer_sync(&s->timer); |
1401 |
s->timer.enable = value & 1;
|
1402 |
s->timer.st = value & 1;
|
1403 |
omap_timer_update(&s->timer); |
1404 |
} |
1405 |
break;
|
1406 |
|
1407 |
default:
|
1408 |
OMAP_BAD_REG(addr); |
1409 |
} |
1410 |
} |
1411 |
|
1412 |
static CPUReadMemoryFunc *omap_os_timer_readfn[] = {
|
1413 |
omap_badwidth_read32, |
1414 |
omap_badwidth_read32, |
1415 |
omap_os_timer_read, |
1416 |
}; |
1417 |
|
1418 |
static CPUWriteMemoryFunc *omap_os_timer_writefn[] = {
|
1419 |
omap_badwidth_write32, |
1420 |
omap_badwidth_write32, |
1421 |
omap_os_timer_write, |
1422 |
}; |
1423 |
|
1424 |
static void omap_os_timer_reset(struct omap_32khz_timer_s *s) |
1425 |
{ |
1426 |
qemu_del_timer(s->timer.timer); |
1427 |
s->timer.enable = 0;
|
1428 |
s->timer.it_ena = 0;
|
1429 |
s->timer.reset_val = 0x00ffffff;
|
1430 |
s->timer.val = 0;
|
1431 |
s->timer.st = 0;
|
1432 |
s->timer.ptv = 0;
|
1433 |
s->timer.ar = 1;
|
1434 |
} |
1435 |
|
1436 |
struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
|
1437 |
qemu_irq irq, omap_clk clk) |
1438 |
{ |
1439 |
int iomemtype;
|
1440 |
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) |
1441 |
qemu_mallocz(sizeof(struct omap_32khz_timer_s)); |
1442 |
|
1443 |
s->timer.irq = irq; |
1444 |
s->timer.clk = clk; |
1445 |
s->timer.base = base; |
1446 |
s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer); |
1447 |
omap_os_timer_reset(s); |
1448 |
omap_timer_clk_setup(&s->timer); |
1449 |
|
1450 |
iomemtype = cpu_register_io_memory(0, omap_os_timer_readfn,
|
1451 |
omap_os_timer_writefn, s); |
1452 |
cpu_register_physical_memory(s->timer.base, 0x800, iomemtype);
|
1453 |
|
1454 |
return s;
|
1455 |
} |
1456 |
|
1457 |
/* Ultra Low-Power Device Module */
|
1458 |
static uint32_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr) |
1459 |
{ |
1460 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1461 |
int offset = addr - s->ulpd_pm_base;
|
1462 |
uint16_t ret; |
1463 |
|
1464 |
switch (offset) {
|
1465 |
case 0x14: /* IT_STATUS */ |
1466 |
ret = s->ulpd_pm_regs[offset >> 2];
|
1467 |
s->ulpd_pm_regs[offset >> 2] = 0; |
1468 |
qemu_irq_lower(s->irq[1][OMAP_INT_GAUGE_32K]);
|
1469 |
return ret;
|
1470 |
|
1471 |
case 0x18: /* Reserved */ |
1472 |
case 0x1c: /* Reserved */ |
1473 |
case 0x20: /* Reserved */ |
1474 |
case 0x28: /* Reserved */ |
1475 |
case 0x2c: /* Reserved */ |
1476 |
OMAP_BAD_REG(addr); |
1477 |
case 0x00: /* COUNTER_32_LSB */ |
1478 |
case 0x04: /* COUNTER_32_MSB */ |
1479 |
case 0x08: /* COUNTER_HIGH_FREQ_LSB */ |
1480 |
case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ |
1481 |
case 0x10: /* GAUGING_CTRL */ |
1482 |
case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ |
1483 |
case 0x30: /* CLOCK_CTRL */ |
1484 |
case 0x34: /* SOFT_REQ */ |
1485 |
case 0x38: /* COUNTER_32_FIQ */ |
1486 |
case 0x3c: /* DPLL_CTRL */ |
1487 |
case 0x40: /* STATUS_REQ */ |
1488 |
/* XXX: check clk::usecount state for every clock */
|
1489 |
case 0x48: /* LOCL_TIME */ |
1490 |
case 0x4c: /* APLL_CTRL */ |
1491 |
case 0x50: /* POWER_CTRL */ |
1492 |
return s->ulpd_pm_regs[offset >> 2]; |
1493 |
} |
1494 |
|
1495 |
OMAP_BAD_REG(addr); |
1496 |
return 0; |
1497 |
} |
1498 |
|
1499 |
static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s, |
1500 |
uint16_t diff, uint16_t value) |
1501 |
{ |
1502 |
if (diff & (1 << 4)) /* USB_MCLK_EN */ |
1503 |
omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1); |
1504 |
if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */ |
1505 |
omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1); |
1506 |
} |
1507 |
|
1508 |
static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s, |
1509 |
uint16_t diff, uint16_t value) |
1510 |
{ |
1511 |
if (diff & (1 << 0)) /* SOFT_DPLL_REQ */ |
1512 |
omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1); |
1513 |
if (diff & (1 << 1)) /* SOFT_COM_REQ */ |
1514 |
omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1); |
1515 |
if (diff & (1 << 2)) /* SOFT_SDW_REQ */ |
1516 |
omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1); |
1517 |
if (diff & (1 << 3)) /* SOFT_USB_REQ */ |
1518 |
omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1); |
1519 |
} |
1520 |
|
1521 |
static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr, |
1522 |
uint32_t value) |
1523 |
{ |
1524 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1525 |
int offset = addr - s->ulpd_pm_base;
|
1526 |
int64_t now, ticks; |
1527 |
int div, mult;
|
1528 |
static const int bypass_div[4] = { 1, 2, 4, 4 }; |
1529 |
uint16_t diff; |
1530 |
|
1531 |
switch (offset) {
|
1532 |
case 0x00: /* COUNTER_32_LSB */ |
1533 |
case 0x04: /* COUNTER_32_MSB */ |
1534 |
case 0x08: /* COUNTER_HIGH_FREQ_LSB */ |
1535 |
case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ |
1536 |
case 0x14: /* IT_STATUS */ |
1537 |
case 0x40: /* STATUS_REQ */ |
1538 |
OMAP_RO_REG(addr); |
1539 |
break;
|
1540 |
|
1541 |
case 0x10: /* GAUGING_CTRL */ |
1542 |
/* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */
|
1543 |
if ((s->ulpd_pm_regs[offset >> 2] ^ value) & 1) { |
1544 |
now = qemu_get_clock(vm_clock); |
1545 |
|
1546 |
if (value & 1) |
1547 |
s->ulpd_gauge_start = now; |
1548 |
else {
|
1549 |
now -= s->ulpd_gauge_start; |
1550 |
|
1551 |
/* 32-kHz ticks */
|
1552 |
ticks = muldiv64(now, 32768, ticks_per_sec);
|
1553 |
s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff; |
1554 |
s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff; |
1555 |
if (ticks >> 32) /* OVERFLOW_32K */ |
1556 |
s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2; |
1557 |
|
1558 |
/* High frequency ticks */
|
1559 |
ticks = muldiv64(now, 12000000, ticks_per_sec);
|
1560 |
s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff; |
1561 |
s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff; |
1562 |
if (ticks >> 32) /* OVERFLOW_HI_FREQ */ |
1563 |
s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1; |
1564 |
|
1565 |
s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */ |
1566 |
qemu_irq_raise(s->irq[1][OMAP_INT_GAUGE_32K]);
|
1567 |
} |
1568 |
} |
1569 |
s->ulpd_pm_regs[offset >> 2] = value;
|
1570 |
break;
|
1571 |
|
1572 |
case 0x18: /* Reserved */ |
1573 |
case 0x1c: /* Reserved */ |
1574 |
case 0x20: /* Reserved */ |
1575 |
case 0x28: /* Reserved */ |
1576 |
case 0x2c: /* Reserved */ |
1577 |
OMAP_BAD_REG(addr); |
1578 |
case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ |
1579 |
case 0x38: /* COUNTER_32_FIQ */ |
1580 |
case 0x48: /* LOCL_TIME */ |
1581 |
case 0x50: /* POWER_CTRL */ |
1582 |
s->ulpd_pm_regs[offset >> 2] = value;
|
1583 |
break;
|
1584 |
|
1585 |
case 0x30: /* CLOCK_CTRL */ |
1586 |
diff = s->ulpd_pm_regs[offset >> 2] ^ value;
|
1587 |
s->ulpd_pm_regs[offset >> 2] = value & 0x3f; |
1588 |
omap_ulpd_clk_update(s, diff, value); |
1589 |
break;
|
1590 |
|
1591 |
case 0x34: /* SOFT_REQ */ |
1592 |
diff = s->ulpd_pm_regs[offset >> 2] ^ value;
|
1593 |
s->ulpd_pm_regs[offset >> 2] = value & 0x1f; |
1594 |
omap_ulpd_req_update(s, diff, value); |
1595 |
break;
|
1596 |
|
1597 |
case 0x3c: /* DPLL_CTRL */ |
1598 |
/* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is
|
1599 |
* omitted altogether, probably a typo. */
|
1600 |
/* This register has identical semantics with DPLL(1:3) control
|
1601 |
* registers, see omap_dpll_write() */
|
1602 |
diff = s->ulpd_pm_regs[offset >> 2] & value;
|
1603 |
s->ulpd_pm_regs[offset >> 2] = value & 0x2fff; |
1604 |
if (diff & (0x3ff << 2)) { |
1605 |
if (value & (1 << 4)) { /* PLL_ENABLE */ |
1606 |
div = ((value >> 5) & 3) + 1; /* PLL_DIV */ |
1607 |
mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ |
1608 |
} else {
|
1609 |
div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ |
1610 |
mult = 1;
|
1611 |
} |
1612 |
omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult);
|
1613 |
} |
1614 |
|
1615 |
/* Enter the desired mode. */
|
1616 |
s->ulpd_pm_regs[offset >> 2] =
|
1617 |
(s->ulpd_pm_regs[offset >> 2] & 0xfffe) | |
1618 |
((s->ulpd_pm_regs[offset >> 2] >> 4) & 1); |
1619 |
|
1620 |
/* Act as if the lock is restored. */
|
1621 |
s->ulpd_pm_regs[offset >> 2] |= 2; |
1622 |
break;
|
1623 |
|
1624 |
case 0x4c: /* APLL_CTRL */ |
1625 |
diff = s->ulpd_pm_regs[offset >> 2] & value;
|
1626 |
s->ulpd_pm_regs[offset >> 2] = value & 0xf; |
1627 |
if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */ |
1628 |
omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s,
|
1629 |
(value & (1 << 0)) ? "apll" : "dpll4")); |
1630 |
break;
|
1631 |
|
1632 |
default:
|
1633 |
OMAP_BAD_REG(addr); |
1634 |
} |
1635 |
} |
1636 |
|
1637 |
static CPUReadMemoryFunc *omap_ulpd_pm_readfn[] = {
|
1638 |
omap_badwidth_read16, |
1639 |
omap_ulpd_pm_read, |
1640 |
omap_badwidth_read16, |
1641 |
}; |
1642 |
|
1643 |
static CPUWriteMemoryFunc *omap_ulpd_pm_writefn[] = {
|
1644 |
omap_badwidth_write16, |
1645 |
omap_ulpd_pm_write, |
1646 |
omap_badwidth_write16, |
1647 |
}; |
1648 |
|
1649 |
static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu) |
1650 |
{ |
1651 |
mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001; |
1652 |
mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000; |
1653 |
mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001; |
1654 |
mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000; |
1655 |
mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000; |
1656 |
mpu->ulpd_pm_regs[0x18 >> 2] = 0x01; |
1657 |
mpu->ulpd_pm_regs[0x1c >> 2] = 0x01; |
1658 |
mpu->ulpd_pm_regs[0x20 >> 2] = 0x01; |
1659 |
mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff; |
1660 |
mpu->ulpd_pm_regs[0x28 >> 2] = 0x01; |
1661 |
mpu->ulpd_pm_regs[0x2c >> 2] = 0x01; |
1662 |
omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000); |
1663 |
mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000; |
1664 |
omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000); |
1665 |
mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000; |
1666 |
mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001; |
1667 |
mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211; |
1668 |
mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */ |
1669 |
mpu->ulpd_pm_regs[0x48 >> 2] = 0x960; |
1670 |
mpu->ulpd_pm_regs[0x4c >> 2] = 0x08; |
1671 |
mpu->ulpd_pm_regs[0x50 >> 2] = 0x08; |
1672 |
omap_clk_setrate(omap_findclk(mpu, "dpll4"), 1, 4); |
1673 |
omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4")); |
1674 |
} |
1675 |
|
1676 |
static void omap_ulpd_pm_init(target_phys_addr_t base, |
1677 |
struct omap_mpu_state_s *mpu)
|
1678 |
{ |
1679 |
int iomemtype = cpu_register_io_memory(0, omap_ulpd_pm_readfn, |
1680 |
omap_ulpd_pm_writefn, mpu); |
1681 |
|
1682 |
mpu->ulpd_pm_base = base; |
1683 |
cpu_register_physical_memory(mpu->ulpd_pm_base, 0x800, iomemtype);
|
1684 |
omap_ulpd_pm_reset(mpu); |
1685 |
} |
1686 |
|
1687 |
/* OMAP Pin Configuration */
|
1688 |
static uint32_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr) |
1689 |
{ |
1690 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1691 |
int offset = addr - s->pin_cfg_base;
|
1692 |
|
1693 |
switch (offset) {
|
1694 |
case 0x00: /* FUNC_MUX_CTRL_0 */ |
1695 |
case 0x04: /* FUNC_MUX_CTRL_1 */ |
1696 |
case 0x08: /* FUNC_MUX_CTRL_2 */ |
1697 |
return s->func_mux_ctrl[offset >> 2]; |
1698 |
|
1699 |
case 0x0c: /* COMP_MODE_CTRL_0 */ |
1700 |
return s->comp_mode_ctrl[0]; |
1701 |
|
1702 |
case 0x10: /* FUNC_MUX_CTRL_3 */ |
1703 |
case 0x14: /* FUNC_MUX_CTRL_4 */ |
1704 |
case 0x18: /* FUNC_MUX_CTRL_5 */ |
1705 |
case 0x1c: /* FUNC_MUX_CTRL_6 */ |
1706 |
case 0x20: /* FUNC_MUX_CTRL_7 */ |
1707 |
case 0x24: /* FUNC_MUX_CTRL_8 */ |
1708 |
case 0x28: /* FUNC_MUX_CTRL_9 */ |
1709 |
case 0x2c: /* FUNC_MUX_CTRL_A */ |
1710 |
case 0x30: /* FUNC_MUX_CTRL_B */ |
1711 |
case 0x34: /* FUNC_MUX_CTRL_C */ |
1712 |
case 0x38: /* FUNC_MUX_CTRL_D */ |
1713 |
return s->func_mux_ctrl[(offset >> 2) - 1]; |
1714 |
|
1715 |
case 0x40: /* PULL_DWN_CTRL_0 */ |
1716 |
case 0x44: /* PULL_DWN_CTRL_1 */ |
1717 |
case 0x48: /* PULL_DWN_CTRL_2 */ |
1718 |
case 0x4c: /* PULL_DWN_CTRL_3 */ |
1719 |
return s->pull_dwn_ctrl[(offset & 0xf) >> 2]; |
1720 |
|
1721 |
case 0x50: /* GATE_INH_CTRL_0 */ |
1722 |
return s->gate_inh_ctrl[0]; |
1723 |
|
1724 |
case 0x60: /* VOLTAGE_CTRL_0 */ |
1725 |
return s->voltage_ctrl[0]; |
1726 |
|
1727 |
case 0x70: /* TEST_DBG_CTRL_0 */ |
1728 |
return s->test_dbg_ctrl[0]; |
1729 |
|
1730 |
case 0x80: /* MOD_CONF_CTRL_0 */ |
1731 |
return s->mod_conf_ctrl[0]; |
1732 |
} |
1733 |
|
1734 |
OMAP_BAD_REG(addr); |
1735 |
return 0; |
1736 |
} |
1737 |
|
1738 |
static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s, |
1739 |
uint32_t diff, uint32_t value) |
1740 |
{ |
1741 |
if (s->compat1509) {
|
1742 |
if (diff & (1 << 9)) /* BLUETOOTH */ |
1743 |
omap_clk_onoff(omap_findclk(s, "bt_mclk_out"),
|
1744 |
(~value >> 9) & 1); |
1745 |
if (diff & (1 << 7)) /* USB.CLKO */ |
1746 |
omap_clk_onoff(omap_findclk(s, "usb.clko"),
|
1747 |
(value >> 7) & 1); |
1748 |
} |
1749 |
} |
1750 |
|
1751 |
static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s, |
1752 |
uint32_t diff, uint32_t value) |
1753 |
{ |
1754 |
if (s->compat1509) {
|
1755 |
if (diff & (1 << 31)) /* MCBSP3_CLK_HIZ_DI */ |
1756 |
omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"),
|
1757 |
(value >> 31) & 1); |
1758 |
if (diff & (1 << 1)) /* CLK32K */ |
1759 |
omap_clk_onoff(omap_findclk(s, "clk32k_out"),
|
1760 |
(~value >> 1) & 1); |
1761 |
} |
1762 |
} |
1763 |
|
1764 |
static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s, |
1765 |
uint32_t diff, uint32_t value) |
1766 |
{ |
1767 |
if (diff & (1 << 31)) /* CONF_MOD_UART3_CLK_MODE_R */ |
1768 |
omap_clk_reparent(omap_findclk(s, "uart3_ck"),
|
1769 |
omap_findclk(s, ((value >> 31) & 1) ? |
1770 |
"ck_48m" : "armper_ck")); |
1771 |
if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */ |
1772 |
omap_clk_reparent(omap_findclk(s, "uart2_ck"),
|
1773 |
omap_findclk(s, ((value >> 30) & 1) ? |
1774 |
"ck_48m" : "armper_ck")); |
1775 |
if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */ |
1776 |
omap_clk_reparent(omap_findclk(s, "uart1_ck"),
|
1777 |
omap_findclk(s, ((value >> 29) & 1) ? |
1778 |
"ck_48m" : "armper_ck")); |
1779 |
if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */ |
1780 |
omap_clk_reparent(omap_findclk(s, "mmc_ck"),
|
1781 |
omap_findclk(s, ((value >> 23) & 1) ? |
1782 |
"ck_48m" : "armper_ck")); |
1783 |
if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */ |
1784 |
omap_clk_reparent(omap_findclk(s, "com_mclk_out"),
|
1785 |
omap_findclk(s, ((value >> 12) & 1) ? |
1786 |
"ck_48m" : "armper_ck")); |
1787 |
if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */ |
1788 |
omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1); |
1789 |
} |
1790 |
|
1791 |
static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr, |
1792 |
uint32_t value) |
1793 |
{ |
1794 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1795 |
int offset = addr - s->pin_cfg_base;
|
1796 |
uint32_t diff; |
1797 |
|
1798 |
switch (offset) {
|
1799 |
case 0x00: /* FUNC_MUX_CTRL_0 */ |
1800 |
diff = s->func_mux_ctrl[offset >> 2] ^ value;
|
1801 |
s->func_mux_ctrl[offset >> 2] = value;
|
1802 |
omap_pin_funcmux0_update(s, diff, value); |
1803 |
return;
|
1804 |
|
1805 |
case 0x04: /* FUNC_MUX_CTRL_1 */ |
1806 |
diff = s->func_mux_ctrl[offset >> 2] ^ value;
|
1807 |
s->func_mux_ctrl[offset >> 2] = value;
|
1808 |
omap_pin_funcmux1_update(s, diff, value); |
1809 |
return;
|
1810 |
|
1811 |
case 0x08: /* FUNC_MUX_CTRL_2 */ |
1812 |
s->func_mux_ctrl[offset >> 2] = value;
|
1813 |
return;
|
1814 |
|
1815 |
case 0x0c: /* COMP_MODE_CTRL_0 */ |
1816 |
s->comp_mode_ctrl[0] = value;
|
1817 |
s->compat1509 = (value != 0x0000eaef);
|
1818 |
omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]); |
1819 |
omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]); |
1820 |
return;
|
1821 |
|
1822 |
case 0x10: /* FUNC_MUX_CTRL_3 */ |
1823 |
case 0x14: /* FUNC_MUX_CTRL_4 */ |
1824 |
case 0x18: /* FUNC_MUX_CTRL_5 */ |
1825 |
case 0x1c: /* FUNC_MUX_CTRL_6 */ |
1826 |
case 0x20: /* FUNC_MUX_CTRL_7 */ |
1827 |
case 0x24: /* FUNC_MUX_CTRL_8 */ |
1828 |
case 0x28: /* FUNC_MUX_CTRL_9 */ |
1829 |
case 0x2c: /* FUNC_MUX_CTRL_A */ |
1830 |
case 0x30: /* FUNC_MUX_CTRL_B */ |
1831 |
case 0x34: /* FUNC_MUX_CTRL_C */ |
1832 |
case 0x38: /* FUNC_MUX_CTRL_D */ |
1833 |
s->func_mux_ctrl[(offset >> 2) - 1] = value; |
1834 |
return;
|
1835 |
|
1836 |
case 0x40: /* PULL_DWN_CTRL_0 */ |
1837 |
case 0x44: /* PULL_DWN_CTRL_1 */ |
1838 |
case 0x48: /* PULL_DWN_CTRL_2 */ |
1839 |
case 0x4c: /* PULL_DWN_CTRL_3 */ |
1840 |
s->pull_dwn_ctrl[(offset & 0xf) >> 2] = value; |
1841 |
return;
|
1842 |
|
1843 |
case 0x50: /* GATE_INH_CTRL_0 */ |
1844 |
s->gate_inh_ctrl[0] = value;
|
1845 |
return;
|
1846 |
|
1847 |
case 0x60: /* VOLTAGE_CTRL_0 */ |
1848 |
s->voltage_ctrl[0] = value;
|
1849 |
return;
|
1850 |
|
1851 |
case 0x70: /* TEST_DBG_CTRL_0 */ |
1852 |
s->test_dbg_ctrl[0] = value;
|
1853 |
return;
|
1854 |
|
1855 |
case 0x80: /* MOD_CONF_CTRL_0 */ |
1856 |
diff = s->mod_conf_ctrl[0] ^ value;
|
1857 |
s->mod_conf_ctrl[0] = value;
|
1858 |
omap_pin_modconf1_update(s, diff, value); |
1859 |
return;
|
1860 |
|
1861 |
default:
|
1862 |
OMAP_BAD_REG(addr); |
1863 |
} |
1864 |
} |
1865 |
|
1866 |
static CPUReadMemoryFunc *omap_pin_cfg_readfn[] = {
|
1867 |
omap_badwidth_read32, |
1868 |
omap_badwidth_read32, |
1869 |
omap_pin_cfg_read, |
1870 |
}; |
1871 |
|
1872 |
static CPUWriteMemoryFunc *omap_pin_cfg_writefn[] = {
|
1873 |
omap_badwidth_write32, |
1874 |
omap_badwidth_write32, |
1875 |
omap_pin_cfg_write, |
1876 |
}; |
1877 |
|
1878 |
static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu) |
1879 |
{ |
1880 |
/* Start in Compatibility Mode. */
|
1881 |
mpu->compat1509 = 1;
|
1882 |
omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0); |
1883 |
omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0); |
1884 |
omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0); |
1885 |
memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl)); |
1886 |
memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl)); |
1887 |
memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl)); |
1888 |
memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl)); |
1889 |
memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl)); |
1890 |
memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl)); |
1891 |
memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl)); |
1892 |
} |
1893 |
|
1894 |
static void omap_pin_cfg_init(target_phys_addr_t base, |
1895 |
struct omap_mpu_state_s *mpu)
|
1896 |
{ |
1897 |
int iomemtype = cpu_register_io_memory(0, omap_pin_cfg_readfn, |
1898 |
omap_pin_cfg_writefn, mpu); |
1899 |
|
1900 |
mpu->pin_cfg_base = base; |
1901 |
cpu_register_physical_memory(mpu->pin_cfg_base, 0x800, iomemtype);
|
1902 |
omap_pin_cfg_reset(mpu); |
1903 |
} |
1904 |
|
1905 |
/* Device Identification, Die Identification */
|
1906 |
static uint32_t omap_id_read(void *opaque, target_phys_addr_t addr) |
1907 |
{ |
1908 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1909 |
|
1910 |
switch (addr) {
|
1911 |
case 0xfffe1800: /* DIE_ID_LSB */ |
1912 |
return 0xc9581f0e; |
1913 |
case 0xfffe1804: /* DIE_ID_MSB */ |
1914 |
return 0xa8858bfa; |
1915 |
|
1916 |
case 0xfffe2000: /* PRODUCT_ID_LSB */ |
1917 |
return 0x00aaaafc; |
1918 |
case 0xfffe2004: /* PRODUCT_ID_MSB */ |
1919 |
return 0xcafeb574; |
1920 |
|
1921 |
case 0xfffed400: /* JTAG_ID_LSB */ |
1922 |
switch (s->mpu_model) {
|
1923 |
case omap310:
|
1924 |
return 0x03310315; |
1925 |
case omap1510:
|
1926 |
return 0x03310115; |
1927 |
} |
1928 |
break;
|
1929 |
|
1930 |
case 0xfffed404: /* JTAG_ID_MSB */ |
1931 |
switch (s->mpu_model) {
|
1932 |
case omap310:
|
1933 |
return 0xfb57402f; |
1934 |
case omap1510:
|
1935 |
return 0xfb47002f; |
1936 |
} |
1937 |
break;
|
1938 |
} |
1939 |
|
1940 |
OMAP_BAD_REG(addr); |
1941 |
return 0; |
1942 |
} |
1943 |
|
1944 |
static void omap_id_write(void *opaque, target_phys_addr_t addr, |
1945 |
uint32_t value) |
1946 |
{ |
1947 |
OMAP_BAD_REG(addr); |
1948 |
} |
1949 |
|
1950 |
static CPUReadMemoryFunc *omap_id_readfn[] = {
|
1951 |
omap_badwidth_read32, |
1952 |
omap_badwidth_read32, |
1953 |
omap_id_read, |
1954 |
}; |
1955 |
|
1956 |
static CPUWriteMemoryFunc *omap_id_writefn[] = {
|
1957 |
omap_badwidth_write32, |
1958 |
omap_badwidth_write32, |
1959 |
omap_id_write, |
1960 |
}; |
1961 |
|
1962 |
static void omap_id_init(struct omap_mpu_state_s *mpu) |
1963 |
{ |
1964 |
int iomemtype = cpu_register_io_memory(0, omap_id_readfn, |
1965 |
omap_id_writefn, mpu); |
1966 |
cpu_register_physical_memory(0xfffe1800, 0x800, iomemtype); |
1967 |
cpu_register_physical_memory(0xfffed400, 0x100, iomemtype); |
1968 |
if (!cpu_is_omap15xx(mpu))
|
1969 |
cpu_register_physical_memory(0xfffe2000, 0x800, iomemtype); |
1970 |
} |
1971 |
|
1972 |
/* MPUI Control (Dummy) */
|
1973 |
static uint32_t omap_mpui_read(void *opaque, target_phys_addr_t addr) |
1974 |
{ |
1975 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1976 |
int offset = addr - s->mpui_base;
|
1977 |
|
1978 |
switch (offset) {
|
1979 |
case 0x00: /* CTRL */ |
1980 |
return s->mpui_ctrl;
|
1981 |
case 0x04: /* DEBUG_ADDR */ |
1982 |
return 0x01ffffff; |
1983 |
case 0x08: /* DEBUG_DATA */ |
1984 |
return 0xffffffff; |
1985 |
case 0x0c: /* DEBUG_FLAG */ |
1986 |
return 0x00000800; |
1987 |
case 0x10: /* STATUS */ |
1988 |
return 0x00000000; |
1989 |
|
1990 |
/* Not in OMAP310 */
|
1991 |
case 0x14: /* DSP_STATUS */ |
1992 |
case 0x18: /* DSP_BOOT_CONFIG */ |
1993 |
return 0x00000000; |
1994 |
case 0x1c: /* DSP_MPUI_CONFIG */ |
1995 |
return 0x0000ffff; |
1996 |
} |
1997 |
|
1998 |
OMAP_BAD_REG(addr); |
1999 |
return 0; |
2000 |
} |
2001 |
|
2002 |
static void omap_mpui_write(void *opaque, target_phys_addr_t addr, |
2003 |
uint32_t value) |
2004 |
{ |
2005 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2006 |
int offset = addr - s->mpui_base;
|
2007 |
|
2008 |
switch (offset) {
|
2009 |
case 0x00: /* CTRL */ |
2010 |
s->mpui_ctrl = value & 0x007fffff;
|
2011 |
break;
|
2012 |
|
2013 |
case 0x04: /* DEBUG_ADDR */ |
2014 |
case 0x08: /* DEBUG_DATA */ |
2015 |
case 0x0c: /* DEBUG_FLAG */ |
2016 |
case 0x10: /* STATUS */ |
2017 |
/* Not in OMAP310 */
|
2018 |
case 0x14: /* DSP_STATUS */ |
2019 |
OMAP_RO_REG(addr); |
2020 |
case 0x18: /* DSP_BOOT_CONFIG */ |
2021 |
case 0x1c: /* DSP_MPUI_CONFIG */ |
2022 |
break;
|
2023 |
|
2024 |
default:
|
2025 |
OMAP_BAD_REG(addr); |
2026 |
} |
2027 |
} |
2028 |
|
2029 |
static CPUReadMemoryFunc *omap_mpui_readfn[] = {
|
2030 |
omap_badwidth_read32, |
2031 |
omap_badwidth_read32, |
2032 |
omap_mpui_read, |
2033 |
}; |
2034 |
|
2035 |
static CPUWriteMemoryFunc *omap_mpui_writefn[] = {
|
2036 |
omap_badwidth_write32, |
2037 |
omap_badwidth_write32, |
2038 |
omap_mpui_write, |
2039 |
}; |
2040 |
|
2041 |
static void omap_mpui_reset(struct omap_mpu_state_s *s) |
2042 |
{ |
2043 |
s->mpui_ctrl = 0x0003ff1b;
|
2044 |
} |
2045 |
|
2046 |
static void omap_mpui_init(target_phys_addr_t base, |
2047 |
struct omap_mpu_state_s *mpu)
|
2048 |
{ |
2049 |
int iomemtype = cpu_register_io_memory(0, omap_mpui_readfn, |
2050 |
omap_mpui_writefn, mpu); |
2051 |
|
2052 |
mpu->mpui_base = base; |
2053 |
cpu_register_physical_memory(mpu->mpui_base, 0x100, iomemtype);
|
2054 |
|
2055 |
omap_mpui_reset(mpu); |
2056 |
} |
2057 |
|
2058 |
/* TIPB Bridges */
|
2059 |
struct omap_tipb_bridge_s {
|
2060 |
target_phys_addr_t base; |
2061 |
qemu_irq abort; |
2062 |
|
2063 |
int width_intr;
|
2064 |
uint16_t control; |
2065 |
uint16_t alloc; |
2066 |
uint16_t buffer; |
2067 |
uint16_t enh_control; |
2068 |
}; |
2069 |
|
2070 |
static uint32_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr) |
2071 |
{ |
2072 |
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; |
2073 |
int offset = addr - s->base;
|
2074 |
|
2075 |
switch (offset) {
|
2076 |
case 0x00: /* TIPB_CNTL */ |
2077 |
return s->control;
|
2078 |
case 0x04: /* TIPB_BUS_ALLOC */ |
2079 |
return s->alloc;
|
2080 |
case 0x08: /* MPU_TIPB_CNTL */ |
2081 |
return s->buffer;
|
2082 |
case 0x0c: /* ENHANCED_TIPB_CNTL */ |
2083 |
return s->enh_control;
|
2084 |
case 0x10: /* ADDRESS_DBG */ |
2085 |
case 0x14: /* DATA_DEBUG_LOW */ |
2086 |
case 0x18: /* DATA_DEBUG_HIGH */ |
2087 |
return 0xffff; |
2088 |
case 0x1c: /* DEBUG_CNTR_SIG */ |
2089 |
return 0x00f8; |
2090 |
} |
2091 |
|
2092 |
OMAP_BAD_REG(addr); |
2093 |
return 0; |
2094 |
} |
2095 |
|
2096 |
static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr, |
2097 |
uint32_t value) |
2098 |
{ |
2099 |
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; |
2100 |
int offset = addr - s->base;
|
2101 |
|
2102 |
switch (offset) {
|
2103 |
case 0x00: /* TIPB_CNTL */ |
2104 |
s->control = value & 0xffff;
|
2105 |
break;
|
2106 |
|
2107 |
case 0x04: /* TIPB_BUS_ALLOC */ |
2108 |
s->alloc = value & 0x003f;
|
2109 |
break;
|
2110 |
|
2111 |
case 0x08: /* MPU_TIPB_CNTL */ |
2112 |
s->buffer = value & 0x0003;
|
2113 |
break;
|
2114 |
|
2115 |
case 0x0c: /* ENHANCED_TIPB_CNTL */ |
2116 |
s->width_intr = !(value & 2);
|
2117 |
s->enh_control = value & 0x000f;
|
2118 |
break;
|
2119 |
|
2120 |
case 0x10: /* ADDRESS_DBG */ |
2121 |
case 0x14: /* DATA_DEBUG_LOW */ |
2122 |
case 0x18: /* DATA_DEBUG_HIGH */ |
2123 |
case 0x1c: /* DEBUG_CNTR_SIG */ |
2124 |
OMAP_RO_REG(addr); |
2125 |
break;
|
2126 |
|
2127 |
default:
|
2128 |
OMAP_BAD_REG(addr); |
2129 |
} |
2130 |
} |
2131 |
|
2132 |
static CPUReadMemoryFunc *omap_tipb_bridge_readfn[] = {
|
2133 |
omap_badwidth_read16, |
2134 |
omap_tipb_bridge_read, |
2135 |
omap_tipb_bridge_read, |
2136 |
}; |
2137 |
|
2138 |
static CPUWriteMemoryFunc *omap_tipb_bridge_writefn[] = {
|
2139 |
omap_badwidth_write16, |
2140 |
omap_tipb_bridge_write, |
2141 |
omap_tipb_bridge_write, |
2142 |
}; |
2143 |
|
2144 |
static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s) |
2145 |
{ |
2146 |
s->control = 0xffff;
|
2147 |
s->alloc = 0x0009;
|
2148 |
s->buffer = 0x0000;
|
2149 |
s->enh_control = 0x000f;
|
2150 |
} |
2151 |
|
2152 |
struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
|
2153 |
qemu_irq abort_irq, omap_clk clk) |
2154 |
{ |
2155 |
int iomemtype;
|
2156 |
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) |
2157 |
qemu_mallocz(sizeof(struct omap_tipb_bridge_s)); |
2158 |
|
2159 |
s->abort = abort_irq; |
2160 |
s->base = base; |
2161 |
omap_tipb_bridge_reset(s); |
2162 |
|
2163 |
iomemtype = cpu_register_io_memory(0, omap_tipb_bridge_readfn,
|
2164 |
omap_tipb_bridge_writefn, s); |
2165 |
cpu_register_physical_memory(s->base, 0x100, iomemtype);
|
2166 |
|
2167 |
return s;
|
2168 |
} |
2169 |
|
2170 |
/* Dummy Traffic Controller's Memory Interface */
|
2171 |
static uint32_t omap_tcmi_read(void *opaque, target_phys_addr_t addr) |
2172 |
{ |
2173 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2174 |
int offset = addr - s->tcmi_base;
|
2175 |
uint32_t ret; |
2176 |
|
2177 |
switch (offset) {
|
2178 |
case 0xfffecc00: /* IMIF_PRIO */ |
2179 |
case 0xfffecc04: /* EMIFS_PRIO */ |
2180 |
case 0xfffecc08: /* EMIFF_PRIO */ |
2181 |
case 0xfffecc0c: /* EMIFS_CONFIG */ |
2182 |
case 0xfffecc10: /* EMIFS_CS0_CONFIG */ |
2183 |
case 0xfffecc14: /* EMIFS_CS1_CONFIG */ |
2184 |
case 0xfffecc18: /* EMIFS_CS2_CONFIG */ |
2185 |
case 0xfffecc1c: /* EMIFS_CS3_CONFIG */ |
2186 |
case 0xfffecc24: /* EMIFF_MRS */ |
2187 |
case 0xfffecc28: /* TIMEOUT1 */ |
2188 |
case 0xfffecc2c: /* TIMEOUT2 */ |
2189 |
case 0xfffecc30: /* TIMEOUT3 */ |
2190 |
case 0xfffecc3c: /* EMIFF_SDRAM_CONFIG_2 */ |
2191 |
case 0xfffecc40: /* EMIFS_CFG_DYN_WAIT */ |
2192 |
return s->tcmi_regs[offset >> 2]; |
2193 |
|
2194 |
case 0xfffecc20: /* EMIFF_SDRAM_CONFIG */ |
2195 |
ret = s->tcmi_regs[offset >> 2];
|
2196 |
s->tcmi_regs[offset >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */ |
2197 |
/* XXX: We can try using the VGA_DIRTY flag for this */
|
2198 |
return ret;
|
2199 |
} |
2200 |
|
2201 |
OMAP_BAD_REG(addr); |
2202 |
return 0; |
2203 |
} |
2204 |
|
2205 |
static void omap_tcmi_write(void *opaque, target_phys_addr_t addr, |
2206 |
uint32_t value) |
2207 |
{ |
2208 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2209 |
int offset = addr - s->tcmi_base;
|
2210 |
|
2211 |
switch (offset) {
|
2212 |
case 0xfffecc00: /* IMIF_PRIO */ |
2213 |
case 0xfffecc04: /* EMIFS_PRIO */ |
2214 |
case 0xfffecc08: /* EMIFF_PRIO */ |
2215 |
case 0xfffecc10: /* EMIFS_CS0_CONFIG */ |
2216 |
case 0xfffecc14: /* EMIFS_CS1_CONFIG */ |
2217 |
case 0xfffecc18: /* EMIFS_CS2_CONFIG */ |
2218 |
case 0xfffecc1c: /* EMIFS_CS3_CONFIG */ |
2219 |
case 0xfffecc20: /* EMIFF_SDRAM_CONFIG */ |
2220 |
case 0xfffecc24: /* EMIFF_MRS */ |
2221 |
case 0xfffecc28: /* TIMEOUT1 */ |
2222 |
case 0xfffecc2c: /* TIMEOUT2 */ |
2223 |
case 0xfffecc30: /* TIMEOUT3 */ |
2224 |
case 0xfffecc3c: /* EMIFF_SDRAM_CONFIG_2 */ |
2225 |
case 0xfffecc40: /* EMIFS_CFG_DYN_WAIT */ |
2226 |
s->tcmi_regs[offset >> 2] = value;
|
2227 |
break;
|
2228 |
case 0xfffecc0c: /* EMIFS_CONFIG */ |
2229 |
s->tcmi_regs[offset >> 2] = (value & 0xf) | (1 << 4); |
2230 |
break;
|
2231 |
|
2232 |
default:
|
2233 |
OMAP_BAD_REG(addr); |
2234 |
} |
2235 |
} |
2236 |
|
2237 |
static CPUReadMemoryFunc *omap_tcmi_readfn[] = {
|
2238 |
omap_badwidth_read32, |
2239 |
omap_badwidth_read32, |
2240 |
omap_tcmi_read, |
2241 |
}; |
2242 |
|
2243 |
static CPUWriteMemoryFunc *omap_tcmi_writefn[] = {
|
2244 |
omap_badwidth_write32, |
2245 |
omap_badwidth_write32, |
2246 |
omap_tcmi_write, |
2247 |
}; |
2248 |
|
2249 |
static void omap_tcmi_reset(struct omap_mpu_state_s *mpu) |
2250 |
{ |
2251 |
mpu->tcmi_regs[0x00 >> 2] = 0x00000000; |
2252 |
mpu->tcmi_regs[0x04 >> 2] = 0x00000000; |
2253 |
mpu->tcmi_regs[0x08 >> 2] = 0x00000000; |
2254 |
mpu->tcmi_regs[0x0c >> 2] = 0x00000010; |
2255 |
mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb; |
2256 |
mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb; |
2257 |
mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb; |
2258 |
mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb; |
2259 |
mpu->tcmi_regs[0x20 >> 2] = 0x00618800; |
2260 |
mpu->tcmi_regs[0x24 >> 2] = 0x00000037; |
2261 |
mpu->tcmi_regs[0x28 >> 2] = 0x00000000; |
2262 |
mpu->tcmi_regs[0x2c >> 2] = 0x00000000; |
2263 |
mpu->tcmi_regs[0x30 >> 2] = 0x00000000; |
2264 |
mpu->tcmi_regs[0x3c >> 2] = 0x00000003; |
2265 |
mpu->tcmi_regs[0x40 >> 2] = 0x00000000; |
2266 |
} |
2267 |
|
2268 |
static void omap_tcmi_init(target_phys_addr_t base, |
2269 |
struct omap_mpu_state_s *mpu)
|
2270 |
{ |
2271 |
int iomemtype = cpu_register_io_memory(0, omap_tcmi_readfn, |
2272 |
omap_tcmi_writefn, mpu); |
2273 |
|
2274 |
mpu->tcmi_base = base; |
2275 |
cpu_register_physical_memory(mpu->tcmi_base, 0x100, iomemtype);
|
2276 |
omap_tcmi_reset(mpu); |
2277 |
} |
2278 |
|
2279 |
/* Digital phase-locked loops control */
|
2280 |
static uint32_t omap_dpll_read(void *opaque, target_phys_addr_t addr) |
2281 |
{ |
2282 |
struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; |
2283 |
int offset = addr - s->base;
|
2284 |
|
2285 |
if (offset == 0x00) /* CTL_REG */ |
2286 |
return s->mode;
|
2287 |
|
2288 |
OMAP_BAD_REG(addr); |
2289 |
return 0; |
2290 |
} |
2291 |
|
2292 |
static void omap_dpll_write(void *opaque, target_phys_addr_t addr, |
2293 |
uint32_t value) |
2294 |
{ |
2295 |
struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; |
2296 |
uint16_t diff; |
2297 |
int offset = addr - s->base;
|
2298 |
static const int bypass_div[4] = { 1, 2, 4, 4 }; |
2299 |
int div, mult;
|
2300 |
|
2301 |
if (offset == 0x00) { /* CTL_REG */ |
2302 |
/* See omap_ulpd_pm_write() too */
|
2303 |
diff = s->mode & value; |
2304 |
s->mode = value & 0x2fff;
|
2305 |
if (diff & (0x3ff << 2)) { |
2306 |
if (value & (1 << 4)) { /* PLL_ENABLE */ |
2307 |
div = ((value >> 5) & 3) + 1; /* PLL_DIV */ |
2308 |
mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ |
2309 |
} else {
|
2310 |
div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ |
2311 |
mult = 1;
|
2312 |
} |
2313 |
omap_clk_setrate(s->dpll, div, mult); |
2314 |
} |
2315 |
|
2316 |
/* Enter the desired mode. */
|
2317 |
s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1); |
2318 |
|
2319 |
/* Act as if the lock is restored. */
|
2320 |
s->mode |= 2;
|
2321 |
} else {
|
2322 |
OMAP_BAD_REG(addr); |
2323 |
} |
2324 |
} |
2325 |
|
2326 |
static CPUReadMemoryFunc *omap_dpll_readfn[] = {
|
2327 |
omap_badwidth_read16, |
2328 |
omap_dpll_read, |
2329 |
omap_badwidth_read16, |
2330 |
}; |
2331 |
|
2332 |
static CPUWriteMemoryFunc *omap_dpll_writefn[] = {
|
2333 |
omap_badwidth_write16, |
2334 |
omap_dpll_write, |
2335 |
omap_badwidth_write16, |
2336 |
}; |
2337 |
|
2338 |
static void omap_dpll_reset(struct dpll_ctl_s *s) |
2339 |
{ |
2340 |
s->mode = 0x2002;
|
2341 |
omap_clk_setrate(s->dpll, 1, 1); |
2342 |
} |
2343 |
|
2344 |
static void omap_dpll_init(struct dpll_ctl_s *s, target_phys_addr_t base, |
2345 |
omap_clk clk) |
2346 |
{ |
2347 |
int iomemtype = cpu_register_io_memory(0, omap_dpll_readfn, |
2348 |
omap_dpll_writefn, s); |
2349 |
|
2350 |
s->base = base; |
2351 |
s->dpll = clk; |
2352 |
omap_dpll_reset(s); |
2353 |
|
2354 |
cpu_register_physical_memory(s->base, 0x100, iomemtype);
|
2355 |
} |
2356 |
|
2357 |
/* UARTs */
|
2358 |
struct omap_uart_s {
|
2359 |
SerialState *serial; /* TODO */
|
2360 |
}; |
2361 |
|
2362 |
static void omap_uart_reset(struct omap_uart_s *s) |
2363 |
{ |
2364 |
} |
2365 |
|
2366 |
struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
|
2367 |
qemu_irq irq, omap_clk clk, CharDriverState *chr) |
2368 |
{ |
2369 |
struct omap_uart_s *s = (struct omap_uart_s *) |
2370 |
qemu_mallocz(sizeof(struct omap_uart_s)); |
2371 |
if (chr)
|
2372 |
s->serial = serial_mm_init(base, 2, irq, chr, 1); |
2373 |
return s;
|
2374 |
} |
2375 |
|
2376 |
/* MPU Clock/Reset/Power Mode Control */
|
2377 |
static uint32_t omap_clkm_read(void *opaque, target_phys_addr_t addr) |
2378 |
{ |
2379 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2380 |
int offset = addr - s->clkm.mpu_base;
|
2381 |
|
2382 |
switch (offset) {
|
2383 |
case 0x00: /* ARM_CKCTL */ |
2384 |
return s->clkm.arm_ckctl;
|
2385 |
|
2386 |
case 0x04: /* ARM_IDLECT1 */ |
2387 |
return s->clkm.arm_idlect1;
|
2388 |
|
2389 |
case 0x08: /* ARM_IDLECT2 */ |
2390 |
return s->clkm.arm_idlect2;
|
2391 |
|
2392 |
case 0x0c: /* ARM_EWUPCT */ |
2393 |
return s->clkm.arm_ewupct;
|
2394 |
|
2395 |
case 0x10: /* ARM_RSTCT1 */ |
2396 |
return s->clkm.arm_rstct1;
|
2397 |
|
2398 |
case 0x14: /* ARM_RSTCT2 */ |
2399 |
return s->clkm.arm_rstct2;
|
2400 |
|
2401 |
case 0x18: /* ARM_SYSST */ |
2402 |
return (s->clkm.clocking_scheme < 11) | s->clkm.cold_start; |
2403 |
|
2404 |
case 0x1c: /* ARM_CKOUT1 */ |
2405 |
return s->clkm.arm_ckout1;
|
2406 |
|
2407 |
case 0x20: /* ARM_CKOUT2 */ |
2408 |
break;
|
2409 |
} |
2410 |
|
2411 |
OMAP_BAD_REG(addr); |
2412 |
return 0; |
2413 |
} |
2414 |
|
2415 |
static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s, |
2416 |
uint16_t diff, uint16_t value) |
2417 |
{ |
2418 |
omap_clk clk; |
2419 |
|
2420 |
if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */ |
2421 |
if (value & (1 << 14)) |
2422 |
/* Reserved */;
|
2423 |
else {
|
2424 |
clk = omap_findclk(s, "arminth_ck");
|
2425 |
omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
|
2426 |
} |
2427 |
} |
2428 |
if (diff & (1 << 12)) { /* ARM_TIMXO */ |
2429 |
clk = omap_findclk(s, "armtim_ck");
|
2430 |
if (value & (1 << 12)) |
2431 |
omap_clk_reparent(clk, omap_findclk(s, "clkin"));
|
2432 |
else
|
2433 |
omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
|
2434 |
} |
2435 |
/* XXX: en_dspck */
|
2436 |
if (diff & (3 << 10)) { /* DSPMMUDIV */ |
2437 |
clk = omap_findclk(s, "dspmmu_ck");
|
2438 |
omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1); |
2439 |
} |
2440 |
if (diff & (3 << 8)) { /* TCDIV */ |
2441 |
clk = omap_findclk(s, "tc_ck");
|
2442 |
omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1); |
2443 |
} |
2444 |
if (diff & (3 << 6)) { /* DSPDIV */ |
2445 |
clk = omap_findclk(s, "dsp_ck");
|
2446 |
omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1); |
2447 |
} |
2448 |
if (diff & (3 << 4)) { /* ARMDIV */ |
2449 |
clk = omap_findclk(s, "arm_ck");
|
2450 |
omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1); |
2451 |
} |
2452 |
if (diff & (3 << 2)) { /* LCDDIV */ |
2453 |
clk = omap_findclk(s, "lcd_ck");
|
2454 |
omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1); |
2455 |
} |
2456 |
if (diff & (3 << 0)) { /* PERDIV */ |
2457 |
clk = omap_findclk(s, "armper_ck");
|
2458 |
omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1); |
2459 |
} |
2460 |
} |
2461 |
|
2462 |
static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s, |
2463 |
uint16_t diff, uint16_t value) |
2464 |
{ |
2465 |
omap_clk clk; |
2466 |
|
2467 |
if (value & (1 << 11)) /* SETARM_IDLE */ |
2468 |
cpu_interrupt(s->env, CPU_INTERRUPT_HALT); |
2469 |
if (!(value & (1 << 10))) /* WKUP_MODE */ |
2470 |
qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */
|
2471 |
|
2472 |
#define SET_CANIDLE(clock, bit) \
|
2473 |
if (diff & (1 << bit)) { \ |
2474 |
clk = omap_findclk(s, clock); \ |
2475 |
omap_clk_canidle(clk, (value >> bit) & 1); \
|
2476 |
} |
2477 |
SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */ |
2478 |
SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */ |
2479 |
SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */ |
2480 |
SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */ |
2481 |
SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */ |
2482 |
SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */ |
2483 |
SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */ |
2484 |
SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */ |
2485 |
SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */ |
2486 |
SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */ |
2487 |
SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */ |
2488 |
SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */ |
2489 |
SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */ |
2490 |
SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */ |
2491 |
} |
2492 |
|
2493 |
static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s, |
2494 |
uint16_t diff, uint16_t value) |
2495 |
{ |
2496 |
omap_clk clk; |
2497 |
|
2498 |
#define SET_ONOFF(clock, bit) \
|
2499 |
if (diff & (1 << bit)) { \ |
2500 |
clk = omap_findclk(s, clock); \ |
2501 |
omap_clk_onoff(clk, (value >> bit) & 1); \
|
2502 |
} |
2503 |
SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */ |
2504 |
SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */ |
2505 |
SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */ |
2506 |
SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */ |
2507 |
SET_ONOFF("lb_ck", 4) /* EN_LBCK */ |
2508 |
SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */ |
2509 |
SET_ONOFF("mpui_ck", 6) /* EN_APICK */ |
2510 |
SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */ |
2511 |
SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */ |
2512 |
SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */ |
2513 |
SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */ |
2514 |
} |
2515 |
|
2516 |
static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s, |
2517 |
uint16_t diff, uint16_t value) |
2518 |
{ |
2519 |
omap_clk clk; |
2520 |
|
2521 |
if (diff & (3 << 4)) { /* TCLKOUT */ |
2522 |
clk = omap_findclk(s, "tclk_out");
|
2523 |
switch ((value >> 4) & 3) { |
2524 |
case 1: |
2525 |
omap_clk_reparent(clk, omap_findclk(s, "ck_gen3"));
|
2526 |
omap_clk_onoff(clk, 1);
|
2527 |
break;
|
2528 |
case 2: |
2529 |
omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
|
2530 |
omap_clk_onoff(clk, 1);
|
2531 |
break;
|
2532 |
default:
|
2533 |
omap_clk_onoff(clk, 0);
|
2534 |
} |
2535 |
} |
2536 |
if (diff & (3 << 2)) { /* DCLKOUT */ |
2537 |
clk = omap_findclk(s, "dclk_out");
|
2538 |
switch ((value >> 2) & 3) { |
2539 |
case 0: |
2540 |
omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck"));
|
2541 |
break;
|
2542 |
case 1: |
2543 |
omap_clk_reparent(clk, omap_findclk(s, "ck_gen2"));
|
2544 |
break;
|
2545 |
case 2: |
2546 |
omap_clk_reparent(clk, omap_findclk(s, "dsp_ck"));
|
2547 |
break;
|
2548 |
case 3: |
2549 |
omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
|
2550 |
break;
|
2551 |
} |
2552 |
} |
2553 |
if (diff & (3 << 0)) { /* ACLKOUT */ |
2554 |
clk = omap_findclk(s, "aclk_out");
|
2555 |
switch ((value >> 0) & 3) { |
2556 |
case 1: |
2557 |
omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
|
2558 |
omap_clk_onoff(clk, 1);
|
2559 |
break;
|
2560 |
case 2: |
2561 |
omap_clk_reparent(clk, omap_findclk(s, "arm_ck"));
|
2562 |
omap_clk_onoff(clk, 1);
|
2563 |
break;
|
2564 |
case 3: |
2565 |
omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
|
2566 |
omap_clk_onoff(clk, 1);
|
2567 |
break;
|
2568 |
default:
|
2569 |
omap_clk_onoff(clk, 0);
|
2570 |
} |
2571 |
} |
2572 |
} |
2573 |
|
2574 |
static void omap_clkm_write(void *opaque, target_phys_addr_t addr, |
2575 |
uint32_t value) |
2576 |
{ |
2577 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2578 |
int offset = addr - s->clkm.mpu_base;
|
2579 |
uint16_t diff; |
2580 |
omap_clk clk; |
2581 |
static const char *clkschemename[8] = { |
2582 |
"fully synchronous", "fully asynchronous", "synchronous scalable", |
2583 |
"mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4", |
2584 |
}; |
2585 |
|
2586 |
switch (offset) {
|
2587 |
case 0x00: /* ARM_CKCTL */ |
2588 |
diff = s->clkm.arm_ckctl ^ value; |
2589 |
s->clkm.arm_ckctl = value & 0x7fff;
|
2590 |
omap_clkm_ckctl_update(s, diff, value); |
2591 |
return;
|
2592 |
|
2593 |
case 0x04: /* ARM_IDLECT1 */ |
2594 |
diff = s->clkm.arm_idlect1 ^ value; |
2595 |
s->clkm.arm_idlect1 = value & 0x0fff;
|
2596 |
omap_clkm_idlect1_update(s, diff, value); |
2597 |
return;
|
2598 |
|
2599 |
case 0x08: /* ARM_IDLECT2 */ |
2600 |
diff = s->clkm.arm_idlect2 ^ value; |
2601 |
s->clkm.arm_idlect2 = value & 0x07ff;
|
2602 |
omap_clkm_idlect2_update(s, diff, value); |
2603 |
return;
|
2604 |
|
2605 |
case 0x0c: /* ARM_EWUPCT */ |
2606 |
diff = s->clkm.arm_ewupct ^ value; |
2607 |
s->clkm.arm_ewupct = value & 0x003f;
|
2608 |
return;
|
2609 |
|
2610 |
case 0x10: /* ARM_RSTCT1 */ |
2611 |
diff = s->clkm.arm_rstct1 ^ value; |
2612 |
s->clkm.arm_rstct1 = value & 0x0007;
|
2613 |
if (value & 9) { |
2614 |
qemu_system_reset_request(); |
2615 |
s->clkm.cold_start = 0xa;
|
2616 |
} |
2617 |
if (diff & ~value & 4) { /* DSP_RST */ |
2618 |
omap_mpui_reset(s); |
2619 |
omap_tipb_bridge_reset(s->private_tipb); |
2620 |
omap_tipb_bridge_reset(s->public_tipb); |
2621 |
} |
2622 |
if (diff & 2) { /* DSP_EN */ |
2623 |
clk = omap_findclk(s, "dsp_ck");
|
2624 |
omap_clk_canidle(clk, (~value >> 1) & 1); |
2625 |
} |
2626 |
return;
|
2627 |
|
2628 |
case 0x14: /* ARM_RSTCT2 */ |
2629 |
s->clkm.arm_rstct2 = value & 0x0001;
|
2630 |
return;
|
2631 |
|
2632 |
case 0x18: /* ARM_SYSST */ |
2633 |
if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) { |
2634 |
s->clkm.clocking_scheme = (value >> 11) & 7; |
2635 |
printf("%s: clocking scheme set to %s\n", __FUNCTION__,
|
2636 |
clkschemename[s->clkm.clocking_scheme]); |
2637 |
} |
2638 |
s->clkm.cold_start &= value & 0x3f;
|
2639 |
return;
|
2640 |
|
2641 |
case 0x1c: /* ARM_CKOUT1 */ |
2642 |
diff = s->clkm.arm_ckout1 ^ value; |
2643 |
s->clkm.arm_ckout1 = value & 0x003f;
|
2644 |
omap_clkm_ckout1_update(s, diff, value); |
2645 |
return;
|
2646 |
|
2647 |
case 0x20: /* ARM_CKOUT2 */ |
2648 |
default:
|
2649 |
OMAP_BAD_REG(addr); |
2650 |
} |
2651 |
} |
2652 |
|
2653 |
static CPUReadMemoryFunc *omap_clkm_readfn[] = {
|
2654 |
omap_badwidth_read16, |
2655 |
omap_clkm_read, |
2656 |
omap_badwidth_read16, |
2657 |
}; |
2658 |
|
2659 |
static CPUWriteMemoryFunc *omap_clkm_writefn[] = {
|
2660 |
omap_badwidth_write16, |
2661 |
omap_clkm_write, |
2662 |
omap_badwidth_write16, |
2663 |
}; |
2664 |
|
2665 |
static uint32_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr) |
2666 |
{ |
2667 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2668 |
int offset = addr - s->clkm.dsp_base;
|
2669 |
|
2670 |
switch (offset) {
|
2671 |
case 0x04: /* DSP_IDLECT1 */ |
2672 |
return s->clkm.dsp_idlect1;
|
2673 |
|
2674 |
case 0x08: /* DSP_IDLECT2 */ |
2675 |
return s->clkm.dsp_idlect2;
|
2676 |
|
2677 |
case 0x14: /* DSP_RSTCT2 */ |
2678 |
return s->clkm.dsp_rstct2;
|
2679 |
|
2680 |
case 0x18: /* DSP_SYSST */ |
2681 |
return (s->clkm.clocking_scheme < 11) | s->clkm.cold_start | |
2682 |
(s->env->halted << 6); /* Quite useless... */ |
2683 |
} |
2684 |
|
2685 |
OMAP_BAD_REG(addr); |
2686 |
return 0; |
2687 |
} |
2688 |
|
2689 |
static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s, |
2690 |
uint16_t diff, uint16_t value) |
2691 |
{ |
2692 |
omap_clk clk; |
2693 |
|
2694 |
SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */ |
2695 |
} |
2696 |
|
2697 |
static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s, |
2698 |
uint16_t diff, uint16_t value) |
2699 |
{ |
2700 |
omap_clk clk; |
2701 |
|
2702 |
SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */ |
2703 |
} |
2704 |
|
2705 |
static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr, |
2706 |
uint32_t value) |
2707 |
{ |
2708 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2709 |
int offset = addr - s->clkm.dsp_base;
|
2710 |
uint16_t diff; |
2711 |
|
2712 |
switch (offset) {
|
2713 |
case 0x04: /* DSP_IDLECT1 */ |
2714 |
diff = s->clkm.dsp_idlect1 ^ value; |
2715 |
s->clkm.dsp_idlect1 = value & 0x01f7;
|
2716 |
omap_clkdsp_idlect1_update(s, diff, value); |
2717 |
break;
|
2718 |
|
2719 |
case 0x08: /* DSP_IDLECT2 */ |
2720 |
s->clkm.dsp_idlect2 = value & 0x0037;
|
2721 |
diff = s->clkm.dsp_idlect1 ^ value; |
2722 |
omap_clkdsp_idlect2_update(s, diff, value); |
2723 |
break;
|
2724 |
|
2725 |
case 0x14: /* DSP_RSTCT2 */ |
2726 |
s->clkm.dsp_rstct2 = value & 0x0001;
|
2727 |
break;
|
2728 |
|
2729 |
case 0x18: /* DSP_SYSST */ |
2730 |
s->clkm.cold_start &= value & 0x3f;
|
2731 |
break;
|
2732 |
|
2733 |
default:
|
2734 |
OMAP_BAD_REG(addr); |
2735 |
} |
2736 |
} |
2737 |
|
2738 |
static CPUReadMemoryFunc *omap_clkdsp_readfn[] = {
|
2739 |
omap_badwidth_read16, |
2740 |
omap_clkdsp_read, |
2741 |
omap_badwidth_read16, |
2742 |
}; |
2743 |
|
2744 |
static CPUWriteMemoryFunc *omap_clkdsp_writefn[] = {
|
2745 |
omap_badwidth_write16, |
2746 |
omap_clkdsp_write, |
2747 |
omap_badwidth_write16, |
2748 |
}; |
2749 |
|
2750 |
static void omap_clkm_reset(struct omap_mpu_state_s *s) |
2751 |
{ |
2752 |
if (s->wdt && s->wdt->reset)
|
2753 |
s->clkm.cold_start = 0x6;
|
2754 |
s->clkm.clocking_scheme = 0;
|
2755 |
omap_clkm_ckctl_update(s, ~0, 0x3000); |
2756 |
s->clkm.arm_ckctl = 0x3000;
|
2757 |
omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 & 0x0400, 0x0400); |
2758 |
s->clkm.arm_idlect1 = 0x0400;
|
2759 |
omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 & 0x0100, 0x0100); |
2760 |
s->clkm.arm_idlect2 = 0x0100;
|
2761 |
s->clkm.arm_ewupct = 0x003f;
|
2762 |
s->clkm.arm_rstct1 = 0x0000;
|
2763 |
s->clkm.arm_rstct2 = 0x0000;
|
2764 |
s->clkm.arm_ckout1 = 0x0015;
|
2765 |
s->clkm.dpll1_mode = 0x2002;
|
2766 |
omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040); |
2767 |
s->clkm.dsp_idlect1 = 0x0040;
|
2768 |
omap_clkdsp_idlect2_update(s, ~0, 0x0000); |
2769 |
s->clkm.dsp_idlect2 = 0x0000;
|
2770 |
s->clkm.dsp_rstct2 = 0x0000;
|
2771 |
} |
2772 |
|
2773 |
static void omap_clkm_init(target_phys_addr_t mpu_base, |
2774 |
target_phys_addr_t dsp_base, struct omap_mpu_state_s *s)
|
2775 |
{ |
2776 |
int iomemtype[2] = { |
2777 |
cpu_register_io_memory(0, omap_clkm_readfn, omap_clkm_writefn, s),
|
2778 |
cpu_register_io_memory(0, omap_clkdsp_readfn, omap_clkdsp_writefn, s),
|
2779 |
}; |
2780 |
|
2781 |
s->clkm.mpu_base = mpu_base; |
2782 |
s->clkm.dsp_base = dsp_base; |
2783 |
s->clkm.cold_start = 0x3a;
|
2784 |
omap_clkm_reset(s); |
2785 |
|
2786 |
cpu_register_physical_memory(s->clkm.mpu_base, 0x100, iomemtype[0]); |
2787 |
cpu_register_physical_memory(s->clkm.dsp_base, 0x1000, iomemtype[1]); |
2788 |
} |
2789 |
|
2790 |
/* MPU I/O */
|
2791 |
struct omap_mpuio_s {
|
2792 |
target_phys_addr_t base; |
2793 |
qemu_irq irq; |
2794 |
qemu_irq kbd_irq; |
2795 |
qemu_irq *in; |
2796 |
qemu_irq handler[16];
|
2797 |
qemu_irq wakeup; |
2798 |
|
2799 |
uint16_t inputs; |
2800 |
uint16_t outputs; |
2801 |
uint16_t dir; |
2802 |
uint16_t edge; |
2803 |
uint16_t mask; |
2804 |
uint16_t ints; |
2805 |
|
2806 |
uint16_t debounce; |
2807 |
uint16_t latch; |
2808 |
uint8_t event; |
2809 |
|
2810 |
uint8_t buttons[5];
|
2811 |
uint8_t row_latch; |
2812 |
uint8_t cols; |
2813 |
int kbd_mask;
|
2814 |
int clk;
|
2815 |
}; |
2816 |
|
2817 |
static void omap_mpuio_set(void *opaque, int line, int level) |
2818 |
{ |
2819 |
struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; |
2820 |
uint16_t prev = s->inputs; |
2821 |
|
2822 |
if (level)
|
2823 |
s->inputs |= 1 << line;
|
2824 |
else
|
2825 |
s->inputs &= ~(1 << line);
|
2826 |
|
2827 |
if (((1 << line) & s->dir & ~s->mask) && s->clk) { |
2828 |
if ((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) {
|
2829 |
s->ints |= 1 << line;
|
2830 |
qemu_irq_raise(s->irq); |
2831 |
/* TODO: wakeup */
|
2832 |
} |
2833 |
if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */ |
2834 |
(s->event >> 1) == line) /* PIN_SELECT */ |
2835 |
s->latch = s->inputs; |
2836 |
} |
2837 |
} |
2838 |
|
2839 |
static void omap_mpuio_kbd_update(struct omap_mpuio_s *s) |
2840 |
{ |
2841 |
int i;
|
2842 |
uint8_t *row, rows = 0, cols = ~s->cols;
|
2843 |
|
2844 |
for (row = s->buttons + 4, i = 1 << 4; i; row --, i >>= 1) |
2845 |
if (*row & cols)
|
2846 |
rows |= i; |
2847 |
|
2848 |
qemu_set_irq(s->kbd_irq, rows && ~s->kbd_mask && s->clk); |
2849 |
s->row_latch = rows ^ 0x1f;
|
2850 |
} |
2851 |
|
2852 |
static uint32_t omap_mpuio_read(void *opaque, target_phys_addr_t addr) |
2853 |
{ |
2854 |
struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; |
2855 |
int offset = addr - s->base;
|
2856 |
uint16_t ret; |
2857 |
|
2858 |
switch (offset) {
|
2859 |
case 0x00: /* INPUT_LATCH */ |
2860 |
return s->inputs;
|
2861 |
|
2862 |
case 0x04: /* OUTPUT_REG */ |
2863 |
return s->outputs;
|
2864 |
|
2865 |
case 0x08: /* IO_CNTL */ |
2866 |
return s->dir;
|
2867 |
|
2868 |
case 0x10: /* KBR_LATCH */ |
2869 |
return s->row_latch;
|
2870 |
|
2871 |
case 0x14: /* KBC_REG */ |
2872 |
return s->cols;
|
2873 |
|
2874 |
case 0x18: /* GPIO_EVENT_MODE_REG */ |
2875 |
return s->event;
|
2876 |
|
2877 |
case 0x1c: /* GPIO_INT_EDGE_REG */ |
2878 |
return s->edge;
|
2879 |
|
2880 |
case 0x20: /* KBD_INT */ |
2881 |
return (s->row_latch != 0x1f) && !s->kbd_mask; |
2882 |
|
2883 |
case 0x24: /* GPIO_INT */ |
2884 |
ret = s->ints; |
2885 |
s->ints &= s->mask; |
2886 |
if (ret)
|
2887 |
qemu_irq_lower(s->irq); |
2888 |
return ret;
|
2889 |
|
2890 |
case 0x28: /* KBD_MASKIT */ |
2891 |
return s->kbd_mask;
|
2892 |
|
2893 |
case 0x2c: /* GPIO_MASKIT */ |
2894 |
return s->mask;
|
2895 |
|
2896 |
case 0x30: /* GPIO_DEBOUNCING_REG */ |
2897 |
return s->debounce;
|
2898 |
|
2899 |
case 0x34: /* GPIO_LATCH_REG */ |
2900 |
return s->latch;
|
2901 |
} |
2902 |
|
2903 |
OMAP_BAD_REG(addr); |
2904 |
return 0; |
2905 |
} |
2906 |
|
2907 |
static void omap_mpuio_write(void *opaque, target_phys_addr_t addr, |
2908 |
uint32_t value) |
2909 |
{ |
2910 |
struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; |
2911 |
int offset = addr - s->base;
|
2912 |
uint16_t diff; |
2913 |
int ln;
|
2914 |
|
2915 |
switch (offset) {
|
2916 |
case 0x04: /* OUTPUT_REG */ |
2917 |
diff = s->outputs ^ (value & ~s->dir); |
2918 |
s->outputs = value; |
2919 |
value &= ~s->dir; |
2920 |
while ((ln = ffs(diff))) {
|
2921 |
ln --; |
2922 |
if (s->handler[ln])
|
2923 |
qemu_set_irq(s->handler[ln], (value >> ln) & 1);
|
2924 |
diff &= ~(1 << ln);
|
2925 |
} |
2926 |
break;
|
2927 |
|
2928 |
case 0x08: /* IO_CNTL */ |
2929 |
diff = s->outputs & (s->dir ^ value); |
2930 |
s->dir = value; |
2931 |
|
2932 |
value = s->outputs & ~s->dir; |
2933 |
while ((ln = ffs(diff))) {
|
2934 |
ln --; |
2935 |
if (s->handler[ln])
|
2936 |
qemu_set_irq(s->handler[ln], (value >> ln) & 1);
|
2937 |
diff &= ~(1 << ln);
|
2938 |
} |
2939 |
break;
|
2940 |
|
2941 |
case 0x14: /* KBC_REG */ |
2942 |
s->cols = value; |
2943 |
omap_mpuio_kbd_update(s); |
2944 |
break;
|
2945 |
|
2946 |
case 0x18: /* GPIO_EVENT_MODE_REG */ |
2947 |
s->event = value & 0x1f;
|
2948 |
break;
|
2949 |
|
2950 |
case 0x1c: /* GPIO_INT_EDGE_REG */ |
2951 |
s->edge = value; |
2952 |
break;
|
2953 |
|
2954 |
case 0x28: /* KBD_MASKIT */ |
2955 |
s->kbd_mask = value & 1;
|
2956 |
omap_mpuio_kbd_update(s); |
2957 |
break;
|
2958 |
|
2959 |
case 0x2c: /* GPIO_MASKIT */ |
2960 |
s->mask = value; |
2961 |
break;
|
2962 |
|
2963 |
case 0x30: /* GPIO_DEBOUNCING_REG */ |
2964 |
s->debounce = value & 0x1ff;
|
2965 |
break;
|
2966 |
|
2967 |
case 0x00: /* INPUT_LATCH */ |
2968 |
case 0x10: /* KBR_LATCH */ |
2969 |
case 0x20: /* KBD_INT */ |
2970 |
case 0x24: /* GPIO_INT */ |
2971 |
case 0x34: /* GPIO_LATCH_REG */ |
2972 |
OMAP_RO_REG(addr); |
2973 |
return;
|
2974 |
|
2975 |
default:
|
2976 |
OMAP_BAD_REG(addr); |
2977 |
return;
|
2978 |
} |
2979 |
} |
2980 |
|
2981 |
static CPUReadMemoryFunc *omap_mpuio_readfn[] = {
|
2982 |
omap_badwidth_read16, |
2983 |
omap_mpuio_read, |
2984 |
omap_badwidth_read16, |
2985 |
}; |
2986 |
|
2987 |
static CPUWriteMemoryFunc *omap_mpuio_writefn[] = {
|
2988 |
omap_badwidth_write16, |
2989 |
omap_mpuio_write, |
2990 |
omap_badwidth_write16, |
2991 |
}; |
2992 |
|
2993 |
void omap_mpuio_reset(struct omap_mpuio_s *s) |
2994 |
{ |
2995 |
s->inputs = 0;
|
2996 |
s->outputs = 0;
|
2997 |
s->dir = ~0;
|
2998 |
s->event = 0;
|
2999 |
s->edge = 0;
|
3000 |
s->kbd_mask = 0;
|
3001 |
s->mask = 0;
|
3002 |
s->debounce = 0;
|
3003 |
s->latch = 0;
|
3004 |
s->ints = 0;
|
3005 |
s->row_latch = 0x1f;
|
3006 |
s->clk = 1;
|
3007 |
} |
3008 |
|
3009 |
static void omap_mpuio_onoff(void *opaque, int line, int on) |
3010 |
{ |
3011 |
struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; |
3012 |
|
3013 |
s->clk = on; |
3014 |
if (on)
|
3015 |
omap_mpuio_kbd_update(s); |
3016 |
} |
3017 |
|
3018 |
struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
|
3019 |
qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup, |
3020 |
omap_clk clk) |
3021 |
{ |
3022 |
int iomemtype;
|
3023 |
struct omap_mpuio_s *s = (struct omap_mpuio_s *) |
3024 |
qemu_mallocz(sizeof(struct omap_mpuio_s)); |
3025 |
|
3026 |
s->base = base; |
3027 |
s->irq = gpio_int; |
3028 |
s->kbd_irq = kbd_int; |
3029 |
s->wakeup = wakeup; |
3030 |
s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16);
|
3031 |
omap_mpuio_reset(s); |
3032 |
|
3033 |
iomemtype = cpu_register_io_memory(0, omap_mpuio_readfn,
|
3034 |
omap_mpuio_writefn, s); |
3035 |
cpu_register_physical_memory(s->base, 0x800, iomemtype);
|
3036 |
|
3037 |
omap_clk_adduser(clk, qemu_allocate_irqs(omap_mpuio_onoff, s, 1)[0]); |
3038 |
|
3039 |
return s;
|
3040 |
} |
3041 |
|
3042 |
qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s)
|
3043 |
{ |
3044 |
return s->in;
|
3045 |
} |
3046 |
|
3047 |
void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler) |
3048 |
{ |
3049 |
if (line >= 16 || line < 0) |
3050 |
cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
|
3051 |
s->handler[line] = handler; |
3052 |
} |
3053 |
|
3054 |
void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down) |
3055 |
{ |
3056 |
if (row >= 5 || row < 0) |
3057 |
cpu_abort(cpu_single_env, "%s: No key %i-%i\n",
|
3058 |
__FUNCTION__, col, row); |
3059 |
|
3060 |
if (down)
|
3061 |
s->buttons[row] |= 1 << col;
|
3062 |
else
|
3063 |
s->buttons[row] &= ~(1 << col);
|
3064 |
|
3065 |
omap_mpuio_kbd_update(s); |
3066 |
} |
3067 |
|
3068 |
/* General-Purpose I/O */
|
3069 |
struct omap_gpio_s {
|
3070 |
target_phys_addr_t base; |
3071 |
qemu_irq irq; |
3072 |
qemu_irq *in; |
3073 |
qemu_irq handler[16];
|
3074 |
|
3075 |
uint16_t inputs; |
3076 |
uint16_t outputs; |
3077 |
uint16_t dir; |
3078 |
uint16_t edge; |
3079 |
uint16_t mask; |
3080 |
uint16_t ints; |
3081 |
}; |
3082 |
|
3083 |
static void omap_gpio_set(void *opaque, int line, int level) |
3084 |
{ |
3085 |
struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; |
3086 |
uint16_t prev = s->inputs; |
3087 |
|
3088 |
if (level)
|
3089 |
s->inputs |= 1 << line;
|
3090 |
else
|
3091 |
s->inputs &= ~(1 << line);
|
3092 |
|
3093 |
if (((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) &
|
3094 |
(1 << line) & s->dir & ~s->mask) {
|
3095 |
s->ints |= 1 << line;
|
3096 |
qemu_irq_raise(s->irq); |
3097 |
} |
3098 |
} |
3099 |
|
3100 |
static uint32_t omap_gpio_read(void *opaque, target_phys_addr_t addr) |
3101 |
{ |
3102 |
struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; |
3103 |
int offset = addr - s->base;
|
3104 |
uint16_t ret; |
3105 |
|
3106 |
switch (offset) {
|
3107 |
case 0x00: /* DATA_INPUT */ |
3108 |
return s->inputs;
|
3109 |
|
3110 |
case 0x04: /* DATA_OUTPUT */ |
3111 |
return s->outputs;
|
3112 |
|
3113 |
case 0x08: /* DIRECTION_CONTROL */ |
3114 |
return s->dir;
|
3115 |
|
3116 |
case 0x0c: /* INTERRUPT_CONTROL */ |
3117 |
return s->edge;
|
3118 |
|
3119 |
case 0x10: /* INTERRUPT_MASK */ |
3120 |
return s->mask;
|
3121 |
|
3122 |
case 0x14: /* INTERRUPT_STATUS */ |
3123 |
return s->ints;
|
3124 |
} |
3125 |
|
3126 |
OMAP_BAD_REG(addr); |
3127 |
return 0; |
3128 |
} |
3129 |
|
3130 |
static void omap_gpio_write(void *opaque, target_phys_addr_t addr, |
3131 |
uint32_t value) |
3132 |
{ |
3133 |
struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; |
3134 |
int offset = addr - s->base;
|
3135 |
uint16_t diff; |
3136 |
int ln;
|
3137 |
|
3138 |
switch (offset) {
|
3139 |
case 0x00: /* DATA_INPUT */ |
3140 |
OMAP_RO_REG(addr); |
3141 |
return;
|
3142 |
|
3143 |
case 0x04: /* DATA_OUTPUT */ |
3144 |
diff = s->outputs ^ (value & ~s->dir); |
3145 |
s->outputs = value; |
3146 |
value &= ~s->dir; |
3147 |
while ((ln = ffs(diff))) {
|
3148 |
ln --; |
3149 |
if (s->handler[ln])
|
3150 |
qemu_set_irq(s->handler[ln], (value >> ln) & 1);
|
3151 |
diff &= ~(1 << ln);
|
3152 |
} |
3153 |
break;
|
3154 |
|
3155 |
case 0x08: /* DIRECTION_CONTROL */ |
3156 |
diff = s->outputs & (s->dir ^ value); |
3157 |
s->dir = value; |
3158 |
|
3159 |
value = s->outputs & ~s->dir; |
3160 |
while ((ln = ffs(diff))) {
|
3161 |
ln --; |
3162 |
if (s->handler[ln])
|
3163 |
qemu_set_irq(s->handler[ln], (value >> ln) & 1);
|
3164 |
diff &= ~(1 << ln);
|
3165 |
} |
3166 |
break;
|
3167 |
|
3168 |
case 0x0c: /* INTERRUPT_CONTROL */ |
3169 |
s->edge = value; |
3170 |
break;
|
3171 |
|
3172 |
case 0x10: /* INTERRUPT_MASK */ |
3173 |
s->mask = value; |
3174 |
break;
|
3175 |
|
3176 |
case 0x14: /* INTERRUPT_STATUS */ |
3177 |
s->ints &= ~value; |
3178 |
if (!s->ints)
|
3179 |
qemu_irq_lower(s->irq); |
3180 |
break;
|
3181 |
|
3182 |
default:
|
3183 |
OMAP_BAD_REG(addr); |
3184 |
return;
|
3185 |
} |
3186 |
} |
3187 |
|
3188 |
static CPUReadMemoryFunc *omap_gpio_readfn[] = {
|
3189 |
omap_gpio_read, |
3190 |
omap_badwidth_read32, |
3191 |
omap_badwidth_read32, |
3192 |
}; |
3193 |
|
3194 |
static CPUWriteMemoryFunc *omap_gpio_writefn[] = {
|
3195 |
omap_gpio_write, |
3196 |
omap_badwidth_write32, |
3197 |
omap_badwidth_write32, |
3198 |
}; |
3199 |
|
3200 |
void omap_gpio_reset(struct omap_gpio_s *s) |
3201 |
{ |
3202 |
s->inputs = 0;
|
3203 |
s->outputs = ~0;
|
3204 |
s->dir = ~0;
|
3205 |
s->edge = ~0;
|
3206 |
s->mask = ~0;
|
3207 |
s->ints = 0;
|
3208 |
} |
3209 |
|
3210 |
struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base,
|
3211 |
qemu_irq irq, omap_clk clk) |
3212 |
{ |
3213 |
int iomemtype;
|
3214 |
struct omap_gpio_s *s = (struct omap_gpio_s *) |
3215 |
qemu_mallocz(sizeof(struct omap_gpio_s)); |
3216 |
|
3217 |
s->base = base; |
3218 |
s->irq = irq; |
3219 |
s->in = qemu_allocate_irqs(omap_gpio_set, s, 16);
|
3220 |
omap_gpio_reset(s); |
3221 |
|
3222 |
iomemtype = cpu_register_io_memory(0, omap_gpio_readfn,
|
3223 |
omap_gpio_writefn, s); |
3224 |
cpu_register_physical_memory(s->base, 0x1000, iomemtype);
|
3225 |
|
3226 |
return s;
|
3227 |
} |
3228 |
|
3229 |
qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s)
|
3230 |
{ |
3231 |
return s->in;
|
3232 |
} |
3233 |
|
3234 |
void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler) |
3235 |
{ |
3236 |
if (line >= 16 || line < 0) |
3237 |
cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
|
3238 |
s->handler[line] = handler; |
3239 |
} |
3240 |
|
3241 |
/* General chip reset */
|
3242 |
static void omap_mpu_reset(void *opaque) |
3243 |
{ |
3244 |
struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; |
3245 |
|
3246 |
omap_clkm_reset(mpu); |
3247 |
omap_inth_reset(mpu->ih[0]);
|
3248 |
omap_inth_reset(mpu->ih[1]);
|
3249 |
omap_dma_reset(mpu->dma); |
3250 |
omap_mpu_timer_reset(mpu->timer[0]);
|
3251 |
omap_mpu_timer_reset(mpu->timer[1]);
|
3252 |
omap_mpu_timer_reset(mpu->timer[2]);
|
3253 |
omap_wd_timer_reset(mpu->wdt); |
3254 |
omap_os_timer_reset(mpu->os_timer); |
3255 |
omap_lcdc_reset(mpu->lcd); |
3256 |
omap_ulpd_pm_reset(mpu); |
3257 |
omap_pin_cfg_reset(mpu); |
3258 |
omap_mpui_reset(mpu); |
3259 |
omap_tipb_bridge_reset(mpu->private_tipb); |
3260 |
omap_tipb_bridge_reset(mpu->public_tipb); |
3261 |
omap_dpll_reset(&mpu->dpll[0]);
|
3262 |
omap_dpll_reset(&mpu->dpll[1]);
|
3263 |
omap_dpll_reset(&mpu->dpll[2]);
|
3264 |
omap_uart_reset(mpu->uart1); |
3265 |
omap_uart_reset(mpu->uart2); |
3266 |
omap_uart_reset(mpu->uart3); |
3267 |
omap_mmc_reset(mpu->mmc); |
3268 |
omap_mpuio_reset(mpu->mpuio); |
3269 |
omap_gpio_reset(mpu->gpio); |
3270 |
cpu_reset(mpu->env); |
3271 |
} |
3272 |
|
3273 |
static void omap_mpu_wakeup(void *opaque, int irq, int req) |
3274 |
{ |
3275 |
struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; |
3276 |
|
3277 |
if (mpu->env->halted)
|
3278 |
cpu_interrupt(mpu->env, CPU_INTERRUPT_EXITTB); |
3279 |
} |
3280 |
|
3281 |
struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size, |
3282 |
DisplayState *ds, const char *core) |
3283 |
{ |
3284 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) |
3285 |
qemu_mallocz(sizeof(struct omap_mpu_state_s)); |
3286 |
ram_addr_t imif_base, emiff_base; |
3287 |
|
3288 |
/* Core */
|
3289 |
s->mpu_model = omap310; |
3290 |
s->env = cpu_init(); |
3291 |
s->sdram_size = sdram_size; |
3292 |
s->sram_size = OMAP15XX_SRAM_SIZE; |
3293 |
|
3294 |
cpu_arm_set_model(s->env, core ?: "ti925t");
|
3295 |
|
3296 |
s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0]; |
3297 |
|
3298 |
/* Clocks */
|
3299 |
omap_clk_init(s); |
3300 |
|
3301 |
/* Memory-mapped stuff */
|
3302 |
cpu_register_physical_memory(OMAP_EMIFF_BASE, s->sdram_size, |
3303 |
(emiff_base = qemu_ram_alloc(s->sdram_size)) | IO_MEM_RAM); |
3304 |
cpu_register_physical_memory(OMAP_IMIF_BASE, s->sram_size, |
3305 |
(imif_base = qemu_ram_alloc(s->sram_size)) | IO_MEM_RAM); |
3306 |
|
3307 |
omap_clkm_init(0xfffece00, 0xe1008000, s); |
3308 |
|
3309 |
s->ih[0] = omap_inth_init(0xfffecb00, 0x100, |
3310 |
arm_pic_init_cpu(s->env), |
3311 |
omap_findclk(s, "arminth_ck"));
|
3312 |
s->ih[1] = omap_inth_init(0xfffe0000, 0x800, |
3313 |
&s->ih[0]->pins[OMAP_INT_15XX_IH2_IRQ],
|
3314 |
omap_findclk(s, "arminth_ck"));
|
3315 |
s->irq[0] = s->ih[0]->pins; |
3316 |
s->irq[1] = s->ih[1]->pins; |
3317 |
|
3318 |
s->dma = omap_dma_init(0xfffed800, s->irq[0], s, |
3319 |
omap_findclk(s, "dma_ck"));
|
3320 |
s->port[emiff ].addr_valid = omap_validate_emiff_addr; |
3321 |
s->port[emifs ].addr_valid = omap_validate_emifs_addr; |
3322 |
s->port[imif ].addr_valid = omap_validate_imif_addr; |
3323 |
s->port[tipb ].addr_valid = omap_validate_tipb_addr; |
3324 |
s->port[local ].addr_valid = omap_validate_local_addr; |
3325 |
s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr; |
3326 |
|
3327 |
s->timer[0] = omap_mpu_timer_init(0xfffec500, |
3328 |
s->irq[0][OMAP_INT_TIMER1],
|
3329 |
omap_findclk(s, "mputim_ck"));
|
3330 |
s->timer[1] = omap_mpu_timer_init(0xfffec600, |
3331 |
s->irq[0][OMAP_INT_TIMER2],
|
3332 |
omap_findclk(s, "mputim_ck"));
|
3333 |
s->timer[2] = omap_mpu_timer_init(0xfffec700, |
3334 |
s->irq[0][OMAP_INT_TIMER3],
|
3335 |
omap_findclk(s, "mputim_ck"));
|
3336 |
|
3337 |
s->wdt = omap_wd_timer_init(0xfffec800,
|
3338 |
s->irq[0][OMAP_INT_WD_TIMER],
|
3339 |
omap_findclk(s, "armwdt_ck"));
|
3340 |
|
3341 |
s->os_timer = omap_os_timer_init(0xfffb9000,
|
3342 |
s->irq[1][OMAP_INT_OS_TIMER],
|
3343 |
omap_findclk(s, "clk32-kHz"));
|
3344 |
|
3345 |
s->lcd = omap_lcdc_init(0xfffec000, s->irq[0][OMAP_INT_LCD_CTRL], |
3346 |
&s->dma->lcd_ch, ds, imif_base, emiff_base, |
3347 |
omap_findclk(s, "lcd_ck"));
|
3348 |
|
3349 |
omap_ulpd_pm_init(0xfffe0800, s);
|
3350 |
omap_pin_cfg_init(0xfffe1000, s);
|
3351 |
omap_id_init(s); |
3352 |
|
3353 |
omap_mpui_init(0xfffec900, s);
|
3354 |
|
3355 |
s->private_tipb = omap_tipb_bridge_init(0xfffeca00,
|
3356 |
s->irq[0][OMAP_INT_BRIDGE_PRIV],
|
3357 |
omap_findclk(s, "tipb_ck"));
|
3358 |
s->public_tipb = omap_tipb_bridge_init(0xfffed300,
|
3359 |
s->irq[0][OMAP_INT_BRIDGE_PUB],
|
3360 |
omap_findclk(s, "tipb_ck"));
|
3361 |
|
3362 |
omap_tcmi_init(0xfffecc00, s);
|
3363 |
|
3364 |
s->uart1 = omap_uart_init(0xfffb0000, s->irq[1][OMAP_INT_UART1], |
3365 |
omap_findclk(s, "uart1_ck"),
|
3366 |
serial_hds[0]);
|
3367 |
s->uart2 = omap_uart_init(0xfffb0800, s->irq[1][OMAP_INT_UART2], |
3368 |
omap_findclk(s, "uart2_ck"),
|
3369 |
serial_hds[0] ? serial_hds[1] : 0); |
3370 |
s->uart3 = omap_uart_init(0xe1019800, s->irq[0][OMAP_INT_UART3], |
3371 |
omap_findclk(s, "uart3_ck"),
|
3372 |
serial_hds[0] && serial_hds[1] ? serial_hds[2] : 0); |
3373 |
|
3374 |
omap_dpll_init(&s->dpll[0], 0xfffecf00, omap_findclk(s, "dpll1")); |
3375 |
omap_dpll_init(&s->dpll[1], 0xfffed000, omap_findclk(s, "dpll2")); |
3376 |
omap_dpll_init(&s->dpll[2], 0xfffed100, omap_findclk(s, "dpll3")); |
3377 |
|
3378 |
s->mmc = omap_mmc_init(0xfffb7800, s->irq[1][OMAP_INT_OQN], |
3379 |
&s->drq[OMAP_DMA_MMC_TX], omap_findclk(s, "mmc_ck"));
|
3380 |
|
3381 |
s->mpuio = omap_mpuio_init(0xfffb5000,
|
3382 |
s->irq[1][OMAP_INT_KEYBOARD], s->irq[1][OMAP_INT_MPUIO], |
3383 |
s->wakeup, omap_findclk(s, "clk32-kHz"));
|
3384 |
|
3385 |
s->gpio = omap_gpio_init(0xfffcf000, s->irq[1][OMAP_INT_KEYBOARD], |
3386 |
omap_findclk(s, "mpuper_ck"));
|
3387 |
|
3388 |
qemu_register_reset(omap_mpu_reset, s); |
3389 |
|
3390 |
return s;
|
3391 |
} |