root / hw / i8254.c @ 64d50b8b
History | View | Annotate | Download (13.3 kB)
1 | 80cabfad | bellard | /*
|
---|---|---|---|
2 | 80cabfad | bellard | * QEMU 8253/8254 interval timer emulation
|
3 | 5fafdf24 | ths | *
|
4 | 80cabfad | bellard | * Copyright (c) 2003-2004 Fabrice Bellard
|
5 | 5fafdf24 | ths | *
|
6 | 80cabfad | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 | 80cabfad | bellard | * of this software and associated documentation files (the "Software"), to deal
|
8 | 80cabfad | bellard | * in the Software without restriction, including without limitation the rights
|
9 | 80cabfad | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 | 80cabfad | bellard | * copies of the Software, and to permit persons to whom the Software is
|
11 | 80cabfad | bellard | * furnished to do so, subject to the following conditions:
|
12 | 80cabfad | bellard | *
|
13 | 80cabfad | bellard | * The above copyright notice and this permission notice shall be included in
|
14 | 80cabfad | bellard | * all copies or substantial portions of the Software.
|
15 | 80cabfad | bellard | *
|
16 | 80cabfad | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 | 80cabfad | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 | 80cabfad | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 | 80cabfad | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 | 80cabfad | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 | 80cabfad | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 | 80cabfad | bellard | * THE SOFTWARE.
|
23 | 80cabfad | bellard | */
|
24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "pc.h" |
26 | 87ecb68b | pbrook | #include "isa.h" |
27 | 87ecb68b | pbrook | #include "qemu-timer.h" |
28 | 80cabfad | bellard | |
29 | b0a21b53 | bellard | //#define DEBUG_PIT
|
30 | b0a21b53 | bellard | |
31 | ec844b96 | bellard | #define RW_STATE_LSB 1 |
32 | ec844b96 | bellard | #define RW_STATE_MSB 2 |
33 | ec844b96 | bellard | #define RW_STATE_WORD0 3 |
34 | ec844b96 | bellard | #define RW_STATE_WORD1 4 |
35 | 80cabfad | bellard | |
36 | ec844b96 | bellard | typedef struct PITChannelState { |
37 | ec844b96 | bellard | int count; /* can be 65536 */ |
38 | ec844b96 | bellard | uint16_t latched_count; |
39 | ec844b96 | bellard | uint8_t count_latched; |
40 | ec844b96 | bellard | uint8_t status_latched; |
41 | ec844b96 | bellard | uint8_t status; |
42 | ec844b96 | bellard | uint8_t read_state; |
43 | ec844b96 | bellard | uint8_t write_state; |
44 | ec844b96 | bellard | uint8_t write_latch; |
45 | ec844b96 | bellard | uint8_t rw_mode; |
46 | ec844b96 | bellard | uint8_t mode; |
47 | ec844b96 | bellard | uint8_t bcd; /* not supported */
|
48 | ec844b96 | bellard | uint8_t gate; /* timer start */
|
49 | ec844b96 | bellard | int64_t count_load_time; |
50 | ec844b96 | bellard | /* irq handling */
|
51 | ec844b96 | bellard | int64_t next_transition_time; |
52 | ec844b96 | bellard | QEMUTimer *irq_timer; |
53 | d537cf6c | pbrook | qemu_irq irq; |
54 | ec844b96 | bellard | } PITChannelState; |
55 | ec844b96 | bellard | |
56 | ec844b96 | bellard | struct PITState {
|
57 | ec844b96 | bellard | PITChannelState channels[3];
|
58 | ec844b96 | bellard | }; |
59 | ec844b96 | bellard | |
60 | ec844b96 | bellard | static PITState pit_state;
|
61 | 80cabfad | bellard | |
62 | b0a21b53 | bellard | static void pit_irq_timer_update(PITChannelState *s, int64_t current_time); |
63 | b0a21b53 | bellard | |
64 | 80cabfad | bellard | static int pit_get_count(PITChannelState *s) |
65 | 80cabfad | bellard | { |
66 | 80cabfad | bellard | uint64_t d; |
67 | 80cabfad | bellard | int counter;
|
68 | 80cabfad | bellard | |
69 | b0a21b53 | bellard | d = muldiv64(qemu_get_clock(vm_clock) - s->count_load_time, PIT_FREQ, ticks_per_sec); |
70 | 80cabfad | bellard | switch(s->mode) {
|
71 | 80cabfad | bellard | case 0: |
72 | 80cabfad | bellard | case 1: |
73 | 80cabfad | bellard | case 4: |
74 | 80cabfad | bellard | case 5: |
75 | 80cabfad | bellard | counter = (s->count - d) & 0xffff;
|
76 | 80cabfad | bellard | break;
|
77 | 80cabfad | bellard | case 3: |
78 | 80cabfad | bellard | /* XXX: may be incorrect for odd counts */
|
79 | 80cabfad | bellard | counter = s->count - ((2 * d) % s->count);
|
80 | 80cabfad | bellard | break;
|
81 | 80cabfad | bellard | default:
|
82 | 80cabfad | bellard | counter = s->count - (d % s->count); |
83 | 80cabfad | bellard | break;
|
84 | 80cabfad | bellard | } |
85 | 80cabfad | bellard | return counter;
|
86 | 80cabfad | bellard | } |
87 | 80cabfad | bellard | |
88 | 80cabfad | bellard | /* get pit output bit */
|
89 | ec844b96 | bellard | static int pit_get_out1(PITChannelState *s, int64_t current_time) |
90 | 80cabfad | bellard | { |
91 | 80cabfad | bellard | uint64_t d; |
92 | 80cabfad | bellard | int out;
|
93 | 80cabfad | bellard | |
94 | b0a21b53 | bellard | d = muldiv64(current_time - s->count_load_time, PIT_FREQ, ticks_per_sec); |
95 | 80cabfad | bellard | switch(s->mode) {
|
96 | 80cabfad | bellard | default:
|
97 | 80cabfad | bellard | case 0: |
98 | 80cabfad | bellard | out = (d >= s->count); |
99 | 80cabfad | bellard | break;
|
100 | 80cabfad | bellard | case 1: |
101 | 80cabfad | bellard | out = (d < s->count); |
102 | 80cabfad | bellard | break;
|
103 | 80cabfad | bellard | case 2: |
104 | 80cabfad | bellard | if ((d % s->count) == 0 && d != 0) |
105 | 80cabfad | bellard | out = 1;
|
106 | 80cabfad | bellard | else
|
107 | 80cabfad | bellard | out = 0;
|
108 | 80cabfad | bellard | break;
|
109 | 80cabfad | bellard | case 3: |
110 | 80cabfad | bellard | out = (d % s->count) < ((s->count + 1) >> 1); |
111 | 80cabfad | bellard | break;
|
112 | 80cabfad | bellard | case 4: |
113 | 80cabfad | bellard | case 5: |
114 | 80cabfad | bellard | out = (d == s->count); |
115 | 80cabfad | bellard | break;
|
116 | 80cabfad | bellard | } |
117 | 80cabfad | bellard | return out;
|
118 | 80cabfad | bellard | } |
119 | 80cabfad | bellard | |
120 | ec844b96 | bellard | int pit_get_out(PITState *pit, int channel, int64_t current_time) |
121 | ec844b96 | bellard | { |
122 | ec844b96 | bellard | PITChannelState *s = &pit->channels[channel]; |
123 | ec844b96 | bellard | return pit_get_out1(s, current_time);
|
124 | ec844b96 | bellard | } |
125 | ec844b96 | bellard | |
126 | b0a21b53 | bellard | /* return -1 if no transition will occur. */
|
127 | 5fafdf24 | ths | static int64_t pit_get_next_transition_time(PITChannelState *s,
|
128 | b0a21b53 | bellard | int64_t current_time) |
129 | 80cabfad | bellard | { |
130 | b0a21b53 | bellard | uint64_t d, next_time, base; |
131 | b0a21b53 | bellard | int period2;
|
132 | 80cabfad | bellard | |
133 | b0a21b53 | bellard | d = muldiv64(current_time - s->count_load_time, PIT_FREQ, ticks_per_sec); |
134 | 80cabfad | bellard | switch(s->mode) {
|
135 | 80cabfad | bellard | default:
|
136 | 80cabfad | bellard | case 0: |
137 | 80cabfad | bellard | case 1: |
138 | b0a21b53 | bellard | if (d < s->count)
|
139 | b0a21b53 | bellard | next_time = s->count; |
140 | b0a21b53 | bellard | else
|
141 | b0a21b53 | bellard | return -1; |
142 | 80cabfad | bellard | break;
|
143 | 80cabfad | bellard | case 2: |
144 | b0a21b53 | bellard | base = (d / s->count) * s->count; |
145 | b0a21b53 | bellard | if ((d - base) == 0 && d != 0) |
146 | b0a21b53 | bellard | next_time = base + s->count; |
147 | b0a21b53 | bellard | else
|
148 | b0a21b53 | bellard | next_time = base + s->count + 1;
|
149 | 80cabfad | bellard | break;
|
150 | 80cabfad | bellard | case 3: |
151 | b0a21b53 | bellard | base = (d / s->count) * s->count; |
152 | b0a21b53 | bellard | period2 = ((s->count + 1) >> 1); |
153 | 5fafdf24 | ths | if ((d - base) < period2)
|
154 | b0a21b53 | bellard | next_time = base + period2; |
155 | b0a21b53 | bellard | else
|
156 | b0a21b53 | bellard | next_time = base + s->count; |
157 | 80cabfad | bellard | break;
|
158 | 80cabfad | bellard | case 4: |
159 | 80cabfad | bellard | case 5: |
160 | b0a21b53 | bellard | if (d < s->count)
|
161 | b0a21b53 | bellard | next_time = s->count; |
162 | b0a21b53 | bellard | else if (d == s->count) |
163 | b0a21b53 | bellard | next_time = s->count + 1;
|
164 | 80cabfad | bellard | else
|
165 | b0a21b53 | bellard | return -1; |
166 | 80cabfad | bellard | break;
|
167 | 80cabfad | bellard | } |
168 | b0a21b53 | bellard | /* convert to timer units */
|
169 | b0a21b53 | bellard | next_time = s->count_load_time + muldiv64(next_time, ticks_per_sec, PIT_FREQ); |
170 | 1154e441 | bellard | /* fix potential rounding problems */
|
171 | 1154e441 | bellard | /* XXX: better solution: use a clock at PIT_FREQ Hz */
|
172 | 1154e441 | bellard | if (next_time <= current_time)
|
173 | 1154e441 | bellard | next_time = current_time + 1;
|
174 | b0a21b53 | bellard | return next_time;
|
175 | 80cabfad | bellard | } |
176 | 80cabfad | bellard | |
177 | 80cabfad | bellard | /* val must be 0 or 1 */
|
178 | ec844b96 | bellard | void pit_set_gate(PITState *pit, int channel, int val) |
179 | 80cabfad | bellard | { |
180 | ec844b96 | bellard | PITChannelState *s = &pit->channels[channel]; |
181 | ec844b96 | bellard | |
182 | 80cabfad | bellard | switch(s->mode) {
|
183 | 80cabfad | bellard | default:
|
184 | 80cabfad | bellard | case 0: |
185 | 80cabfad | bellard | case 4: |
186 | 80cabfad | bellard | /* XXX: just disable/enable counting */
|
187 | 80cabfad | bellard | break;
|
188 | 80cabfad | bellard | case 1: |
189 | 80cabfad | bellard | case 5: |
190 | 80cabfad | bellard | if (s->gate < val) {
|
191 | 80cabfad | bellard | /* restart counting on rising edge */
|
192 | b0a21b53 | bellard | s->count_load_time = qemu_get_clock(vm_clock); |
193 | b0a21b53 | bellard | pit_irq_timer_update(s, s->count_load_time); |
194 | 80cabfad | bellard | } |
195 | 80cabfad | bellard | break;
|
196 | 80cabfad | bellard | case 2: |
197 | 80cabfad | bellard | case 3: |
198 | 80cabfad | bellard | if (s->gate < val) {
|
199 | 80cabfad | bellard | /* restart counting on rising edge */
|
200 | b0a21b53 | bellard | s->count_load_time = qemu_get_clock(vm_clock); |
201 | b0a21b53 | bellard | pit_irq_timer_update(s, s->count_load_time); |
202 | 80cabfad | bellard | } |
203 | 80cabfad | bellard | /* XXX: disable/enable counting */
|
204 | 80cabfad | bellard | break;
|
205 | 80cabfad | bellard | } |
206 | 80cabfad | bellard | s->gate = val; |
207 | 80cabfad | bellard | } |
208 | 80cabfad | bellard | |
209 | ec844b96 | bellard | int pit_get_gate(PITState *pit, int channel) |
210 | ec844b96 | bellard | { |
211 | ec844b96 | bellard | PITChannelState *s = &pit->channels[channel]; |
212 | ec844b96 | bellard | return s->gate;
|
213 | ec844b96 | bellard | } |
214 | ec844b96 | bellard | |
215 | fd06c375 | bellard | int pit_get_initial_count(PITState *pit, int channel) |
216 | fd06c375 | bellard | { |
217 | fd06c375 | bellard | PITChannelState *s = &pit->channels[channel]; |
218 | fd06c375 | bellard | return s->count;
|
219 | fd06c375 | bellard | } |
220 | fd06c375 | bellard | |
221 | fd06c375 | bellard | int pit_get_mode(PITState *pit, int channel) |
222 | fd06c375 | bellard | { |
223 | fd06c375 | bellard | PITChannelState *s = &pit->channels[channel]; |
224 | fd06c375 | bellard | return s->mode;
|
225 | fd06c375 | bellard | } |
226 | fd06c375 | bellard | |
227 | 80cabfad | bellard | static inline void pit_load_count(PITChannelState *s, int val) |
228 | 80cabfad | bellard | { |
229 | 80cabfad | bellard | if (val == 0) |
230 | 80cabfad | bellard | val = 0x10000;
|
231 | b0a21b53 | bellard | s->count_load_time = qemu_get_clock(vm_clock); |
232 | 80cabfad | bellard | s->count = val; |
233 | b0a21b53 | bellard | pit_irq_timer_update(s, s->count_load_time); |
234 | 80cabfad | bellard | } |
235 | 80cabfad | bellard | |
236 | ec844b96 | bellard | /* if already latched, do not latch again */
|
237 | ec844b96 | bellard | static void pit_latch_count(PITChannelState *s) |
238 | ec844b96 | bellard | { |
239 | ec844b96 | bellard | if (!s->count_latched) {
|
240 | ec844b96 | bellard | s->latched_count = pit_get_count(s); |
241 | ec844b96 | bellard | s->count_latched = s->rw_mode; |
242 | ec844b96 | bellard | } |
243 | ec844b96 | bellard | } |
244 | ec844b96 | bellard | |
245 | b41a2cd1 | bellard | static void pit_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
246 | 80cabfad | bellard | { |
247 | ec844b96 | bellard | PITState *pit = opaque; |
248 | 80cabfad | bellard | int channel, access;
|
249 | 80cabfad | bellard | PITChannelState *s; |
250 | 80cabfad | bellard | |
251 | 80cabfad | bellard | addr &= 3;
|
252 | 80cabfad | bellard | if (addr == 3) { |
253 | 80cabfad | bellard | channel = val >> 6;
|
254 | ec844b96 | bellard | if (channel == 3) { |
255 | ec844b96 | bellard | /* read back command */
|
256 | ec844b96 | bellard | for(channel = 0; channel < 3; channel++) { |
257 | ec844b96 | bellard | s = &pit->channels[channel]; |
258 | ec844b96 | bellard | if (val & (2 << channel)) { |
259 | ec844b96 | bellard | if (!(val & 0x20)) { |
260 | ec844b96 | bellard | pit_latch_count(s); |
261 | ec844b96 | bellard | } |
262 | ec844b96 | bellard | if (!(val & 0x10) && !s->status_latched) { |
263 | ec844b96 | bellard | /* status latch */
|
264 | ec844b96 | bellard | /* XXX: add BCD and null count */
|
265 | ec844b96 | bellard | s->status = (pit_get_out1(s, qemu_get_clock(vm_clock)) << 7) |
|
266 | ec844b96 | bellard | (s->rw_mode << 4) |
|
267 | ec844b96 | bellard | (s->mode << 1) |
|
268 | ec844b96 | bellard | s->bcd; |
269 | ec844b96 | bellard | s->status_latched = 1;
|
270 | ec844b96 | bellard | } |
271 | ec844b96 | bellard | } |
272 | ec844b96 | bellard | } |
273 | ec844b96 | bellard | } else {
|
274 | ec844b96 | bellard | s = &pit->channels[channel]; |
275 | ec844b96 | bellard | access = (val >> 4) & 3; |
276 | ec844b96 | bellard | if (access == 0) { |
277 | ec844b96 | bellard | pit_latch_count(s); |
278 | ec844b96 | bellard | } else {
|
279 | ec844b96 | bellard | s->rw_mode = access; |
280 | ec844b96 | bellard | s->read_state = access; |
281 | ec844b96 | bellard | s->write_state = access; |
282 | ec844b96 | bellard | |
283 | ec844b96 | bellard | s->mode = (val >> 1) & 7; |
284 | ec844b96 | bellard | s->bcd = val & 1;
|
285 | ec844b96 | bellard | /* XXX: update irq timer ? */
|
286 | ec844b96 | bellard | } |
287 | 80cabfad | bellard | } |
288 | 80cabfad | bellard | } else {
|
289 | ec844b96 | bellard | s = &pit->channels[addr]; |
290 | ec844b96 | bellard | switch(s->write_state) {
|
291 | ec844b96 | bellard | default:
|
292 | 80cabfad | bellard | case RW_STATE_LSB:
|
293 | 80cabfad | bellard | pit_load_count(s, val); |
294 | 80cabfad | bellard | break;
|
295 | 80cabfad | bellard | case RW_STATE_MSB:
|
296 | 80cabfad | bellard | pit_load_count(s, val << 8);
|
297 | 80cabfad | bellard | break;
|
298 | 80cabfad | bellard | case RW_STATE_WORD0:
|
299 | ec844b96 | bellard | s->write_latch = val; |
300 | ec844b96 | bellard | s->write_state = RW_STATE_WORD1; |
301 | ec844b96 | bellard | break;
|
302 | 80cabfad | bellard | case RW_STATE_WORD1:
|
303 | ec844b96 | bellard | pit_load_count(s, s->write_latch | (val << 8));
|
304 | ec844b96 | bellard | s->write_state = RW_STATE_WORD0; |
305 | 80cabfad | bellard | break;
|
306 | 80cabfad | bellard | } |
307 | 80cabfad | bellard | } |
308 | 80cabfad | bellard | } |
309 | 80cabfad | bellard | |
310 | b41a2cd1 | bellard | static uint32_t pit_ioport_read(void *opaque, uint32_t addr) |
311 | 80cabfad | bellard | { |
312 | ec844b96 | bellard | PITState *pit = opaque; |
313 | 80cabfad | bellard | int ret, count;
|
314 | 80cabfad | bellard | PITChannelState *s; |
315 | 3b46e624 | ths | |
316 | 80cabfad | bellard | addr &= 3;
|
317 | ec844b96 | bellard | s = &pit->channels[addr]; |
318 | ec844b96 | bellard | if (s->status_latched) {
|
319 | ec844b96 | bellard | s->status_latched = 0;
|
320 | ec844b96 | bellard | ret = s->status; |
321 | ec844b96 | bellard | } else if (s->count_latched) { |
322 | ec844b96 | bellard | switch(s->count_latched) {
|
323 | ec844b96 | bellard | default:
|
324 | ec844b96 | bellard | case RW_STATE_LSB:
|
325 | ec844b96 | bellard | ret = s->latched_count & 0xff;
|
326 | ec844b96 | bellard | s->count_latched = 0;
|
327 | ec844b96 | bellard | break;
|
328 | ec844b96 | bellard | case RW_STATE_MSB:
|
329 | 80cabfad | bellard | ret = s->latched_count >> 8;
|
330 | ec844b96 | bellard | s->count_latched = 0;
|
331 | ec844b96 | bellard | break;
|
332 | ec844b96 | bellard | case RW_STATE_WORD0:
|
333 | 80cabfad | bellard | ret = s->latched_count & 0xff;
|
334 | ec844b96 | bellard | s->count_latched = RW_STATE_MSB; |
335 | ec844b96 | bellard | break;
|
336 | ec844b96 | bellard | } |
337 | ec844b96 | bellard | } else {
|
338 | ec844b96 | bellard | switch(s->read_state) {
|
339 | ec844b96 | bellard | default:
|
340 | ec844b96 | bellard | case RW_STATE_LSB:
|
341 | ec844b96 | bellard | count = pit_get_count(s); |
342 | ec844b96 | bellard | ret = count & 0xff;
|
343 | ec844b96 | bellard | break;
|
344 | ec844b96 | bellard | case RW_STATE_MSB:
|
345 | ec844b96 | bellard | count = pit_get_count(s); |
346 | ec844b96 | bellard | ret = (count >> 8) & 0xff; |
347 | ec844b96 | bellard | break;
|
348 | ec844b96 | bellard | case RW_STATE_WORD0:
|
349 | ec844b96 | bellard | count = pit_get_count(s); |
350 | ec844b96 | bellard | ret = count & 0xff;
|
351 | ec844b96 | bellard | s->read_state = RW_STATE_WORD1; |
352 | ec844b96 | bellard | break;
|
353 | ec844b96 | bellard | case RW_STATE_WORD1:
|
354 | ec844b96 | bellard | count = pit_get_count(s); |
355 | ec844b96 | bellard | ret = (count >> 8) & 0xff; |
356 | ec844b96 | bellard | s->read_state = RW_STATE_WORD0; |
357 | ec844b96 | bellard | break;
|
358 | ec844b96 | bellard | } |
359 | 80cabfad | bellard | } |
360 | 80cabfad | bellard | return ret;
|
361 | 80cabfad | bellard | } |
362 | 80cabfad | bellard | |
363 | b0a21b53 | bellard | static void pit_irq_timer_update(PITChannelState *s, int64_t current_time) |
364 | b0a21b53 | bellard | { |
365 | b0a21b53 | bellard | int64_t expire_time; |
366 | b0a21b53 | bellard | int irq_level;
|
367 | b0a21b53 | bellard | |
368 | b0a21b53 | bellard | if (!s->irq_timer)
|
369 | b0a21b53 | bellard | return;
|
370 | b0a21b53 | bellard | expire_time = pit_get_next_transition_time(s, current_time); |
371 | ec844b96 | bellard | irq_level = pit_get_out1(s, current_time); |
372 | d537cf6c | pbrook | qemu_set_irq(s->irq, irq_level); |
373 | b0a21b53 | bellard | #ifdef DEBUG_PIT
|
374 | b0a21b53 | bellard | printf("irq_level=%d next_delay=%f\n",
|
375 | 5fafdf24 | ths | irq_level, |
376 | b0a21b53 | bellard | (double)(expire_time - current_time) / ticks_per_sec);
|
377 | b0a21b53 | bellard | #endif
|
378 | b0a21b53 | bellard | s->next_transition_time = expire_time; |
379 | b0a21b53 | bellard | if (expire_time != -1) |
380 | b0a21b53 | bellard | qemu_mod_timer(s->irq_timer, expire_time); |
381 | b0a21b53 | bellard | else
|
382 | b0a21b53 | bellard | qemu_del_timer(s->irq_timer); |
383 | b0a21b53 | bellard | } |
384 | b0a21b53 | bellard | |
385 | b0a21b53 | bellard | static void pit_irq_timer(void *opaque) |
386 | b0a21b53 | bellard | { |
387 | b0a21b53 | bellard | PITChannelState *s = opaque; |
388 | b0a21b53 | bellard | |
389 | b0a21b53 | bellard | pit_irq_timer_update(s, s->next_transition_time); |
390 | b0a21b53 | bellard | } |
391 | b0a21b53 | bellard | |
392 | b0a21b53 | bellard | static void pit_save(QEMUFile *f, void *opaque) |
393 | b0a21b53 | bellard | { |
394 | ec844b96 | bellard | PITState *pit = opaque; |
395 | b0a21b53 | bellard | PITChannelState *s; |
396 | b0a21b53 | bellard | int i;
|
397 | 3b46e624 | ths | |
398 | b0a21b53 | bellard | for(i = 0; i < 3; i++) { |
399 | ec844b96 | bellard | s = &pit->channels[i]; |
400 | bee8d684 | ths | qemu_put_be32(f, s->count); |
401 | b0a21b53 | bellard | qemu_put_be16s(f, &s->latched_count); |
402 | ec844b96 | bellard | qemu_put_8s(f, &s->count_latched); |
403 | ec844b96 | bellard | qemu_put_8s(f, &s->status_latched); |
404 | ec844b96 | bellard | qemu_put_8s(f, &s->status); |
405 | ec844b96 | bellard | qemu_put_8s(f, &s->read_state); |
406 | ec844b96 | bellard | qemu_put_8s(f, &s->write_state); |
407 | ec844b96 | bellard | qemu_put_8s(f, &s->write_latch); |
408 | ec844b96 | bellard | qemu_put_8s(f, &s->rw_mode); |
409 | b0a21b53 | bellard | qemu_put_8s(f, &s->mode); |
410 | b0a21b53 | bellard | qemu_put_8s(f, &s->bcd); |
411 | b0a21b53 | bellard | qemu_put_8s(f, &s->gate); |
412 | bee8d684 | ths | qemu_put_be64(f, s->count_load_time); |
413 | b0a21b53 | bellard | if (s->irq_timer) {
|
414 | bee8d684 | ths | qemu_put_be64(f, s->next_transition_time); |
415 | b0a21b53 | bellard | qemu_put_timer(f, s->irq_timer); |
416 | b0a21b53 | bellard | } |
417 | b0a21b53 | bellard | } |
418 | b0a21b53 | bellard | } |
419 | b0a21b53 | bellard | |
420 | b0a21b53 | bellard | static int pit_load(QEMUFile *f, void *opaque, int version_id) |
421 | b0a21b53 | bellard | { |
422 | ec844b96 | bellard | PITState *pit = opaque; |
423 | b0a21b53 | bellard | PITChannelState *s; |
424 | b0a21b53 | bellard | int i;
|
425 | 3b46e624 | ths | |
426 | b0a21b53 | bellard | if (version_id != 1) |
427 | b0a21b53 | bellard | return -EINVAL;
|
428 | b0a21b53 | bellard | |
429 | b0a21b53 | bellard | for(i = 0; i < 3; i++) { |
430 | ec844b96 | bellard | s = &pit->channels[i]; |
431 | bee8d684 | ths | s->count=qemu_get_be32(f); |
432 | b0a21b53 | bellard | qemu_get_be16s(f, &s->latched_count); |
433 | ec844b96 | bellard | qemu_get_8s(f, &s->count_latched); |
434 | ec844b96 | bellard | qemu_get_8s(f, &s->status_latched); |
435 | ec844b96 | bellard | qemu_get_8s(f, &s->status); |
436 | ec844b96 | bellard | qemu_get_8s(f, &s->read_state); |
437 | ec844b96 | bellard | qemu_get_8s(f, &s->write_state); |
438 | ec844b96 | bellard | qemu_get_8s(f, &s->write_latch); |
439 | ec844b96 | bellard | qemu_get_8s(f, &s->rw_mode); |
440 | b0a21b53 | bellard | qemu_get_8s(f, &s->mode); |
441 | b0a21b53 | bellard | qemu_get_8s(f, &s->bcd); |
442 | b0a21b53 | bellard | qemu_get_8s(f, &s->gate); |
443 | bee8d684 | ths | s->count_load_time=qemu_get_be64(f); |
444 | b0a21b53 | bellard | if (s->irq_timer) {
|
445 | bee8d684 | ths | s->next_transition_time=qemu_get_be64(f); |
446 | b0a21b53 | bellard | qemu_get_timer(f, s->irq_timer); |
447 | b0a21b53 | bellard | } |
448 | b0a21b53 | bellard | } |
449 | b0a21b53 | bellard | return 0; |
450 | b0a21b53 | bellard | } |
451 | b0a21b53 | bellard | |
452 | d7d02e3c | bellard | static void pit_reset(void *opaque) |
453 | 80cabfad | bellard | { |
454 | d7d02e3c | bellard | PITState *pit = opaque; |
455 | 80cabfad | bellard | PITChannelState *s; |
456 | 80cabfad | bellard | int i;
|
457 | 80cabfad | bellard | |
458 | 80cabfad | bellard | for(i = 0;i < 3; i++) { |
459 | ec844b96 | bellard | s = &pit->channels[i]; |
460 | 80cabfad | bellard | s->mode = 3;
|
461 | 80cabfad | bellard | s->gate = (i != 2);
|
462 | 80cabfad | bellard | pit_load_count(s, 0);
|
463 | 80cabfad | bellard | } |
464 | d7d02e3c | bellard | } |
465 | d7d02e3c | bellard | |
466 | 16b29ae1 | aliguori | /* When HPET is operating in legacy mode, i8254 timer0 is disabled */
|
467 | 16b29ae1 | aliguori | void hpet_pit_disable(void) { |
468 | 16b29ae1 | aliguori | PITChannelState *s; |
469 | 16b29ae1 | aliguori | s = &pit_state.channels[0];
|
470 | e0dd114c | aliguori | if (s->irq_timer)
|
471 | e0dd114c | aliguori | qemu_del_timer(s->irq_timer); |
472 | 16b29ae1 | aliguori | } |
473 | 16b29ae1 | aliguori | |
474 | c50c2d68 | aurel32 | /* When HPET is reset or leaving legacy mode, it must reenable i8254
|
475 | 16b29ae1 | aliguori | * timer 0
|
476 | 16b29ae1 | aliguori | */
|
477 | 16b29ae1 | aliguori | |
478 | 16b29ae1 | aliguori | void hpet_pit_enable(void) |
479 | 16b29ae1 | aliguori | { |
480 | 16b29ae1 | aliguori | PITState *pit = &pit_state; |
481 | 16b29ae1 | aliguori | PITChannelState *s; |
482 | 16b29ae1 | aliguori | s = &pit->channels[0];
|
483 | 16b29ae1 | aliguori | s->mode = 3;
|
484 | 16b29ae1 | aliguori | s->gate = 1;
|
485 | 16b29ae1 | aliguori | pit_load_count(s, 0);
|
486 | 16b29ae1 | aliguori | } |
487 | 16b29ae1 | aliguori | |
488 | d537cf6c | pbrook | PITState *pit_init(int base, qemu_irq irq)
|
489 | d7d02e3c | bellard | { |
490 | d7d02e3c | bellard | PITState *pit = &pit_state; |
491 | d7d02e3c | bellard | PITChannelState *s; |
492 | d7d02e3c | bellard | |
493 | d7d02e3c | bellard | s = &pit->channels[0];
|
494 | d7d02e3c | bellard | /* the timer 0 is connected to an IRQ */
|
495 | d7d02e3c | bellard | s->irq_timer = qemu_new_timer(vm_clock, pit_irq_timer, s); |
496 | d7d02e3c | bellard | s->irq = irq; |
497 | 80cabfad | bellard | |
498 | ec844b96 | bellard | register_savevm("i8254", base, 1, pit_save, pit_load, pit); |
499 | b0a21b53 | bellard | |
500 | 8217606e | Jan Kiszka | qemu_register_reset(pit_reset, 0, pit);
|
501 | ec844b96 | bellard | register_ioport_write(base, 4, 1, pit_ioport_write, pit); |
502 | ec844b96 | bellard | register_ioport_read(base, 3, 1, pit_ioport_read, pit); |
503 | d7d02e3c | bellard | |
504 | d7d02e3c | bellard | pit_reset(pit); |
505 | d7d02e3c | bellard | |
506 | ec844b96 | bellard | return pit;
|
507 | 80cabfad | bellard | } |