root / hw / mc146818rtc.c @ 64d50b8b
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1 | 80cabfad | bellard | /*
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2 | 80cabfad | bellard | * QEMU MC146818 RTC emulation
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3 | 5fafdf24 | ths | *
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4 | 80cabfad | bellard | * Copyright (c) 2003-2004 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 80cabfad | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 80cabfad | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 80cabfad | bellard | * in the Software without restriction, including without limitation the rights
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9 | 80cabfad | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 80cabfad | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 80cabfad | bellard | * furnished to do so, subject to the following conditions:
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12 | 80cabfad | bellard | *
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13 | 80cabfad | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 80cabfad | bellard | * all copies or substantial portions of the Software.
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15 | 80cabfad | bellard | *
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16 | 80cabfad | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 80cabfad | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 80cabfad | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 80cabfad | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 80cabfad | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 80cabfad | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 80cabfad | bellard | * THE SOFTWARE.
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23 | 80cabfad | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "qemu-timer.h" |
26 | 87ecb68b | pbrook | #include "sysemu.h" |
27 | 87ecb68b | pbrook | #include "pc.h" |
28 | 87ecb68b | pbrook | #include "isa.h" |
29 | 16b29ae1 | aliguori | #include "hpet_emul.h" |
30 | 80cabfad | bellard | |
31 | 80cabfad | bellard | //#define DEBUG_CMOS
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32 | 80cabfad | bellard | |
33 | 80cabfad | bellard | #define RTC_SECONDS 0 |
34 | 80cabfad | bellard | #define RTC_SECONDS_ALARM 1 |
35 | 80cabfad | bellard | #define RTC_MINUTES 2 |
36 | 80cabfad | bellard | #define RTC_MINUTES_ALARM 3 |
37 | 80cabfad | bellard | #define RTC_HOURS 4 |
38 | 80cabfad | bellard | #define RTC_HOURS_ALARM 5 |
39 | 80cabfad | bellard | #define RTC_ALARM_DONT_CARE 0xC0 |
40 | 80cabfad | bellard | |
41 | 80cabfad | bellard | #define RTC_DAY_OF_WEEK 6 |
42 | 80cabfad | bellard | #define RTC_DAY_OF_MONTH 7 |
43 | 80cabfad | bellard | #define RTC_MONTH 8 |
44 | 80cabfad | bellard | #define RTC_YEAR 9 |
45 | 80cabfad | bellard | |
46 | 80cabfad | bellard | #define RTC_REG_A 10 |
47 | 80cabfad | bellard | #define RTC_REG_B 11 |
48 | 80cabfad | bellard | #define RTC_REG_C 12 |
49 | 80cabfad | bellard | #define RTC_REG_D 13 |
50 | 80cabfad | bellard | |
51 | dff38e7b | bellard | #define REG_A_UIP 0x80 |
52 | 80cabfad | bellard | |
53 | 100d9891 | aurel32 | #define REG_B_SET 0x80 |
54 | 100d9891 | aurel32 | #define REG_B_PIE 0x40 |
55 | 100d9891 | aurel32 | #define REG_B_AIE 0x20 |
56 | 100d9891 | aurel32 | #define REG_B_UIE 0x10 |
57 | 100d9891 | aurel32 | #define REG_B_SQWE 0x08 |
58 | 100d9891 | aurel32 | #define REG_B_DM 0x04 |
59 | dff38e7b | bellard | |
60 | 72716184 | Anthony Liguori | #define REG_C_UF 0x10 |
61 | 72716184 | Anthony Liguori | #define REG_C_IRQF 0x80 |
62 | 72716184 | Anthony Liguori | #define REG_C_PF 0x40 |
63 | 72716184 | Anthony Liguori | #define REG_C_AF 0x20 |
64 | 72716184 | Anthony Liguori | |
65 | dff38e7b | bellard | struct RTCState {
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66 | dff38e7b | bellard | uint8_t cmos_data[128];
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67 | dff38e7b | bellard | uint8_t cmos_index; |
68 | 43f493af | bellard | struct tm current_tm;
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69 | 42fc73a1 | aurel32 | int base_year;
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70 | d537cf6c | pbrook | qemu_irq irq; |
71 | 100d9891 | aurel32 | qemu_irq sqw_irq; |
72 | 18c6e2ff | ths | int it_shift;
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73 | dff38e7b | bellard | /* periodic timer */
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74 | dff38e7b | bellard | QEMUTimer *periodic_timer; |
75 | dff38e7b | bellard | int64_t next_periodic_time; |
76 | dff38e7b | bellard | /* second update */
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77 | dff38e7b | bellard | int64_t next_second_time; |
78 | 73822ec8 | aliguori | #ifdef TARGET_I386
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79 | 73822ec8 | aliguori | uint32_t irq_coalesced; |
80 | 73822ec8 | aliguori | uint32_t period; |
81 | 93b66569 | aliguori | QEMUTimer *coalesced_timer; |
82 | 73822ec8 | aliguori | #endif
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83 | dff38e7b | bellard | QEMUTimer *second_timer; |
84 | dff38e7b | bellard | QEMUTimer *second_timer2; |
85 | dff38e7b | bellard | }; |
86 | dff38e7b | bellard | |
87 | 16b29ae1 | aliguori | static void rtc_irq_raise(qemu_irq irq) { |
88 | c50c2d68 | aurel32 | /* When HPET is operating in legacy mode, RTC interrupts are disabled
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89 | 16b29ae1 | aliguori | * We block qemu_irq_raise, but not qemu_irq_lower, in case legacy
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90 | c50c2d68 | aurel32 | * mode is established while interrupt is raised. We want it to
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91 | 16b29ae1 | aliguori | * be lowered in any case
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92 | c50c2d68 | aurel32 | */
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93 | 16b29ae1 | aliguori | #if defined TARGET_I386 || defined TARGET_X86_64
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94 | c50c2d68 | aurel32 | if (!hpet_in_legacy_mode())
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95 | 16b29ae1 | aliguori | #endif
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96 | 16b29ae1 | aliguori | qemu_irq_raise(irq); |
97 | 16b29ae1 | aliguori | } |
98 | 16b29ae1 | aliguori | |
99 | dff38e7b | bellard | static void rtc_set_time(RTCState *s); |
100 | dff38e7b | bellard | static void rtc_copy_date(RTCState *s); |
101 | dff38e7b | bellard | |
102 | 93b66569 | aliguori | #ifdef TARGET_I386
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103 | 93b66569 | aliguori | static void rtc_coalesced_timer_update(RTCState *s) |
104 | 93b66569 | aliguori | { |
105 | 93b66569 | aliguori | if (s->irq_coalesced == 0) { |
106 | 93b66569 | aliguori | qemu_del_timer(s->coalesced_timer); |
107 | 93b66569 | aliguori | } else {
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108 | 93b66569 | aliguori | /* divide each RTC interval to 2 - 8 smaller intervals */
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109 | 93b66569 | aliguori | int c = MIN(s->irq_coalesced, 7) + 1; |
110 | 93b66569 | aliguori | int64_t next_clock = qemu_get_clock(vm_clock) + |
111 | 93b66569 | aliguori | muldiv64(s->period / c, ticks_per_sec, 32768);
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112 | 93b66569 | aliguori | qemu_mod_timer(s->coalesced_timer, next_clock); |
113 | 93b66569 | aliguori | } |
114 | 93b66569 | aliguori | } |
115 | 93b66569 | aliguori | |
116 | 93b66569 | aliguori | static void rtc_coalesced_timer(void *opaque) |
117 | 93b66569 | aliguori | { |
118 | 93b66569 | aliguori | RTCState *s = opaque; |
119 | 93b66569 | aliguori | |
120 | 93b66569 | aliguori | if (s->irq_coalesced != 0) { |
121 | 93b66569 | aliguori | apic_reset_irq_delivered(); |
122 | 93b66569 | aliguori | s->cmos_data[RTC_REG_C] |= 0xc0;
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123 | 93b66569 | aliguori | rtc_irq_raise(s->irq); |
124 | 93b66569 | aliguori | if (apic_get_irq_delivered()) {
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125 | 93b66569 | aliguori | s->irq_coalesced--; |
126 | 93b66569 | aliguori | } |
127 | 93b66569 | aliguori | } |
128 | 93b66569 | aliguori | |
129 | 93b66569 | aliguori | rtc_coalesced_timer_update(s); |
130 | 93b66569 | aliguori | } |
131 | 93b66569 | aliguori | #endif
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132 | 93b66569 | aliguori | |
133 | dff38e7b | bellard | static void rtc_timer_update(RTCState *s, int64_t current_time) |
134 | dff38e7b | bellard | { |
135 | dff38e7b | bellard | int period_code, period;
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136 | dff38e7b | bellard | int64_t cur_clock, next_irq_clock; |
137 | 100d9891 | aurel32 | int enable_pie;
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138 | dff38e7b | bellard | |
139 | dff38e7b | bellard | period_code = s->cmos_data[RTC_REG_A] & 0x0f;
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140 | 16b29ae1 | aliguori | #if defined TARGET_I386 || defined TARGET_X86_64
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141 | c50c2d68 | aurel32 | /* disable periodic timer if hpet is in legacy mode, since interrupts are
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142 | 16b29ae1 | aliguori | * disabled anyway.
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143 | 16b29ae1 | aliguori | */
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144 | a8b01dd8 | pbrook | enable_pie = !hpet_in_legacy_mode(); |
145 | 16b29ae1 | aliguori | #else
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146 | 100d9891 | aurel32 | enable_pie = 1;
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147 | 16b29ae1 | aliguori | #endif
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148 | 100d9891 | aurel32 | if (period_code != 0 |
149 | 100d9891 | aurel32 | && (((s->cmos_data[RTC_REG_B] & REG_B_PIE) && enable_pie) |
150 | 100d9891 | aurel32 | || ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) { |
151 | dff38e7b | bellard | if (period_code <= 2) |
152 | dff38e7b | bellard | period_code += 7;
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153 | dff38e7b | bellard | /* period in 32 Khz cycles */
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154 | dff38e7b | bellard | period = 1 << (period_code - 1); |
155 | 73822ec8 | aliguori | #ifdef TARGET_I386
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156 | 73822ec8 | aliguori | if(period != s->period)
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157 | 73822ec8 | aliguori | s->irq_coalesced = (s->irq_coalesced * s->period) / period; |
158 | 73822ec8 | aliguori | s->period = period; |
159 | 73822ec8 | aliguori | #endif
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160 | dff38e7b | bellard | /* compute 32 khz clock */
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161 | dff38e7b | bellard | cur_clock = muldiv64(current_time, 32768, ticks_per_sec);
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162 | dff38e7b | bellard | next_irq_clock = (cur_clock & ~(period - 1)) + period;
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163 | dff38e7b | bellard | s->next_periodic_time = muldiv64(next_irq_clock, ticks_per_sec, 32768) + 1; |
164 | dff38e7b | bellard | qemu_mod_timer(s->periodic_timer, s->next_periodic_time); |
165 | dff38e7b | bellard | } else {
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166 | 73822ec8 | aliguori | #ifdef TARGET_I386
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167 | 73822ec8 | aliguori | s->irq_coalesced = 0;
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168 | 73822ec8 | aliguori | #endif
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169 | dff38e7b | bellard | qemu_del_timer(s->periodic_timer); |
170 | dff38e7b | bellard | } |
171 | dff38e7b | bellard | } |
172 | dff38e7b | bellard | |
173 | dff38e7b | bellard | static void rtc_periodic_timer(void *opaque) |
174 | dff38e7b | bellard | { |
175 | dff38e7b | bellard | RTCState *s = opaque; |
176 | dff38e7b | bellard | |
177 | dff38e7b | bellard | rtc_timer_update(s, s->next_periodic_time); |
178 | 100d9891 | aurel32 | if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
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179 | 100d9891 | aurel32 | s->cmos_data[RTC_REG_C] |= 0xc0;
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180 | 93b66569 | aliguori | #ifdef TARGET_I386
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181 | 93b66569 | aliguori | if(rtc_td_hack) {
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182 | 93b66569 | aliguori | apic_reset_irq_delivered(); |
183 | 93b66569 | aliguori | rtc_irq_raise(s->irq); |
184 | 93b66569 | aliguori | if (!apic_get_irq_delivered()) {
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185 | 93b66569 | aliguori | s->irq_coalesced++; |
186 | 93b66569 | aliguori | rtc_coalesced_timer_update(s); |
187 | 93b66569 | aliguori | } |
188 | 93b66569 | aliguori | } else
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189 | 93b66569 | aliguori | #endif
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190 | 100d9891 | aurel32 | rtc_irq_raise(s->irq); |
191 | 100d9891 | aurel32 | } |
192 | 100d9891 | aurel32 | if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) {
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193 | 100d9891 | aurel32 | /* Not square wave at all but we don't want 2048Hz interrupts!
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194 | 100d9891 | aurel32 | Must be seen as a pulse. */
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195 | 100d9891 | aurel32 | qemu_irq_raise(s->sqw_irq); |
196 | 100d9891 | aurel32 | } |
197 | dff38e7b | bellard | } |
198 | 80cabfad | bellard | |
199 | b41a2cd1 | bellard | static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) |
200 | 80cabfad | bellard | { |
201 | b41a2cd1 | bellard | RTCState *s = opaque; |
202 | 80cabfad | bellard | |
203 | 80cabfad | bellard | if ((addr & 1) == 0) { |
204 | 80cabfad | bellard | s->cmos_index = data & 0x7f;
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205 | 80cabfad | bellard | } else {
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206 | 80cabfad | bellard | #ifdef DEBUG_CMOS
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207 | 80cabfad | bellard | printf("cmos: write index=0x%02x val=0x%02x\n",
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208 | 80cabfad | bellard | s->cmos_index, data); |
209 | 3b46e624 | ths | #endif
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210 | dff38e7b | bellard | switch(s->cmos_index) {
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211 | 80cabfad | bellard | case RTC_SECONDS_ALARM:
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212 | 80cabfad | bellard | case RTC_MINUTES_ALARM:
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213 | 80cabfad | bellard | case RTC_HOURS_ALARM:
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214 | 80cabfad | bellard | /* XXX: not supported */
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215 | 80cabfad | bellard | s->cmos_data[s->cmos_index] = data; |
216 | 80cabfad | bellard | break;
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217 | 80cabfad | bellard | case RTC_SECONDS:
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218 | 80cabfad | bellard | case RTC_MINUTES:
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219 | 80cabfad | bellard | case RTC_HOURS:
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220 | 80cabfad | bellard | case RTC_DAY_OF_WEEK:
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221 | 80cabfad | bellard | case RTC_DAY_OF_MONTH:
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222 | 80cabfad | bellard | case RTC_MONTH:
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223 | 80cabfad | bellard | case RTC_YEAR:
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224 | 80cabfad | bellard | s->cmos_data[s->cmos_index] = data; |
225 | dff38e7b | bellard | /* if in set mode, do not update the time */
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226 | dff38e7b | bellard | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
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227 | dff38e7b | bellard | rtc_set_time(s); |
228 | dff38e7b | bellard | } |
229 | 80cabfad | bellard | break;
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230 | 80cabfad | bellard | case RTC_REG_A:
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231 | dff38e7b | bellard | /* UIP bit is read only */
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232 | dff38e7b | bellard | s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) | |
233 | dff38e7b | bellard | (s->cmos_data[RTC_REG_A] & REG_A_UIP); |
234 | dff38e7b | bellard | rtc_timer_update(s, qemu_get_clock(vm_clock)); |
235 | dff38e7b | bellard | break;
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236 | 80cabfad | bellard | case RTC_REG_B:
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237 | dff38e7b | bellard | if (data & REG_B_SET) {
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238 | dff38e7b | bellard | /* set mode: reset UIP mode */
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239 | dff38e7b | bellard | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; |
240 | dff38e7b | bellard | data &= ~REG_B_UIE; |
241 | dff38e7b | bellard | } else {
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242 | dff38e7b | bellard | /* if disabling set mode, update the time */
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243 | dff38e7b | bellard | if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
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244 | dff38e7b | bellard | rtc_set_time(s); |
245 | dff38e7b | bellard | } |
246 | dff38e7b | bellard | } |
247 | dff38e7b | bellard | s->cmos_data[RTC_REG_B] = data; |
248 | dff38e7b | bellard | rtc_timer_update(s, qemu_get_clock(vm_clock)); |
249 | 80cabfad | bellard | break;
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250 | 80cabfad | bellard | case RTC_REG_C:
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251 | 80cabfad | bellard | case RTC_REG_D:
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252 | 80cabfad | bellard | /* cannot write to them */
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253 | 80cabfad | bellard | break;
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254 | 80cabfad | bellard | default:
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255 | 80cabfad | bellard | s->cmos_data[s->cmos_index] = data; |
256 | 80cabfad | bellard | break;
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257 | 80cabfad | bellard | } |
258 | 80cabfad | bellard | } |
259 | 80cabfad | bellard | } |
260 | 80cabfad | bellard | |
261 | dff38e7b | bellard | static inline int to_bcd(RTCState *s, int a) |
262 | 80cabfad | bellard | { |
263 | 6f1bf24d | aurel32 | if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
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264 | dff38e7b | bellard | return a;
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265 | dff38e7b | bellard | } else {
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266 | dff38e7b | bellard | return ((a / 10) << 4) | (a % 10); |
267 | dff38e7b | bellard | } |
268 | 80cabfad | bellard | } |
269 | 80cabfad | bellard | |
270 | dff38e7b | bellard | static inline int from_bcd(RTCState *s, int a) |
271 | 80cabfad | bellard | { |
272 | 6f1bf24d | aurel32 | if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
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273 | dff38e7b | bellard | return a;
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274 | dff38e7b | bellard | } else {
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275 | dff38e7b | bellard | return ((a >> 4) * 10) + (a & 0x0f); |
276 | dff38e7b | bellard | } |
277 | dff38e7b | bellard | } |
278 | dff38e7b | bellard | |
279 | dff38e7b | bellard | static void rtc_set_time(RTCState *s) |
280 | dff38e7b | bellard | { |
281 | 43f493af | bellard | struct tm *tm = &s->current_tm;
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282 | dff38e7b | bellard | |
283 | dff38e7b | bellard | tm->tm_sec = from_bcd(s, s->cmos_data[RTC_SECONDS]); |
284 | dff38e7b | bellard | tm->tm_min = from_bcd(s, s->cmos_data[RTC_MINUTES]); |
285 | 43f493af | bellard | tm->tm_hour = from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
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286 | 43f493af | bellard | if (!(s->cmos_data[RTC_REG_B] & 0x02) && |
287 | 43f493af | bellard | (s->cmos_data[RTC_HOURS] & 0x80)) {
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288 | 43f493af | bellard | tm->tm_hour += 12;
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289 | 43f493af | bellard | } |
290 | 6f1bf24d | aurel32 | tm->tm_wday = from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
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291 | dff38e7b | bellard | tm->tm_mday = from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]); |
292 | dff38e7b | bellard | tm->tm_mon = from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
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293 | 42fc73a1 | aurel32 | tm->tm_year = from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year - 1900;
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294 | 43f493af | bellard | } |
295 | 43f493af | bellard | |
296 | 43f493af | bellard | static void rtc_copy_date(RTCState *s) |
297 | 43f493af | bellard | { |
298 | 43f493af | bellard | const struct tm *tm = &s->current_tm; |
299 | 42fc73a1 | aurel32 | int year;
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300 | dff38e7b | bellard | |
301 | 43f493af | bellard | s->cmos_data[RTC_SECONDS] = to_bcd(s, tm->tm_sec); |
302 | 43f493af | bellard | s->cmos_data[RTC_MINUTES] = to_bcd(s, tm->tm_min); |
303 | 43f493af | bellard | if (s->cmos_data[RTC_REG_B] & 0x02) { |
304 | 43f493af | bellard | /* 24 hour format */
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305 | 43f493af | bellard | s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour); |
306 | 43f493af | bellard | } else {
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307 | 43f493af | bellard | /* 12 hour format */
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308 | 43f493af | bellard | s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour % 12);
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309 | 43f493af | bellard | if (tm->tm_hour >= 12) |
310 | 43f493af | bellard | s->cmos_data[RTC_HOURS] |= 0x80;
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311 | 43f493af | bellard | } |
312 | 6f1bf24d | aurel32 | s->cmos_data[RTC_DAY_OF_WEEK] = to_bcd(s, tm->tm_wday + 1);
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313 | 43f493af | bellard | s->cmos_data[RTC_DAY_OF_MONTH] = to_bcd(s, tm->tm_mday); |
314 | 43f493af | bellard | s->cmos_data[RTC_MONTH] = to_bcd(s, tm->tm_mon + 1);
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315 | 42fc73a1 | aurel32 | year = (tm->tm_year - s->base_year) % 100;
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316 | 42fc73a1 | aurel32 | if (year < 0) |
317 | 42fc73a1 | aurel32 | year += 100;
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318 | 42fc73a1 | aurel32 | s->cmos_data[RTC_YEAR] = to_bcd(s, year); |
319 | 43f493af | bellard | } |
320 | 43f493af | bellard | |
321 | 43f493af | bellard | /* month is between 0 and 11. */
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322 | 43f493af | bellard | static int get_days_in_month(int month, int year) |
323 | 43f493af | bellard | { |
324 | 5fafdf24 | ths | static const int days_tab[12] = { |
325 | 5fafdf24 | ths | 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 |
326 | 43f493af | bellard | }; |
327 | 43f493af | bellard | int d;
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328 | 43f493af | bellard | if ((unsigned )month >= 12) |
329 | 43f493af | bellard | return 31; |
330 | 43f493af | bellard | d = days_tab[month]; |
331 | 43f493af | bellard | if (month == 1) { |
332 | 43f493af | bellard | if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0)) |
333 | 43f493af | bellard | d++; |
334 | 43f493af | bellard | } |
335 | 43f493af | bellard | return d;
|
336 | 43f493af | bellard | } |
337 | 43f493af | bellard | |
338 | 43f493af | bellard | /* update 'tm' to the next second */
|
339 | 43f493af | bellard | static void rtc_next_second(struct tm *tm) |
340 | 43f493af | bellard | { |
341 | 43f493af | bellard | int days_in_month;
|
342 | 43f493af | bellard | |
343 | 43f493af | bellard | tm->tm_sec++; |
344 | 43f493af | bellard | if ((unsigned)tm->tm_sec >= 60) { |
345 | 43f493af | bellard | tm->tm_sec = 0;
|
346 | 43f493af | bellard | tm->tm_min++; |
347 | 43f493af | bellard | if ((unsigned)tm->tm_min >= 60) { |
348 | 43f493af | bellard | tm->tm_min = 0;
|
349 | 43f493af | bellard | tm->tm_hour++; |
350 | 43f493af | bellard | if ((unsigned)tm->tm_hour >= 24) { |
351 | 43f493af | bellard | tm->tm_hour = 0;
|
352 | 43f493af | bellard | /* next day */
|
353 | 43f493af | bellard | tm->tm_wday++; |
354 | 43f493af | bellard | if ((unsigned)tm->tm_wday >= 7) |
355 | 43f493af | bellard | tm->tm_wday = 0;
|
356 | 5fafdf24 | ths | days_in_month = get_days_in_month(tm->tm_mon, |
357 | 43f493af | bellard | tm->tm_year + 1900);
|
358 | 43f493af | bellard | tm->tm_mday++; |
359 | 43f493af | bellard | if (tm->tm_mday < 1) { |
360 | 43f493af | bellard | tm->tm_mday = 1;
|
361 | 43f493af | bellard | } else if (tm->tm_mday > days_in_month) { |
362 | 43f493af | bellard | tm->tm_mday = 1;
|
363 | 43f493af | bellard | tm->tm_mon++; |
364 | 43f493af | bellard | if (tm->tm_mon >= 12) { |
365 | 43f493af | bellard | tm->tm_mon = 0;
|
366 | 43f493af | bellard | tm->tm_year++; |
367 | 43f493af | bellard | } |
368 | 43f493af | bellard | } |
369 | 43f493af | bellard | } |
370 | 43f493af | bellard | } |
371 | 43f493af | bellard | } |
372 | dff38e7b | bellard | } |
373 | dff38e7b | bellard | |
374 | 43f493af | bellard | |
375 | dff38e7b | bellard | static void rtc_update_second(void *opaque) |
376 | dff38e7b | bellard | { |
377 | dff38e7b | bellard | RTCState *s = opaque; |
378 | 4721c457 | bellard | int64_t delay; |
379 | dff38e7b | bellard | |
380 | dff38e7b | bellard | /* if the oscillator is not in normal operation, we do not update */
|
381 | dff38e7b | bellard | if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) { |
382 | dff38e7b | bellard | s->next_second_time += ticks_per_sec; |
383 | dff38e7b | bellard | qemu_mod_timer(s->second_timer, s->next_second_time); |
384 | dff38e7b | bellard | } else {
|
385 | 43f493af | bellard | rtc_next_second(&s->current_tm); |
386 | 3b46e624 | ths | |
387 | dff38e7b | bellard | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
|
388 | dff38e7b | bellard | /* update in progress bit */
|
389 | dff38e7b | bellard | s->cmos_data[RTC_REG_A] |= REG_A_UIP; |
390 | dff38e7b | bellard | } |
391 | 4721c457 | bellard | /* should be 244 us = 8 / 32768 seconds, but currently the
|
392 | 4721c457 | bellard | timers do not have the necessary resolution. */
|
393 | 4721c457 | bellard | delay = (ticks_per_sec * 1) / 100; |
394 | 4721c457 | bellard | if (delay < 1) |
395 | 4721c457 | bellard | delay = 1;
|
396 | 5fafdf24 | ths | qemu_mod_timer(s->second_timer2, |
397 | 4721c457 | bellard | s->next_second_time + delay); |
398 | dff38e7b | bellard | } |
399 | dff38e7b | bellard | } |
400 | dff38e7b | bellard | |
401 | dff38e7b | bellard | static void rtc_update_second2(void *opaque) |
402 | dff38e7b | bellard | { |
403 | dff38e7b | bellard | RTCState *s = opaque; |
404 | dff38e7b | bellard | |
405 | dff38e7b | bellard | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
|
406 | dff38e7b | bellard | rtc_copy_date(s); |
407 | dff38e7b | bellard | } |
408 | dff38e7b | bellard | |
409 | dff38e7b | bellard | /* check alarm */
|
410 | dff38e7b | bellard | if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
|
411 | dff38e7b | bellard | if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 || |
412 | 43f493af | bellard | s->cmos_data[RTC_SECONDS_ALARM] == s->current_tm.tm_sec) && |
413 | dff38e7b | bellard | ((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 || |
414 | 43f493af | bellard | s->cmos_data[RTC_MINUTES_ALARM] == s->current_tm.tm_mon) && |
415 | dff38e7b | bellard | ((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 || |
416 | 43f493af | bellard | s->cmos_data[RTC_HOURS_ALARM] == s->current_tm.tm_hour)) { |
417 | dff38e7b | bellard | |
418 | 5fafdf24 | ths | s->cmos_data[RTC_REG_C] |= 0xa0;
|
419 | 16b29ae1 | aliguori | rtc_irq_raise(s->irq); |
420 | dff38e7b | bellard | } |
421 | dff38e7b | bellard | } |
422 | dff38e7b | bellard | |
423 | dff38e7b | bellard | /* update ended interrupt */
|
424 | dff38e7b | bellard | if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
|
425 | 5fafdf24 | ths | s->cmos_data[RTC_REG_C] |= 0x90;
|
426 | 16b29ae1 | aliguori | rtc_irq_raise(s->irq); |
427 | dff38e7b | bellard | } |
428 | dff38e7b | bellard | |
429 | dff38e7b | bellard | /* clear update in progress bit */
|
430 | dff38e7b | bellard | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; |
431 | dff38e7b | bellard | |
432 | dff38e7b | bellard | s->next_second_time += ticks_per_sec; |
433 | dff38e7b | bellard | qemu_mod_timer(s->second_timer, s->next_second_time); |
434 | 80cabfad | bellard | } |
435 | 80cabfad | bellard | |
436 | b41a2cd1 | bellard | static uint32_t cmos_ioport_read(void *opaque, uint32_t addr) |
437 | 80cabfad | bellard | { |
438 | b41a2cd1 | bellard | RTCState *s = opaque; |
439 | 80cabfad | bellard | int ret;
|
440 | 80cabfad | bellard | if ((addr & 1) == 0) { |
441 | 80cabfad | bellard | return 0xff; |
442 | 80cabfad | bellard | } else {
|
443 | 80cabfad | bellard | switch(s->cmos_index) {
|
444 | 80cabfad | bellard | case RTC_SECONDS:
|
445 | 80cabfad | bellard | case RTC_MINUTES:
|
446 | 80cabfad | bellard | case RTC_HOURS:
|
447 | 80cabfad | bellard | case RTC_DAY_OF_WEEK:
|
448 | 80cabfad | bellard | case RTC_DAY_OF_MONTH:
|
449 | 80cabfad | bellard | case RTC_MONTH:
|
450 | 80cabfad | bellard | case RTC_YEAR:
|
451 | 80cabfad | bellard | ret = s->cmos_data[s->cmos_index]; |
452 | 80cabfad | bellard | break;
|
453 | 80cabfad | bellard | case RTC_REG_A:
|
454 | 80cabfad | bellard | ret = s->cmos_data[s->cmos_index]; |
455 | 80cabfad | bellard | break;
|
456 | 80cabfad | bellard | case RTC_REG_C:
|
457 | 80cabfad | bellard | ret = s->cmos_data[s->cmos_index]; |
458 | d537cf6c | pbrook | qemu_irq_lower(s->irq); |
459 | 5fafdf24 | ths | s->cmos_data[RTC_REG_C] = 0x00;
|
460 | 80cabfad | bellard | break;
|
461 | 80cabfad | bellard | default:
|
462 | 80cabfad | bellard | ret = s->cmos_data[s->cmos_index]; |
463 | 80cabfad | bellard | break;
|
464 | 80cabfad | bellard | } |
465 | 80cabfad | bellard | #ifdef DEBUG_CMOS
|
466 | 80cabfad | bellard | printf("cmos: read index=0x%02x val=0x%02x\n",
|
467 | 80cabfad | bellard | s->cmos_index, ret); |
468 | 80cabfad | bellard | #endif
|
469 | 80cabfad | bellard | return ret;
|
470 | 80cabfad | bellard | } |
471 | 80cabfad | bellard | } |
472 | 80cabfad | bellard | |
473 | dff38e7b | bellard | void rtc_set_memory(RTCState *s, int addr, int val) |
474 | dff38e7b | bellard | { |
475 | dff38e7b | bellard | if (addr >= 0 && addr <= 127) |
476 | dff38e7b | bellard | s->cmos_data[addr] = val; |
477 | dff38e7b | bellard | } |
478 | dff38e7b | bellard | |
479 | dff38e7b | bellard | void rtc_set_date(RTCState *s, const struct tm *tm) |
480 | dff38e7b | bellard | { |
481 | 43f493af | bellard | s->current_tm = *tm; |
482 | dff38e7b | bellard | rtc_copy_date(s); |
483 | dff38e7b | bellard | } |
484 | dff38e7b | bellard | |
485 | ea55ffb3 | ths | /* PC cmos mappings */
|
486 | ea55ffb3 | ths | #define REG_IBM_CENTURY_BYTE 0x32 |
487 | ea55ffb3 | ths | #define REG_IBM_PS2_CENTURY_BYTE 0x37 |
488 | ea55ffb3 | ths | |
489 | 9596ebb7 | pbrook | static void rtc_set_date_from_host(RTCState *s) |
490 | ea55ffb3 | ths | { |
491 | f6503059 | balrog | struct tm tm;
|
492 | ea55ffb3 | ths | int val;
|
493 | ea55ffb3 | ths | |
494 | ea55ffb3 | ths | /* set the CMOS date */
|
495 | f6503059 | balrog | qemu_get_timedate(&tm, 0);
|
496 | f6503059 | balrog | rtc_set_date(s, &tm); |
497 | ea55ffb3 | ths | |
498 | f6503059 | balrog | val = to_bcd(s, (tm.tm_year / 100) + 19); |
499 | ea55ffb3 | ths | rtc_set_memory(s, REG_IBM_CENTURY_BYTE, val); |
500 | ea55ffb3 | ths | rtc_set_memory(s, REG_IBM_PS2_CENTURY_BYTE, val); |
501 | ea55ffb3 | ths | } |
502 | ea55ffb3 | ths | |
503 | dff38e7b | bellard | static void rtc_save(QEMUFile *f, void *opaque) |
504 | dff38e7b | bellard | { |
505 | dff38e7b | bellard | RTCState *s = opaque; |
506 | dff38e7b | bellard | |
507 | dff38e7b | bellard | qemu_put_buffer(f, s->cmos_data, 128);
|
508 | dff38e7b | bellard | qemu_put_8s(f, &s->cmos_index); |
509 | 3b46e624 | ths | |
510 | bee8d684 | ths | qemu_put_be32(f, s->current_tm.tm_sec); |
511 | bee8d684 | ths | qemu_put_be32(f, s->current_tm.tm_min); |
512 | bee8d684 | ths | qemu_put_be32(f, s->current_tm.tm_hour); |
513 | bee8d684 | ths | qemu_put_be32(f, s->current_tm.tm_wday); |
514 | bee8d684 | ths | qemu_put_be32(f, s->current_tm.tm_mday); |
515 | bee8d684 | ths | qemu_put_be32(f, s->current_tm.tm_mon); |
516 | bee8d684 | ths | qemu_put_be32(f, s->current_tm.tm_year); |
517 | dff38e7b | bellard | |
518 | dff38e7b | bellard | qemu_put_timer(f, s->periodic_timer); |
519 | bee8d684 | ths | qemu_put_be64(f, s->next_periodic_time); |
520 | dff38e7b | bellard | |
521 | bee8d684 | ths | qemu_put_be64(f, s->next_second_time); |
522 | dff38e7b | bellard | qemu_put_timer(f, s->second_timer); |
523 | dff38e7b | bellard | qemu_put_timer(f, s->second_timer2); |
524 | 80cabfad | bellard | } |
525 | 80cabfad | bellard | |
526 | dff38e7b | bellard | static int rtc_load(QEMUFile *f, void *opaque, int version_id) |
527 | 80cabfad | bellard | { |
528 | dff38e7b | bellard | RTCState *s = opaque; |
529 | dff38e7b | bellard | |
530 | dff38e7b | bellard | if (version_id != 1) |
531 | dff38e7b | bellard | return -EINVAL;
|
532 | 80cabfad | bellard | |
533 | dff38e7b | bellard | qemu_get_buffer(f, s->cmos_data, 128);
|
534 | dff38e7b | bellard | qemu_get_8s(f, &s->cmos_index); |
535 | 43f493af | bellard | |
536 | bee8d684 | ths | s->current_tm.tm_sec=qemu_get_be32(f); |
537 | bee8d684 | ths | s->current_tm.tm_min=qemu_get_be32(f); |
538 | bee8d684 | ths | s->current_tm.tm_hour=qemu_get_be32(f); |
539 | bee8d684 | ths | s->current_tm.tm_wday=qemu_get_be32(f); |
540 | bee8d684 | ths | s->current_tm.tm_mday=qemu_get_be32(f); |
541 | bee8d684 | ths | s->current_tm.tm_mon=qemu_get_be32(f); |
542 | bee8d684 | ths | s->current_tm.tm_year=qemu_get_be32(f); |
543 | dff38e7b | bellard | |
544 | dff38e7b | bellard | qemu_get_timer(f, s->periodic_timer); |
545 | bee8d684 | ths | s->next_periodic_time=qemu_get_be64(f); |
546 | dff38e7b | bellard | |
547 | bee8d684 | ths | s->next_second_time=qemu_get_be64(f); |
548 | dff38e7b | bellard | qemu_get_timer(f, s->second_timer); |
549 | dff38e7b | bellard | qemu_get_timer(f, s->second_timer2); |
550 | dff38e7b | bellard | return 0; |
551 | dff38e7b | bellard | } |
552 | dff38e7b | bellard | |
553 | 73822ec8 | aliguori | #ifdef TARGET_I386
|
554 | 73822ec8 | aliguori | static void rtc_save_td(QEMUFile *f, void *opaque) |
555 | 73822ec8 | aliguori | { |
556 | 73822ec8 | aliguori | RTCState *s = opaque; |
557 | 73822ec8 | aliguori | |
558 | 73822ec8 | aliguori | qemu_put_be32(f, s->irq_coalesced); |
559 | 73822ec8 | aliguori | qemu_put_be32(f, s->period); |
560 | 73822ec8 | aliguori | } |
561 | 73822ec8 | aliguori | |
562 | 73822ec8 | aliguori | static int rtc_load_td(QEMUFile *f, void *opaque, int version_id) |
563 | 73822ec8 | aliguori | { |
564 | 73822ec8 | aliguori | RTCState *s = opaque; |
565 | 73822ec8 | aliguori | |
566 | 73822ec8 | aliguori | if (version_id != 1) |
567 | 73822ec8 | aliguori | return -EINVAL;
|
568 | 73822ec8 | aliguori | |
569 | 73822ec8 | aliguori | s->irq_coalesced = qemu_get_be32(f); |
570 | 73822ec8 | aliguori | s->period = qemu_get_be32(f); |
571 | 93b66569 | aliguori | rtc_coalesced_timer_update(s); |
572 | 73822ec8 | aliguori | return 0; |
573 | 73822ec8 | aliguori | } |
574 | 73822ec8 | aliguori | #endif
|
575 | 73822ec8 | aliguori | |
576 | eeb7c03c | Gleb Natapov | static void rtc_reset(void *opaque) |
577 | eeb7c03c | Gleb Natapov | { |
578 | eeb7c03c | Gleb Natapov | RTCState *s = opaque; |
579 | eeb7c03c | Gleb Natapov | |
580 | 72716184 | Anthony Liguori | s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE); |
581 | 72716184 | Anthony Liguori | s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF); |
582 | eeb7c03c | Gleb Natapov | |
583 | 72716184 | Anthony Liguori | qemu_irq_lower(s->irq); |
584 | eeb7c03c | Gleb Natapov | |
585 | eeb7c03c | Gleb Natapov | #ifdef TARGET_I386
|
586 | eeb7c03c | Gleb Natapov | if (rtc_td_hack)
|
587 | eeb7c03c | Gleb Natapov | s->irq_coalesced = 0;
|
588 | eeb7c03c | Gleb Natapov | #endif
|
589 | eeb7c03c | Gleb Natapov | } |
590 | eeb7c03c | Gleb Natapov | |
591 | 100d9891 | aurel32 | RTCState *rtc_init_sqw(int base, qemu_irq irq, qemu_irq sqw_irq, int base_year) |
592 | dff38e7b | bellard | { |
593 | dff38e7b | bellard | RTCState *s; |
594 | dff38e7b | bellard | |
595 | dff38e7b | bellard | s = qemu_mallocz(sizeof(RTCState));
|
596 | 80cabfad | bellard | |
597 | 80cabfad | bellard | s->irq = irq; |
598 | 100d9891 | aurel32 | s->sqw_irq = sqw_irq; |
599 | 80cabfad | bellard | s->cmos_data[RTC_REG_A] = 0x26;
|
600 | 80cabfad | bellard | s->cmos_data[RTC_REG_B] = 0x02;
|
601 | 80cabfad | bellard | s->cmos_data[RTC_REG_C] = 0x00;
|
602 | 80cabfad | bellard | s->cmos_data[RTC_REG_D] = 0x80;
|
603 | 80cabfad | bellard | |
604 | 42fc73a1 | aurel32 | s->base_year = base_year; |
605 | ea55ffb3 | ths | rtc_set_date_from_host(s); |
606 | ea55ffb3 | ths | |
607 | 5fafdf24 | ths | s->periodic_timer = qemu_new_timer(vm_clock, |
608 | dff38e7b | bellard | rtc_periodic_timer, s); |
609 | 93b66569 | aliguori | #ifdef TARGET_I386
|
610 | 93b66569 | aliguori | if (rtc_td_hack)
|
611 | 93b66569 | aliguori | s->coalesced_timer = qemu_new_timer(vm_clock, rtc_coalesced_timer, s); |
612 | 93b66569 | aliguori | #endif
|
613 | 5fafdf24 | ths | s->second_timer = qemu_new_timer(vm_clock, |
614 | dff38e7b | bellard | rtc_update_second, s); |
615 | 5fafdf24 | ths | s->second_timer2 = qemu_new_timer(vm_clock, |
616 | dff38e7b | bellard | rtc_update_second2, s); |
617 | dff38e7b | bellard | |
618 | dff38e7b | bellard | s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100; |
619 | dff38e7b | bellard | qemu_mod_timer(s->second_timer2, s->next_second_time); |
620 | dff38e7b | bellard | |
621 | b41a2cd1 | bellard | register_ioport_write(base, 2, 1, cmos_ioport_write, s); |
622 | b41a2cd1 | bellard | register_ioport_read(base, 2, 1, cmos_ioport_read, s); |
623 | dff38e7b | bellard | |
624 | dff38e7b | bellard | register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s); |
625 | 73822ec8 | aliguori | #ifdef TARGET_I386
|
626 | 73822ec8 | aliguori | if (rtc_td_hack)
|
627 | 73822ec8 | aliguori | register_savevm("mc146818rtc-td", base, 1, rtc_save_td, rtc_load_td, s); |
628 | 73822ec8 | aliguori | #endif
|
629 | eeb7c03c | Gleb Natapov | qemu_register_reset(rtc_reset, 0, s);
|
630 | eeb7c03c | Gleb Natapov | |
631 | dff38e7b | bellard | return s;
|
632 | 80cabfad | bellard | } |
633 | 80cabfad | bellard | |
634 | 100d9891 | aurel32 | RTCState *rtc_init(int base, qemu_irq irq, int base_year) |
635 | 100d9891 | aurel32 | { |
636 | 100d9891 | aurel32 | return rtc_init_sqw(base, irq, NULL, base_year); |
637 | 100d9891 | aurel32 | } |
638 | 100d9891 | aurel32 | |
639 | 2ca9d013 | ths | /* Memory mapped interface */
|
640 | 9596ebb7 | pbrook | static uint32_t cmos_mm_readb (void *opaque, target_phys_addr_t addr) |
641 | 2ca9d013 | ths | { |
642 | 2ca9d013 | ths | RTCState *s = opaque; |
643 | 2ca9d013 | ths | |
644 | 8da3ff18 | pbrook | return cmos_ioport_read(s, addr >> s->it_shift) & 0xFF; |
645 | 2ca9d013 | ths | } |
646 | 2ca9d013 | ths | |
647 | 9596ebb7 | pbrook | static void cmos_mm_writeb (void *opaque, |
648 | 9596ebb7 | pbrook | target_phys_addr_t addr, uint32_t value) |
649 | 2ca9d013 | ths | { |
650 | 2ca9d013 | ths | RTCState *s = opaque; |
651 | 2ca9d013 | ths | |
652 | 8da3ff18 | pbrook | cmos_ioport_write(s, addr >> s->it_shift, value & 0xFF);
|
653 | 2ca9d013 | ths | } |
654 | 2ca9d013 | ths | |
655 | 9596ebb7 | pbrook | static uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr) |
656 | 2ca9d013 | ths | { |
657 | 2ca9d013 | ths | RTCState *s = opaque; |
658 | 18c6e2ff | ths | uint32_t val; |
659 | 2ca9d013 | ths | |
660 | 8da3ff18 | pbrook | val = cmos_ioport_read(s, addr >> s->it_shift) & 0xFFFF;
|
661 | 18c6e2ff | ths | #ifdef TARGET_WORDS_BIGENDIAN
|
662 | 18c6e2ff | ths | val = bswap16(val); |
663 | 18c6e2ff | ths | #endif
|
664 | 18c6e2ff | ths | return val;
|
665 | 2ca9d013 | ths | } |
666 | 2ca9d013 | ths | |
667 | 9596ebb7 | pbrook | static void cmos_mm_writew (void *opaque, |
668 | 9596ebb7 | pbrook | target_phys_addr_t addr, uint32_t value) |
669 | 2ca9d013 | ths | { |
670 | 2ca9d013 | ths | RTCState *s = opaque; |
671 | 18c6e2ff | ths | #ifdef TARGET_WORDS_BIGENDIAN
|
672 | 18c6e2ff | ths | value = bswap16(value); |
673 | 18c6e2ff | ths | #endif
|
674 | 8da3ff18 | pbrook | cmos_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
|
675 | 2ca9d013 | ths | } |
676 | 2ca9d013 | ths | |
677 | 9596ebb7 | pbrook | static uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr) |
678 | 2ca9d013 | ths | { |
679 | 2ca9d013 | ths | RTCState *s = opaque; |
680 | 18c6e2ff | ths | uint32_t val; |
681 | 2ca9d013 | ths | |
682 | 8da3ff18 | pbrook | val = cmos_ioport_read(s, addr >> s->it_shift); |
683 | 18c6e2ff | ths | #ifdef TARGET_WORDS_BIGENDIAN
|
684 | 18c6e2ff | ths | val = bswap32(val); |
685 | 18c6e2ff | ths | #endif
|
686 | 18c6e2ff | ths | return val;
|
687 | 2ca9d013 | ths | } |
688 | 2ca9d013 | ths | |
689 | 9596ebb7 | pbrook | static void cmos_mm_writel (void *opaque, |
690 | 9596ebb7 | pbrook | target_phys_addr_t addr, uint32_t value) |
691 | 2ca9d013 | ths | { |
692 | 2ca9d013 | ths | RTCState *s = opaque; |
693 | 18c6e2ff | ths | #ifdef TARGET_WORDS_BIGENDIAN
|
694 | 18c6e2ff | ths | value = bswap32(value); |
695 | 18c6e2ff | ths | #endif
|
696 | 8da3ff18 | pbrook | cmos_ioport_write(s, addr >> s->it_shift, value); |
697 | 2ca9d013 | ths | } |
698 | 2ca9d013 | ths | |
699 | 2ca9d013 | ths | static CPUReadMemoryFunc *rtc_mm_read[] = {
|
700 | 2ca9d013 | ths | &cmos_mm_readb, |
701 | 2ca9d013 | ths | &cmos_mm_readw, |
702 | 2ca9d013 | ths | &cmos_mm_readl, |
703 | 2ca9d013 | ths | }; |
704 | 2ca9d013 | ths | |
705 | 2ca9d013 | ths | static CPUWriteMemoryFunc *rtc_mm_write[] = {
|
706 | 2ca9d013 | ths | &cmos_mm_writeb, |
707 | 2ca9d013 | ths | &cmos_mm_writew, |
708 | 2ca9d013 | ths | &cmos_mm_writel, |
709 | 2ca9d013 | ths | }; |
710 | 2ca9d013 | ths | |
711 | 42fc73a1 | aurel32 | RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
|
712 | 42fc73a1 | aurel32 | int base_year)
|
713 | 2ca9d013 | ths | { |
714 | 2ca9d013 | ths | RTCState *s; |
715 | 2ca9d013 | ths | int io_memory;
|
716 | 2ca9d013 | ths | |
717 | 2ca9d013 | ths | s = qemu_mallocz(sizeof(RTCState));
|
718 | 2ca9d013 | ths | |
719 | 2ca9d013 | ths | s->irq = irq; |
720 | 2ca9d013 | ths | s->cmos_data[RTC_REG_A] = 0x26;
|
721 | 2ca9d013 | ths | s->cmos_data[RTC_REG_B] = 0x02;
|
722 | 2ca9d013 | ths | s->cmos_data[RTC_REG_C] = 0x00;
|
723 | 2ca9d013 | ths | s->cmos_data[RTC_REG_D] = 0x80;
|
724 | 2ca9d013 | ths | |
725 | 42fc73a1 | aurel32 | s->base_year = base_year; |
726 | 2ca9d013 | ths | rtc_set_date_from_host(s); |
727 | 2ca9d013 | ths | |
728 | 2ca9d013 | ths | s->periodic_timer = qemu_new_timer(vm_clock, |
729 | 2ca9d013 | ths | rtc_periodic_timer, s); |
730 | 2ca9d013 | ths | s->second_timer = qemu_new_timer(vm_clock, |
731 | 2ca9d013 | ths | rtc_update_second, s); |
732 | 2ca9d013 | ths | s->second_timer2 = qemu_new_timer(vm_clock, |
733 | 2ca9d013 | ths | rtc_update_second2, s); |
734 | 2ca9d013 | ths | |
735 | 2ca9d013 | ths | s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100; |
736 | 2ca9d013 | ths | qemu_mod_timer(s->second_timer2, s->next_second_time); |
737 | 2ca9d013 | ths | |
738 | 1eed09cb | Avi Kivity | io_memory = cpu_register_io_memory(rtc_mm_read, rtc_mm_write, s); |
739 | 18c6e2ff | ths | cpu_register_physical_memory(base, 2 << it_shift, io_memory);
|
740 | 2ca9d013 | ths | |
741 | 2ca9d013 | ths | register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s); |
742 | 73822ec8 | aliguori | #ifdef TARGET_I386
|
743 | 73822ec8 | aliguori | if (rtc_td_hack)
|
744 | 73822ec8 | aliguori | register_savevm("mc146818rtc-td", base, 1, rtc_save_td, rtc_load_td, s); |
745 | 73822ec8 | aliguori | #endif
|
746 | eeb7c03c | Gleb Natapov | qemu_register_reset(rtc_reset, 0, s);
|
747 | 2ca9d013 | ths | return s;
|
748 | 2ca9d013 | ths | } |