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1 | b92e5a22 | bellard | /*
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2 | b92e5a22 | bellard | * Software MMU support
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3 | 5fafdf24 | ths | *
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4 | b92e5a22 | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | b92e5a22 | bellard | *
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6 | b92e5a22 | bellard | * This library is free software; you can redistribute it and/or
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7 | b92e5a22 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | b92e5a22 | bellard | * License as published by the Free Software Foundation; either
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9 | b92e5a22 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | b92e5a22 | bellard | *
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11 | b92e5a22 | bellard | * This library is distributed in the hope that it will be useful,
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12 | b92e5a22 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | b92e5a22 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | b92e5a22 | bellard | * Lesser General Public License for more details.
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15 | b92e5a22 | bellard | *
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16 | b92e5a22 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | b92e5a22 | bellard | * License along with this library; if not, write to the Free Software
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18 | fad6cb1a | aurel32 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
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19 | b92e5a22 | bellard | */
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20 | b92e5a22 | bellard | #define DATA_SIZE (1 << SHIFT) |
21 | b92e5a22 | bellard | |
22 | b92e5a22 | bellard | #if DATA_SIZE == 8 |
23 | b92e5a22 | bellard | #define SUFFIX q
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24 | 61382a50 | bellard | #define USUFFIX q
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25 | b92e5a22 | bellard | #define DATA_TYPE uint64_t
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26 | b92e5a22 | bellard | #elif DATA_SIZE == 4 |
27 | b92e5a22 | bellard | #define SUFFIX l
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28 | 61382a50 | bellard | #define USUFFIX l
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29 | b92e5a22 | bellard | #define DATA_TYPE uint32_t
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30 | b92e5a22 | bellard | #elif DATA_SIZE == 2 |
31 | b92e5a22 | bellard | #define SUFFIX w
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32 | 61382a50 | bellard | #define USUFFIX uw
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33 | b92e5a22 | bellard | #define DATA_TYPE uint16_t
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34 | b92e5a22 | bellard | #elif DATA_SIZE == 1 |
35 | b92e5a22 | bellard | #define SUFFIX b
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36 | 61382a50 | bellard | #define USUFFIX ub
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37 | b92e5a22 | bellard | #define DATA_TYPE uint8_t
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38 | b92e5a22 | bellard | #else
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39 | b92e5a22 | bellard | #error unsupported data size
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40 | b92e5a22 | bellard | #endif
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41 | b92e5a22 | bellard | |
42 | b769d8fe | bellard | #ifdef SOFTMMU_CODE_ACCESS
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43 | b769d8fe | bellard | #define READ_ACCESS_TYPE 2 |
44 | 84b7b8e7 | bellard | #define ADDR_READ addr_code
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45 | b769d8fe | bellard | #else
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46 | b769d8fe | bellard | #define READ_ACCESS_TYPE 0 |
47 | 84b7b8e7 | bellard | #define ADDR_READ addr_read
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48 | b769d8fe | bellard | #endif
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49 | b769d8fe | bellard | |
50 | 5fafdf24 | ths | static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
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51 | 6ebbf390 | j_mayer | int mmu_idx,
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52 | 61382a50 | bellard | void *retaddr);
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53 | 5fafdf24 | ths | static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr, |
54 | 2e70f6ef | pbrook | target_ulong addr, |
55 | 2e70f6ef | pbrook | void *retaddr)
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56 | b92e5a22 | bellard | { |
57 | b92e5a22 | bellard | DATA_TYPE res; |
58 | b92e5a22 | bellard | int index;
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59 | 0f459d16 | pbrook | index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
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60 | 0f459d16 | pbrook | physaddr = (physaddr & TARGET_PAGE_MASK) + addr; |
61 | 2e70f6ef | pbrook | env->mem_io_pc = (unsigned long)retaddr; |
62 | 2e70f6ef | pbrook | if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
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63 | 2e70f6ef | pbrook | && !can_do_io(env)) { |
64 | 2e70f6ef | pbrook | cpu_io_recompile(env, retaddr); |
65 | 2e70f6ef | pbrook | } |
66 | b92e5a22 | bellard | |
67 | db8886d3 | aliguori | env->mem_io_vaddr = addr; |
68 | b92e5a22 | bellard | #if SHIFT <= 2 |
69 | a4193c8a | bellard | res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr); |
70 | b92e5a22 | bellard | #else
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71 | b92e5a22 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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72 | a4193c8a | bellard | res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32; |
73 | a4193c8a | bellard | res |= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4); |
74 | b92e5a22 | bellard | #else
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75 | a4193c8a | bellard | res = io_mem_read[index][2](io_mem_opaque[index], physaddr);
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76 | a4193c8a | bellard | res |= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32; |
77 | b92e5a22 | bellard | #endif
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78 | b92e5a22 | bellard | #endif /* SHIFT > 2 */ |
79 | f1c85677 | bellard | #ifdef USE_KQEMU
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80 | f1c85677 | bellard | env->last_io_time = cpu_get_time_fast(); |
81 | f1c85677 | bellard | #endif
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82 | b92e5a22 | bellard | return res;
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83 | b92e5a22 | bellard | } |
84 | b92e5a22 | bellard | |
85 | b92e5a22 | bellard | /* handle all cases except unaligned access which span two pages */
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86 | d656469f | bellard | DATA_TYPE REGPARM glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr, |
87 | d656469f | bellard | int mmu_idx)
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88 | b92e5a22 | bellard | { |
89 | b92e5a22 | bellard | DATA_TYPE res; |
90 | 61382a50 | bellard | int index;
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91 | c27004ec | bellard | target_ulong tlb_addr; |
92 | 0f459d16 | pbrook | target_phys_addr_t addend; |
93 | b92e5a22 | bellard | void *retaddr;
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94 | 3b46e624 | ths | |
95 | b92e5a22 | bellard | /* test if there is match for unaligned or IO access */
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96 | b92e5a22 | bellard | /* XXX: could done more in memory macro in a non portable way */
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97 | b92e5a22 | bellard | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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98 | b92e5a22 | bellard | redo:
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99 | 6ebbf390 | j_mayer | tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ; |
100 | b92e5a22 | bellard | if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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101 | b92e5a22 | bellard | if (tlb_addr & ~TARGET_PAGE_MASK) {
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102 | b92e5a22 | bellard | /* IO access */
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103 | b92e5a22 | bellard | if ((addr & (DATA_SIZE - 1)) != 0) |
104 | b92e5a22 | bellard | goto do_unaligned_access;
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105 | 2e70f6ef | pbrook | retaddr = GETPC(); |
106 | 0f459d16 | pbrook | addend = env->iotlb[mmu_idx][index]; |
107 | 2e70f6ef | pbrook | res = glue(io_read, SUFFIX)(addend, addr, retaddr); |
108 | 98699967 | bellard | } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) { |
109 | b92e5a22 | bellard | /* slow unaligned access (it spans two pages or IO) */
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110 | b92e5a22 | bellard | do_unaligned_access:
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111 | 61382a50 | bellard | retaddr = GETPC(); |
112 | a64d4718 | bellard | #ifdef ALIGNED_ONLY
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113 | 6ebbf390 | j_mayer | do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr); |
114 | a64d4718 | bellard | #endif
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115 | 5fafdf24 | ths | res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr, |
116 | 6ebbf390 | j_mayer | mmu_idx, retaddr); |
117 | b92e5a22 | bellard | } else {
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118 | a64d4718 | bellard | /* unaligned/aligned access in the same page */
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119 | a64d4718 | bellard | #ifdef ALIGNED_ONLY
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120 | a64d4718 | bellard | if ((addr & (DATA_SIZE - 1)) != 0) { |
121 | a64d4718 | bellard | retaddr = GETPC(); |
122 | 6ebbf390 | j_mayer | do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr); |
123 | a64d4718 | bellard | } |
124 | a64d4718 | bellard | #endif
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125 | 0f459d16 | pbrook | addend = env->tlb_table[mmu_idx][index].addend; |
126 | 0f459d16 | pbrook | res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
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127 | b92e5a22 | bellard | } |
128 | b92e5a22 | bellard | } else {
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129 | b92e5a22 | bellard | /* the page is not in the TLB : fill it */
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130 | 61382a50 | bellard | retaddr = GETPC(); |
131 | a64d4718 | bellard | #ifdef ALIGNED_ONLY
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132 | a64d4718 | bellard | if ((addr & (DATA_SIZE - 1)) != 0) |
133 | 6ebbf390 | j_mayer | do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr); |
134 | a64d4718 | bellard | #endif
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135 | 6ebbf390 | j_mayer | tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr); |
136 | b92e5a22 | bellard | goto redo;
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137 | b92e5a22 | bellard | } |
138 | b92e5a22 | bellard | return res;
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139 | b92e5a22 | bellard | } |
140 | b92e5a22 | bellard | |
141 | b92e5a22 | bellard | /* handle all unaligned cases */
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142 | 5fafdf24 | ths | static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
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143 | 6ebbf390 | j_mayer | int mmu_idx,
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144 | 61382a50 | bellard | void *retaddr)
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145 | b92e5a22 | bellard | { |
146 | b92e5a22 | bellard | DATA_TYPE res, res1, res2; |
147 | 61382a50 | bellard | int index, shift;
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148 | 0f459d16 | pbrook | target_phys_addr_t addend; |
149 | c27004ec | bellard | target_ulong tlb_addr, addr1, addr2; |
150 | b92e5a22 | bellard | |
151 | b92e5a22 | bellard | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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152 | b92e5a22 | bellard | redo:
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153 | 6ebbf390 | j_mayer | tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ; |
154 | b92e5a22 | bellard | if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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155 | b92e5a22 | bellard | if (tlb_addr & ~TARGET_PAGE_MASK) {
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156 | b92e5a22 | bellard | /* IO access */
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157 | b92e5a22 | bellard | if ((addr & (DATA_SIZE - 1)) != 0) |
158 | b92e5a22 | bellard | goto do_unaligned_access;
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159 | 2e70f6ef | pbrook | retaddr = GETPC(); |
160 | 0f459d16 | pbrook | addend = env->iotlb[mmu_idx][index]; |
161 | 2e70f6ef | pbrook | res = glue(io_read, SUFFIX)(addend, addr, retaddr); |
162 | 98699967 | bellard | } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) { |
163 | b92e5a22 | bellard | do_unaligned_access:
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164 | b92e5a22 | bellard | /* slow unaligned access (it spans two pages) */
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165 | b92e5a22 | bellard | addr1 = addr & ~(DATA_SIZE - 1);
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166 | b92e5a22 | bellard | addr2 = addr1 + DATA_SIZE; |
167 | 5fafdf24 | ths | res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr1, |
168 | 6ebbf390 | j_mayer | mmu_idx, retaddr); |
169 | 5fafdf24 | ths | res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr2, |
170 | 6ebbf390 | j_mayer | mmu_idx, retaddr); |
171 | b92e5a22 | bellard | shift = (addr & (DATA_SIZE - 1)) * 8; |
172 | b92e5a22 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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173 | b92e5a22 | bellard | res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
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174 | b92e5a22 | bellard | #else
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175 | b92e5a22 | bellard | res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
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176 | b92e5a22 | bellard | #endif
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177 | 6986f88c | bellard | res = (DATA_TYPE)res; |
178 | b92e5a22 | bellard | } else {
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179 | b92e5a22 | bellard | /* unaligned/aligned access in the same page */
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180 | 0f459d16 | pbrook | addend = env->tlb_table[mmu_idx][index].addend; |
181 | 0f459d16 | pbrook | res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
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182 | b92e5a22 | bellard | } |
183 | b92e5a22 | bellard | } else {
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184 | b92e5a22 | bellard | /* the page is not in the TLB : fill it */
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185 | 6ebbf390 | j_mayer | tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr); |
186 | b92e5a22 | bellard | goto redo;
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187 | b92e5a22 | bellard | } |
188 | b92e5a22 | bellard | return res;
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189 | b92e5a22 | bellard | } |
190 | b92e5a22 | bellard | |
191 | b769d8fe | bellard | #ifndef SOFTMMU_CODE_ACCESS
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192 | b769d8fe | bellard | |
193 | 5fafdf24 | ths | static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr, |
194 | 5fafdf24 | ths | DATA_TYPE val, |
195 | 6ebbf390 | j_mayer | int mmu_idx,
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196 | b769d8fe | bellard | void *retaddr);
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197 | b769d8fe | bellard | |
198 | 5fafdf24 | ths | static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr, |
199 | b769d8fe | bellard | DATA_TYPE val, |
200 | 0f459d16 | pbrook | target_ulong addr, |
201 | b769d8fe | bellard | void *retaddr)
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202 | b769d8fe | bellard | { |
203 | b769d8fe | bellard | int index;
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204 | 0f459d16 | pbrook | index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
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205 | 0f459d16 | pbrook | physaddr = (physaddr & TARGET_PAGE_MASK) + addr; |
206 | 2e70f6ef | pbrook | if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
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207 | 2e70f6ef | pbrook | && !can_do_io(env)) { |
208 | 2e70f6ef | pbrook | cpu_io_recompile(env, retaddr); |
209 | 2e70f6ef | pbrook | } |
210 | b769d8fe | bellard | |
211 | 2e70f6ef | pbrook | env->mem_io_vaddr = addr; |
212 | 2e70f6ef | pbrook | env->mem_io_pc = (unsigned long)retaddr; |
213 | b769d8fe | bellard | #if SHIFT <= 2 |
214 | b769d8fe | bellard | io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val); |
215 | b769d8fe | bellard | #else
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216 | b769d8fe | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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217 | b769d8fe | bellard | io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32); |
218 | b769d8fe | bellard | io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val); |
219 | b769d8fe | bellard | #else
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220 | b769d8fe | bellard | io_mem_write[index][2](io_mem_opaque[index], physaddr, val);
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221 | b769d8fe | bellard | io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32); |
222 | b769d8fe | bellard | #endif
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223 | b769d8fe | bellard | #endif /* SHIFT > 2 */ |
224 | f1c85677 | bellard | #ifdef USE_KQEMU
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225 | f1c85677 | bellard | env->last_io_time = cpu_get_time_fast(); |
226 | f1c85677 | bellard | #endif
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227 | b769d8fe | bellard | } |
228 | b92e5a22 | bellard | |
229 | d656469f | bellard | void REGPARM glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
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230 | d656469f | bellard | DATA_TYPE val, |
231 | d656469f | bellard | int mmu_idx)
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232 | b92e5a22 | bellard | { |
233 | 0f459d16 | pbrook | target_phys_addr_t addend; |
234 | c27004ec | bellard | target_ulong tlb_addr; |
235 | b92e5a22 | bellard | void *retaddr;
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236 | 61382a50 | bellard | int index;
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237 | 3b46e624 | ths | |
238 | b92e5a22 | bellard | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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239 | b92e5a22 | bellard | redo:
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240 | 6ebbf390 | j_mayer | tlb_addr = env->tlb_table[mmu_idx][index].addr_write; |
241 | b92e5a22 | bellard | if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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242 | b92e5a22 | bellard | if (tlb_addr & ~TARGET_PAGE_MASK) {
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243 | b92e5a22 | bellard | /* IO access */
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244 | b92e5a22 | bellard | if ((addr & (DATA_SIZE - 1)) != 0) |
245 | b92e5a22 | bellard | goto do_unaligned_access;
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246 | d720b93d | bellard | retaddr = GETPC(); |
247 | 0f459d16 | pbrook | addend = env->iotlb[mmu_idx][index]; |
248 | 0f459d16 | pbrook | glue(io_write, SUFFIX)(addend, val, addr, retaddr); |
249 | 98699967 | bellard | } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) { |
250 | b92e5a22 | bellard | do_unaligned_access:
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251 | 61382a50 | bellard | retaddr = GETPC(); |
252 | a64d4718 | bellard | #ifdef ALIGNED_ONLY
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253 | 6ebbf390 | j_mayer | do_unaligned_access(addr, 1, mmu_idx, retaddr);
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254 | a64d4718 | bellard | #endif
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255 | 5fafdf24 | ths | glue(glue(slow_st, SUFFIX), MMUSUFFIX)(addr, val, |
256 | 6ebbf390 | j_mayer | mmu_idx, retaddr); |
257 | b92e5a22 | bellard | } else {
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258 | b92e5a22 | bellard | /* aligned/unaligned access in the same page */
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259 | a64d4718 | bellard | #ifdef ALIGNED_ONLY
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260 | a64d4718 | bellard | if ((addr & (DATA_SIZE - 1)) != 0) { |
261 | a64d4718 | bellard | retaddr = GETPC(); |
262 | 6ebbf390 | j_mayer | do_unaligned_access(addr, 1, mmu_idx, retaddr);
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263 | a64d4718 | bellard | } |
264 | a64d4718 | bellard | #endif
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265 | 0f459d16 | pbrook | addend = env->tlb_table[mmu_idx][index].addend; |
266 | 0f459d16 | pbrook | glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
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267 | b92e5a22 | bellard | } |
268 | b92e5a22 | bellard | } else {
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269 | b92e5a22 | bellard | /* the page is not in the TLB : fill it */
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270 | 61382a50 | bellard | retaddr = GETPC(); |
271 | a64d4718 | bellard | #ifdef ALIGNED_ONLY
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272 | a64d4718 | bellard | if ((addr & (DATA_SIZE - 1)) != 0) |
273 | 6ebbf390 | j_mayer | do_unaligned_access(addr, 1, mmu_idx, retaddr);
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274 | a64d4718 | bellard | #endif
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275 | 6ebbf390 | j_mayer | tlb_fill(addr, 1, mmu_idx, retaddr);
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276 | b92e5a22 | bellard | goto redo;
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277 | b92e5a22 | bellard | } |
278 | b92e5a22 | bellard | } |
279 | b92e5a22 | bellard | |
280 | b92e5a22 | bellard | /* handles all unaligned cases */
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281 | 5fafdf24 | ths | static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr, |
282 | 61382a50 | bellard | DATA_TYPE val, |
283 | 6ebbf390 | j_mayer | int mmu_idx,
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284 | 61382a50 | bellard | void *retaddr)
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285 | b92e5a22 | bellard | { |
286 | 0f459d16 | pbrook | target_phys_addr_t addend; |
287 | c27004ec | bellard | target_ulong tlb_addr; |
288 | 61382a50 | bellard | int index, i;
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289 | b92e5a22 | bellard | |
290 | b92e5a22 | bellard | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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291 | b92e5a22 | bellard | redo:
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292 | 6ebbf390 | j_mayer | tlb_addr = env->tlb_table[mmu_idx][index].addr_write; |
293 | b92e5a22 | bellard | if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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294 | b92e5a22 | bellard | if (tlb_addr & ~TARGET_PAGE_MASK) {
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295 | b92e5a22 | bellard | /* IO access */
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296 | b92e5a22 | bellard | if ((addr & (DATA_SIZE - 1)) != 0) |
297 | b92e5a22 | bellard | goto do_unaligned_access;
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298 | 0f459d16 | pbrook | addend = env->iotlb[mmu_idx][index]; |
299 | 0f459d16 | pbrook | glue(io_write, SUFFIX)(addend, val, addr, retaddr); |
300 | 98699967 | bellard | } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) { |
301 | b92e5a22 | bellard | do_unaligned_access:
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302 | b92e5a22 | bellard | /* XXX: not efficient, but simple */
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303 | 6c41b272 | balrog | /* Note: relies on the fact that tlb_fill() does not remove the
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304 | 6c41b272 | balrog | * previous page from the TLB cache. */
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305 | 7221fa98 | balrog | for(i = DATA_SIZE - 1; i >= 0; i--) { |
306 | b92e5a22 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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307 | 5fafdf24 | ths | glue(slow_stb, MMUSUFFIX)(addr + i, val >> (((DATA_SIZE - 1) * 8) - (i * 8)), |
308 | 6ebbf390 | j_mayer | mmu_idx, retaddr); |
309 | b92e5a22 | bellard | #else
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310 | 5fafdf24 | ths | glue(slow_stb, MMUSUFFIX)(addr + i, val >> (i * 8),
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311 | 6ebbf390 | j_mayer | mmu_idx, retaddr); |
312 | b92e5a22 | bellard | #endif
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313 | b92e5a22 | bellard | } |
314 | b92e5a22 | bellard | } else {
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315 | b92e5a22 | bellard | /* aligned/unaligned access in the same page */
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316 | 0f459d16 | pbrook | addend = env->tlb_table[mmu_idx][index].addend; |
317 | 0f459d16 | pbrook | glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
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318 | b92e5a22 | bellard | } |
319 | b92e5a22 | bellard | } else {
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320 | b92e5a22 | bellard | /* the page is not in the TLB : fill it */
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321 | 6ebbf390 | j_mayer | tlb_fill(addr, 1, mmu_idx, retaddr);
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322 | b92e5a22 | bellard | goto redo;
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323 | b92e5a22 | bellard | } |
324 | b92e5a22 | bellard | } |
325 | b92e5a22 | bellard | |
326 | b769d8fe | bellard | #endif /* !defined(SOFTMMU_CODE_ACCESS) */ |
327 | b769d8fe | bellard | |
328 | b769d8fe | bellard | #undef READ_ACCESS_TYPE
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329 | b92e5a22 | bellard | #undef SHIFT
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330 | b92e5a22 | bellard | #undef DATA_TYPE
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331 | b92e5a22 | bellard | #undef SUFFIX
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332 | 61382a50 | bellard | #undef USUFFIX
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333 | b92e5a22 | bellard | #undef DATA_SIZE
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334 | 84b7b8e7 | bellard | #undef ADDR_READ |