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1 | d4abd567 | blueswir1 | /*
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2 | d4abd567 | blueswir1 | * These files from binutils are concatenated:
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3 | d4abd567 | blueswir1 | * include/opcode/sparc.h, opcodes/sparc-opc.c, opcodes/sparc-dis.c
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4 | d4abd567 | blueswir1 | */
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5 | d4abd567 | blueswir1 | |
6 | d4abd567 | blueswir1 | /* include/opcode/sparc.h */
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7 | d4abd567 | blueswir1 | |
8 | 46f42f29 | blueswir1 | /* Definitions for opcode table for the sparc.
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9 | 46f42f29 | blueswir1 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002,
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10 | 46f42f29 | blueswir1 | 2003, 2005 Free Software Foundation, Inc.
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11 | 46f42f29 | blueswir1 | |
12 | 46f42f29 | blueswir1 | This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
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13 | 46f42f29 | blueswir1 | the GNU Binutils.
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14 | 46f42f29 | blueswir1 | |
15 | 46f42f29 | blueswir1 | GAS/GDB is free software; you can redistribute it and/or modify
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16 | 46f42f29 | blueswir1 | it under the terms of the GNU General Public License as published by
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17 | 46f42f29 | blueswir1 | the Free Software Foundation; either version 2, or (at your option)
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18 | 46f42f29 | blueswir1 | any later version.
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19 | aa0aa4fa | bellard | |
20 | 46f42f29 | blueswir1 | GAS/GDB is distributed in the hope that it will be useful,
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21 | 46f42f29 | blueswir1 | but WITHOUT ANY WARRANTY; without even the implied warranty of
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22 | 46f42f29 | blueswir1 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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23 | 46f42f29 | blueswir1 | GNU General Public License for more details.
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24 | aa0aa4fa | bellard | |
25 | 46f42f29 | blueswir1 | You should have received a copy of the GNU General Public License
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26 | 8167ee88 | Blue Swirl | along with GAS or GDB; see the file COPYING. If not,
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27 | 8167ee88 | Blue Swirl | see <http://www.gnu.org/licenses/>. */
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28 | aa0aa4fa | bellard | |
29 | aa0aa4fa | bellard | #include <stdlib.h> |
30 | aa0aa4fa | bellard | #include "dis-asm.h" |
31 | aa0aa4fa | bellard | |
32 | aa0aa4fa | bellard | /* The SPARC opcode table (and other related data) is defined in
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33 | aa0aa4fa | bellard | the opcodes library in sparc-opc.c. If you change anything here, make
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34 | aa0aa4fa | bellard | sure you fix up that file, and vice versa. */
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35 | aa0aa4fa | bellard | |
36 | aa0aa4fa | bellard | /* FIXME-someday: perhaps the ,a's and such should be embedded in the
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37 | aa0aa4fa | bellard | instruction's name rather than the args. This would make gas faster, pinsn
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38 | aa0aa4fa | bellard | slower, but would mess up some macros a bit. xoxorich. */
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39 | aa0aa4fa | bellard | |
40 | aa0aa4fa | bellard | /* List of instruction sets variations.
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41 | aa0aa4fa | bellard | These values are such that each element is either a superset of a
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42 | aa0aa4fa | bellard | preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P
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43 | aa0aa4fa | bellard | returns non-zero.
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44 | aa0aa4fa | bellard | The values are indices into `sparc_opcode_archs' defined in sparc-opc.c.
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45 | aa0aa4fa | bellard | Don't change this without updating sparc-opc.c. */
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46 | aa0aa4fa | bellard | |
47 | 46f42f29 | blueswir1 | enum sparc_opcode_arch_val
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48 | 46f42f29 | blueswir1 | { |
49 | aa0aa4fa | bellard | SPARC_OPCODE_ARCH_V6 = 0,
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50 | aa0aa4fa | bellard | SPARC_OPCODE_ARCH_V7, |
51 | aa0aa4fa | bellard | SPARC_OPCODE_ARCH_V8, |
52 | aa0aa4fa | bellard | SPARC_OPCODE_ARCH_SPARCLET, |
53 | aa0aa4fa | bellard | SPARC_OPCODE_ARCH_SPARCLITE, |
54 | 46f42f29 | blueswir1 | /* V9 variants must appear last. */
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55 | aa0aa4fa | bellard | SPARC_OPCODE_ARCH_V9, |
56 | 46f42f29 | blueswir1 | SPARC_OPCODE_ARCH_V9A, /* V9 with ultrasparc additions. */
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57 | 46f42f29 | blueswir1 | SPARC_OPCODE_ARCH_V9B, /* V9 with ultrasparc and cheetah additions. */
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58 | 46f42f29 | blueswir1 | SPARC_OPCODE_ARCH_BAD /* Error return from sparc_opcode_lookup_arch. */
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59 | aa0aa4fa | bellard | }; |
60 | aa0aa4fa | bellard | |
61 | aa0aa4fa | bellard | /* The highest architecture in the table. */
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62 | aa0aa4fa | bellard | #define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1) |
63 | aa0aa4fa | bellard | |
64 | aa0aa4fa | bellard | /* Given an enum sparc_opcode_arch_val, return the bitmask to use in
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65 | aa0aa4fa | bellard | insn encoding/decoding. */
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66 | aa0aa4fa | bellard | #define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch)) |
67 | aa0aa4fa | bellard | |
68 | aa0aa4fa | bellard | /* Given a valid sparc_opcode_arch_val, return non-zero if it's v9. */
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69 | aa0aa4fa | bellard | #define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9)
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70 | aa0aa4fa | bellard | |
71 | aa0aa4fa | bellard | /* Table of cpu variants. */
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72 | aa0aa4fa | bellard | |
73 | 46f42f29 | blueswir1 | typedef struct sparc_opcode_arch |
74 | 46f42f29 | blueswir1 | { |
75 | aa0aa4fa | bellard | const char *name; |
76 | aa0aa4fa | bellard | /* Mask of sparc_opcode_arch_val's supported.
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77 | aa0aa4fa | bellard | EG: For v7 this would be
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78 | aa0aa4fa | bellard | (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)).
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79 | aa0aa4fa | bellard | These are short's because sparc_opcode.architecture is. */
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80 | aa0aa4fa | bellard | short supported;
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81 | 46f42f29 | blueswir1 | } sparc_opcode_arch; |
82 | aa0aa4fa | bellard | |
83 | f82a3d48 | blueswir1 | static const struct sparc_opcode_arch sparc_opcode_archs[]; |
84 | aa0aa4fa | bellard | |
85 | aa0aa4fa | bellard | /* Return the bitmask of supported architectures for ARCH. */
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86 | aa0aa4fa | bellard | #define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported)
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87 | aa0aa4fa | bellard | |
88 | aa0aa4fa | bellard | /* Non-zero if ARCH1 conflicts with ARCH2.
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89 | aa0aa4fa | bellard | IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */
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90 | aa0aa4fa | bellard | #define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \
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91 | 46f42f29 | blueswir1 | (((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ |
92 | 46f42f29 | blueswir1 | != SPARC_OPCODE_SUPPORTED (ARCH1)) \ |
93 | 46f42f29 | blueswir1 | && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ |
94 | aa0aa4fa | bellard | != SPARC_OPCODE_SUPPORTED (ARCH2))) |
95 | aa0aa4fa | bellard | |
96 | aa0aa4fa | bellard | /* Structure of an opcode table entry. */
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97 | aa0aa4fa | bellard | |
98 | 46f42f29 | blueswir1 | typedef struct sparc_opcode |
99 | 46f42f29 | blueswir1 | { |
100 | aa0aa4fa | bellard | const char *name; |
101 | 46f42f29 | blueswir1 | unsigned long match; /* Bits that must be set. */ |
102 | 46f42f29 | blueswir1 | unsigned long lose; /* Bits that must not be set. */ |
103 | aa0aa4fa | bellard | const char *args; |
104 | 46f42f29 | blueswir1 | /* This was called "delayed" in versions before the flags. */
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105 | aa0aa4fa | bellard | char flags;
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106 | f930d07e | blueswir1 | short architecture; /* Bitmask of sparc_opcode_arch_val's. */ |
107 | 46f42f29 | blueswir1 | } sparc_opcode; |
108 | 46f42f29 | blueswir1 | |
109 | 46f42f29 | blueswir1 | #define F_DELAYED 1 /* Delayed branch. */ |
110 | 46f42f29 | blueswir1 | #define F_ALIAS 2 /* Alias for a "real" instruction. */ |
111 | 46f42f29 | blueswir1 | #define F_UNBR 4 /* Unconditional branch. */ |
112 | 46f42f29 | blueswir1 | #define F_CONDBR 8 /* Conditional branch. */ |
113 | 46f42f29 | blueswir1 | #define F_JSR 16 /* Subroutine call. */ |
114 | 46f42f29 | blueswir1 | #define F_FLOAT 32 /* Floating point instruction (not a branch). */ |
115 | 46f42f29 | blueswir1 | #define F_FBR 64 /* Floating point branch. */ |
116 | aa0aa4fa | bellard | /* FIXME: Add F_ANACHRONISTIC flag for v9. */
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117 | aa0aa4fa | bellard | |
118 | 46f42f29 | blueswir1 | /* All sparc opcodes are 32 bits, except for the `set' instruction (really a
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119 | 46f42f29 | blueswir1 | macro), which is 64 bits. It is handled as a special case.
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120 | aa0aa4fa | bellard | |
121 | 46f42f29 | blueswir1 | The match component is a mask saying which bits must match a particular
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122 | 46f42f29 | blueswir1 | opcode in order for an instruction to be an instance of that opcode.
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123 | aa0aa4fa | bellard | |
124 | 46f42f29 | blueswir1 | The args component is a string containing one character for each operand of the
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125 | 46f42f29 | blueswir1 | instruction.
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126 | aa0aa4fa | bellard | |
127 | 46f42f29 | blueswir1 | Kinds of operands:
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128 | f930d07e | blueswir1 | # Number used by optimizer. It is ignored.
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129 | f930d07e | blueswir1 | 1 rs1 register.
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130 | f930d07e | blueswir1 | 2 rs2 register.
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131 | f930d07e | blueswir1 | d rd register.
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132 | f930d07e | blueswir1 | e frs1 floating point register.
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133 | f930d07e | blueswir1 | v frs1 floating point register (double/even).
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134 | f930d07e | blueswir1 | V frs1 floating point register (quad/multiple of 4).
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135 | f930d07e | blueswir1 | f frs2 floating point register.
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136 | f930d07e | blueswir1 | B frs2 floating point register (double/even).
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137 | f930d07e | blueswir1 | R frs2 floating point register (quad/multiple of 4).
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138 | f930d07e | blueswir1 | g frsd floating point register.
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139 | f930d07e | blueswir1 | H frsd floating point register (double/even).
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140 | f930d07e | blueswir1 | J frsd floating point register (quad/multiple of 4).
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141 | f930d07e | blueswir1 | b crs1 coprocessor register
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142 | f930d07e | blueswir1 | c crs2 coprocessor register
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143 | f930d07e | blueswir1 | D crsd coprocessor register
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144 | f930d07e | blueswir1 | m alternate space register (asr) in rd
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145 | f930d07e | blueswir1 | M alternate space register (asr) in rs1
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146 | f930d07e | blueswir1 | h 22 high bits.
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147 | f930d07e | blueswir1 | X 5 bit unsigned immediate
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148 | f930d07e | blueswir1 | Y 6 bit unsigned immediate
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149 | f930d07e | blueswir1 | 3 SIAM mode (3 bits). (v9b)
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150 | f930d07e | blueswir1 | K MEMBAR mask (7 bits). (v9)
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151 | f930d07e | blueswir1 | j 10 bit Immediate. (v9)
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152 | f930d07e | blueswir1 | I 11 bit Immediate. (v9)
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153 | f930d07e | blueswir1 | i 13 bit Immediate.
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154 | f930d07e | blueswir1 | n 22 bit immediate.
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155 | f930d07e | blueswir1 | k 2+14 bit PC relative immediate. (v9)
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156 | f930d07e | blueswir1 | G 19 bit PC relative immediate. (v9)
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157 | f930d07e | blueswir1 | l 22 bit PC relative immediate.
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158 | f930d07e | blueswir1 | L 30 bit PC relative immediate.
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159 | f930d07e | blueswir1 | a Annul. The annul bit is set.
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160 | f930d07e | blueswir1 | A Alternate address space. Stored as 8 bits.
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161 | f930d07e | blueswir1 | C Coprocessor state register.
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162 | f930d07e | blueswir1 | F floating point state register.
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163 | f930d07e | blueswir1 | p Processor state register.
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164 | f930d07e | blueswir1 | N Branch predict clear ",pn" (v9)
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165 | f930d07e | blueswir1 | T Branch predict set ",pt" (v9)
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166 | f930d07e | blueswir1 | z %icc. (v9)
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167 | f930d07e | blueswir1 | Z %xcc. (v9)
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168 | f930d07e | blueswir1 | q Floating point queue.
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169 | f930d07e | blueswir1 | r Single register that is both rs1 and rd.
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170 | f930d07e | blueswir1 | O Single register that is both rs2 and rd.
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171 | f930d07e | blueswir1 | Q Coprocessor queue.
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172 | f930d07e | blueswir1 | S Special case.
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173 | f930d07e | blueswir1 | t Trap base register.
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174 | f930d07e | blueswir1 | w Window invalid mask register.
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175 | f930d07e | blueswir1 | y Y register.
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176 | f930d07e | blueswir1 | u sparclet coprocessor registers in rd position
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177 | f930d07e | blueswir1 | U sparclet coprocessor registers in rs1 position
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178 | f930d07e | blueswir1 | E %ccr. (v9)
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179 | f930d07e | blueswir1 | s %fprs. (v9)
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180 | f930d07e | blueswir1 | P %pc. (v9)
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181 | f930d07e | blueswir1 | W %tick. (v9)
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182 | f930d07e | blueswir1 | o %asi. (v9)
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183 | f930d07e | blueswir1 | 6 %fcc0. (v9)
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184 | f930d07e | blueswir1 | 7 %fcc1. (v9)
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185 | f930d07e | blueswir1 | 8 %fcc2. (v9)
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186 | f930d07e | blueswir1 | 9 %fcc3. (v9)
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187 | f930d07e | blueswir1 | ! Privileged Register in rd (v9)
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188 | f930d07e | blueswir1 | ? Privileged Register in rs1 (v9)
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189 | f930d07e | blueswir1 | * Prefetch function constant. (v9)
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190 | f930d07e | blueswir1 | x OPF field (v9 impdep).
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191 | f930d07e | blueswir1 | 0 32/64 bit immediate for set or setx (v9) insns
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192 | f930d07e | blueswir1 | _ Ancillary state register in rd (v9a)
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193 | f930d07e | blueswir1 | / Ancillary state register in rs1 (v9a)
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194 | aa0aa4fa | bellard | |
195 | 46f42f29 | blueswir1 | The following chars are unused: (note: ,[] are used as punctuation)
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196 | 46f42f29 | blueswir1 | [45]. */
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197 | 46f42f29 | blueswir1 | |
198 | 46f42f29 | blueswir1 | #define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */ |
199 | 46f42f29 | blueswir1 | #define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */ |
200 | 46f42f29 | blueswir1 | #define OP(x) ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns. */ |
201 | 46f42f29 | blueswir1 | #define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */ |
202 | 46f42f29 | blueswir1 | #define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */ |
203 | 46f42f29 | blueswir1 | #define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */ |
204 | 46f42f29 | blueswir1 | #define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */ |
205 | 46f42f29 | blueswir1 | #define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */ |
206 | 46f42f29 | blueswir1 | #define F3(x, y, z) (OP (x) | OP3(y) | F3I(z)) /* Format3 insns. */ |
207 | 46f42f29 | blueswir1 | #define F1(x) (OP (x))
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208 | 46f42f29 | blueswir1 | #define DISP30(x) ((x) & 0x3fffffff) |
209 | 46f42f29 | blueswir1 | #define ASI(x) (((x) & 0xff) << 5) /* Asi field of format3 insns. */ |
210 | 46f42f29 | blueswir1 | #define RS2(x) ((x) & 0x1f) /* Rs2 field. */ |
211 | 46f42f29 | blueswir1 | #define SIMM13(x) ((x) & 0x1fff) /* Simm13 field. */ |
212 | 46f42f29 | blueswir1 | #define RD(x) (((x) & 0x1f) << 25) /* Destination register field. */ |
213 | 46f42f29 | blueswir1 | #define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */ |
214 | 46f42f29 | blueswir1 | #define ASI_RS2(x) (SIMM13 (x))
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215 | 46f42f29 | blueswir1 | #define MEMBAR(x) ((x) & 0x7f) |
216 | 46f42f29 | blueswir1 | #define SLCPOP(x) (((x) & 0x7f) << 6) /* Sparclet cpop. */ |
217 | 46f42f29 | blueswir1 | |
218 | 46f42f29 | blueswir1 | #define ANNUL (1 << 29) |
219 | 46f42f29 | blueswir1 | #define BPRED (1 << 19) /* V9. */ |
220 | 46f42f29 | blueswir1 | #define IMMED F3I (1) |
221 | 46f42f29 | blueswir1 | #define RD_G0 RD (~0) |
222 | 46f42f29 | blueswir1 | #define RS1_G0 RS1 (~0) |
223 | 46f42f29 | blueswir1 | #define RS2_G0 RS2 (~0) |
224 | aa0aa4fa | bellard | |
225 | f82a3d48 | blueswir1 | static const struct sparc_opcode sparc_opcodes[]; |
226 | aa0aa4fa | bellard | |
227 | 46f42f29 | blueswir1 | static const char *sparc_decode_asi_v8 (int); |
228 | 46f42f29 | blueswir1 | static const char *sparc_decode_asi_v9 (int); |
229 | 46f42f29 | blueswir1 | static const char *sparc_decode_membar (int); |
230 | 46f42f29 | blueswir1 | static const char *sparc_decode_prefetch (int); |
231 | 46f42f29 | blueswir1 | static const char *sparc_decode_sparclet_cpreg (int); |
232 | 46f42f29 | blueswir1 | |
233 | 46f42f29 | blueswir1 | /* Local Variables:
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234 | 46f42f29 | blueswir1 | fill-column: 131
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235 | 46f42f29 | blueswir1 | comment-column: 0
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236 | 46f42f29 | blueswir1 | End: */
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237 | aa0aa4fa | bellard | |
238 | d4abd567 | blueswir1 | /* opcodes/sparc-opc.c */
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239 | d4abd567 | blueswir1 | |
240 | 46f42f29 | blueswir1 | /* Table of opcodes for the sparc.
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241 | 46f42f29 | blueswir1 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
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242 | 46f42f29 | blueswir1 | 2000, 2002, 2004, 2005
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243 | 46f42f29 | blueswir1 | Free Software Foundation, Inc.
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244 | 46f42f29 | blueswir1 | |
245 | 46f42f29 | blueswir1 | This file is part of the BFD library.
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246 | 46f42f29 | blueswir1 | |
247 | 46f42f29 | blueswir1 | BFD is free software; you can redistribute it and/or modify it under
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248 | 46f42f29 | blueswir1 | the terms of the GNU General Public License as published by the Free
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249 | 46f42f29 | blueswir1 | Software Foundation; either version 2, or (at your option) any later
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250 | 46f42f29 | blueswir1 | version.
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251 | 46f42f29 | blueswir1 | |
252 | 46f42f29 | blueswir1 | BFD is distributed in the hope that it will be useful, but WITHOUT ANY
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253 | 46f42f29 | blueswir1 | WARRANTY; without even the implied warranty of MERCHANTABILITY or
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254 | 46f42f29 | blueswir1 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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255 | 46f42f29 | blueswir1 | for more details.
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256 | 46f42f29 | blueswir1 | |
257 | 46f42f29 | blueswir1 | You should have received a copy of the GNU General Public License
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258 | 8167ee88 | Blue Swirl | along with this software; see the file COPYING. If not,
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259 | 8167ee88 | Blue Swirl | see <http://www.gnu.org/licenses/>. */
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260 | 46f42f29 | blueswir1 | |
261 | 46f42f29 | blueswir1 | /* FIXME-someday: perhaps the ,a's and such should be embedded in the
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262 | 46f42f29 | blueswir1 | instruction's name rather than the args. This would make gas faster, pinsn
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263 | 46f42f29 | blueswir1 | slower, but would mess up some macros a bit. xoxorich. */
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264 | 46f42f29 | blueswir1 | |
265 | aa0aa4fa | bellard | /* Some defines to make life easy. */
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266 | f930d07e | blueswir1 | #define MASK_V6 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6)
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267 | f930d07e | blueswir1 | #define MASK_V7 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7)
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268 | f930d07e | blueswir1 | #define MASK_V8 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)
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269 | f930d07e | blueswir1 | #define MASK_SPARCLET SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET)
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270 | f930d07e | blueswir1 | #define MASK_SPARCLITE SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
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271 | f930d07e | blueswir1 | #define MASK_V9 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9)
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272 | f930d07e | blueswir1 | #define MASK_V9A SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)
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273 | f930d07e | blueswir1 | #define MASK_V9B SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B)
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274 | aa0aa4fa | bellard | |
275 | aa0aa4fa | bellard | /* Bit masks of architectures supporting the insn. */
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276 | aa0aa4fa | bellard | |
277 | f930d07e | blueswir1 | #define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET \
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278 | f930d07e | blueswir1 | | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B) |
279 | 46f42f29 | blueswir1 | /* v6 insns not supported on the sparclet. */
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280 | f930d07e | blueswir1 | #define v6notlet (MASK_V6 | MASK_V7 | MASK_V8 \
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281 | f930d07e | blueswir1 | | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B) |
282 | f930d07e | blueswir1 | #define v7 (MASK_V7 | MASK_V8 | MASK_SPARCLET \
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283 | f930d07e | blueswir1 | | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B) |
284 | aa0aa4fa | bellard | /* Although not all insns are implemented in hardware, sparclite is defined
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285 | aa0aa4fa | bellard | to be a superset of v8. Unimplemented insns trap and are then theoretically
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286 | aa0aa4fa | bellard | implemented in software.
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287 | aa0aa4fa | bellard | It's not clear that the same is true for sparclet, although the docs
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288 | aa0aa4fa | bellard | suggest it is. Rather than complicating things, the sparclet assembler
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289 | aa0aa4fa | bellard | recognizes all v8 insns. */
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290 | f930d07e | blueswir1 | #define v8 (MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE \
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291 | f930d07e | blueswir1 | | MASK_V9 | MASK_V9A | MASK_V9B) |
292 | f930d07e | blueswir1 | #define sparclet (MASK_SPARCLET)
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293 | f930d07e | blueswir1 | #define sparclite (MASK_SPARCLITE)
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294 | f930d07e | blueswir1 | #define v9 (MASK_V9 | MASK_V9A | MASK_V9B)
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295 | f930d07e | blueswir1 | #define v9a (MASK_V9A | MASK_V9B)
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296 | f930d07e | blueswir1 | #define v9b (MASK_V9B)
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297 | 46f42f29 | blueswir1 | /* v6 insns not supported by v9. */
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298 | f930d07e | blueswir1 | #define v6notv9 (MASK_V6 | MASK_V7 | MASK_V8 \
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299 | f930d07e | blueswir1 | | MASK_SPARCLET | MASK_SPARCLITE) |
300 | aa0aa4fa | bellard | /* v9a instructions which would appear to be aliases to v9's impdep's
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301 | 46f42f29 | blueswir1 | otherwise. */
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302 | f930d07e | blueswir1 | #define v9notv9a (MASK_V9)
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303 | aa0aa4fa | bellard | |
304 | aa0aa4fa | bellard | /* Table of opcode architectures.
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305 | aa0aa4fa | bellard | The order is defined in opcode/sparc.h. */
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306 | aa0aa4fa | bellard | |
307 | 46f42f29 | blueswir1 | static const struct sparc_opcode_arch sparc_opcode_archs[] = |
308 | 46f42f29 | blueswir1 | { |
309 | aa0aa4fa | bellard | { "v6", MASK_V6 },
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310 | aa0aa4fa | bellard | { "v7", MASK_V6 | MASK_V7 },
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311 | aa0aa4fa | bellard | { "v8", MASK_V6 | MASK_V7 | MASK_V8 },
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312 | aa0aa4fa | bellard | { "sparclet", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET },
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313 | aa0aa4fa | bellard | { "sparclite", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLITE },
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314 | 7f75ffd3 | blueswir1 | /* ??? Don't some v8 privileged insns conflict with v9? */
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315 | aa0aa4fa | bellard | { "v9", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 },
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316 | aa0aa4fa | bellard | /* v9 with ultrasparc additions */
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317 | aa0aa4fa | bellard | { "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A },
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318 | aa0aa4fa | bellard | /* v9 with cheetah additions */
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319 | aa0aa4fa | bellard | { "v9b", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B },
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320 | aa0aa4fa | bellard | { NULL, 0 } |
321 | aa0aa4fa | bellard | }; |
322 | aa0aa4fa | bellard | |
323 | aa0aa4fa | bellard | /* Branch condition field. */
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324 | 46f42f29 | blueswir1 | #define COND(x) (((x) & 0xf) << 25) |
325 | aa0aa4fa | bellard | |
326 | aa0aa4fa | bellard | /* v9: Move (MOVcc and FMOVcc) condition field. */
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327 | 46f42f29 | blueswir1 | #define MCOND(x,i_or_f) ((((i_or_f) & 1) << 18) | (((x) >> 11) & (0xf << 14))) /* v9 */ |
328 | aa0aa4fa | bellard | |
329 | aa0aa4fa | bellard | /* v9: Move register (MOVRcc and FMOVRcc) condition field. */
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330 | 46f42f29 | blueswir1 | #define RCOND(x) (((x) & 0x7) << 10) /* v9 */ |
331 | 46f42f29 | blueswir1 | |
332 | 46f42f29 | blueswir1 | #define CONDA (COND (0x8)) |
333 | 46f42f29 | blueswir1 | #define CONDCC (COND (0xd)) |
334 | 46f42f29 | blueswir1 | #define CONDCS (COND (0x5)) |
335 | 46f42f29 | blueswir1 | #define CONDE (COND (0x1)) |
336 | 46f42f29 | blueswir1 | #define CONDG (COND (0xa)) |
337 | 46f42f29 | blueswir1 | #define CONDGE (COND (0xb)) |
338 | 46f42f29 | blueswir1 | #define CONDGU (COND (0xc)) |
339 | 46f42f29 | blueswir1 | #define CONDL (COND (0x3)) |
340 | 46f42f29 | blueswir1 | #define CONDLE (COND (0x2)) |
341 | 46f42f29 | blueswir1 | #define CONDLEU (COND (0x4)) |
342 | 46f42f29 | blueswir1 | #define CONDN (COND (0x0)) |
343 | 46f42f29 | blueswir1 | #define CONDNE (COND (0x9)) |
344 | 46f42f29 | blueswir1 | #define CONDNEG (COND (0x6)) |
345 | 46f42f29 | blueswir1 | #define CONDPOS (COND (0xe)) |
346 | 46f42f29 | blueswir1 | #define CONDVC (COND (0xf)) |
347 | 46f42f29 | blueswir1 | #define CONDVS (COND (0x7)) |
348 | f930d07e | blueswir1 | |
349 | f930d07e | blueswir1 | #define CONDNZ CONDNE
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350 | f930d07e | blueswir1 | #define CONDZ CONDE
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351 | f930d07e | blueswir1 | #define CONDGEU CONDCC
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352 | f930d07e | blueswir1 | #define CONDLU CONDCS
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353 | f930d07e | blueswir1 | |
354 | 46f42f29 | blueswir1 | #define FCONDA (COND (0x8)) |
355 | 46f42f29 | blueswir1 | #define FCONDE (COND (0x9)) |
356 | 46f42f29 | blueswir1 | #define FCONDG (COND (0x6)) |
357 | 46f42f29 | blueswir1 | #define FCONDGE (COND (0xb)) |
358 | 46f42f29 | blueswir1 | #define FCONDL (COND (0x4)) |
359 | 46f42f29 | blueswir1 | #define FCONDLE (COND (0xd)) |
360 | 46f42f29 | blueswir1 | #define FCONDLG (COND (0x2)) |
361 | 46f42f29 | blueswir1 | #define FCONDN (COND (0x0)) |
362 | 46f42f29 | blueswir1 | #define FCONDNE (COND (0x1)) |
363 | 46f42f29 | blueswir1 | #define FCONDO (COND (0xf)) |
364 | 46f42f29 | blueswir1 | #define FCONDU (COND (0x7)) |
365 | 46f42f29 | blueswir1 | #define FCONDUE (COND (0xa)) |
366 | 46f42f29 | blueswir1 | #define FCONDUG (COND (0x5)) |
367 | 46f42f29 | blueswir1 | #define FCONDUGE (COND (0xc)) |
368 | 46f42f29 | blueswir1 | #define FCONDUL (COND (0x3)) |
369 | 46f42f29 | blueswir1 | #define FCONDULE (COND (0xe)) |
370 | f930d07e | blueswir1 | |
371 | f930d07e | blueswir1 | #define FCONDNZ FCONDNE
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372 | f930d07e | blueswir1 | #define FCONDZ FCONDE
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373 | f930d07e | blueswir1 | |
374 | 46f42f29 | blueswir1 | #define ICC (0) /* v9 */ |
375 | 46f42f29 | blueswir1 | #define XCC (1 << 12) /* v9 */ |
376 | 46f42f29 | blueswir1 | #define FCC(x) (((x) & 0x3) << 11) /* v9 */ |
377 | 46f42f29 | blueswir1 | #define FBFCC(x) (((x) & 0x3) << 20) /* v9 */ |
378 | aa0aa4fa | bellard | |
379 | aa0aa4fa | bellard | /* The order of the opcodes in the table is significant:
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380 | 5fafdf24 | ths | |
381 | f930d07e | blueswir1 | * The assembler requires that all instances of the same mnemonic must
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382 | f930d07e | blueswir1 | be consecutive. If they aren't, the assembler will bomb at runtime.
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383 | aa0aa4fa | bellard | |
384 | 46f42f29 | blueswir1 | * The disassembler should not care about the order of the opcodes. */
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385 | aa0aa4fa | bellard | |
386 | aa0aa4fa | bellard | /* Entries for commutative arithmetic operations. */
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387 | aa0aa4fa | bellard | /* ??? More entries can make use of this. */
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388 | aa0aa4fa | bellard | #define COMMUTEOP(opcode, op3, arch_mask) \
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389 | f930d07e | blueswir1 | { opcode, F3(2, op3, 0), F3(~2, ~op3, ~0)|ASI(~0), "1,2,d", 0, arch_mask }, \ |
390 | f930d07e | blueswir1 | { opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "1,i,d", 0, arch_mask }, \ |
391 | f930d07e | blueswir1 | { opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "i,1,d", 0, arch_mask } |
392 | aa0aa4fa | bellard | |
393 | f82a3d48 | blueswir1 | static const struct sparc_opcode sparc_opcodes[] = { |
394 | aa0aa4fa | bellard | |
395 | f930d07e | blueswir1 | { "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", 0, v6 }, |
396 | f930d07e | blueswir1 | { "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", 0, v6 }, /* ld [rs1+%g0],d */ |
397 | f930d07e | blueswir1 | { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", 0, v6 }, |
398 | f930d07e | blueswir1 | { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", 0, v6 }, |
399 | f930d07e | blueswir1 | { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", 0, v6 }, |
400 | f930d07e | blueswir1 | { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ld [rs1+0],d */ |
401 | f930d07e | blueswir1 | { "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0), "[1+2],g", 0, v6 }, |
402 | f930d07e | blueswir1 | { "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0, "[1],g", 0, v6 }, /* ld [rs1+%g0],d */ |
403 | f930d07e | blueswir1 | { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[1+i],g", 0, v6 }, |
404 | f930d07e | blueswir1 | { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[i+1],g", 0, v6 }, |
405 | f930d07e | blueswir1 | { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0, "[i],g", 0, v6 }, |
406 | f930d07e | blueswir1 | { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0), "[1],g", 0, v6 }, /* ld [rs1+0],d */ |
407 | f930d07e | blueswir1 | |
408 | f930d07e | blueswir1 | { "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RD(~0), "[1+2],F", 0, v6 }, |
409 | f930d07e | blueswir1 | { "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+%g0],d */ |
410 | f930d07e | blueswir1 | { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[1+i],F", 0, v6 }, |
411 | f930d07e | blueswir1 | { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[i+1],F", 0, v6 }, |
412 | f930d07e | blueswir1 | { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~0),"[i],F", 0, v6 }, |
413 | f930d07e | blueswir1 | { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+0],d */ |
414 | f930d07e | blueswir1 | |
415 | f930d07e | blueswir1 | { "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2],D", 0, v6notv9 }, |
416 | f930d07e | blueswir1 | { "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1],D", 0, v6notv9 }, /* ld [rs1+%g0],d */ |
417 | f930d07e | blueswir1 | { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i],D", 0, v6notv9 }, |
418 | f930d07e | blueswir1 | { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1],D", 0, v6notv9 }, |
419 | f930d07e | blueswir1 | { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i],D", 0, v6notv9 }, |
420 | f930d07e | blueswir1 | { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1],D", 0, v6notv9 }, /* ld [rs1+0],d */ |
421 | f930d07e | blueswir1 | { "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0), "[1+2],C", 0, v6notv9 }, |
422 | f930d07e | blueswir1 | { "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0, "[1],C", 0, v6notv9 }, /* ld [rs1+%g0],d */ |
423 | f930d07e | blueswir1 | { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[1+i],C", 0, v6notv9 }, |
424 | f930d07e | blueswir1 | { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[i+1],C", 0, v6notv9 }, |
425 | f930d07e | blueswir1 | { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0, "[i],C", 0, v6notv9 }, |
426 | f930d07e | blueswir1 | { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0), "[1],C", 0, v6notv9 }, /* ld [rs1+0],d */ |
427 | aa0aa4fa | bellard | |
428 | aa0aa4fa | bellard | /* The v9 LDUW is the same as the old 'ld' opcode, it is not the same as the
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429 | aa0aa4fa | bellard | 'ld' pseudo-op in v9. */
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430 | f930d07e | blueswir1 | { "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", F_ALIAS, v9 }, |
431 | f930d07e | blueswir1 | { "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", F_ALIAS, v9 }, /* ld [rs1+%g0],d */ |
432 | f930d07e | blueswir1 | { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", F_ALIAS, v9 }, |
433 | f930d07e | blueswir1 | { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", F_ALIAS, v9 }, |
434 | f930d07e | blueswir1 | { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", F_ALIAS, v9 }, |
435 | f930d07e | blueswir1 | { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", F_ALIAS, v9 }, /* ld [rs1+0],d */ |
436 | f930d07e | blueswir1 | |
437 | f930d07e | blueswir1 | { "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0), "[1+2],d", 0, v6 }, |
438 | f930d07e | blueswir1 | { "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldd [rs1+%g0],d */ |
439 | f930d07e | blueswir1 | { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[1+i],d", 0, v6 }, |
440 | f930d07e | blueswir1 | { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[i+1],d", 0, v6 }, |
441 | f930d07e | blueswir1 | { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0, "[i],d", 0, v6 }, |
442 | f930d07e | blueswir1 | { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldd [rs1+0],d */ |
443 | f930d07e | blueswir1 | { "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0), "[1+2],H", 0, v6 }, |
444 | f930d07e | blueswir1 | { "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0), "[1],H", 0, v6 }, /* ldd [rs1+%g0],d */ |
445 | f930d07e | blueswir1 | { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[1+i],H", 0, v6 }, |
446 | f930d07e | blueswir1 | { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[i+1],H", 0, v6 }, |
447 | f930d07e | blueswir1 | { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0, "[i],H", 0, v6 }, |
448 | f930d07e | blueswir1 | { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0), "[1],H", 0, v6 }, /* ldd [rs1+0],d */ |
449 | f930d07e | blueswir1 | |
450 | f930d07e | blueswir1 | { "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0), "[1+2],D", 0, v6notv9 }, |
451 | f930d07e | blueswir1 | { "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI_RS2(~0), "[1],D", 0, v6notv9 }, /* ldd [rs1+%g0],d */ |
452 | f930d07e | blueswir1 | { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i],D", 0, v6notv9 }, |
453 | f930d07e | blueswir1 | { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1],D", 0, v6notv9 }, |
454 | f930d07e | blueswir1 | { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i],D", 0, v6notv9 }, |
455 | f930d07e | blueswir1 | { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1],D", 0, v6notv9 }, /* ldd [rs1+0],d */ |
456 | f930d07e | blueswir1 | |
457 | f930d07e | blueswir1 | { "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI(~0), "[1+2],J", 0, v9 }, |
458 | f930d07e | blueswir1 | { "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI_RS2(~0), "[1],J", 0, v9 }, /* ldd [rs1+%g0],d */ |
459 | f930d07e | blueswir1 | { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[1+i],J", 0, v9 }, |
460 | f930d07e | blueswir1 | { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[i+1],J", 0, v9 }, |
461 | f930d07e | blueswir1 | { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|RS1_G0, "[i],J", 0, v9 }, |
462 | f930d07e | blueswir1 | { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|SIMM13(~0), "[1],J", 0, v9 }, /* ldd [rs1+0],d */ |
463 | f930d07e | blueswir1 | |
464 | f930d07e | blueswir1 | { "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI(~0), "[1+2],d", 0, v6 }, |
465 | f930d07e | blueswir1 | { "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldsb [rs1+%g0],d */ |
466 | f930d07e | blueswir1 | { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[1+i],d", 0, v6 }, |
467 | f930d07e | blueswir1 | { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[i+1],d", 0, v6 }, |
468 | f930d07e | blueswir1 | { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|RS1_G0, "[i],d", 0, v6 }, |
469 | f930d07e | blueswir1 | { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldsb [rs1+0],d */ |
470 | f930d07e | blueswir1 | |
471 | f930d07e | blueswir1 | { "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldsh [rs1+%g0],d */ |
472 | f930d07e | blueswir1 | { "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI(~0), "[1+2],d", 0, v6 }, |
473 | f930d07e | blueswir1 | { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[1+i],d", 0, v6 }, |
474 | f930d07e | blueswir1 | { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[i+1],d", 0, v6 }, |
475 | f930d07e | blueswir1 | { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|RS1_G0, "[i],d", 0, v6 }, |
476 | f930d07e | blueswir1 | { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldsh [rs1+0],d */ |
477 | f930d07e | blueswir1 | |
478 | f930d07e | blueswir1 | { "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI(~0), "[1+2],d", 0, v6 }, |
479 | f930d07e | blueswir1 | { "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldstub [rs1+%g0],d */ |
480 | f930d07e | blueswir1 | { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[1+i],d", 0, v6 }, |
481 | f930d07e | blueswir1 | { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[i+1],d", 0, v6 }, |
482 | f930d07e | blueswir1 | { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|RS1_G0, "[i],d", 0, v6 }, |
483 | f930d07e | blueswir1 | { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldstub [rs1+0],d */ |
484 | f930d07e | blueswir1 | |
485 | f930d07e | blueswir1 | { "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI(~0), "[1+2],d", 0, v9 }, |
486 | f930d07e | blueswir1 | { "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI_RS2(~0), "[1],d", 0, v9 }, /* ldsw [rs1+%g0],d */ |
487 | f930d07e | blueswir1 | { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[1+i],d", 0, v9 }, |
488 | f930d07e | blueswir1 | { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[i+1],d", 0, v9 }, |
489 | f930d07e | blueswir1 | { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|RS1_G0, "[i],d", 0, v9 }, |
490 | f930d07e | blueswir1 | { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|SIMM13(~0), "[1],d", 0, v9 }, /* ldsw [rs1+0],d */ |
491 | f930d07e | blueswir1 | |
492 | f930d07e | blueswir1 | { "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI(~0), "[1+2],d", 0, v6 }, |
493 | f930d07e | blueswir1 | { "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldub [rs1+%g0],d */ |
494 | f930d07e | blueswir1 | { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[1+i],d", 0, v6 }, |
495 | f930d07e | blueswir1 | { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[i+1],d", 0, v6 }, |
496 | f930d07e | blueswir1 | { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|RS1_G0, "[i],d", 0, v6 }, |
497 | f930d07e | blueswir1 | { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldub [rs1+0],d */ |
498 | f930d07e | blueswir1 | |
499 | f930d07e | blueswir1 | { "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI(~0), "[1+2],d", 0, v6 }, |
500 | f930d07e | blueswir1 | { "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* lduh [rs1+%g0],d */ |
501 | f930d07e | blueswir1 | { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[1+i],d", 0, v6 }, |
502 | f930d07e | blueswir1 | { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[i+1],d", 0, v6 }, |
503 | f930d07e | blueswir1 | { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|RS1_G0, "[i],d", 0, v6 }, |
504 | f930d07e | blueswir1 | { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* lduh [rs1+0],d */ |
505 | f930d07e | blueswir1 | |
506 | f930d07e | blueswir1 | { "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI(~0), "[1+2],d", 0, v9 }, |
507 | f930d07e | blueswir1 | { "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI_RS2(~0), "[1],d", 0, v9 }, /* ldx [rs1+%g0],d */ |
508 | f930d07e | blueswir1 | { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[1+i],d", 0, v9 }, |
509 | f930d07e | blueswir1 | { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[i+1],d", 0, v9 }, |
510 | f930d07e | blueswir1 | { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|RS1_G0, "[i],d", 0, v9 }, |
511 | f930d07e | blueswir1 | { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|SIMM13(~0), "[1],d", 0, v9 }, /* ldx [rs1+0],d */ |
512 | f930d07e | blueswir1 | |
513 | f930d07e | blueswir1 | { "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RD(~1), "[1+2],F", 0, v9 }, |
514 | f930d07e | blueswir1 | { "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RS2_G0|RD(~1), "[1],F", 0, v9 }, /* ld [rs1+%g0],d */ |
515 | f930d07e | blueswir1 | { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[1+i],F", 0, v9 }, |
516 | f930d07e | blueswir1 | { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[i+1],F", 0, v9 }, |
517 | f930d07e | blueswir1 | { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~1), "[i],F", 0, v9 }, |
518 | f930d07e | blueswir1 | { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~1),"[1],F", 0, v9 }, /* ld [rs1+0],d */ |
519 | f930d07e | blueswir1 | |
520 | f930d07e | blueswir1 | { "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", 0, v6 }, |
521 | f930d07e | blueswir1 | { "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lda [rs1+%g0],d */ |
522 | f930d07e | blueswir1 | { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", 0, v9 }, |
523 | f930d07e | blueswir1 | { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", 0, v9 }, |
524 | f930d07e | blueswir1 | { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", 0, v9 }, |
525 | f930d07e | blueswir1 | { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ |
526 | f930d07e | blueswir1 | { "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2]A,g", 0, v9 }, |
527 | f930d07e | blueswir1 | { "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1]A,g", 0, v9 }, /* lda [rs1+%g0],d */ |
528 | f930d07e | blueswir1 | { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i]o,g", 0, v9 }, |
529 | f930d07e | blueswir1 | { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1]o,g", 0, v9 }, |
530 | f930d07e | blueswir1 | { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i]o,g", 0, v9 }, |
531 | f930d07e | blueswir1 | { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1]o,g", 0, v9 }, /* ld [rs1+0],d */ |
532 | f930d07e | blueswir1 | |
533 | f930d07e | blueswir1 | { "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0), "[1+2]A,d", 0, v6 }, |
534 | f930d07e | blueswir1 | { "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldda [rs1+%g0],d */ |
535 | f930d07e | blueswir1 | { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[1+i]o,d", 0, v9 }, |
536 | f930d07e | blueswir1 | { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[i+1]o,d", 0, v9 }, |
537 | f930d07e | blueswir1 | { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0, "[i]o,d", 0, v9 }, |
538 | f930d07e | blueswir1 | { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ |
539 | f930d07e | blueswir1 | |
540 | f930d07e | blueswir1 | { "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0), "[1+2]A,H", 0, v9 }, |
541 | f930d07e | blueswir1 | { "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|RS2_G0, "[1]A,H", 0, v9 }, /* ldda [rs1+%g0],d */ |
542 | f930d07e | blueswir1 | { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i]o,H", 0, v9 }, |
543 | f930d07e | blueswir1 | { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1]o,H", 0, v9 }, |
544 | f930d07e | blueswir1 | { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i]o,H", 0, v9 }, |
545 | f930d07e | blueswir1 | { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1]o,H", 0, v9 }, /* ld [rs1+0],d */ |
546 | f930d07e | blueswir1 | |
547 | f930d07e | blueswir1 | { "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0), "[1+2]A,J", 0, v9 }, |
548 | f930d07e | blueswir1 | { "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0)|RS2_G0, "[1]A,J", 0, v9 }, /* ldd [rs1+%g0],d */ |
549 | f930d07e | blueswir1 | { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[1+i]o,J", 0, v9 }, |
550 | f930d07e | blueswir1 | { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[i+1]o,J", 0, v9 }, |
551 | f930d07e | blueswir1 | { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|RS1_G0, "[i]o,J", 0, v9 }, |
552 | f930d07e | blueswir1 | { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|SIMM13(~0), "[1]o,J", 0, v9 }, /* ldd [rs1+0],d */ |
553 | f930d07e | blueswir1 | |
554 | f930d07e | blueswir1 | { "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0), "[1+2]A,d", 0, v6 }, |
555 | f930d07e | blueswir1 | { "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldsba [rs1+%g0],d */ |
556 | f930d07e | blueswir1 | { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[1+i]o,d", 0, v9 }, |
557 | f930d07e | blueswir1 | { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[i+1]o,d", 0, v9 }, |
558 | f930d07e | blueswir1 | { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|RS1_G0, "[i]o,d", 0, v9 }, |
559 | f930d07e | blueswir1 | { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ |
560 | f930d07e | blueswir1 | |
561 | f930d07e | blueswir1 | { "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0), "[1+2]A,d", 0, v6 }, |
562 | f930d07e | blueswir1 | { "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldsha [rs1+%g0],d */ |
563 | f930d07e | blueswir1 | { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[1+i]o,d", 0, v9 }, |
564 | f930d07e | blueswir1 | { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[i+1]o,d", 0, v9 }, |
565 | f930d07e | blueswir1 | { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|RS1_G0, "[i]o,d", 0, v9 }, |
566 | f930d07e | blueswir1 | { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ |
567 | f930d07e | blueswir1 | |
568 | f930d07e | blueswir1 | { "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0), "[1+2]A,d", 0, v6 }, |
569 | f930d07e | blueswir1 | { "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldstuba [rs1+%g0],d */ |
570 | f930d07e | blueswir1 | { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[1+i]o,d", 0, v9 }, |
571 | f930d07e | blueswir1 | { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[i+1]o,d", 0, v9 }, |
572 | f930d07e | blueswir1 | { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|RS1_G0, "[i]o,d", 0, v9 }, |
573 | f930d07e | blueswir1 | { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ |
574 | f930d07e | blueswir1 | |
575 | f930d07e | blueswir1 | { "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0), "[1+2]A,d", 0, v9 }, |
576 | f930d07e | blueswir1 | { "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0)|RS2_G0, "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */ |
577 | f930d07e | blueswir1 | { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[1+i]o,d", 0, v9 }, |
578 | f930d07e | blueswir1 | { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[i+1]o,d", 0, v9 }, |
579 | f930d07e | blueswir1 | { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|RS1_G0, "[i]o,d", 0, v9 }, |
580 | f930d07e | blueswir1 | { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ |
581 | f930d07e | blueswir1 | |
582 | f930d07e | blueswir1 | { "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0), "[1+2]A,d", 0, v6 }, |
583 | f930d07e | blueswir1 | { "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lduba [rs1+%g0],d */ |
584 | f930d07e | blueswir1 | { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[1+i]o,d", 0, v9 }, |
585 | f930d07e | blueswir1 | { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[i+1]o,d", 0, v9 }, |
586 | f930d07e | blueswir1 | { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|RS1_G0, "[i]o,d", 0, v9 }, |
587 | f930d07e | blueswir1 | { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ |
588 | f930d07e | blueswir1 | |
589 | f930d07e | blueswir1 | { "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0), "[1+2]A,d", 0, v6 }, |
590 | f930d07e | blueswir1 | { "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lduha [rs1+%g0],d */ |
591 | f930d07e | blueswir1 | { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[1+i]o,d", 0, v9 }, |
592 | f930d07e | blueswir1 | { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[i+1]o,d", 0, v9 }, |
593 | f930d07e | blueswir1 | { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|RS1_G0, "[i]o,d", 0, v9 }, |
594 | f930d07e | blueswir1 | { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ |
595 | f930d07e | blueswir1 | |
596 | f930d07e | blueswir1 | { "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", F_ALIAS, v9 }, /* lduwa === lda */ |
597 | f930d07e | blueswir1 | { "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", F_ALIAS, v9 }, /* lda [rs1+%g0],d */ |
598 | f930d07e | blueswir1 | { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", F_ALIAS, v9 }, |
599 | f930d07e | blueswir1 | { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", F_ALIAS, v9 }, |
600 | f930d07e | blueswir1 | { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", F_ALIAS, v9 }, |
601 | f930d07e | blueswir1 | { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", F_ALIAS, v9 }, /* ld [rs1+0],d */ |
602 | f930d07e | blueswir1 | |
603 | f930d07e | blueswir1 | { "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0), "[1+2]A,d", 0, v9 }, |
604 | f930d07e | blueswir1 | { "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0)|RS2_G0, "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */ |
605 | f930d07e | blueswir1 | { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[1+i]o,d", 0, v9 }, |
606 | f930d07e | blueswir1 | { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[i+1]o,d", 0, v9 }, |
607 | f930d07e | blueswir1 | { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|RS1_G0, "[i]o,d", 0, v9 }, |
608 | f930d07e | blueswir1 | { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ |
609 | f930d07e | blueswir1 | |
610 | f930d07e | blueswir1 | { "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, |
611 | f930d07e | blueswir1 | { "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* st d,[rs1+%g0] */ |
612 | f930d07e | blueswir1 | { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", 0, v6 }, |
613 | f930d07e | blueswir1 | { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", 0, v6 }, |
614 | f930d07e | blueswir1 | { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", 0, v6 }, |
615 | f930d07e | blueswir1 | { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* st d,[rs1+0] */ |
616 | f930d07e | blueswir1 | { "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0), "g,[1+2]", 0, v6 }, |
617 | f930d07e | blueswir1 | { "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0), "g,[1]", 0, v6 }, /* st d[rs1+%g0] */ |
618 | f930d07e | blueswir1 | { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[1+i]", 0, v6 }, |
619 | f930d07e | blueswir1 | { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[i+1]", 0, v6 }, |
620 | f930d07e | blueswir1 | { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0, "g,[i]", 0, v6 }, |
621 | f930d07e | blueswir1 | { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0), "g,[1]", 0, v6 }, /* st d,[rs1+0] */ |
622 | f930d07e | blueswir1 | |
623 | f930d07e | blueswir1 | { "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0), "D,[1+2]", 0, v6notv9 }, |
624 | f930d07e | blueswir1 | { "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0), "D,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */ |
625 | f930d07e | blueswir1 | { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[1+i]", 0, v6notv9 }, |
626 | f930d07e | blueswir1 | { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[i+1]", 0, v6notv9 }, |
627 | f930d07e | blueswir1 | { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "D,[i]", 0, v6notv9 }, |
628 | f930d07e | blueswir1 | { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "D,[1]", 0, v6notv9 }, /* st d,[rs1+0] */ |
629 | f930d07e | blueswir1 | { "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0), "C,[1+2]", 0, v6notv9 }, |
630 | f930d07e | blueswir1 | { "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0), "C,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */ |
631 | f930d07e | blueswir1 | { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[1+i]", 0, v6notv9 }, |
632 | f930d07e | blueswir1 | { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[i+1]", 0, v6notv9 }, |
633 | f930d07e | blueswir1 | { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0, "C,[i]", 0, v6notv9 }, |
634 | f930d07e | blueswir1 | { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0), "C,[1]", 0, v6notv9 }, /* st d,[rs1+0] */ |
635 | f930d07e | blueswir1 | |
636 | f930d07e | blueswir1 | { "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI(~0), "F,[1+2]", 0, v6 }, |
637 | f930d07e | blueswir1 | { "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI_RS2(~0), "F,[1]", 0, v6 }, /* st d,[rs1+%g0] */ |
638 | f930d07e | blueswir1 | { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[1+i]", 0, v6 }, |
639 | f930d07e | blueswir1 | { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[i+1]", 0, v6 }, |
640 | f930d07e | blueswir1 | { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|RS1_G0, "F,[i]", 0, v6 }, |
641 | f930d07e | blueswir1 | { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|SIMM13(~0), "F,[1]", 0, v6 }, /* st d,[rs1+0] */ |
642 | f930d07e | blueswir1 | |
643 | f930d07e | blueswir1 | { "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 }, |
644 | f930d07e | blueswir1 | { "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ |
645 | f930d07e | blueswir1 | { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 }, |
646 | f930d07e | blueswir1 | { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 }, |
647 | f930d07e | blueswir1 | { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 }, |
648 | f930d07e | blueswir1 | { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ |
649 | f930d07e | blueswir1 | { "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 }, |
650 | f930d07e | blueswir1 | { "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ |
651 | f930d07e | blueswir1 | { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 }, |
652 | f930d07e | blueswir1 | { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 }, |
653 | f930d07e | blueswir1 | { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 }, |
654 | f930d07e | blueswir1 | { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ |
655 | f930d07e | blueswir1 | { "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 }, |
656 | f930d07e | blueswir1 | { "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ |
657 | f930d07e | blueswir1 | { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 }, |
658 | f930d07e | blueswir1 | { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 }, |
659 | f930d07e | blueswir1 | { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 }, |
660 | f930d07e | blueswir1 | { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ |
661 | f930d07e | blueswir1 | |
662 | f930d07e | blueswir1 | { "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, |
663 | f930d07e | blueswir1 | { "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* st d,[rs1+%g0] */ |
664 | f930d07e | blueswir1 | { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v6 }, |
665 | f930d07e | blueswir1 | { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v6 }, |
666 | f930d07e | blueswir1 | { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, |
667 | f930d07e | blueswir1 | { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* st d,[rs1+0] */ |
668 | f930d07e | blueswir1 | |
669 | f930d07e | blueswir1 | { "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", 0, v6 }, |
670 | f930d07e | blueswir1 | { "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* sta d,[rs1+%g0] */ |
671 | f930d07e | blueswir1 | { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", 0, v9 }, |
672 | f930d07e | blueswir1 | { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", 0, v9 }, |
673 | f930d07e | blueswir1 | { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", 0, v9 }, |
674 | f930d07e | blueswir1 | { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* st d,[rs1+0] */ |
675 | f930d07e | blueswir1 | |
676 | f930d07e | blueswir1 | { "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0), "g,[1+2]A", 0, v9 }, |
677 | f930d07e | blueswir1 | { "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|RS2(~0), "g,[1]A", 0, v9 }, /* sta d,[rs1+%g0] */ |
678 | f930d07e | blueswir1 | { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[1+i]o", 0, v9 }, |
679 | f930d07e | blueswir1 | { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[i+1]o", 0, v9 }, |
680 | f930d07e | blueswir1 | { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "g,[i]o", 0, v9 }, |
681 | f930d07e | blueswir1 | { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "g,[1]o", 0, v9 }, /* st d,[rs1+0] */ |
682 | f930d07e | blueswir1 | |
683 | f930d07e | blueswir1 | { "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 }, |
684 | f930d07e | blueswir1 | { "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */ |
685 | f930d07e | blueswir1 | { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 }, |
686 | f930d07e | blueswir1 | { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 }, |
687 | f930d07e | blueswir1 | { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, |
688 | f930d07e | blueswir1 | { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */ |
689 | f930d07e | blueswir1 | { "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 }, |
690 | f930d07e | blueswir1 | { "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */ |
691 | f930d07e | blueswir1 | { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 }, |
692 | f930d07e | blueswir1 | { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 }, |
693 | f930d07e | blueswir1 | { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, |
694 | f930d07e | blueswir1 | { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */ |
695 | f930d07e | blueswir1 | { "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 }, |
696 | f930d07e | blueswir1 | { "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */ |
697 | f930d07e | blueswir1 | { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 }, |
698 | f930d07e | blueswir1 | { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 }, |
699 | f930d07e | blueswir1 | { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, |
700 | f930d07e | blueswir1 | { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */ |
701 | f930d07e | blueswir1 | |
702 | f930d07e | blueswir1 | { "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, |
703 | f930d07e | blueswir1 | { "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* stb d,[rs1+%g0] */ |
704 | f930d07e | blueswir1 | { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", 0, v6 }, |
705 | f930d07e | blueswir1 | { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", 0, v6 }, |
706 | f930d07e | blueswir1 | { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", 0, v6 }, |
707 | f930d07e | blueswir1 | { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* stb d,[rs1+0] */ |
708 | f930d07e | blueswir1 | |
709 | f930d07e | blueswir1 | { "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, |
710 | f930d07e | blueswir1 | { "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+%g0] */ |
711 | f930d07e | blueswir1 | { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, v6 }, |
712 | f930d07e | blueswir1 | { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, v6 }, |
713 | f930d07e | blueswir1 | { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, |
714 | f930d07e | blueswir1 | { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+0] */ |
715 | f930d07e | blueswir1 | { "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, |
716 | f930d07e | blueswir1 | { "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+%g0] */ |
717 | f930d07e | blueswir1 | { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, v6 }, |
718 | f930d07e | blueswir1 | { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, v6 }, |
719 | f930d07e | blueswir1 | { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, |
720 | f930d07e | blueswir1 | { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+0] */ |
721 | f930d07e | blueswir1 | |
722 | f930d07e | blueswir1 | { "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", 0, v6 }, |
723 | f930d07e | blueswir1 | { "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stba d,[rs1+%g0] */ |
724 | f930d07e | blueswir1 | { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", 0, v9 }, |
725 | f930d07e | blueswir1 | { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", 0, v9 }, |
726 | f930d07e | blueswir1 | { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", 0, v9 }, |
727 | f930d07e | blueswir1 | { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* stb d,[rs1+0] */ |
728 | f930d07e | blueswir1 | |
729 | f930d07e | blueswir1 | { "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, v6 }, |
730 | f930d07e | blueswir1 | { "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stba d,[rs1+%g0] */ |
731 | f930d07e | blueswir1 | { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, v9 }, |
732 | f930d07e | blueswir1 | { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, v9 }, |
733 | f930d07e | blueswir1 | { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, |
734 | f930d07e | blueswir1 | { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* stb d,[rs1+0] */ |
735 | f930d07e | blueswir1 | { "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, v6 }, |
736 | f930d07e | blueswir1 | { "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stba d,[rs1+%g0] */ |
737 | f930d07e | blueswir1 | { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, v9 }, |
738 | f930d07e | blueswir1 | { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, v9 }, |
739 | f930d07e | blueswir1 | { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, |
740 | f930d07e | blueswir1 | { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* stb d,[rs1+0] */ |
741 | f930d07e | blueswir1 | |
742 | f930d07e | blueswir1 | { "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, |
743 | f930d07e | blueswir1 | { "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* std d,[rs1+%g0] */ |
744 | f930d07e | blueswir1 | { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", 0, v6 }, |
745 | f930d07e | blueswir1 | { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", 0, v6 }, |
746 | f930d07e | blueswir1 | { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", 0, v6 }, |
747 | f930d07e | blueswir1 | { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* std d,[rs1+0] */ |
748 | f930d07e | blueswir1 | |
749 | f930d07e | blueswir1 | { "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "q,[1+2]", 0, v6notv9 }, |
750 | f930d07e | blueswir1 | { "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "q,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */ |
751 | f930d07e | blueswir1 | { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[1+i]", 0, v6notv9 }, |
752 | f930d07e | blueswir1 | { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[i+1]", 0, v6notv9 }, |
753 | f930d07e | blueswir1 | { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "q,[i]", 0, v6notv9 }, |
754 | f930d07e | blueswir1 | { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "q,[1]", 0, v6notv9 }, /* std d,[rs1+0] */ |
755 | f930d07e | blueswir1 | { "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI(~0), "H,[1+2]", 0, v6 }, |
756 | f930d07e | blueswir1 | { "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI_RS2(~0), "H,[1]", 0, v6 }, /* std d,[rs1+%g0] */ |
757 | f930d07e | blueswir1 | { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[1+i]", 0, v6 }, |
758 | f930d07e | blueswir1 | { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[i+1]", 0, v6 }, |
759 | f930d07e | blueswir1 | { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|RS1_G0, "H,[i]", 0, v6 }, |
760 | f930d07e | blueswir1 | { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|SIMM13(~0), "H,[1]", 0, v6 }, /* std d,[rs1+0] */ |
761 | f930d07e | blueswir1 | |
762 | f930d07e | blueswir1 | { "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "Q,[1+2]", 0, v6notv9 }, |
763 | f930d07e | blueswir1 | { "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "Q,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */ |
764 | f930d07e | blueswir1 | { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[1+i]", 0, v6notv9 }, |
765 | f930d07e | blueswir1 | { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[i+1]", 0, v6notv9 }, |
766 | f930d07e | blueswir1 | { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "Q,[i]", 0, v6notv9 }, |
767 | f930d07e | blueswir1 | { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "Q,[1]", 0, v6notv9 }, /* std d,[rs1+0] */ |
768 | f930d07e | blueswir1 | { "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI(~0), "D,[1+2]", 0, v6notv9 }, |
769 | f930d07e | blueswir1 | { "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI_RS2(~0), "D,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */ |
770 | f930d07e | blueswir1 | { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[1+i]", 0, v6notv9 }, |
771 | f930d07e | blueswir1 | { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[i+1]", 0, v6notv9 }, |
772 | f930d07e | blueswir1 | { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "D,[i]", 0, v6notv9 }, |
773 | f930d07e | blueswir1 | { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "D,[1]", 0, v6notv9 }, /* std d,[rs1+0] */ |
774 | f930d07e | blueswir1 | |
775 | f930d07e | blueswir1 | { "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, |
776 | f930d07e | blueswir1 | { "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* std d,[rs1+%g0] */ |
777 | f930d07e | blueswir1 | { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", F_ALIAS, v6 }, |
778 | f930d07e | blueswir1 | { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", F_ALIAS, v6 }, |
779 | f930d07e | blueswir1 | { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, |
780 | f930d07e | blueswir1 | { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* std d,[rs1+0] */ |
781 | f930d07e | blueswir1 | |
782 | f930d07e | blueswir1 | { "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0), "d,[1+2]A", 0, v6 }, |
783 | f930d07e | blueswir1 | { "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stda d,[rs1+%g0] */ |
784 | f930d07e | blueswir1 | { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[1+i]o", 0, v9 }, |
785 | f930d07e | blueswir1 | { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[i+1]o", 0, v9 }, |
786 | f930d07e | blueswir1 | { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0, "d,[i]o", 0, v9 }, |
787 | f930d07e | blueswir1 | { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* std d,[rs1+0] */ |
788 | f930d07e | blueswir1 | { "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0), "H,[1+2]A", 0, v9 }, |
789 | f930d07e | blueswir1 | { "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|RS2(~0), "H,[1]A", 0, v9 }, /* stda d,[rs1+%g0] */ |
790 | f930d07e | blueswir1 | { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[1+i]o", 0, v9 }, |
791 | f930d07e | blueswir1 | { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[i+1]o", 0, v9 }, |
792 | f930d07e | blueswir1 | { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "H,[i]o", 0, v9 }, |
793 | f930d07e | blueswir1 | { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "H,[1]o", 0, v9 }, /* std d,[rs1+0] */ |
794 | f930d07e | blueswir1 | |
795 | f930d07e | blueswir1 | { "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, |
796 | f930d07e | blueswir1 | { "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* sth d,[rs1+%g0] */ |
797 | f930d07e | blueswir1 | { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", 0, v6 }, |
798 | f930d07e | blueswir1 | { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", 0, v6 }, |
799 | f930d07e | blueswir1 | { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", 0, v6 }, |
800 | f930d07e | blueswir1 | { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* sth d,[rs1+0] */ |
801 | f930d07e | blueswir1 | |
802 | f930d07e | blueswir1 | { "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, |
803 | f930d07e | blueswir1 | { "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+%g0] */ |
804 | f930d07e | blueswir1 | { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, v6 }, |
805 | f930d07e | blueswir1 | { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, v6 }, |
806 | f930d07e | blueswir1 | { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, |
807 | f930d07e | blueswir1 | { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+0] */ |
808 | f930d07e | blueswir1 | { "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, |
809 | f930d07e | blueswir1 | { "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+%g0] */ |
810 | f930d07e | blueswir1 | { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, v6 }, |
811 | f930d07e | blueswir1 | { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, v6 }, |
812 | f930d07e | blueswir1 | { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, |
813 | f930d07e | blueswir1 | { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+0] */ |
814 | f930d07e | blueswir1 | |
815 | f930d07e | blueswir1 | { "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", 0, v6 }, |
816 | f930d07e | blueswir1 | { "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stha ,[rs1+%g0] */ |
817 | f930d07e | blueswir1 | { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", 0, v9 }, |
818 | f930d07e | blueswir1 | { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", 0, v9 }, |
819 | f930d07e | blueswir1 | { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", 0, v9 }, |
820 | f930d07e | blueswir1 | { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* sth d,[rs1+0] */ |
821 | f930d07e | blueswir1 | |
822 | f930d07e | blueswir1 | { "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, v6 }, |
823 | f930d07e | blueswir1 | { "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stha ,[rs1+%g0] */ |
824 | f930d07e | blueswir1 | { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, v9 }, |
825 | f930d07e | blueswir1 | { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, v9 }, |
826 | f930d07e | blueswir1 | { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, |
827 | f930d07e | blueswir1 | { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* sth d,[rs1+0] */ |
828 | f930d07e | blueswir1 | { "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, v6 }, |
829 | f930d07e | blueswir1 | { "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stha ,[rs1+%g0] */ |
830 | f930d07e | blueswir1 | { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, v9 }, |
831 | f930d07e | blueswir1 | { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, v9 }, |
832 | f930d07e | blueswir1 | { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, |
833 | f930d07e | blueswir1 | { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* sth d,[rs1+0] */ |
834 | f930d07e | blueswir1 | |
835 | f930d07e | blueswir1 | { "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI(~0), "d,[1+2]", 0, v9 }, |
836 | f930d07e | blueswir1 | { "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI_RS2(~0), "d,[1]", 0, v9 }, /* stx d,[rs1+%g0] */ |
837 | f930d07e | blueswir1 | { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[1+i]", 0, v9 }, |
838 | f930d07e | blueswir1 | { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[i+1]", 0, v9 }, |
839 | f930d07e | blueswir1 | { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RS1_G0, "d,[i]", 0, v9 }, |
840 | f930d07e | blueswir1 | { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|SIMM13(~0), "d,[1]", 0, v9 }, /* stx d,[rs1+0] */ |
841 | f930d07e | blueswir1 | |
842 | f930d07e | blueswir1 | { "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI(~0)|RD(~1), "F,[1+2]", 0, v9 }, |
843 | f930d07e | blueswir1 | { "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI_RS2(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+%g0] */ |
844 | f930d07e | blueswir1 | { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[1+i]", 0, v9 }, |
845 | f930d07e | blueswir1 | { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[i+1]", 0, v9 }, |
846 | f930d07e | blueswir1 | { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RS1_G0|RD(~1), "F,[i]", 0, v9 }, |
847 | f930d07e | blueswir1 | { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|SIMM13(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+0] */ |
848 | f930d07e | blueswir1 | |
849 | f930d07e | blueswir1 | { "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0), "d,[1+2]A", 0, v9 }, |
850 | f930d07e | blueswir1 | { "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0)|RS2(~0), "d,[1]A", 0, v9 }, /* stxa d,[rs1+%g0] */ |
851 | f930d07e | blueswir1 | { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[1+i]o", 0, v9 }, |
852 | f930d07e | blueswir1 | { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[i+1]o", 0, v9 }, |
853 | f930d07e | blueswir1 | { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|RS1_G0, "d,[i]o", 0, v9 }, |
854 | f930d07e | blueswir1 | { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* stx d,[rs1+0] */ |
855 | f930d07e | blueswir1 | |
856 | f930d07e | blueswir1 | { "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "J,[1+2]", 0, v9 }, |
857 | f930d07e | blueswir1 | { "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "J,[1]", 0, v9 }, /* stq [rs1+%g0] */ |
858 | f930d07e | blueswir1 | { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[1+i]", 0, v9 }, |
859 | f930d07e | blueswir1 | { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[i+1]", 0, v9 }, |
860 | f930d07e | blueswir1 | { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "J,[i]", 0, v9 }, |
861 | f930d07e | blueswir1 | { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "J,[1]", 0, v9 }, /* stq [rs1+0] */ |
862 | f930d07e | blueswir1 | |
863 | f930d07e | blueswir1 | { "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "J,[1+2]A", 0, v9 }, |
864 | f930d07e | blueswir1 | { "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "J,[1]A", 0, v9 }, /* stqa [rs1+%g0] */ |
865 | f930d07e | blueswir1 | { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[1+i]o", 0, v9 }, |
866 | f930d07e | blueswir1 | { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[i+1]o", 0, v9 }, |
867 | f930d07e | blueswir1 | { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "J,[i]o", 0, v9 }, |
868 | f930d07e | blueswir1 | { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "J,[1]o", 0, v9 }, /* stqa [rs1+0] */ |
869 | f930d07e | blueswir1 | |
870 | f930d07e | blueswir1 | { "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0), "[1+2],d", 0, v7 }, |
871 | f930d07e | blueswir1 | { "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI_RS2(~0), "[1],d", 0, v7 }, /* swap [rs1+%g0],d */ |
872 | f930d07e | blueswir1 | { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[1+i],d", 0, v7 }, |
873 | f930d07e | blueswir1 | { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[i+1],d", 0, v7 }, |
874 | f930d07e | blueswir1 | { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|RS1_G0, "[i],d", 0, v7 }, |
875 | f930d07e | blueswir1 | { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|SIMM13(~0), "[1],d", 0, v7 }, /* swap [rs1+0],d */ |
876 | f930d07e | blueswir1 | |
877 | f930d07e | blueswir1 | { "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0), "[1+2]A,d", 0, v7 }, |
878 | f930d07e | blueswir1 | { "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0)|RS2(~0), "[1]A,d", 0, v7 }, /* swapa [rs1+%g0],d */ |
879 | f930d07e | blueswir1 | { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[1+i]o,d", 0, v9 }, |
880 | f930d07e | blueswir1 | { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[i+1]o,d", 0, v9 }, |
881 | f930d07e | blueswir1 | { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|RS1_G0, "[i]o,d", 0, v9 }, |
882 | f930d07e | blueswir1 | { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* swap [rs1+0],d */ |
883 | f930d07e | blueswir1 | |
884 | f930d07e | blueswir1 | { "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
885 | f930d07e | blueswir1 | { "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, v6 }, /* restore %g0,%g0,%g0 */ |
886 | f930d07e | blueswir1 | { "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1), "1,i,d", 0, v6 }, |
887 | f930d07e | blueswir1 | { "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1)|RD_G0|RS1_G0|SIMM13(~0), "", 0, v6 }, /* restore %g0,0,%g0 */ |
888 | f930d07e | blueswir1 | |
889 | f930d07e | blueswir1 | { "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, v6 }, /* rett rs1+rs2 */ |
890 | f930d07e | blueswir1 | { "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, v6 }, /* rett rs1,%g0 */ |
891 | f930d07e | blueswir1 | { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, v6 }, /* rett rs1+X */ |
892 | f930d07e | blueswir1 | { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */ |
893 | f930d07e | blueswir1 | { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */ |
894 | f930d07e | blueswir1 | { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* rett X */ |
895 | f930d07e | blueswir1 | { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, v6 }, /* rett rs1+0 */ |
896 | f930d07e | blueswir1 | |
897 | f930d07e | blueswir1 | { "save", F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
898 | f930d07e | blueswir1 | { "save", F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1), "1,i,d", 0, v6 }, |
899 | f930d07e | blueswir1 | { "save", 0x81e00000, ~0x81e00000, "", F_ALIAS, v6 }, |
900 | f930d07e | blueswir1 | |
901 | f930d07e | blueswir1 | { "ret", F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %i7+8,%g0 */ |
902 | aa0aa4fa | bellard | { "retl", F3(2, 0x38, 1)|RS1(0x0f)|SIMM13(8), F3(~2, ~0x38, ~1)|RS1(~0x0f)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %o7+8,%g0 */ |
903 | aa0aa4fa | bellard | |
904 | f930d07e | blueswir1 | { "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI(~0), "1+2,d", F_JSR|F_DELAYED, v6 }, |
905 | f930d07e | blueswir1 | { "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI_RS2(~0), "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,d */ |
906 | f930d07e | blueswir1 | { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|SIMM13(~0), "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,d */ |
907 | f930d07e | blueswir1 | { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RS1_G0, "i,d", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,d */ |
908 | f930d07e | blueswir1 | { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "1+i,d", F_JSR|F_DELAYED, v6 }, |
909 | f930d07e | blueswir1 | { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "i+1,d", F_JSR|F_DELAYED, v6 }, |
910 | f930d07e | blueswir1 | |
911 | f930d07e | blueswir1 | { "done", F3(2, 0x3e, 0)|RD(0), F3(~2, ~0x3e, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, v9 }, |
912 | f930d07e | blueswir1 | { "retry", F3(2, 0x3e, 0)|RD(1), F3(~2, ~0x3e, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 }, |
913 | f930d07e | blueswir1 | { "saved", F3(2, 0x31, 0)|RD(0), F3(~2, ~0x31, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, v9 }, |
914 | f930d07e | blueswir1 | { "restored", F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 }, |
915 | 46f42f29 | blueswir1 | { "allclean", F3(2, 0x31, 0)|RD(2), F3(~2, ~0x31, ~0)|RD(~2)|RS1_G0|SIMM13(~0), "", 0, v9 }, |
916 | 46f42f29 | blueswir1 | { "otherw", F3(2, 0x31, 0)|RD(3), F3(~2, ~0x31, ~0)|RD(~3)|RS1_G0|SIMM13(~0), "", 0, v9 }, |
917 | 46f42f29 | blueswir1 | { "normalw", F3(2, 0x31, 0)|RD(4), F3(~2, ~0x31, ~0)|RD(~4)|RS1_G0|SIMM13(~0), "", 0, v9 }, |
918 | 46f42f29 | blueswir1 | { "invalw", F3(2, 0x31, 0)|RD(5), F3(~2, ~0x31, ~0)|RD(~5)|RS1_G0|SIMM13(~0), "", 0, v9 }, |
919 | f930d07e | blueswir1 | { "sir", F3(2, 0x30, 1)|RD(0xf), F3(~2, ~0x30, ~1)|RD(~0xf)|RS1_G0, "i", 0, v9 }, |
920 | f930d07e | blueswir1 | |
921 | f930d07e | blueswir1 | { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", 0, v8 }, |
922 | f930d07e | blueswir1 | { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", 0, v8 }, /* flush rs1+%g0 */ |
923 | f930d07e | blueswir1 | { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", 0, v8 }, /* flush rs1+0 */ |
924 | f930d07e | blueswir1 | { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", 0, v8 }, /* flush %g0+i */ |
925 | f930d07e | blueswir1 | { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", 0, v8 }, |
926 | f930d07e | blueswir1 | { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", 0, v8 }, |
927 | aa0aa4fa | bellard | |
928 | aa0aa4fa | bellard | /* IFLUSH was renamed to FLUSH in v8. */
|
929 | f930d07e | blueswir1 | { "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", F_ALIAS, v6 }, |
930 | f930d07e | blueswir1 | { "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", F_ALIAS, v6 }, /* flush rs1+%g0 */ |
931 | f930d07e | blueswir1 | { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", F_ALIAS, v6 }, /* flush rs1+0 */ |
932 | f930d07e | blueswir1 | { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", F_ALIAS, v6 }, |
933 | f930d07e | blueswir1 | { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", F_ALIAS, v6 }, |
934 | f930d07e | blueswir1 | { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", F_ALIAS, v6 }, |
935 | f930d07e | blueswir1 | |
936 | f930d07e | blueswir1 | { "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI(~0), "1+2", 0, v9 }, |
937 | f930d07e | blueswir1 | { "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI_RS2(~0), "1", 0, v9 }, /* return rs1+%g0 */ |
938 | f930d07e | blueswir1 | { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|SIMM13(~0), "1", 0, v9 }, /* return rs1+0 */ |
939 | f930d07e | blueswir1 | { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RS1_G0, "i", 0, v9 }, /* return %g0+i */ |
940 | f930d07e | blueswir1 | { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "1+i", 0, v9 }, |
941 | f930d07e | blueswir1 | { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "i+1", 0, v9 }, |
942 | f930d07e | blueswir1 | |
943 | f930d07e | blueswir1 | { "flushw", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, v9 }, |
944 | f930d07e | blueswir1 | |
945 | f930d07e | blueswir1 | { "membar", F3(2, 0x28, 1)|RS1(0xf), F3(~2, ~0x28, ~1)|RD_G0|RS1(~0xf)|SIMM13(~127), "K", 0, v9 }, |
946 | f930d07e | blueswir1 | { "stbar", F3(2, 0x28, 0)|RS1(0xf), F3(~2, ~0x28, ~0)|RD_G0|RS1(~0xf)|SIMM13(~0), "", 0, v8 }, |
947 | f930d07e | blueswir1 | |
948 | f930d07e | blueswir1 | { "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0), "[1+2],*", 0, v9 }, |
949 | f930d07e | blueswir1 | { "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0)|RS2_G0, "[1],*", 0, v9 }, /* prefetch [rs1+%g0],prefetch_fcn */ |
950 | f930d07e | blueswir1 | { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[1+i],*", 0, v9 }, |
951 | f930d07e | blueswir1 | { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[i+1],*", 0, v9 }, |
952 | f930d07e | blueswir1 | { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|RS1_G0, "[i],*", 0, v9 }, |
953 | f930d07e | blueswir1 | { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|SIMM13(~0), "[1],*", 0, v9 }, /* prefetch [rs1+0],prefetch_fcn */ |
954 | f930d07e | blueswir1 | { "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0), "[1+2]A,*", 0, v9 }, |
955 | f930d07e | blueswir1 | { "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0)|RS2_G0, "[1]A,*", 0, v9 }, /* prefetcha [rs1+%g0],prefetch_fcn */ |
956 | f930d07e | blueswir1 | { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[1+i]o,*", 0, v9 }, |
957 | f930d07e | blueswir1 | { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[i+1]o,*", 0, v9 }, |
958 | f930d07e | blueswir1 | { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|RS1_G0, "[i]o,*", 0, v9 }, |
959 | f930d07e | blueswir1 | { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|SIMM13(~0), "[1]o,*", 0, v9 }, /* prefetcha [rs1+0],d */ |
960 | f930d07e | blueswir1 | |
961 | f930d07e | blueswir1 | { "sll", F3(2, 0x25, 0), F3(~2, ~0x25, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 }, |
962 | f930d07e | blueswir1 | { "sll", F3(2, 0x25, 1), F3(~2, ~0x25, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 }, |
963 | f930d07e | blueswir1 | { "sra", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 }, |
964 | f930d07e | blueswir1 | { "sra", F3(2, 0x27, 1), F3(~2, ~0x27, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 }, |
965 | f930d07e | blueswir1 | { "srl", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 }, |
966 | f930d07e | blueswir1 | { "srl", F3(2, 0x26, 1), F3(~2, ~0x26, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 }, |
967 | f930d07e | blueswir1 | |
968 | f930d07e | blueswir1 | { "sllx", F3(2, 0x25, 0)|(1<<12), F3(~2, ~0x25, ~0)|(0x7f<<5), "1,2,d", 0, v9 }, |
969 | f930d07e | blueswir1 | { "sllx", F3(2, 0x25, 1)|(1<<12), F3(~2, ~0x25, ~1)|(0x3f<<6), "1,Y,d", 0, v9 }, |
970 | f930d07e | blueswir1 | { "srax", F3(2, 0x27, 0)|(1<<12), F3(~2, ~0x27, ~0)|(0x7f<<5), "1,2,d", 0, v9 }, |
971 | f930d07e | blueswir1 | { "srax", F3(2, 0x27, 1)|(1<<12), F3(~2, ~0x27, ~1)|(0x3f<<6), "1,Y,d", 0, v9 }, |
972 | f930d07e | blueswir1 | { "srlx", F3(2, 0x26, 0)|(1<<12), F3(~2, ~0x26, ~0)|(0x7f<<5), "1,2,d", 0, v9 }, |
973 | f930d07e | blueswir1 | { "srlx", F3(2, 0x26, 1)|(1<<12), F3(~2, ~0x26, ~1)|(0x3f<<6), "1,Y,d", 0, v9 }, |
974 | f930d07e | blueswir1 | |
975 | f930d07e | blueswir1 | { "mulscc", F3(2, 0x24, 0), F3(~2, ~0x24, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
976 | f930d07e | blueswir1 | { "mulscc", F3(2, 0x24, 1), F3(~2, ~0x24, ~1), "1,i,d", 0, v6 }, |
977 | f930d07e | blueswir1 | |
978 | f930d07e | blueswir1 | { "divscc", F3(2, 0x1d, 0), F3(~2, ~0x1d, ~0)|ASI(~0), "1,2,d", 0, sparclite }, |
979 | f930d07e | blueswir1 | { "divscc", F3(2, 0x1d, 1), F3(~2, ~0x1d, ~1), "1,i,d", 0, sparclite }, |
980 | f930d07e | blueswir1 | |
981 | f930d07e | blueswir1 | { "scan", F3(2, 0x2c, 0), F3(~2, ~0x2c, ~0)|ASI(~0), "1,2,d", 0, sparclet|sparclite }, |
982 | f930d07e | blueswir1 | { "scan", F3(2, 0x2c, 1), F3(~2, ~0x2c, ~1), "1,i,d", 0, sparclet|sparclite }, |
983 | f930d07e | blueswir1 | |
984 | f930d07e | blueswir1 | { "popc", F3(2, 0x2e, 0), F3(~2, ~0x2e, ~0)|RS1_G0|ASI(~0),"2,d", 0, v9 }, |
985 | f930d07e | blueswir1 | { "popc", F3(2, 0x2e, 1), F3(~2, ~0x2e, ~1)|RS1_G0, "i,d", 0, v9 }, |
986 | f930d07e | blueswir1 | |
987 | f930d07e | blueswir1 | { "clr", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "d", F_ALIAS, v6 }, /* or %g0,%g0,d */ |
988 | f930d07e | blueswir1 | { "clr", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0|SIMM13(~0), "d", F_ALIAS, v6 }, /* or %g0,0,d */ |
989 | f930d07e | blueswir1 | { "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 }, |
990 | f930d07e | blueswir1 | { "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+%g0] */ |
991 | f930d07e | blueswir1 | { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 }, |
992 | f930d07e | blueswir1 | { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 }, |
993 | f930d07e | blueswir1 | { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 }, |
994 | f930d07e | blueswir1 | { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+0] */ |
995 | f930d07e | blueswir1 | |
996 | f930d07e | blueswir1 | { "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 }, |
997 | f930d07e | blueswir1 | { "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+%g0] */ |
998 | f930d07e | blueswir1 | { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 }, |
999 | f930d07e | blueswir1 | { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 }, |
1000 | f930d07e | blueswir1 | { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 }, |
1001 | f930d07e | blueswir1 | { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+0] */ |
1002 | f930d07e | blueswir1 | |
1003 | f930d07e | blueswir1 | { "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 }, |
1004 | f930d07e | blueswir1 | { "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+%g0] */ |
1005 | f930d07e | blueswir1 | { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 }, |
1006 | f930d07e | blueswir1 | { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 }, |
1007 | f930d07e | blueswir1 | { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 }, |
1008 | f930d07e | blueswir1 | { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+0] */ |
1009 | f930d07e | blueswir1 | |
1010 | f930d07e | blueswir1 | { "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v9 }, |
1011 | f930d07e | blueswir1 | { "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+%g0] */ |
1012 | f930d07e | blueswir1 | { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[1+i]", F_ALIAS, v9 }, |
1013 | f930d07e | blueswir1 | { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[i+1]", F_ALIAS, v9 }, |
1014 | f930d07e | blueswir1 | { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v9 }, |
1015 | f930d07e | blueswir1 | { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+0] */ |
1016 | f930d07e | blueswir1 | |
1017 | f930d07e | blueswir1 | { "orcc", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1018 | f930d07e | blueswir1 | { "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "1,i,d", 0, v6 }, |
1019 | f930d07e | blueswir1 | { "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "i,1,d", 0, v6 }, |
1020 | aa0aa4fa | bellard | |
1021 | aa0aa4fa | bellard | /* This is not a commutative instruction. */
|
1022 | f930d07e | blueswir1 | { "orncc", F3(2, 0x16, 0), F3(~2, ~0x16, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1023 | f930d07e | blueswir1 | { "orncc", F3(2, 0x16, 1), F3(~2, ~0x16, ~1), "1,i,d", 0, v6 }, |
1024 | aa0aa4fa | bellard | |
1025 | aa0aa4fa | bellard | /* This is not a commutative instruction. */
|
1026 | f930d07e | blueswir1 | { "orn", F3(2, 0x06, 0), F3(~2, ~0x06, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1027 | f930d07e | blueswir1 | { "orn", F3(2, 0x06, 1), F3(~2, ~0x06, ~1), "1,i,d", 0, v6 }, |
1028 | f930d07e | blueswir1 | |
1029 | f930d07e | blueswir1 | { "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|ASI_RS2(~0), "1", 0, v6 }, /* orcc rs1, %g0, %g0 */ |
1030 | f930d07e | blueswir1 | { "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|RS1_G0|ASI(~0), "2", 0, v6 }, /* orcc %g0, rs2, %g0 */ |
1031 | f930d07e | blueswir1 | { "tst", F3(2, 0x12, 1), F3(~2, ~0x12, ~1)|RD_G0|SIMM13(~0), "1", 0, v6 }, /* orcc rs1, 0, %g0 */ |
1032 | f930d07e | blueswir1 | |
1033 | f930d07e | blueswir1 | { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", 0, v8 }, /* wr r,r,%asrX */ |
1034 | f930d07e | blueswir1 | { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", 0, v8 }, /* wr r,i,%asrX */ |
1035 | f930d07e | blueswir1 | { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */ |
1036 | f930d07e | blueswir1 | { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", 0, v6 }, /* wr r,r,%y */ |
1037 | f930d07e | blueswir1 | { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", 0, v6 }, /* wr r,i,%y */ |
1038 | f930d07e | blueswir1 | { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */ |
1039 | f930d07e | blueswir1 | { "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", 0, v6notv9 }, /* wr r,r,%psr */ |
1040 | f930d07e | blueswir1 | { "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", 0, v6notv9 }, /* wr r,i,%psr */ |
1041 | f930d07e | blueswir1 | { "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */ |
1042 | f930d07e | blueswir1 | { "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", 0, v6notv9 }, /* wr r,r,%wim */ |
1043 | f930d07e | blueswir1 | { "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", 0, v6notv9 }, /* wr r,i,%wim */ |
1044 | f930d07e | blueswir1 | { "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */ |
1045 | f930d07e | blueswir1 | { "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", 0, v6notv9 }, /* wr r,r,%tbr */ |
1046 | f930d07e | blueswir1 | { "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", 0, v6notv9 }, /* wr r,i,%tbr */ |
1047 | f930d07e | blueswir1 | { "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */ |
1048 | f930d07e | blueswir1 | |
1049 | f930d07e | blueswir1 | { "wr", F3(2, 0x30, 0)|RD(2), F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0), "1,2,E", 0, v9 }, /* wr r,r,%ccr */ |
1050 | f930d07e | blueswir1 | { "wr", F3(2, 0x30, 1)|RD(2), F3(~2, ~0x30, ~1)|RD(~2), "1,i,E", 0, v9 }, /* wr r,i,%ccr */ |
1051 | f930d07e | blueswir1 | { "wr", F3(2, 0x30, 0)|RD(3), F3(~2, ~0x30, ~0)|RD(~3)|ASI(~0), "1,2,o", 0, v9 }, /* wr r,r,%asi */ |
1052 | f930d07e | blueswir1 | { "wr", F3(2, 0x30, 1)|RD(3), F3(~2, ~0x30, ~1)|RD(~3), "1,i,o", 0, v9 }, /* wr r,i,%asi */ |
1053 | f930d07e | blueswir1 | { "wr", F3(2, 0x30, 0)|RD(6), F3(~2, ~0x30, ~0)|RD(~6)|ASI(~0), "1,2,s", 0, v9 }, /* wr r,r,%fprs */ |
1054 | f930d07e | blueswir1 | { "wr", F3(2, 0x30, 1)|RD(6), F3(~2, ~0x30, ~1)|RD(~6), "1,i,s", 0, v9 }, /* wr r,i,%fprs */ |
1055 | f930d07e | blueswir1 | |
1056 | f930d07e | blueswir1 | { "wr", F3(2, 0x30, 0)|RD(16), F3(~2, ~0x30, ~0)|RD(~16)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%pcr */ |
1057 | f930d07e | blueswir1 | { "wr", F3(2, 0x30, 1)|RD(16), F3(~2, ~0x30, ~1)|RD(~16), "1,i,_", 0, v9a }, /* wr r,i,%pcr */ |
1058 | f930d07e | blueswir1 | { "wr", F3(2, 0x30, 0)|RD(17), F3(~2, ~0x30, ~0)|RD(~17)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%pic */ |
1059 | f930d07e | blueswir1 | { "wr", F3(2, 0x30, 1)|RD(17), F3(~2, ~0x30, ~1)|RD(~17), "1,i,_", 0, v9a }, /* wr r,i,%pic */ |
1060 | f930d07e | blueswir1 | { "wr", F3(2, 0x30, 0)|RD(18), F3(~2, ~0x30, ~0)|RD(~18)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%dcr */ |
1061 | f930d07e | blueswir1 | { "wr", F3(2, 0x30, 1)|RD(18), F3(~2, ~0x30, ~1)|RD(~18), "1,i,_", 0, v9a }, /* wr r,i,%dcr */ |
1062 | f930d07e | blueswir1 | { "wr", F3(2, 0x30, 0)|RD(19), F3(~2, ~0x30, ~0)|RD(~19)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%gsr */ |
1063 | f930d07e | blueswir1 | { "wr", F3(2, 0x30, 1)|RD(19), F3(~2, ~0x30, ~1)|RD(~19), "1,i,_", 0, v9a }, /* wr r,i,%gsr */ |
1064 | f930d07e | blueswir1 | { "wr", F3(2, 0x30, 0)|RD(20), F3(~2, ~0x30, ~0)|RD(~20)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%set_softint */ |
1065 | f930d07e | blueswir1 | { "wr", F3(2, 0x30, 1)|RD(20), F3(~2, ~0x30, ~1)|RD(~20), "1,i,_", 0, v9a }, /* wr r,i,%set_softint */ |
1066 | f930d07e | blueswir1 | { "wr", F3(2, 0x30, 0)|RD(21), F3(~2, ~0x30, ~0)|RD(~21)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%clear_softint */ |
1067 | f930d07e | blueswir1 | { "wr", F3(2, 0x30, 1)|RD(21), F3(~2, ~0x30, ~1)|RD(~21), "1,i,_", 0, v9a }, /* wr r,i,%clear_softint */ |
1068 | f930d07e | blueswir1 | { "wr", F3(2, 0x30, 0)|RD(22), F3(~2, ~0x30, ~0)|RD(~22)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%softint */ |
1069 | f930d07e | blueswir1 | { "wr", F3(2, 0x30, 1)|RD(22), F3(~2, ~0x30, ~1)|RD(~22), "1,i,_", 0, v9a }, /* wr r,i,%softint */ |
1070 | f930d07e | blueswir1 | { "wr", F3(2, 0x30, 0)|RD(23), F3(~2, ~0x30, ~0)|RD(~23)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%tick_cmpr */ |
1071 | f930d07e | blueswir1 | { "wr", F3(2, 0x30, 1)|RD(23), F3(~2, ~0x30, ~1)|RD(~23), "1,i,_", 0, v9a }, /* wr r,i,%tick_cmpr */ |
1072 | f930d07e | blueswir1 | { "wr", F3(2, 0x30, 0)|RD(24), F3(~2, ~0x30, ~0)|RD(~24)|ASI(~0), "1,2,_", 0, v9b }, /* wr r,r,%sys_tick */ |
1073 | f930d07e | blueswir1 | { "wr", F3(2, 0x30, 1)|RD(24), F3(~2, ~0x30, ~1)|RD(~24), "1,i,_", 0, v9b }, /* wr r,i,%sys_tick */ |
1074 | f930d07e | blueswir1 | { "wr", F3(2, 0x30, 0)|RD(25), F3(~2, ~0x30, ~0)|RD(~25)|ASI(~0), "1,2,_", 0, v9b }, /* wr r,r,%sys_tick_cmpr */ |
1075 | f930d07e | blueswir1 | { "wr", F3(2, 0x30, 1)|RD(25), F3(~2, ~0x30, ~1)|RD(~25), "1,i,_", 0, v9b }, /* wr r,i,%sys_tick_cmpr */ |
1076 | f930d07e | blueswir1 | |
1077 | f930d07e | blueswir1 | { "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", 0, v8 }, /* rd %asrX,r */ |
1078 | f930d07e | blueswir1 | { "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", 0, v6 }, /* rd %y,r */ |
1079 | f930d07e | blueswir1 | { "rd", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", 0, v6notv9 }, /* rd %psr,r */ |
1080 | f930d07e | blueswir1 | { "rd", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", 0, v6notv9 }, /* rd %wim,r */ |
1081 | f930d07e | blueswir1 | { "rd", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", 0, v6notv9 }, /* rd %tbr,r */ |
1082 | f930d07e | blueswir1 | |
1083 | f930d07e | blueswir1 | { "rd", F3(2, 0x28, 0)|RS1(2), F3(~2, ~0x28, ~0)|RS1(~2)|SIMM13(~0), "E,d", 0, v9 }, /* rd %ccr,r */ |
1084 | f930d07e | blueswir1 | { "rd", F3(2, 0x28, 0)|RS1(3), F3(~2, ~0x28, ~0)|RS1(~3)|SIMM13(~0), "o,d", 0, v9 }, /* rd %asi,r */ |
1085 | f930d07e | blueswir1 | { "rd", F3(2, 0x28, 0)|RS1(4), F3(~2, ~0x28, ~0)|RS1(~4)|SIMM13(~0), "W,d", 0, v9 }, /* rd %tick,r */ |
1086 | f930d07e | blueswir1 | { "rd", F3(2, 0x28, 0)|RS1(5), F3(~2, ~0x28, ~0)|RS1(~5)|SIMM13(~0), "P,d", 0, v9 }, /* rd %pc,r */ |
1087 | f930d07e | blueswir1 | { "rd", F3(2, 0x28, 0)|RS1(6), F3(~2, ~0x28, ~0)|RS1(~6)|SIMM13(~0), "s,d", 0, v9 }, /* rd %fprs,r */ |
1088 | f930d07e | blueswir1 | |
1089 | f930d07e | blueswir1 | { "rd", F3(2, 0x28, 0)|RS1(16), F3(~2, ~0x28, ~0)|RS1(~16)|SIMM13(~0), "/,d", 0, v9a }, /* rd %pcr,r */ |
1090 | f930d07e | blueswir1 | { "rd", F3(2, 0x28, 0)|RS1(17), F3(~2, ~0x28, ~0)|RS1(~17)|SIMM13(~0), "/,d", 0, v9a }, /* rd %pic,r */ |
1091 | f930d07e | blueswir1 | { "rd", F3(2, 0x28, 0)|RS1(18), F3(~2, ~0x28, ~0)|RS1(~18)|SIMM13(~0), "/,d", 0, v9a }, /* rd %dcr,r */ |
1092 | f930d07e | blueswir1 | { "rd", F3(2, 0x28, 0)|RS1(19), F3(~2, ~0x28, ~0)|RS1(~19)|SIMM13(~0), "/,d", 0, v9a }, /* rd %gsr,r */ |
1093 | f930d07e | blueswir1 | { "rd", F3(2, 0x28, 0)|RS1(22), F3(~2, ~0x28, ~0)|RS1(~22)|SIMM13(~0), "/,d", 0, v9a }, /* rd %softint,r */ |
1094 | f930d07e | blueswir1 | { "rd", F3(2, 0x28, 0)|RS1(23), F3(~2, ~0x28, ~0)|RS1(~23)|SIMM13(~0), "/,d", 0, v9a }, /* rd %tick_cmpr,r */ |
1095 | f930d07e | blueswir1 | { "rd", F3(2, 0x28, 0)|RS1(24), F3(~2, ~0x28, ~0)|RS1(~24)|SIMM13(~0), "/,d", 0, v9b }, /* rd %sys_tick,r */ |
1096 | f930d07e | blueswir1 | { "rd", F3(2, 0x28, 0)|RS1(25), F3(~2, ~0x28, ~0)|RS1(~25)|SIMM13(~0), "/,d", 0, v9b }, /* rd %sys_tick_cmpr,r */ |
1097 | f930d07e | blueswir1 | |
1098 | f930d07e | blueswir1 | { "rdpr", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|SIMM13(~0), "?,d", 0, v9 }, /* rdpr %priv,r */ |
1099 | f930d07e | blueswir1 | { "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0), "1,2,!", 0, v9 }, /* wrpr r1,r2,%priv */ |
1100 | f930d07e | blueswir1 | { "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|SIMM13(~0), "1,!", 0, v9 }, /* wrpr r1,%priv */ |
1101 | f930d07e | blueswir1 | { "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "1,i,!", 0, v9 }, /* wrpr r1,i,%priv */ |
1102 | f930d07e | blueswir1 | { "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "i,1,!", F_ALIAS, v9 }, /* wrpr i,r1,%priv */ |
1103 | f930d07e | blueswir1 | { "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RS1(~0), "i,!", 0, v9 }, /* wrpr i,%priv */ |
1104 | aa0aa4fa | bellard | |
1105 | 46f42f29 | blueswir1 | { "rdhpr", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|SIMM13(~0), "$,d", 0, v9 }, /* rdhpr %hpriv,r */ |
1106 | 46f42f29 | blueswir1 | { "wrhpr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0), "1,2,%", 0, v9 }, /* wrhpr r1,r2,%hpriv */ |
1107 | 46f42f29 | blueswir1 | { "wrhpr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|SIMM13(~0), "1,%", 0, v9 }, /* wrhpr r1,%hpriv */ |
1108 | 46f42f29 | blueswir1 | { "wrhpr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1), "1,i,%", 0, v9 }, /* wrhpr r1,i,%hpriv */ |
1109 | 46f42f29 | blueswir1 | { "wrhpr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1), "i,1,%", F_ALIAS, v9 }, /* wrhpr i,r1,%hpriv */ |
1110 | 46f42f29 | blueswir1 | { "wrhpr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RS1(~0), "i,%", 0, v9 }, /* wrhpr i,%hpriv */ |
1111 | 46f42f29 | blueswir1 | |
1112 | aa0aa4fa | bellard | /* ??? This group seems wrong. A three operand move? */
|
1113 | f930d07e | blueswir1 | { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", F_ALIAS, v8 }, /* wr r,r,%asrX */ |
1114 | f930d07e | blueswir1 | { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", F_ALIAS, v8 }, /* wr r,i,%asrX */ |
1115 | f930d07e | blueswir1 | { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", F_ALIAS, v6 }, /* wr r,r,%y */ |
1116 | f930d07e | blueswir1 | { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", F_ALIAS, v6 }, /* wr r,i,%y */ |
1117 | f930d07e | blueswir1 | { "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", F_ALIAS, v6notv9 }, /* wr r,r,%psr */ |
1118 | f930d07e | blueswir1 | { "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", F_ALIAS, v6notv9 }, /* wr r,i,%psr */ |
1119 | f930d07e | blueswir1 | { "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", F_ALIAS, v6notv9 }, /* wr r,r,%wim */ |
1120 | f930d07e | blueswir1 | { "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", F_ALIAS, v6notv9 }, /* wr r,i,%wim */ |
1121 | f930d07e | blueswir1 | { "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", F_ALIAS, v6notv9 }, /* wr r,r,%tbr */ |
1122 | f930d07e | blueswir1 | { "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", F_ALIAS, v6notv9 }, /* wr r,i,%tbr */ |
1123 | f930d07e | blueswir1 | |
1124 | f930d07e | blueswir1 | { "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", F_ALIAS, v8 }, /* rd %asr1,r */ |
1125 | f930d07e | blueswir1 | { "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", F_ALIAS, v6 }, /* rd %y,r */ |
1126 | f930d07e | blueswir1 | { "mov", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", F_ALIAS, v6notv9 }, /* rd %psr,r */ |
1127 | f930d07e | blueswir1 | { "mov", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", F_ALIAS, v6notv9 }, /* rd %wim,r */ |
1128 | f930d07e | blueswir1 | { "mov", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", F_ALIAS, v6notv9 }, /* rd %tbr,r */ |
1129 | f930d07e | blueswir1 | |
1130 | f930d07e | blueswir1 | { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */ |
1131 | f930d07e | blueswir1 | { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "i,m", F_ALIAS, v8 }, /* wr %g0,i,%asrX */ |
1132 | f930d07e | blueswir1 | { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|SIMM13(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,0,%asrX */ |
1133 | f930d07e | blueswir1 | { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */ |
1134 | f930d07e | blueswir1 | { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "i,y", F_ALIAS, v6 }, /* wr %g0,i,%y */ |
1135 | f930d07e | blueswir1 | { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|SIMM13(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,0,%y */ |
1136 | f930d07e | blueswir1 | { "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */ |
1137 | f930d07e | blueswir1 | { "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "i,p", F_ALIAS, v6notv9 }, /* wr %g0,i,%psr */ |
1138 | f930d07e | blueswir1 | { "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|SIMM13(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,0,%psr */ |
1139 | f930d07e | blueswir1 | { "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */ |
1140 | f930d07e | blueswir1 | { "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "i,w", F_ALIAS, v6notv9 }, /* wr %g0,i,%wim */ |
1141 | f930d07e | blueswir1 | { "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|SIMM13(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,0,%wim */ |
1142 | f930d07e | blueswir1 | { "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */ |
1143 | f930d07e | blueswir1 | { "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "i,t", F_ALIAS, v6notv9 }, /* wr %g0,i,%tbr */ |
1144 | f930d07e | blueswir1 | { "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|SIMM13(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,0,%tbr */ |
1145 | f930d07e | blueswir1 | |
1146 | f930d07e | blueswir1 | { "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0|ASI(~0), "2,d", 0, v6 }, /* or %g0,rs2,d */ |
1147 | f930d07e | blueswir1 | { "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0, "i,d", 0, v6 }, /* or %g0,i,d */ |
1148 | f930d07e | blueswir1 | { "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI_RS2(~0), "1,d", 0, v6 }, /* or rs1,%g0,d */ |
1149 | f930d07e | blueswir1 | { "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|SIMM13(~0), "1,d", 0, v6 }, /* or rs1,0,d */ |
1150 | f930d07e | blueswir1 | |
1151 | f930d07e | blueswir1 | { "or", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1152 | f930d07e | blueswir1 | { "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "1,i,d", 0, v6 }, |
1153 | f930d07e | blueswir1 | { "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,1,d", 0, v6 }, |
1154 | f930d07e | blueswir1 | |
1155 | f930d07e | blueswir1 | { "bset", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* or rd,rs2,rd */ |
1156 | f930d07e | blueswir1 | { "bset", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,r", F_ALIAS, v6 }, /* or rd,i,rd */ |
1157 | aa0aa4fa | bellard | |
1158 | aa0aa4fa | bellard | /* This is not a commutative instruction. */
|
1159 | f930d07e | blueswir1 | { "andn", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1160 | f930d07e | blueswir1 | { "andn", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "1,i,d", 0, v6 }, |
1161 | aa0aa4fa | bellard | |
1162 | aa0aa4fa | bellard | /* This is not a commutative instruction. */
|
1163 | f930d07e | blueswir1 | { "andncc", F3(2, 0x15, 0), F3(~2, ~0x15, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1164 | f930d07e | blueswir1 | { "andncc", F3(2, 0x15, 1), F3(~2, ~0x15, ~1), "1,i,d", 0, v6 }, |
1165 | f930d07e | blueswir1 | |
1166 | f930d07e | blueswir1 | { "bclr", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* andn rd,rs2,rd */ |
1167 | f930d07e | blueswir1 | { "bclr", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "i,r", F_ALIAS, v6 }, /* andn rd,i,rd */ |
1168 | f930d07e | blueswir1 | |
1169 | f930d07e | blueswir1 | { "cmp", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|RD_G0|ASI(~0), "1,2", 0, v6 }, /* subcc rs1,rs2,%g0 */ |
1170 | f930d07e | blueswir1 | { "cmp", F3(2, 0x14, 1), F3(~2, ~0x14, ~1)|RD_G0, "1,i", 0, v6 }, /* subcc rs1,i,%g0 */ |
1171 | f930d07e | blueswir1 | |
1172 | f930d07e | blueswir1 | { "sub", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1173 | f930d07e | blueswir1 | { "sub", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "1,i,d", 0, v6 }, |
1174 | f930d07e | blueswir1 | |
1175 | f930d07e | blueswir1 | { "subcc", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1176 | f930d07e | blueswir1 | { "subcc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "1,i,d", 0, v6 }, |
1177 | f930d07e | blueswir1 | |
1178 | f930d07e | blueswir1 | { "subx", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, |
1179 | f930d07e | blueswir1 | { "subx", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, v6notv9 }, |
1180 | f930d07e | blueswir1 | { "subc", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, v9 }, |
1181 | f930d07e | blueswir1 | { "subc", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, v9 }, |
1182 | f930d07e | blueswir1 | |
1183 | f930d07e | blueswir1 | { "subxcc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, |
1184 | f930d07e | blueswir1 | { "subxcc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, v6notv9 }, |
1185 | f930d07e | blueswir1 | { "subccc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, v9 }, |
1186 | f930d07e | blueswir1 | { "subccc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, v9 }, |
1187 | f930d07e | blueswir1 | |
1188 | f930d07e | blueswir1 | { "and", F3(2, 0x01, 0), F3(~2, ~0x01, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1189 | f930d07e | blueswir1 | { "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "1,i,d", 0, v6 }, |
1190 | f930d07e | blueswir1 | { "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "i,1,d", 0, v6 }, |
1191 | f930d07e | blueswir1 | |
1192 | f930d07e | blueswir1 | { "andcc", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1193 | f930d07e | blueswir1 | { "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "1,i,d", 0, v6 }, |
1194 | f930d07e | blueswir1 | { "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "i,1,d", 0, v6 }, |
1195 | f930d07e | blueswir1 | |
1196 | f930d07e | blueswir1 | { "dec", F3(2, 0x04, 1)|SIMM13(0x1), F3(~2, ~0x04, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* sub rd,1,rd */ |
1197 | f930d07e | blueswir1 | { "dec", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "i,r", F_ALIAS, v8 }, /* sub rd,imm,rd */ |
1198 | f930d07e | blueswir1 | { "deccc", F3(2, 0x14, 1)|SIMM13(0x1), F3(~2, ~0x14, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* subcc rd,1,rd */ |
1199 | f930d07e | blueswir1 | { "deccc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "i,r", F_ALIAS, v8 }, /* subcc rd,imm,rd */ |
1200 | f930d07e | blueswir1 | { "inc", F3(2, 0x00, 1)|SIMM13(0x1), F3(~2, ~0x00, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* add rd,1,rd */ |
1201 | f930d07e | blueswir1 | { "inc", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,r", F_ALIAS, v8 }, /* add rd,imm,rd */ |
1202 | f930d07e | blueswir1 | { "inccc", F3(2, 0x10, 1)|SIMM13(0x1), F3(~2, ~0x10, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* addcc rd,1,rd */ |
1203 | f930d07e | blueswir1 | { "inccc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,r", F_ALIAS, v8 }, /* addcc rd,imm,rd */ |
1204 | f930d07e | blueswir1 | |
1205 | f930d07e | blueswir1 | { "btst", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|RD_G0|ASI(~0), "1,2", F_ALIAS, v6 }, /* andcc rs1,rs2,%g0 */ |
1206 | f930d07e | blueswir1 | { "btst", F3(2, 0x11, 1), F3(~2, ~0x11, ~1)|RD_G0, "i,1", F_ALIAS, v6 }, /* andcc rs1,i,%g0 */ |
1207 | f930d07e | blueswir1 | |
1208 | f930d07e | blueswir1 | { "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "2,d", F_ALIAS, v6 }, /* sub %g0,rs2,rd */ |
1209 | f930d07e | blueswir1 | { "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "O", F_ALIAS, v6 }, /* sub %g0,rd,rd */ |
1210 | f930d07e | blueswir1 | |
1211 | f930d07e | blueswir1 | { "add", F3(2, 0x00, 0), F3(~2, ~0x00, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1212 | f930d07e | blueswir1 | { "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "1,i,d", 0, v6 }, |
1213 | f930d07e | blueswir1 | { "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,1,d", 0, v6 }, |
1214 | f930d07e | blueswir1 | { "addcc", F3(2, 0x10, 0), F3(~2, ~0x10, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1215 | f930d07e | blueswir1 | { "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "1,i,d", 0, v6 }, |
1216 | f930d07e | blueswir1 | { "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,1,d", 0, v6 }, |
1217 | f930d07e | blueswir1 | |
1218 | f930d07e | blueswir1 | { "addx", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, |
1219 | f930d07e | blueswir1 | { "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, v6notv9 }, |
1220 | f930d07e | blueswir1 | { "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, v6notv9 }, |
1221 | f930d07e | blueswir1 | { "addc", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, v9 }, |
1222 | f930d07e | blueswir1 | { "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, v9 }, |
1223 | f930d07e | blueswir1 | { "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, v9 }, |
1224 | f930d07e | blueswir1 | |
1225 | f930d07e | blueswir1 | { "addxcc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, |
1226 | f930d07e | blueswir1 | { "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, v6notv9 }, |
1227 | f930d07e | blueswir1 | { "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, v6notv9 }, |
1228 | f930d07e | blueswir1 | { "addccc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, v9 }, |
1229 | f930d07e | blueswir1 | { "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, v9 }, |
1230 | f930d07e | blueswir1 | { "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, v9 }, |
1231 | f930d07e | blueswir1 | |
1232 | f930d07e | blueswir1 | { "smul", F3(2, 0x0b, 0), F3(~2, ~0x0b, ~0)|ASI(~0), "1,2,d", 0, v8 }, |
1233 | f930d07e | blueswir1 | { "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "1,i,d", 0, v8 }, |
1234 | f930d07e | blueswir1 | { "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "i,1,d", 0, v8 }, |
1235 | f930d07e | blueswir1 | { "smulcc", F3(2, 0x1b, 0), F3(~2, ~0x1b, ~0)|ASI(~0), "1,2,d", 0, v8 }, |
1236 | f930d07e | blueswir1 | { "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "1,i,d", 0, v8 }, |
1237 | f930d07e | blueswir1 | { "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "i,1,d", 0, v8 }, |
1238 | f930d07e | blueswir1 | { "umul", F3(2, 0x0a, 0), F3(~2, ~0x0a, ~0)|ASI(~0), "1,2,d", 0, v8 }, |
1239 | f930d07e | blueswir1 | { "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "1,i,d", 0, v8 }, |
1240 | f930d07e | blueswir1 | { "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "i,1,d", 0, v8 }, |
1241 | f930d07e | blueswir1 | { "umulcc", F3(2, 0x1a, 0), F3(~2, ~0x1a, ~0)|ASI(~0), "1,2,d", 0, v8 }, |
1242 | f930d07e | blueswir1 | { "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "1,i,d", 0, v8 }, |
1243 | f930d07e | blueswir1 | { "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "i,1,d", 0, v8 }, |
1244 | f930d07e | blueswir1 | { "sdiv", F3(2, 0x0f, 0), F3(~2, ~0x0f, ~0)|ASI(~0), "1,2,d", 0, v8 }, |
1245 | f930d07e | blueswir1 | { "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "1,i,d", 0, v8 }, |
1246 | f930d07e | blueswir1 | { "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "i,1,d", 0, v8 }, |
1247 | f930d07e | blueswir1 | { "sdivcc", F3(2, 0x1f, 0), F3(~2, ~0x1f, ~0)|ASI(~0), "1,2,d", 0, v8 }, |
1248 | f930d07e | blueswir1 | { "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "1,i,d", 0, v8 }, |
1249 | f930d07e | blueswir1 | { "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "i,1,d", 0, v8 }, |
1250 | f930d07e | blueswir1 | { "udiv", F3(2, 0x0e, 0), F3(~2, ~0x0e, ~0)|ASI(~0), "1,2,d", 0, v8 }, |
1251 | f930d07e | blueswir1 | { "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "1,i,d", 0, v8 }, |
1252 | f930d07e | blueswir1 | { "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "i,1,d", 0, v8 }, |
1253 | f930d07e | blueswir1 | { "udivcc", F3(2, 0x1e, 0), F3(~2, ~0x1e, ~0)|ASI(~0), "1,2,d", 0, v8 }, |
1254 | f930d07e | blueswir1 | { "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "1,i,d", 0, v8 }, |
1255 | f930d07e | blueswir1 | { "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "i,1,d", 0, v8 }, |
1256 | f930d07e | blueswir1 | |
1257 | f930d07e | blueswir1 | { "mulx", F3(2, 0x09, 0), F3(~2, ~0x09, ~0)|ASI(~0), "1,2,d", 0, v9 }, |
1258 | f930d07e | blueswir1 | { "mulx", F3(2, 0x09, 1), F3(~2, ~0x09, ~1), "1,i,d", 0, v9 }, |
1259 | f930d07e | blueswir1 | { "sdivx", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, v9 }, |
1260 | f930d07e | blueswir1 | { "sdivx", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, v9 }, |
1261 | f930d07e | blueswir1 | { "udivx", F3(2, 0x0d, 0), F3(~2, ~0x0d, ~0)|ASI(~0), "1,2,d", 0, v9 }, |
1262 | f930d07e | blueswir1 | { "udivx", F3(2, 0x0d, 1), F3(~2, ~0x0d, ~1), "1,i,d", 0, v9 }, |
1263 | f930d07e | blueswir1 | |
1264 | f930d07e | blueswir1 | { "call", F1(0x1), F1(~0x1), "L", F_JSR|F_DELAYED, v6 }, |
1265 | f930d07e | blueswir1 | { "call", F1(0x1), F1(~0x1), "L,#", F_JSR|F_DELAYED, v6 }, |
1266 | f930d07e | blueswir1 | |
1267 | f930d07e | blueswir1 | { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%o7 */ |
1268 | f930d07e | blueswir1 | { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2,#", F_JSR|F_DELAYED, v6 }, |
1269 | f930d07e | blueswir1 | { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%o7 */ |
1270 | f930d07e | blueswir1 | { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1,#", F_JSR|F_DELAYED, v6 }, |
1271 | f930d07e | blueswir1 | { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+i,%o7 */ |
1272 | f930d07e | blueswir1 | { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i,#", F_JSR|F_DELAYED, v6 }, |
1273 | f930d07e | blueswir1 | { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1", F_JSR|F_DELAYED, v6 }, /* jmpl i+rs1,%o7 */ |
1274 | f930d07e | blueswir1 | { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1,#", F_JSR|F_DELAYED, v6 }, |
1275 | f930d07e | blueswir1 | { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,%o7 */ |
1276 | f930d07e | blueswir1 | { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i,#", F_JSR|F_DELAYED, v6 }, |
1277 | f930d07e | blueswir1 | { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,%o7 */ |
1278 | f930d07e | blueswir1 | { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1,#", F_JSR|F_DELAYED, v6 }, |
1279 | aa0aa4fa | bellard | |
1280 | aa0aa4fa | bellard | |
1281 | aa0aa4fa | bellard | /* Conditional instructions.
|
1282 | aa0aa4fa | bellard | |
1283 | aa0aa4fa | bellard | Because this part of the table was such a mess earlier, I have
|
1284 | aa0aa4fa | bellard | macrofied it so that all the branches and traps are generated from
|
1285 | aa0aa4fa | bellard | a single-line description of each condition value. John Gilmore. */
|
1286 | aa0aa4fa | bellard | |
1287 | aa0aa4fa | bellard | /* Define branches -- one annulled, one without, etc. */
|
1288 | aa0aa4fa | bellard | #define br(opcode, mask, lose, flags) \
|
1289 | aa0aa4fa | bellard | { opcode, (mask)|ANNUL, (lose), ",a l", (flags), v6 }, \
|
1290 | aa0aa4fa | bellard | { opcode, (mask) , (lose)|ANNUL, "l", (flags), v6 }
|
1291 | aa0aa4fa | bellard | |
1292 | aa0aa4fa | bellard | #define brx(opcode, mask, lose, flags) /* v9 */ \ |
1293 | aa0aa4fa | bellard | { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), "Z,G", (flags), v9 }, \ |
1294 | aa0aa4fa | bellard | { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), ",T Z,G", (flags), v9 }, \ |
1295 | aa0aa4fa | bellard | { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a Z,G", (flags), v9 }, \ |
1296 | aa0aa4fa | bellard | { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a,T Z,G", (flags), v9 }, \ |
1297 | aa0aa4fa | bellard | { opcode, (mask)|(2<<20), ANNUL|BPRED|(lose), ",N Z,G", (flags), v9 }, \ |
1298 | aa0aa4fa | bellard | { opcode, (mask)|(2<<20)|ANNUL, BPRED|(lose), ",a,N Z,G", (flags), v9 }, \ |
1299 | aa0aa4fa | bellard | { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), "z,G", (flags), v9 }, \ |
1300 | aa0aa4fa | bellard | { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), ",T z,G", (flags), v9 }, \ |
1301 | aa0aa4fa | bellard | { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a z,G", (flags), v9 }, \ |
1302 | aa0aa4fa | bellard | { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a,T z,G", (flags), v9 }, \ |
1303 | aa0aa4fa | bellard | { opcode, (mask), ANNUL|BPRED|(lose)|(2<<20), ",N z,G", (flags), v9 }, \ |
1304 | aa0aa4fa | bellard | { opcode, (mask)|ANNUL, BPRED|(lose)|(2<<20), ",a,N z,G", (flags), v9 } |
1305 | aa0aa4fa | bellard | |
1306 | aa0aa4fa | bellard | /* Define four traps: reg+reg, reg + immediate, immediate alone, reg alone. */
|
1307 | aa0aa4fa | bellard | #define tr(opcode, mask, lose, flags) \
|
1308 | f930d07e | blueswir1 | { opcode, (mask)|(2<<11)|IMMED, (lose)|RS1_G0, "Z,i", (flags), v9 }, /* %g0 + imm */ \ |
1309 | f930d07e | blueswir1 | { opcode, (mask)|(2<<11)|IMMED, (lose), "Z,1+i", (flags), v9 }, /* rs1 + imm */ \ |
1310 | f930d07e | blueswir1 | { opcode, (mask)|(2<<11), IMMED|(lose), "Z,1+2", (flags), v9 }, /* rs1 + rs2 */ \ |
1311 | f930d07e | blueswir1 | { opcode, (mask)|(2<<11), IMMED|(lose)|RS2_G0, "Z,1", (flags), v9 }, /* rs1 + %g0 */ \ |
1312 | f930d07e | blueswir1 | { opcode, (mask)|IMMED, (lose)|RS1_G0, "z,i", (flags)|F_ALIAS, v9 }, /* %g0 + imm */ \ |
1313 | f930d07e | blueswir1 | { opcode, (mask)|IMMED, (lose), "z,1+i", (flags)|F_ALIAS, v9 }, /* rs1 + imm */ \ |
1314 | f930d07e | blueswir1 | { opcode, (mask), IMMED|(lose), "z,1+2", (flags)|F_ALIAS, v9 }, /* rs1 + rs2 */ \ |
1315 | f930d07e | blueswir1 | { opcode, (mask), IMMED|(lose)|RS2_G0, "z,1", (flags)|F_ALIAS, v9 }, /* rs1 + %g0 */ \ |
1316 | f930d07e | blueswir1 | { opcode, (mask)|IMMED, (lose)|RS1_G0, "i", (flags), v6 }, /* %g0 + imm */ \ |
1317 | f930d07e | blueswir1 | { opcode, (mask)|IMMED, (lose), "1+i", (flags), v6 }, /* rs1 + imm */ \ |
1318 | f930d07e | blueswir1 | { opcode, (mask), IMMED|(lose), "1+2", (flags), v6 }, /* rs1 + rs2 */ \ |
1319 | f930d07e | blueswir1 | { opcode, (mask), IMMED|(lose)|RS2_G0, "1", (flags), v6 } /* rs1 + %g0 */ |
1320 | aa0aa4fa | bellard | |
1321 | aa0aa4fa | bellard | /* v9: We must put `brx' before `br', to ensure that we never match something
|
1322 | aa0aa4fa | bellard | v9: against an expression unless it is an expression. Otherwise, we end
|
1323 | aa0aa4fa | bellard | v9: up with undefined symbol tables entries, because they get added, but
|
1324 | aa0aa4fa | bellard | v9: are not deleted if the pattern fails to match. */
|
1325 | aa0aa4fa | bellard | |
1326 | aa0aa4fa | bellard | /* Define both branches and traps based on condition mask */
|
1327 | aa0aa4fa | bellard | #define cond(bop, top, mask, flags) \
|
1328 | aa0aa4fa | bellard | brx(bop, F2(0, 1)|(mask), F2(~0, ~1)|((~mask)&COND(~0)), F_DELAYED|(flags)), /* v9 */ \ |
1329 | aa0aa4fa | bellard | br(bop, F2(0, 2)|(mask), F2(~0, ~2)|((~mask)&COND(~0)), F_DELAYED|(flags)), \ |
1330 | aa0aa4fa | bellard | tr(top, F3(2, 0x3a, 0)|(mask), F3(~2, ~0x3a, 0)|((~mask)&COND(~0)), ((flags) & ~(F_UNBR|F_CONDBR))) |
1331 | aa0aa4fa | bellard | |
1332 | aa0aa4fa | bellard | /* Define all the conditions, all the branches, all the traps. */
|
1333 | aa0aa4fa | bellard | |
1334 | aa0aa4fa | bellard | /* Standard branch, trap mnemonics */
|
1335 | f930d07e | blueswir1 | cond ("b", "ta", CONDA, F_UNBR), |
1336 | aa0aa4fa | bellard | /* Alternative form (just for assembly, not for disassembly) */
|
1337 | f930d07e | blueswir1 | cond ("ba", "t", CONDA, F_UNBR|F_ALIAS), |
1338 | f930d07e | blueswir1 | |
1339 | f930d07e | blueswir1 | cond ("bcc", "tcc", CONDCC, F_CONDBR), |
1340 | f930d07e | blueswir1 | cond ("bcs", "tcs", CONDCS, F_CONDBR), |
1341 | f930d07e | blueswir1 | cond ("be", "te", CONDE, F_CONDBR), |
1342 | f930d07e | blueswir1 | cond ("beq", "teq", CONDE, F_CONDBR|F_ALIAS), |
1343 | f930d07e | blueswir1 | cond ("bg", "tg", CONDG, F_CONDBR), |
1344 | f930d07e | blueswir1 | cond ("bgt", "tgt", CONDG, F_CONDBR|F_ALIAS), |
1345 | f930d07e | blueswir1 | cond ("bge", "tge", CONDGE, F_CONDBR), |
1346 | f930d07e | blueswir1 | cond ("bgeu", "tgeu", CONDGEU, F_CONDBR|F_ALIAS), /* for cc */ |
1347 | f930d07e | blueswir1 | cond ("bgu", "tgu", CONDGU, F_CONDBR), |
1348 | f930d07e | blueswir1 | cond ("bl", "tl", CONDL, F_CONDBR), |
1349 | f930d07e | blueswir1 | cond ("blt", "tlt", CONDL, F_CONDBR|F_ALIAS), |
1350 | f930d07e | blueswir1 | cond ("ble", "tle", CONDLE, F_CONDBR), |
1351 | f930d07e | blueswir1 | cond ("bleu", "tleu", CONDLEU, F_CONDBR), |
1352 | f930d07e | blueswir1 | cond ("blu", "tlu", CONDLU, F_CONDBR|F_ALIAS), /* for cs */ |
1353 | f930d07e | blueswir1 | cond ("bn", "tn", CONDN, F_CONDBR), |
1354 | f930d07e | blueswir1 | cond ("bne", "tne", CONDNE, F_CONDBR), |
1355 | f930d07e | blueswir1 | cond ("bneg", "tneg", CONDNEG, F_CONDBR), |
1356 | f930d07e | blueswir1 | cond ("bnz", "tnz", CONDNZ, F_CONDBR|F_ALIAS), /* for ne */ |
1357 | f930d07e | blueswir1 | cond ("bpos", "tpos", CONDPOS, F_CONDBR), |
1358 | f930d07e | blueswir1 | cond ("bvc", "tvc", CONDVC, F_CONDBR), |
1359 | f930d07e | blueswir1 | cond ("bvs", "tvs", CONDVS, F_CONDBR), |
1360 | f930d07e | blueswir1 | cond ("bz", "tz", CONDZ, F_CONDBR|F_ALIAS), /* for e */ |
1361 | aa0aa4fa | bellard | |
1362 | aa0aa4fa | bellard | #undef cond
|
1363 | aa0aa4fa | bellard | #undef br
|
1364 | aa0aa4fa | bellard | #undef brr /* v9 */ |
1365 | aa0aa4fa | bellard | #undef tr
|
1366 | aa0aa4fa | bellard | |
1367 | aa0aa4fa | bellard | #define brr(opcode, mask, lose, flags) /* v9 */ \ |
1368 | aa0aa4fa | bellard | { opcode, (mask)|BPRED, ANNUL|(lose), "1,k", F_DELAYED|(flags), v9 }, \
|
1369 | aa0aa4fa | bellard | { opcode, (mask)|BPRED, ANNUL|(lose), ",T 1,k", F_DELAYED|(flags), v9 }, \
|
1370 | aa0aa4fa | bellard | { opcode, (mask)|BPRED|ANNUL, (lose), ",a 1,k", F_DELAYED|(flags), v9 }, \
|
1371 | aa0aa4fa | bellard | { opcode, (mask)|BPRED|ANNUL, (lose), ",a,T 1,k", F_DELAYED|(flags), v9 }, \
|
1372 | aa0aa4fa | bellard | { opcode, (mask), ANNUL|BPRED|(lose), ",N 1,k", F_DELAYED|(flags), v9 }, \
|
1373 | aa0aa4fa | bellard | { opcode, (mask)|ANNUL, BPRED|(lose), ",a,N 1,k", F_DELAYED|(flags), v9 }
|
1374 | aa0aa4fa | bellard | |
1375 | aa0aa4fa | bellard | #define condr(bop, mask, flags) /* v9 */ \ |
1376 | aa0aa4fa | bellard | brr(bop, F2(0, 3)|COND(mask), F2(~0, ~3)|COND(~(mask)), (flags)) /* v9 */ |
1377 | aa0aa4fa | bellard | |
1378 | aa0aa4fa | bellard | /* v9 */ condr("brnz", 0x5, F_CONDBR), |
1379 | aa0aa4fa | bellard | /* v9 */ condr("brz", 0x1, F_CONDBR), |
1380 | aa0aa4fa | bellard | /* v9 */ condr("brgez", 0x7, F_CONDBR), |
1381 | aa0aa4fa | bellard | /* v9 */ condr("brlz", 0x3, F_CONDBR), |
1382 | aa0aa4fa | bellard | /* v9 */ condr("brlez", 0x2, F_CONDBR), |
1383 | aa0aa4fa | bellard | /* v9 */ condr("brgz", 0x6, F_CONDBR), |
1384 | aa0aa4fa | bellard | |
1385 | aa0aa4fa | bellard | #undef condr /* v9 */ |
1386 | aa0aa4fa | bellard | #undef brr /* v9 */ |
1387 | aa0aa4fa | bellard | |
1388 | aa0aa4fa | bellard | #define movr(opcode, mask, flags) /* v9 */ \ |
1389 | aa0aa4fa | bellard | { opcode, F3(2, 0x2f, 0)|RCOND(mask), F3(~2, ~0x2f, ~0)|RCOND(~(mask)), "1,2,d", (flags), v9 }, \ |
1390 | aa0aa4fa | bellard | { opcode, F3(2, 0x2f, 1)|RCOND(mask), F3(~2, ~0x2f, ~1)|RCOND(~(mask)), "1,j,d", (flags), v9 } |
1391 | aa0aa4fa | bellard | |
1392 | aa0aa4fa | bellard | #define fmrrs(opcode, mask, lose, flags) /* v9 */ \ |
1393 | aa0aa4fa | bellard | { opcode, (mask), (lose), "1,f,g", (flags) | F_FLOAT, v9 }
|
1394 | aa0aa4fa | bellard | #define fmrrd(opcode, mask, lose, flags) /* v9 */ \ |
1395 | aa0aa4fa | bellard | { opcode, (mask), (lose), "1,B,H", (flags) | F_FLOAT, v9 }
|
1396 | aa0aa4fa | bellard | #define fmrrq(opcode, mask, lose, flags) /* v9 */ \ |
1397 | aa0aa4fa | bellard | { opcode, (mask), (lose), "1,R,J", (flags) | F_FLOAT, v9 }
|
1398 | aa0aa4fa | bellard | |
1399 | aa0aa4fa | bellard | #define fmovrs(mop, mask, flags) /* v9 */ \ |
1400 | aa0aa4fa | bellard | fmrrs(mop, F3(2, 0x35, 0)|OPF_LOW5(5)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~5)|RCOND(~(mask)), (flags)) /* v9 */ |
1401 | aa0aa4fa | bellard | #define fmovrd(mop, mask, flags) /* v9 */ \ |
1402 | aa0aa4fa | bellard | fmrrd(mop, F3(2, 0x35, 0)|OPF_LOW5(6)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~6)|RCOND(~(mask)), (flags)) /* v9 */ |
1403 | aa0aa4fa | bellard | #define fmovrq(mop, mask, flags) /* v9 */ \ |
1404 | aa0aa4fa | bellard | fmrrq(mop, F3(2, 0x35, 0)|OPF_LOW5(7)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~7)|RCOND(~(mask)), (flags)) /* v9 */ |
1405 | aa0aa4fa | bellard | |
1406 | aa0aa4fa | bellard | /* v9 */ movr("movrne", 0x5, 0), |
1407 | aa0aa4fa | bellard | /* v9 */ movr("movre", 0x1, 0), |
1408 | aa0aa4fa | bellard | /* v9 */ movr("movrgez", 0x7, 0), |
1409 | aa0aa4fa | bellard | /* v9 */ movr("movrlz", 0x3, 0), |
1410 | aa0aa4fa | bellard | /* v9 */ movr("movrlez", 0x2, 0), |
1411 | aa0aa4fa | bellard | /* v9 */ movr("movrgz", 0x6, 0), |
1412 | aa0aa4fa | bellard | /* v9 */ movr("movrnz", 0x5, F_ALIAS), |
1413 | aa0aa4fa | bellard | /* v9 */ movr("movrz", 0x1, F_ALIAS), |
1414 | aa0aa4fa | bellard | |
1415 | aa0aa4fa | bellard | /* v9 */ fmovrs("fmovrsne", 0x5, 0), |
1416 | aa0aa4fa | bellard | /* v9 */ fmovrs("fmovrse", 0x1, 0), |
1417 | aa0aa4fa | bellard | /* v9 */ fmovrs("fmovrsgez", 0x7, 0), |
1418 | aa0aa4fa | bellard | /* v9 */ fmovrs("fmovrslz", 0x3, 0), |
1419 | aa0aa4fa | bellard | /* v9 */ fmovrs("fmovrslez", 0x2, 0), |
1420 | aa0aa4fa | bellard | /* v9 */ fmovrs("fmovrsgz", 0x6, 0), |
1421 | aa0aa4fa | bellard | /* v9 */ fmovrs("fmovrsnz", 0x5, F_ALIAS), |
1422 | aa0aa4fa | bellard | /* v9 */ fmovrs("fmovrsz", 0x1, F_ALIAS), |
1423 | aa0aa4fa | bellard | |
1424 | aa0aa4fa | bellard | /* v9 */ fmovrd("fmovrdne", 0x5, 0), |
1425 | aa0aa4fa | bellard | /* v9 */ fmovrd("fmovrde", 0x1, 0), |
1426 | aa0aa4fa | bellard | /* v9 */ fmovrd("fmovrdgez", 0x7, 0), |
1427 | aa0aa4fa | bellard | /* v9 */ fmovrd("fmovrdlz", 0x3, 0), |
1428 | aa0aa4fa | bellard | /* v9 */ fmovrd("fmovrdlez", 0x2, 0), |
1429 | aa0aa4fa | bellard | /* v9 */ fmovrd("fmovrdgz", 0x6, 0), |
1430 | aa0aa4fa | bellard | /* v9 */ fmovrd("fmovrdnz", 0x5, F_ALIAS), |
1431 | aa0aa4fa | bellard | /* v9 */ fmovrd("fmovrdz", 0x1, F_ALIAS), |
1432 | aa0aa4fa | bellard | |
1433 | aa0aa4fa | bellard | /* v9 */ fmovrq("fmovrqne", 0x5, 0), |
1434 | aa0aa4fa | bellard | /* v9 */ fmovrq("fmovrqe", 0x1, 0), |
1435 | aa0aa4fa | bellard | /* v9 */ fmovrq("fmovrqgez", 0x7, 0), |
1436 | aa0aa4fa | bellard | /* v9 */ fmovrq("fmovrqlz", 0x3, 0), |
1437 | aa0aa4fa | bellard | /* v9 */ fmovrq("fmovrqlez", 0x2, 0), |
1438 | aa0aa4fa | bellard | /* v9 */ fmovrq("fmovrqgz", 0x6, 0), |
1439 | aa0aa4fa | bellard | /* v9 */ fmovrq("fmovrqnz", 0x5, F_ALIAS), |
1440 | aa0aa4fa | bellard | /* v9 */ fmovrq("fmovrqz", 0x1, F_ALIAS), |
1441 | aa0aa4fa | bellard | |
1442 | aa0aa4fa | bellard | #undef movr /* v9 */ |
1443 | aa0aa4fa | bellard | #undef fmovr /* v9 */ |
1444 | aa0aa4fa | bellard | #undef fmrr /* v9 */ |
1445 | aa0aa4fa | bellard | |
1446 | aa0aa4fa | bellard | #define movicc(opcode, cond, flags) /* v9 */ \ |
1447 | aa0aa4fa | bellard | { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|XCC|(1<<11), "z,2,d", flags, v9 }, \ |
1448 | aa0aa4fa | bellard | { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|XCC|(1<<11), "z,I,d", flags, v9 }, \ |
1449 | aa0aa4fa | bellard | { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|(1<<11), "Z,2,d", flags, v9 }, \ |
1450 | aa0aa4fa | bellard | { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|(1<<11), "Z,I,d", flags, v9 } |
1451 | aa0aa4fa | bellard | |
1452 | aa0aa4fa | bellard | #define movfcc(opcode, fcond, flags) /* v9 */ \ |
1453 | aa0aa4fa | bellard | { opcode, F3(2, 0x2c, 0)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~0), "6,2,d", flags, v9 }, \ |
1454 | aa0aa4fa | bellard | { opcode, F3(2, 0x2c, 1)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~1), "6,I,d", flags, v9 }, \ |
1455 | aa0aa4fa | bellard | { opcode, F3(2, 0x2c, 0)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~0), "7,2,d", flags, v9 }, \ |
1456 | aa0aa4fa | bellard | { opcode, F3(2, 0x2c, 1)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~1), "7,I,d", flags, v9 }, \ |
1457 | aa0aa4fa | bellard | { opcode, F3(2, 0x2c, 0)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~0), "8,2,d", flags, v9 }, \ |
1458 | aa0aa4fa | bellard | { opcode, F3(2, 0x2c, 1)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~1), "8,I,d", flags, v9 }, \ |
1459 | aa0aa4fa | bellard | { opcode, F3(2, 0x2c, 0)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~0), "9,2,d", flags, v9 }, \ |
1460 | aa0aa4fa | bellard | { opcode, F3(2, 0x2c, 1)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~1), "9,I,d", flags, v9 } |
1461 | aa0aa4fa | bellard | |
1462 | aa0aa4fa | bellard | #define movcc(opcode, cond, fcond, flags) /* v9 */ \ |
1463 | aa0aa4fa | bellard | movfcc (opcode, fcond, flags), /* v9 */ \
|
1464 | aa0aa4fa | bellard | movicc (opcode, cond, flags) /* v9 */
|
1465 | aa0aa4fa | bellard | |
1466 | f930d07e | blueswir1 | /* v9 */ movcc ("mova", CONDA, FCONDA, 0), |
1467 | f930d07e | blueswir1 | /* v9 */ movicc ("movcc", CONDCC, 0), |
1468 | f930d07e | blueswir1 | /* v9 */ movicc ("movgeu", CONDGEU, F_ALIAS), |
1469 | f930d07e | blueswir1 | /* v9 */ movicc ("movcs", CONDCS, 0), |
1470 | f930d07e | blueswir1 | /* v9 */ movicc ("movlu", CONDLU, F_ALIAS), |
1471 | f930d07e | blueswir1 | /* v9 */ movcc ("move", CONDE, FCONDE, 0), |
1472 | f930d07e | blueswir1 | /* v9 */ movcc ("movg", CONDG, FCONDG, 0), |
1473 | f930d07e | blueswir1 | /* v9 */ movcc ("movge", CONDGE, FCONDGE, 0), |
1474 | f930d07e | blueswir1 | /* v9 */ movicc ("movgu", CONDGU, 0), |
1475 | f930d07e | blueswir1 | /* v9 */ movcc ("movl", CONDL, FCONDL, 0), |
1476 | f930d07e | blueswir1 | /* v9 */ movcc ("movle", CONDLE, FCONDLE, 0), |
1477 | f930d07e | blueswir1 | /* v9 */ movicc ("movleu", CONDLEU, 0), |
1478 | f930d07e | blueswir1 | /* v9 */ movfcc ("movlg", FCONDLG, 0), |
1479 | f930d07e | blueswir1 | /* v9 */ movcc ("movn", CONDN, FCONDN, 0), |
1480 | f930d07e | blueswir1 | /* v9 */ movcc ("movne", CONDNE, FCONDNE, 0), |
1481 | f930d07e | blueswir1 | /* v9 */ movicc ("movneg", CONDNEG, 0), |
1482 | f930d07e | blueswir1 | /* v9 */ movcc ("movnz", CONDNZ, FCONDNZ, F_ALIAS), |
1483 | f930d07e | blueswir1 | /* v9 */ movfcc ("movo", FCONDO, 0), |
1484 | f930d07e | blueswir1 | /* v9 */ movicc ("movpos", CONDPOS, 0), |
1485 | f930d07e | blueswir1 | /* v9 */ movfcc ("movu", FCONDU, 0), |
1486 | f930d07e | blueswir1 | /* v9 */ movfcc ("movue", FCONDUE, 0), |
1487 | f930d07e | blueswir1 | /* v9 */ movfcc ("movug", FCONDUG, 0), |
1488 | f930d07e | blueswir1 | /* v9 */ movfcc ("movuge", FCONDUGE, 0), |
1489 | f930d07e | blueswir1 | /* v9 */ movfcc ("movul", FCONDUL, 0), |
1490 | f930d07e | blueswir1 | /* v9 */ movfcc ("movule", FCONDULE, 0), |
1491 | f930d07e | blueswir1 | /* v9 */ movicc ("movvc", CONDVC, 0), |
1492 | f930d07e | blueswir1 | /* v9 */ movicc ("movvs", CONDVS, 0), |
1493 | f930d07e | blueswir1 | /* v9 */ movcc ("movz", CONDZ, FCONDZ, F_ALIAS), |
1494 | aa0aa4fa | bellard | |
1495 | aa0aa4fa | bellard | #undef movicc /* v9 */ |
1496 | aa0aa4fa | bellard | #undef movfcc /* v9 */ |
1497 | aa0aa4fa | bellard | #undef movcc /* v9 */ |
1498 | aa0aa4fa | bellard | |
1499 | f930d07e | blueswir1 | #define FM_SF 1 /* v9 - values for fpsize */ |
1500 | f930d07e | blueswir1 | #define FM_DF 2 /* v9 */ |
1501 | f930d07e | blueswir1 | #define FM_QF 3 /* v9 */ |
1502 | aa0aa4fa | bellard | |
1503 | 46f42f29 | blueswir1 | #define fmoviccx(opcode, fpsize, args, cond, flags) /* v9 */ \ |
1504 | 46f42f29 | blueswir1 | { opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z," args, flags, v9 }, \ |
1505 | 46f42f29 | blueswir1 | { opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z," args, flags, v9 } |
1506 | aa0aa4fa | bellard | |
1507 | 46f42f29 | blueswir1 | #define fmovfccx(opcode, fpsize, args, fcond, flags) /* v9 */ \ |
1508 | 46f42f29 | blueswir1 | { opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags, v9 }, \ |
1509 | 46f42f29 | blueswir1 | { opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags, v9 }, \ |
1510 | 46f42f29 | blueswir1 | { opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags, v9 }, \ |
1511 | 46f42f29 | blueswir1 | { opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags, v9 } |
1512 | aa0aa4fa | bellard | |
1513 | aa0aa4fa | bellard | /* FIXME: use fmovicc/fmovfcc? */ /* v9 */ |
1514 | 46f42f29 | blueswir1 | #define fmovccx(opcode, fpsize, args, cond, fcond, flags) /* v9 */ \ |
1515 | 46f42f29 | blueswir1 | { opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z," args, flags | F_FLOAT, v9 }, \ |
1516 | 46f42f29 | blueswir1 | { opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags | F_FLOAT, v9 }, \ |
1517 | 46f42f29 | blueswir1 | { opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z," args, flags | F_FLOAT, v9 }, \ |
1518 | 46f42f29 | blueswir1 | { opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags | F_FLOAT, v9 }, \ |
1519 | 46f42f29 | blueswir1 | { opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags | F_FLOAT, v9 }, \ |
1520 | 46f42f29 | blueswir1 | { opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags | F_FLOAT, v9 } |
1521 | 46f42f29 | blueswir1 | |
1522 | 46f42f29 | blueswir1 | #define fmovicc(suffix, cond, flags) /* v9 */ \ |
1523 | 46f42f29 | blueswir1 | fmoviccx("fmovd" suffix, FM_DF, "B,H", cond, flags), \ |
1524 | 46f42f29 | blueswir1 | fmoviccx("fmovq" suffix, FM_QF, "R,J", cond, flags), \ |
1525 | 46f42f29 | blueswir1 | fmoviccx("fmovs" suffix, FM_SF, "f,g", cond, flags) |
1526 | 46f42f29 | blueswir1 | |
1527 | 46f42f29 | blueswir1 | #define fmovfcc(suffix, fcond, flags) /* v9 */ \ |
1528 | 46f42f29 | blueswir1 | fmovfccx("fmovd" suffix, FM_DF, "B,H", fcond, flags), \ |
1529 | 46f42f29 | blueswir1 | fmovfccx("fmovq" suffix, FM_QF, "R,J", fcond, flags), \ |
1530 | 46f42f29 | blueswir1 | fmovfccx("fmovs" suffix, FM_SF, "f,g", fcond, flags) |
1531 | 46f42f29 | blueswir1 | |
1532 | 46f42f29 | blueswir1 | #define fmovcc(suffix, cond, fcond, flags) /* v9 */ \ |
1533 | 46f42f29 | blueswir1 | fmovccx("fmovd" suffix, FM_DF, "B,H", cond, fcond, flags), \ |
1534 | 46f42f29 | blueswir1 | fmovccx("fmovq" suffix, FM_QF, "R,J", cond, fcond, flags), \ |
1535 | 46f42f29 | blueswir1 | fmovccx("fmovs" suffix, FM_SF, "f,g", cond, fcond, flags) |
1536 | 46f42f29 | blueswir1 | |
1537 | 46f42f29 | blueswir1 | /* v9 */ fmovcc ("a", CONDA, FCONDA, 0), |
1538 | 46f42f29 | blueswir1 | /* v9 */ fmovicc ("cc", CONDCC, 0), |
1539 | 46f42f29 | blueswir1 | /* v9 */ fmovicc ("cs", CONDCS, 0), |
1540 | 46f42f29 | blueswir1 | /* v9 */ fmovcc ("e", CONDE, FCONDE, 0), |
1541 | 46f42f29 | blueswir1 | /* v9 */ fmovcc ("g", CONDG, FCONDG, 0), |
1542 | 46f42f29 | blueswir1 | /* v9 */ fmovcc ("ge", CONDGE, FCONDGE, 0), |
1543 | 46f42f29 | blueswir1 | /* v9 */ fmovicc ("geu", CONDGEU, F_ALIAS), |
1544 | 46f42f29 | blueswir1 | /* v9 */ fmovicc ("gu", CONDGU, 0), |
1545 | 46f42f29 | blueswir1 | /* v9 */ fmovcc ("l", CONDL, FCONDL, 0), |
1546 | 46f42f29 | blueswir1 | /* v9 */ fmovcc ("le", CONDLE, FCONDLE, 0), |
1547 | 46f42f29 | blueswir1 | /* v9 */ fmovicc ("leu", CONDLEU, 0), |
1548 | 46f42f29 | blueswir1 | /* v9 */ fmovfcc ("lg", FCONDLG, 0), |
1549 | 46f42f29 | blueswir1 | /* v9 */ fmovicc ("lu", CONDLU, F_ALIAS), |
1550 | 46f42f29 | blueswir1 | /* v9 */ fmovcc ("n", CONDN, FCONDN, 0), |
1551 | 46f42f29 | blueswir1 | /* v9 */ fmovcc ("ne", CONDNE, FCONDNE, 0), |
1552 | 46f42f29 | blueswir1 | /* v9 */ fmovicc ("neg", CONDNEG, 0), |
1553 | 46f42f29 | blueswir1 | /* v9 */ fmovcc ("nz", CONDNZ, FCONDNZ, F_ALIAS), |
1554 | 46f42f29 | blueswir1 | /* v9 */ fmovfcc ("o", FCONDO, 0), |
1555 | 46f42f29 | blueswir1 | /* v9 */ fmovicc ("pos", CONDPOS, 0), |
1556 | 46f42f29 | blueswir1 | /* v9 */ fmovfcc ("u", FCONDU, 0), |
1557 | 46f42f29 | blueswir1 | /* v9 */ fmovfcc ("ue", FCONDUE, 0), |
1558 | 46f42f29 | blueswir1 | /* v9 */ fmovfcc ("ug", FCONDUG, 0), |
1559 | 46f42f29 | blueswir1 | /* v9 */ fmovfcc ("uge", FCONDUGE, 0), |
1560 | 46f42f29 | blueswir1 | /* v9 */ fmovfcc ("ul", FCONDUL, 0), |
1561 | 46f42f29 | blueswir1 | /* v9 */ fmovfcc ("ule", FCONDULE, 0), |
1562 | 46f42f29 | blueswir1 | /* v9 */ fmovicc ("vc", CONDVC, 0), |
1563 | 46f42f29 | blueswir1 | /* v9 */ fmovicc ("vs", CONDVS, 0), |
1564 | 46f42f29 | blueswir1 | /* v9 */ fmovcc ("z", CONDZ, FCONDZ, F_ALIAS), |
1565 | 46f42f29 | blueswir1 | |
1566 | 46f42f29 | blueswir1 | #undef fmoviccx /* v9 */ |
1567 | 46f42f29 | blueswir1 | #undef fmovfccx /* v9 */ |
1568 | 46f42f29 | blueswir1 | #undef fmovccx /* v9 */ |
1569 | aa0aa4fa | bellard | #undef fmovicc /* v9 */ |
1570 | aa0aa4fa | bellard | #undef fmovfcc /* v9 */ |
1571 | aa0aa4fa | bellard | #undef fmovcc /* v9 */ |
1572 | aa0aa4fa | bellard | #undef FM_DF /* v9 */ |
1573 | aa0aa4fa | bellard | #undef FM_QF /* v9 */ |
1574 | aa0aa4fa | bellard | #undef FM_SF /* v9 */ |
1575 | aa0aa4fa | bellard | |
1576 | aa0aa4fa | bellard | /* Coprocessor branches. */
|
1577 | aa0aa4fa | bellard | #define CBR(opcode, mask, lose, flags, arch) \
|
1578 | 46f42f29 | blueswir1 | { opcode, (mask), ANNUL | (lose), "l", flags | F_DELAYED, arch }, \
|
1579 | 46f42f29 | blueswir1 | { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED, arch }
|
1580 | aa0aa4fa | bellard | |
1581 | aa0aa4fa | bellard | /* Floating point branches. */
|
1582 | aa0aa4fa | bellard | #define FBR(opcode, mask, lose, flags) \
|
1583 | 46f42f29 | blueswir1 | { opcode, (mask), ANNUL | (lose), "l", flags | F_DELAYED | F_FBR, v6 }, \
|
1584 | 46f42f29 | blueswir1 | { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED | F_FBR, v6 }
|
1585 | aa0aa4fa | bellard | |
1586 | aa0aa4fa | bellard | /* V9 extended floating point branches. */
|
1587 | aa0aa4fa | bellard | #define FBRX(opcode, mask, lose, flags) /* v9 */ \ |
1588 | aa0aa4fa | bellard | { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), "6,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1589 | aa0aa4fa | bellard | { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), ",T 6,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1590 | aa0aa4fa | bellard | { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a 6,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1591 | aa0aa4fa | bellard | { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a,T 6,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1592 | aa0aa4fa | bellard | { opcode, FBFCC(0)|(mask), ANNUL|BPRED|FBFCC(~0)|(lose), ",N 6,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1593 | aa0aa4fa | bellard | { opcode, FBFCC(0)|(mask)|ANNUL, BPRED|FBFCC(~0)|(lose), ",a,N 6,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1594 | aa0aa4fa | bellard | { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), "7,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1595 | aa0aa4fa | bellard | { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), ",T 7,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1596 | aa0aa4fa | bellard | { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a 7,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1597 | aa0aa4fa | bellard | { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a,T 7,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1598 | aa0aa4fa | bellard | { opcode, FBFCC(1)|(mask), ANNUL|BPRED|FBFCC(~1)|(lose), ",N 7,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1599 | aa0aa4fa | bellard | { opcode, FBFCC(1)|(mask)|ANNUL, BPRED|FBFCC(~1)|(lose), ",a,N 7,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1600 | aa0aa4fa | bellard | { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), "8,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1601 | aa0aa4fa | bellard | { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), ",T 8,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1602 | aa0aa4fa | bellard | { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a 8,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1603 | aa0aa4fa | bellard | { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a,T 8,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1604 | aa0aa4fa | bellard | { opcode, FBFCC(2)|(mask), ANNUL|BPRED|FBFCC(~2)|(lose), ",N 8,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1605 | aa0aa4fa | bellard | { opcode, FBFCC(2)|(mask)|ANNUL, BPRED|FBFCC(~2)|(lose), ",a,N 8,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1606 | aa0aa4fa | bellard | { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), "9,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1607 | aa0aa4fa | bellard | { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), ",T 9,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1608 | aa0aa4fa | bellard | { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a 9,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1609 | aa0aa4fa | bellard | { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a,T 9,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1610 | aa0aa4fa | bellard | { opcode, FBFCC(3)|(mask), ANNUL|BPRED|FBFCC(~3)|(lose), ",N 9,G", flags|F_DELAYED|F_FBR, v9 }, \ |
1611 | aa0aa4fa | bellard | { opcode, FBFCC(3)|(mask)|ANNUL, BPRED|FBFCC(~3)|(lose), ",a,N 9,G", flags|F_DELAYED|F_FBR, v9 } |
1612 | aa0aa4fa | bellard | |
1613 | aa0aa4fa | bellard | /* v9: We must put `FBRX' before `FBR', to ensure that we never match
|
1614 | aa0aa4fa | bellard | v9: something against an expression unless it is an expression. Otherwise,
|
1615 | aa0aa4fa | bellard | v9: we end up with undefined symbol tables entries, because they get added,
|
1616 | aa0aa4fa | bellard | v9: but are not deleted if the pattern fails to match. */
|
1617 | aa0aa4fa | bellard | |
1618 | aa0aa4fa | bellard | #define CONDFC(fop, cop, mask, flags) \
|
1619 | aa0aa4fa | bellard | FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \ |
1620 | aa0aa4fa | bellard | FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \ |
1621 | aa0aa4fa | bellard | CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6notlet) |
1622 | aa0aa4fa | bellard | |
1623 | aa0aa4fa | bellard | #define CONDFCL(fop, cop, mask, flags) \
|
1624 | aa0aa4fa | bellard | FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \ |
1625 | aa0aa4fa | bellard | FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \ |
1626 | aa0aa4fa | bellard | CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6) |
1627 | aa0aa4fa | bellard | |
1628 | aa0aa4fa | bellard | #define CONDF(fop, mask, flags) \
|
1629 | aa0aa4fa | bellard | FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \ |
1630 | aa0aa4fa | bellard | FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags) |
1631 | aa0aa4fa | bellard | |
1632 | aa0aa4fa | bellard | CONDFC ("fb", "cb", 0x8, F_UNBR), |
1633 | f930d07e | blueswir1 | CONDFCL ("fba", "cba", 0x8, F_UNBR|F_ALIAS), |
1634 | f930d07e | blueswir1 | CONDFC ("fbe", "cb0", 0x9, F_CONDBR), |
1635 | aa0aa4fa | bellard | CONDF ("fbz", 0x9, F_CONDBR|F_ALIAS), |
1636 | f930d07e | blueswir1 | CONDFC ("fbg", "cb2", 0x6, F_CONDBR), |
1637 | aa0aa4fa | bellard | CONDFC ("fbge", "cb02", 0xb, F_CONDBR), |
1638 | f930d07e | blueswir1 | CONDFC ("fbl", "cb1", 0x4, F_CONDBR), |
1639 | aa0aa4fa | bellard | CONDFC ("fble", "cb01", 0xd, F_CONDBR), |
1640 | aa0aa4fa | bellard | CONDFC ("fblg", "cb12", 0x2, F_CONDBR), |
1641 | f930d07e | blueswir1 | CONDFCL ("fbn", "cbn", 0x0, F_UNBR), |
1642 | aa0aa4fa | bellard | CONDFC ("fbne", "cb123", 0x1, F_CONDBR), |
1643 | aa0aa4fa | bellard | CONDF ("fbnz", 0x1, F_CONDBR|F_ALIAS), |
1644 | f930d07e | blueswir1 | CONDFC ("fbo", "cb012", 0xf, F_CONDBR), |
1645 | f930d07e | blueswir1 | CONDFC ("fbu", "cb3", 0x7, F_CONDBR), |
1646 | aa0aa4fa | bellard | CONDFC ("fbue", "cb03", 0xa, F_CONDBR), |
1647 | aa0aa4fa | bellard | CONDFC ("fbug", "cb23", 0x5, F_CONDBR), |
1648 | aa0aa4fa | bellard | CONDFC ("fbuge", "cb023", 0xc, F_CONDBR), |
1649 | aa0aa4fa | bellard | CONDFC ("fbul", "cb13", 0x3, F_CONDBR), |
1650 | aa0aa4fa | bellard | CONDFC ("fbule", "cb013", 0xe, F_CONDBR), |
1651 | aa0aa4fa | bellard | |
1652 | aa0aa4fa | bellard | #undef CONDFC
|
1653 | aa0aa4fa | bellard | #undef CONDFCL
|
1654 | aa0aa4fa | bellard | #undef CONDF
|
1655 | aa0aa4fa | bellard | #undef CBR
|
1656 | aa0aa4fa | bellard | #undef FBR
|
1657 | f930d07e | blueswir1 | #undef FBRX /* v9 */ |
1658 | aa0aa4fa | bellard | |
1659 | f930d07e | blueswir1 | { "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%g0 */ |
1660 | f930d07e | blueswir1 | { "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%g0 */ |
1661 | f930d07e | blueswir1 | { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+i,%g0 */ |
1662 | f930d07e | blueswir1 | { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, v6 }, /* jmpl i+rs1,%g0 */ |
1663 | f930d07e | blueswir1 | { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* jmpl %g0+i,%g0 */ |
1664 | f930d07e | blueswir1 | { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+0,%g0 */ |
1665 | aa0aa4fa | bellard | |
1666 | f930d07e | blueswir1 | { "nop", F2(0, 4), 0xfeffffff, "", 0, v6 }, /* sethi 0, %g0 */ |
1667 | aa0aa4fa | bellard | |
1668 | f930d07e | blueswir1 | { "set", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v6 }, |
1669 | f930d07e | blueswir1 | { "setuw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v9 }, |
1670 | f930d07e | blueswir1 | { "setsw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v9 }, |
1671 | f930d07e | blueswir1 | { "setx", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,1,d", F_ALIAS, v9 }, |
1672 | aa0aa4fa | bellard | |
1673 | f930d07e | blueswir1 | { "sethi", F2(0x0, 0x4), F2(~0x0, ~0x4), "h,d", 0, v6 }, |
1674 | aa0aa4fa | bellard | |
1675 | f930d07e | blueswir1 | { "taddcc", F3(2, 0x20, 0), F3(~2, ~0x20, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1676 | f930d07e | blueswir1 | { "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "1,i,d", 0, v6 }, |
1677 | f930d07e | blueswir1 | { "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "i,1,d", 0, v6 }, |
1678 | f930d07e | blueswir1 | { "taddcctv", F3(2, 0x22, 0), F3(~2, ~0x22, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1679 | f930d07e | blueswir1 | { "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "1,i,d", 0, v6 }, |
1680 | f930d07e | blueswir1 | { "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "i,1,d", 0, v6 }, |
1681 | aa0aa4fa | bellard | |
1682 | f930d07e | blueswir1 | { "tsubcc", F3(2, 0x21, 0), F3(~2, ~0x21, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1683 | f930d07e | blueswir1 | { "tsubcc", F3(2, 0x21, 1), F3(~2, ~0x21, ~1), "1,i,d", 0, v6 }, |
1684 | f930d07e | blueswir1 | { "tsubcctv", F3(2, 0x23, 0), F3(~2, ~0x23, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1685 | f930d07e | blueswir1 | { "tsubcctv", F3(2, 0x23, 1), F3(~2, ~0x23, ~1), "1,i,d", 0, v6 }, |
1686 | aa0aa4fa | bellard | |
1687 | f930d07e | blueswir1 | { "unimp", F2(0x0, 0x0), 0xffc00000, "n", 0, v6notv9 }, |
1688 | f930d07e | blueswir1 | { "illtrap", F2(0, 0), F2(~0, ~0)|RD_G0, "n", 0, v9 }, |
1689 | aa0aa4fa | bellard | |
1690 | aa0aa4fa | bellard | /* This *is* a commutative instruction. */
|
1691 | f930d07e | blueswir1 | { "xnor", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1692 | f930d07e | blueswir1 | { "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "1,i,d", 0, v6 }, |
1693 | f930d07e | blueswir1 | { "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "i,1,d", 0, v6 }, |
1694 | aa0aa4fa | bellard | /* This *is* a commutative instruction. */
|
1695 | f930d07e | blueswir1 | { "xnorcc", F3(2, 0x17, 0), F3(~2, ~0x17, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1696 | f930d07e | blueswir1 | { "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "1,i,d", 0, v6 }, |
1697 | f930d07e | blueswir1 | { "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "i,1,d", 0, v6 }, |
1698 | f930d07e | blueswir1 | { "xor", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1699 | f930d07e | blueswir1 | { "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "1,i,d", 0, v6 }, |
1700 | f930d07e | blueswir1 | { "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,1,d", 0, v6 }, |
1701 | f930d07e | blueswir1 | { "xorcc", F3(2, 0x13, 0), F3(~2, ~0x13, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
1702 | f930d07e | blueswir1 | { "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "1,i,d", 0, v6 }, |
1703 | f930d07e | blueswir1 | { "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "i,1,d", 0, v6 }, |
1704 | f930d07e | blueswir1 | |
1705 | f930d07e | blueswir1 | { "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,d", F_ALIAS, v6 }, /* xnor rs1,%0,rd */ |
1706 | f930d07e | blueswir1 | { "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "r", F_ALIAS, v6 }, /* xnor rd,%0,rd */ |
1707 | f930d07e | blueswir1 | |
1708 | f930d07e | blueswir1 | { "btog", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* xor rd,rs2,rd */ |
1709 | f930d07e | blueswir1 | { "btog", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,r", F_ALIAS, v6 }, /* xor rd,i,rd */ |
1710 | aa0aa4fa | bellard | |
1711 | aa0aa4fa | bellard | /* FPop1 and FPop2 are not instructions. Don't accept them. */
|
1712 | aa0aa4fa | bellard | |
1713 | f930d07e | blueswir1 | { "fdtoi", F3F(2, 0x34, 0x0d2), F3F(~2, ~0x34, ~0x0d2)|RS1_G0, "B,g", F_FLOAT, v6 }, |
1714 | f930d07e | blueswir1 | { "fstoi", F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0, "f,g", F_FLOAT, v6 }, |
1715 | f930d07e | blueswir1 | { "fqtoi", F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g", F_FLOAT, v8 }, |
1716 | f930d07e | blueswir1 | |
1717 | 46f42f29 | blueswir1 | { "fdtox", F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,H", F_FLOAT, v9 }, |
1718 | 46f42f29 | blueswir1 | { "fstox", F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,H", F_FLOAT, v9 }, |
1719 | 46f42f29 | blueswir1 | { "fqtox", F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,H", F_FLOAT, v9 }, |
1720 | f930d07e | blueswir1 | |
1721 | f930d07e | blueswir1 | { "fitod", F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0, "f,H", F_FLOAT, v6 }, |
1722 | f930d07e | blueswir1 | { "fitos", F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0, "f,g", F_FLOAT, v6 }, |
1723 | f930d07e | blueswir1 | { "fitoq", F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,J", F_FLOAT, v8 }, |
1724 | f930d07e | blueswir1 | |
1725 | 46f42f29 | blueswir1 | { "fxtod", F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "B,H", F_FLOAT, v9 }, |
1726 | 46f42f29 | blueswir1 | { "fxtos", F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "B,g", F_FLOAT, v9 }, |
1727 | 46f42f29 | blueswir1 | { "fxtoq", F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0, "B,J", F_FLOAT, v9 }, |
1728 | f930d07e | blueswir1 | |
1729 | f930d07e | blueswir1 | { "fdtoq", F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0, "B,J", F_FLOAT, v8 }, |
1730 | f930d07e | blueswir1 | { "fdtos", F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0, "B,g", F_FLOAT, v6 }, |
1731 | f930d07e | blueswir1 | { "fqtod", F3F(2, 0x34, 0x0cb), F3F(~2, ~0x34, ~0x0cb)|RS1_G0, "R,H", F_FLOAT, v8 }, |
1732 | f930d07e | blueswir1 | { "fqtos", F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0, "R,g", F_FLOAT, v8 }, |
1733 | f930d07e | blueswir1 | { "fstod", F3F(2, 0x34, 0x0c9), F3F(~2, ~0x34, ~0x0c9)|RS1_G0, "f,H", F_FLOAT, v6 }, |
1734 | f930d07e | blueswir1 | { "fstoq", F3F(2, 0x34, 0x0cd), F3F(~2, ~0x34, ~0x0cd)|RS1_G0, "f,J", F_FLOAT, v8 }, |
1735 | f930d07e | blueswir1 | |
1736 | f930d07e | blueswir1 | { "fdivd", F3F(2, 0x34, 0x04e), F3F(~2, ~0x34, ~0x04e), "v,B,H", F_FLOAT, v6 }, |
1737 | f930d07e | blueswir1 | { "fdivq", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT, v8 }, |
1738 | f930d07e | blueswir1 | { "fdivx", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT|F_ALIAS, v8 }, |
1739 | f930d07e | blueswir1 | { "fdivs", F3F(2, 0x34, 0x04d), F3F(~2, ~0x34, ~0x04d), "e,f,g", F_FLOAT, v6 }, |
1740 | f930d07e | blueswir1 | { "fmuld", F3F(2, 0x34, 0x04a), F3F(~2, ~0x34, ~0x04a), "v,B,H", F_FLOAT, v6 }, |
1741 | f930d07e | blueswir1 | { "fmulq", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT, v8 }, |
1742 | f930d07e | blueswir1 | { "fmulx", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT|F_ALIAS, v8 }, |
1743 | f930d07e | blueswir1 | { "fmuls", F3F(2, 0x34, 0x049), F3F(~2, ~0x34, ~0x049), "e,f,g", F_FLOAT, v6 }, |
1744 | f930d07e | blueswir1 | |
1745 | f930d07e | blueswir1 | { "fdmulq", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT, v8 }, |
1746 | f930d07e | blueswir1 | { "fdmulx", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT|F_ALIAS, v8 }, |
1747 | f930d07e | blueswir1 | { "fsmuld", F3F(2, 0x34, 0x069), F3F(~2, ~0x34, ~0x069), "e,f,H", F_FLOAT, v8 }, |
1748 | f930d07e | blueswir1 | |
1749 | f930d07e | blueswir1 | { "fsqrtd", F3F(2, 0x34, 0x02a), F3F(~2, ~0x34, ~0x02a)|RS1_G0, "B,H", F_FLOAT, v7 }, |
1750 | f930d07e | blueswir1 | { "fsqrtq", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT, v8 }, |
1751 | f930d07e | blueswir1 | { "fsqrtx", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v8 }, |
1752 | f930d07e | blueswir1 | { "fsqrts", F3F(2, 0x34, 0x029), F3F(~2, ~0x34, ~0x029)|RS1_G0, "f,g", F_FLOAT, v7 }, |
1753 | f930d07e | blueswir1 | |
1754 | f930d07e | blueswir1 | { "fabsd", F3F(2, 0x34, 0x00a), F3F(~2, ~0x34, ~0x00a)|RS1_G0, "B,H", F_FLOAT, v9 }, |
1755 | f930d07e | blueswir1 | { "fabsq", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT, v9 }, |
1756 | f930d07e | blueswir1 | { "fabsx", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 }, |
1757 | f930d07e | blueswir1 | { "fabss", F3F(2, 0x34, 0x009), F3F(~2, ~0x34, ~0x009)|RS1_G0, "f,g", F_FLOAT, v6 }, |
1758 | f930d07e | blueswir1 | { "fmovd", F3F(2, 0x34, 0x002), F3F(~2, ~0x34, ~0x002)|RS1_G0, "B,H", F_FLOAT, v9 }, |
1759 | f930d07e | blueswir1 | { "fmovq", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT, v9 }, |
1760 | f930d07e | blueswir1 | { "fmovx", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 }, |
1761 | f930d07e | blueswir1 | { "fmovs", F3F(2, 0x34, 0x001), F3F(~2, ~0x34, ~0x001)|RS1_G0, "f,g", F_FLOAT, v6 }, |
1762 | f930d07e | blueswir1 | { "fnegd", F3F(2, 0x34, 0x006), F3F(~2, ~0x34, ~0x006)|RS1_G0, "B,H", F_FLOAT, v9 }, |
1763 | f930d07e | blueswir1 | { "fnegq", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT, v9 }, |
1764 | f930d07e | blueswir1 | { "fnegx", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 }, |
1765 | f930d07e | blueswir1 | { "fnegs", F3F(2, 0x34, 0x005), F3F(~2, ~0x34, ~0x005)|RS1_G0, "f,g", F_FLOAT, v6 }, |
1766 | f930d07e | blueswir1 | |
1767 | f930d07e | blueswir1 | { "faddd", F3F(2, 0x34, 0x042), F3F(~2, ~0x34, ~0x042), "v,B,H", F_FLOAT, v6 }, |
1768 | f930d07e | blueswir1 | { "faddq", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT, v8 }, |
1769 | f930d07e | blueswir1 | { "faddx", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT|F_ALIAS, v8 }, |
1770 | f930d07e | blueswir1 | { "fadds", F3F(2, 0x34, 0x041), F3F(~2, ~0x34, ~0x041), "e,f,g", F_FLOAT, v6 }, |
1771 | f930d07e | blueswir1 | { "fsubd", F3F(2, 0x34, 0x046), F3F(~2, ~0x34, ~0x046), "v,B,H", F_FLOAT, v6 }, |
1772 | f930d07e | blueswir1 | { "fsubq", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT, v8 }, |
1773 | f930d07e | blueswir1 | { "fsubx", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT|F_ALIAS, v8 }, |
1774 | f930d07e | blueswir1 | { "fsubs", F3F(2, 0x34, 0x045), F3F(~2, ~0x34, ~0x045), "e,f,g", F_FLOAT, v6 }, |
1775 | f930d07e | blueswir1 | |
1776 | f930d07e | blueswir1 | #define CMPFCC(x) (((x)&0x3)<<25) |
1777 | f930d07e | blueswir1 | |
1778 | f930d07e | blueswir1 | { "fcmpd", F3F(2, 0x35, 0x052), F3F(~2, ~0x35, ~0x052)|RD_G0, "v,B", F_FLOAT, v6 }, |
1779 | f930d07e | blueswir1 | { "fcmpd", CMPFCC(0)|F3F(2, 0x35, 0x052), CMPFCC(~0)|F3F(~2, ~0x35, ~0x052), "6,v,B", F_FLOAT, v9 }, |
1780 | f930d07e | blueswir1 | { "fcmpd", CMPFCC(1)|F3F(2, 0x35, 0x052), CMPFCC(~1)|F3F(~2, ~0x35, ~0x052), "7,v,B", F_FLOAT, v9 }, |
1781 | f930d07e | blueswir1 | { "fcmpd", CMPFCC(2)|F3F(2, 0x35, 0x052), CMPFCC(~2)|F3F(~2, ~0x35, ~0x052), "8,v,B", F_FLOAT, v9 }, |
1782 | f930d07e | blueswir1 | { "fcmpd", CMPFCC(3)|F3F(2, 0x35, 0x052), CMPFCC(~3)|F3F(~2, ~0x35, ~0x052), "9,v,B", F_FLOAT, v9 }, |
1783 | f930d07e | blueswir1 | { "fcmped", F3F(2, 0x35, 0x056), F3F(~2, ~0x35, ~0x056)|RD_G0, "v,B", F_FLOAT, v6 }, |
1784 | f930d07e | blueswir1 | { "fcmped", CMPFCC(0)|F3F(2, 0x35, 0x056), CMPFCC(~0)|F3F(~2, ~0x35, ~0x056), "6,v,B", F_FLOAT, v9 }, |
1785 | f930d07e | blueswir1 | { "fcmped", CMPFCC(1)|F3F(2, 0x35, 0x056), CMPFCC(~1)|F3F(~2, ~0x35, ~0x056), "7,v,B", F_FLOAT, v9 }, |
1786 | f930d07e | blueswir1 | { "fcmped", CMPFCC(2)|F3F(2, 0x35, 0x056), CMPFCC(~2)|F3F(~2, ~0x35, ~0x056), "8,v,B", F_FLOAT, v9 }, |
1787 | f930d07e | blueswir1 | { "fcmped", CMPFCC(3)|F3F(2, 0x35, 0x056), CMPFCC(~3)|F3F(~2, ~0x35, ~0x056), "9,v,B", F_FLOAT, v9 }, |
1788 | f930d07e | blueswir1 | { "fcmpq", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT, v8 }, |
1789 | f930d07e | blueswir1 | { "fcmpq", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT, v9 }, |
1790 | f930d07e | blueswir1 | { "fcmpq", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT, v9 }, |
1791 | f930d07e | blueswir1 | { "fcmpq", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT, v9 }, |
1792 | f930d07e | blueswir1 | { "fcmpq", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT, v9 }, |
1793 | f930d07e | blueswir1 | { "fcmpeq", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT, v8 }, |
1794 | f930d07e | blueswir1 | { "fcmpeq", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT, v9 }, |
1795 | f930d07e | blueswir1 | { "fcmpeq", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT, v9 }, |
1796 | f930d07e | blueswir1 | { "fcmpeq", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT, v9 }, |
1797 | f930d07e | blueswir1 | { "fcmpeq", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT, v9 }, |
1798 | f930d07e | blueswir1 | { "fcmpx", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT|F_ALIAS, v8 }, |
1799 | f930d07e | blueswir1 | { "fcmpx", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT|F_ALIAS, v9 }, |
1800 | f930d07e | blueswir1 | { "fcmpx", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT|F_ALIAS, v9 }, |
1801 | f930d07e | blueswir1 | { "fcmpx", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT|F_ALIAS, v9 }, |
1802 | f930d07e | blueswir1 | { "fcmpx", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT|F_ALIAS, v9 }, |
1803 | f930d07e | blueswir1 | { "fcmpex", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT|F_ALIAS, v8 }, |
1804 | f930d07e | blueswir1 | { "fcmpex", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT|F_ALIAS, v9 }, |
1805 | f930d07e | blueswir1 | { "fcmpex", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT|F_ALIAS, v9 }, |
1806 | f930d07e | blueswir1 | { "fcmpex", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT|F_ALIAS, v9 }, |
1807 | f930d07e | blueswir1 | { "fcmpex", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT|F_ALIAS, v9 }, |
1808 | f930d07e | blueswir1 | { "fcmps", F3F(2, 0x35, 0x051), F3F(~2, ~0x35, ~0x051)|RD_G0, "e,f", F_FLOAT, v6 }, |
1809 | f930d07e | blueswir1 | { "fcmps", CMPFCC(0)|F3F(2, 0x35, 0x051), CMPFCC(~0)|F3F(~2, ~0x35, ~0x051), "6,e,f", F_FLOAT, v9 }, |
1810 | f930d07e | blueswir1 | { "fcmps", CMPFCC(1)|F3F(2, 0x35, 0x051), CMPFCC(~1)|F3F(~2, ~0x35, ~0x051), "7,e,f", F_FLOAT, v9 }, |
1811 | f930d07e | blueswir1 | { "fcmps", CMPFCC(2)|F3F(2, 0x35, 0x051), CMPFCC(~2)|F3F(~2, ~0x35, ~0x051), "8,e,f", F_FLOAT, v9 }, |
1812 | f930d07e | blueswir1 | { "fcmps", CMPFCC(3)|F3F(2, 0x35, 0x051), CMPFCC(~3)|F3F(~2, ~0x35, ~0x051), "9,e,f", F_FLOAT, v9 }, |
1813 | f930d07e | blueswir1 | { "fcmpes", F3F(2, 0x35, 0x055), F3F(~2, ~0x35, ~0x055)|RD_G0, "e,f", F_FLOAT, v6 }, |
1814 | f930d07e | blueswir1 | { "fcmpes", CMPFCC(0)|F3F(2, 0x35, 0x055), CMPFCC(~0)|F3F(~2, ~0x35, ~0x055), "6,e,f", F_FLOAT, v9 }, |
1815 | f930d07e | blueswir1 | { "fcmpes", CMPFCC(1)|F3F(2, 0x35, 0x055), CMPFCC(~1)|F3F(~2, ~0x35, ~0x055), "7,e,f", F_FLOAT, v9 }, |
1816 | f930d07e | blueswir1 | { "fcmpes", CMPFCC(2)|F3F(2, 0x35, 0x055), CMPFCC(~2)|F3F(~2, ~0x35, ~0x055), "8,e,f", F_FLOAT, v9 }, |
1817 | f930d07e | blueswir1 | { "fcmpes", CMPFCC(3)|F3F(2, 0x35, 0x055), CMPFCC(~3)|F3F(~2, ~0x35, ~0x055), "9,e,f", F_FLOAT, v9 }, |
1818 | aa0aa4fa | bellard | |
1819 | aa0aa4fa | bellard | /* These Extended FPop (FIFO) instructions are new in the Fujitsu
|
1820 | aa0aa4fa | bellard | MB86934, replacing the CPop instructions from v6 and later
|
1821 | aa0aa4fa | bellard | processors. */
|
1822 | aa0aa4fa | bellard | |
1823 | aa0aa4fa | bellard | #define EFPOP1_2(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op)|RS1_G0, args, 0, sparclite } |
1824 | aa0aa4fa | bellard | #define EFPOP1_3(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op), args, 0, sparclite } |
1825 | aa0aa4fa | bellard | #define EFPOP2_2(name, op, args) { name, F3F(2, 0x37, op), F3F(~2, ~0x37, ~op)|RD_G0, args, 0, sparclite } |
1826 | aa0aa4fa | bellard | |
1827 | f930d07e | blueswir1 | EFPOP1_2 ("efitod", 0x0c8, "f,H"), |
1828 | f930d07e | blueswir1 | EFPOP1_2 ("efitos", 0x0c4, "f,g"), |
1829 | f930d07e | blueswir1 | EFPOP1_2 ("efdtoi", 0x0d2, "B,g"), |
1830 | f930d07e | blueswir1 | EFPOP1_2 ("efstoi", 0x0d1, "f,g"), |
1831 | f930d07e | blueswir1 | EFPOP1_2 ("efstod", 0x0c9, "f,H"), |
1832 | f930d07e | blueswir1 | EFPOP1_2 ("efdtos", 0x0c6, "B,g"), |
1833 | f930d07e | blueswir1 | EFPOP1_2 ("efmovs", 0x001, "f,g"), |
1834 | f930d07e | blueswir1 | EFPOP1_2 ("efnegs", 0x005, "f,g"), |
1835 | f930d07e | blueswir1 | EFPOP1_2 ("efabss", 0x009, "f,g"), |
1836 | f930d07e | blueswir1 | EFPOP1_2 ("efsqrtd", 0x02a, "B,H"), |
1837 | f930d07e | blueswir1 | EFPOP1_2 ("efsqrts", 0x029, "f,g"), |
1838 | f930d07e | blueswir1 | EFPOP1_3 ("efaddd", 0x042, "v,B,H"), |
1839 | f930d07e | blueswir1 | EFPOP1_3 ("efadds", 0x041, "e,f,g"), |
1840 | f930d07e | blueswir1 | EFPOP1_3 ("efsubd", 0x046, "v,B,H"), |
1841 | f930d07e | blueswir1 | EFPOP1_3 ("efsubs", 0x045, "e,f,g"), |
1842 | f930d07e | blueswir1 | EFPOP1_3 ("efdivd", 0x04e, "v,B,H"), |
1843 | f930d07e | blueswir1 | EFPOP1_3 ("efdivs", 0x04d, "e,f,g"), |
1844 | f930d07e | blueswir1 | EFPOP1_3 ("efmuld", 0x04a, "v,B,H"), |
1845 | f930d07e | blueswir1 | EFPOP1_3 ("efmuls", 0x049, "e,f,g"), |
1846 | f930d07e | blueswir1 | EFPOP1_3 ("efsmuld", 0x069, "e,f,H"), |
1847 | f930d07e | blueswir1 | EFPOP2_2 ("efcmpd", 0x052, "v,B"), |
1848 | f930d07e | blueswir1 | EFPOP2_2 ("efcmped", 0x056, "v,B"), |
1849 | f930d07e | blueswir1 | EFPOP2_2 ("efcmps", 0x051, "e,f"), |
1850 | f930d07e | blueswir1 | EFPOP2_2 ("efcmpes", 0x055, "e,f"), |
1851 | aa0aa4fa | bellard | |
1852 | aa0aa4fa | bellard | #undef EFPOP1_2
|
1853 | aa0aa4fa | bellard | #undef EFPOP1_3
|
1854 | aa0aa4fa | bellard | #undef EFPOP2_2
|
1855 | aa0aa4fa | bellard | |
1856 | aa0aa4fa | bellard | /* These are marked F_ALIAS, so that they won't conflict with sparclite insns
|
1857 | aa0aa4fa | bellard | present. Otherwise, the F_ALIAS flag is ignored. */
|
1858 | f930d07e | blueswir1 | { "cpop1", F3(2, 0x36, 0), F3(~2, ~0x36, ~1), "[1+2],d", F_ALIAS, v6notv9 }, |
1859 | f930d07e | blueswir1 | { "cpop2", F3(2, 0x37, 0), F3(~2, ~0x37, ~1), "[1+2],d", F_ALIAS, v6notv9 }, |
1860 | aa0aa4fa | bellard | |
1861 | aa0aa4fa | bellard | /* sparclet specific insns */
|
1862 | aa0aa4fa | bellard | |
1863 | aa0aa4fa | bellard | COMMUTEOP ("umac", 0x3e, sparclet), |
1864 | aa0aa4fa | bellard | COMMUTEOP ("smac", 0x3f, sparclet), |
1865 | aa0aa4fa | bellard | COMMUTEOP ("umacd", 0x2e, sparclet), |
1866 | aa0aa4fa | bellard | COMMUTEOP ("smacd", 0x2f, sparclet), |
1867 | aa0aa4fa | bellard | COMMUTEOP ("umuld", 0x09, sparclet), |
1868 | aa0aa4fa | bellard | COMMUTEOP ("smuld", 0x0d, sparclet), |
1869 | aa0aa4fa | bellard | |
1870 | f930d07e | blueswir1 | { "shuffle", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, sparclet }, |
1871 | f930d07e | blueswir1 | { "shuffle", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, sparclet }, |
1872 | aa0aa4fa | bellard | |
1873 | aa0aa4fa | bellard | /* The manual isn't completely accurate on these insns. The `rs2' field is
|
1874 | aa0aa4fa | bellard | treated as being 6 bits to account for 6 bit immediates to cpush. It is
|
1875 | aa0aa4fa | bellard | assumed that it is intended that bit 5 is 0 when rs2 contains a reg. */
|
1876 | aa0aa4fa | bellard | #define BIT5 (1<<5) |
1877 | f930d07e | blueswir1 | { "crdcxt", F3(2, 0x36, 0)|SLCPOP(4), F3(~2, ~0x36, ~0)|SLCPOP(~4)|BIT5|RS2(~0), "U,d", 0, sparclet }, |
1878 | f930d07e | blueswir1 | { "cwrcxt", F3(2, 0x36, 0)|SLCPOP(3), F3(~2, ~0x36, ~0)|SLCPOP(~3)|BIT5|RS2(~0), "1,u", 0, sparclet }, |
1879 | f930d07e | blueswir1 | { "cpush", F3(2, 0x36, 0)|SLCPOP(0), F3(~2, ~0x36, ~0)|SLCPOP(~0)|BIT5|RD(~0), "1,2", 0, sparclet }, |
1880 | f930d07e | blueswir1 | { "cpush", F3(2, 0x36, 1)|SLCPOP(0), F3(~2, ~0x36, ~1)|SLCPOP(~0)|RD(~0), "1,Y", 0, sparclet }, |
1881 | f930d07e | blueswir1 | { "cpusha", F3(2, 0x36, 0)|SLCPOP(1), F3(~2, ~0x36, ~0)|SLCPOP(~1)|BIT5|RD(~0), "1,2", 0, sparclet }, |
1882 | f930d07e | blueswir1 | { "cpusha", F3(2, 0x36, 1)|SLCPOP(1), F3(~2, ~0x36, ~1)|SLCPOP(~1)|RD(~0), "1,Y", 0, sparclet }, |
1883 | f930d07e | blueswir1 | { "cpull", F3(2, 0x36, 0)|SLCPOP(2), F3(~2, ~0x36, ~0)|SLCPOP(~2)|BIT5|RS1(~0)|RS2(~0), "d", 0, sparclet }, |
1884 | aa0aa4fa | bellard | #undef BIT5
|
1885 | aa0aa4fa | bellard | |
1886 | aa0aa4fa | bellard | /* sparclet coprocessor branch insns */
|
1887 | aa0aa4fa | bellard | #define SLCBCC2(opcode, mask, lose) \
|
1888 | aa0aa4fa | bellard | { opcode, (mask), ANNUL|(lose), "l", F_DELAYED|F_CONDBR, sparclet }, \
|
1889 | aa0aa4fa | bellard | { opcode, (mask)|ANNUL, (lose), ",a l", F_DELAYED|F_CONDBR, sparclet }
|
1890 | aa0aa4fa | bellard | #define SLCBCC(opcode, mask) \
|
1891 | aa0aa4fa | bellard | SLCBCC2(opcode, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask))) |
1892 | aa0aa4fa | bellard | |
1893 | aa0aa4fa | bellard | /* cbn,cba can't be defined here because they're defined elsewhere and GAS
|
1894 | aa0aa4fa | bellard | requires all mnemonics of the same name to be consecutive. */
|
1895 | aa0aa4fa | bellard | /*SLCBCC("cbn", 0), - already defined */
|
1896 | aa0aa4fa | bellard | SLCBCC("cbe", 1), |
1897 | aa0aa4fa | bellard | SLCBCC("cbf", 2), |
1898 | aa0aa4fa | bellard | SLCBCC("cbef", 3), |
1899 | aa0aa4fa | bellard | SLCBCC("cbr", 4), |
1900 | aa0aa4fa | bellard | SLCBCC("cber", 5), |
1901 | aa0aa4fa | bellard | SLCBCC("cbfr", 6), |
1902 | aa0aa4fa | bellard | SLCBCC("cbefr", 7), |
1903 | aa0aa4fa | bellard | /*SLCBCC("cba", 8), - already defined */
|
1904 | aa0aa4fa | bellard | SLCBCC("cbne", 9), |
1905 | aa0aa4fa | bellard | SLCBCC("cbnf", 10), |
1906 | aa0aa4fa | bellard | SLCBCC("cbnef", 11), |
1907 | aa0aa4fa | bellard | SLCBCC("cbnr", 12), |
1908 | aa0aa4fa | bellard | SLCBCC("cbner", 13), |
1909 | aa0aa4fa | bellard | SLCBCC("cbnfr", 14), |
1910 | aa0aa4fa | bellard | SLCBCC("cbnefr", 15), |
1911 | aa0aa4fa | bellard | |
1912 | aa0aa4fa | bellard | #undef SLCBCC2
|
1913 | aa0aa4fa | bellard | #undef SLCBCC
|
1914 | aa0aa4fa | bellard | |
1915 | f930d07e | blueswir1 | { "casa", F3(3, 0x3c, 0), F3(~3, ~0x3c, ~0), "[1]A,2,d", 0, v9 }, |
1916 | f930d07e | blueswir1 | { "casa", F3(3, 0x3c, 1), F3(~3, ~0x3c, ~1), "[1]o,2,d", 0, v9 }, |
1917 | f930d07e | blueswir1 | { "casxa", F3(3, 0x3e, 0), F3(~3, ~0x3e, ~0), "[1]A,2,d", 0, v9 }, |
1918 | f930d07e | blueswir1 | { "casxa", F3(3, 0x3e, 1), F3(~3, ~0x3e, ~1), "[1]o,2,d", 0, v9 }, |
1919 | aa0aa4fa | bellard | |
1920 | aa0aa4fa | bellard | /* v9 synthetic insns */
|
1921 | f930d07e | blueswir1 | { "iprefetch", F2(0, 1)|(2<<20)|BPRED, F2(~0, ~1)|(1<<20)|ANNUL|COND(~0), "G", 0, v9 }, /* bn,a,pt %xcc,label */ |
1922 | f930d07e | blueswir1 | { "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* sra rs1,%g0,rd */ |
1923 | f930d07e | blueswir1 | { "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* sra rd,%g0,rd */ |
1924 | f930d07e | blueswir1 | { "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* srl rs1,%g0,rd */ |
1925 | f930d07e | blueswir1 | { "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* srl rd,%g0,rd */ |
1926 | f930d07e | blueswir1 | { "cas", F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P,rs2,rd */ |
1927 | f930d07e | blueswir1 | { "casl", F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P_L,rs2,rd */ |
1928 | f930d07e | blueswir1 | { "casx", F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P,rs2,rd */ |
1929 | f930d07e | blueswir1 | { "casxl", F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P_L,rs2,rd */ |
1930 | aa0aa4fa | bellard | |
1931 | aa0aa4fa | bellard | /* Ultrasparc extensions */
|
1932 | f930d07e | blueswir1 | { "shutdown", F3F(2, 0x36, 0x080), F3F(~2, ~0x36, ~0x080)|RD_G0|RS1_G0|RS2_G0, "", 0, v9a }, |
1933 | aa0aa4fa | bellard | |
1934 | aa0aa4fa | bellard | /* FIXME: Do we want to mark these as F_FLOAT, or something similar? */
|
1935 | f930d07e | blueswir1 | { "fpadd16", F3F(2, 0x36, 0x050), F3F(~2, ~0x36, ~0x050), "v,B,H", 0, v9a }, |
1936 | f930d07e | blueswir1 | { "fpadd16s", F3F(2, 0x36, 0x051), F3F(~2, ~0x36, ~0x051), "e,f,g", 0, v9a }, |
1937 | f930d07e | blueswir1 | { "fpadd32", F3F(2, 0x36, 0x052), F3F(~2, ~0x36, ~0x052), "v,B,H", 0, v9a }, |
1938 | f930d07e | blueswir1 | { "fpadd32s", F3F(2, 0x36, 0x053), F3F(~2, ~0x36, ~0x053), "e,f,g", 0, v9a }, |
1939 | f930d07e | blueswir1 | { "fpsub16", F3F(2, 0x36, 0x054), F3F(~2, ~0x36, ~0x054), "v,B,H", 0, v9a }, |
1940 | f930d07e | blueswir1 | { "fpsub16s", F3F(2, 0x36, 0x055), F3F(~2, ~0x36, ~0x055), "e,f,g", 0, v9a }, |
1941 | f930d07e | blueswir1 | { "fpsub32", F3F(2, 0x36, 0x056), F3F(~2, ~0x36, ~0x056), "v,B,H", 0, v9a }, |
1942 | f930d07e | blueswir1 | { "fpsub32s", F3F(2, 0x36, 0x057), F3F(~2, ~0x36, ~0x057), "e,f,g", 0, v9a }, |
1943 | f930d07e | blueswir1 | |
1944 | f930d07e | blueswir1 | { "fpack32", F3F(2, 0x36, 0x03a), F3F(~2, ~0x36, ~0x03a), "v,B,H", 0, v9a }, |
1945 | f930d07e | blueswir1 | { "fpack16", F3F(2, 0x36, 0x03b), F3F(~2, ~0x36, ~0x03b)|RS1_G0, "B,g", 0, v9a }, |
1946 | f930d07e | blueswir1 | { "fpackfix", F3F(2, 0x36, 0x03d), F3F(~2, ~0x36, ~0x03d)|RS1_G0, "B,g", 0, v9a }, |
1947 | f930d07e | blueswir1 | { "fexpand", F3F(2, 0x36, 0x04d), F3F(~2, ~0x36, ~0x04d)|RS1_G0, "f,H", 0, v9a }, |
1948 | f930d07e | blueswir1 | { "fpmerge", F3F(2, 0x36, 0x04b), F3F(~2, ~0x36, ~0x04b), "e,f,H", 0, v9a }, |
1949 | aa0aa4fa | bellard | |
1950 | aa0aa4fa | bellard | /* Note that the mixing of 32/64 bit regs is intentional. */
|
1951 | f930d07e | blueswir1 | { "fmul8x16", F3F(2, 0x36, 0x031), F3F(~2, ~0x36, ~0x031), "e,B,H", 0, v9a }, |
1952 | f930d07e | blueswir1 | { "fmul8x16au", F3F(2, 0x36, 0x033), F3F(~2, ~0x36, ~0x033), "e,f,H", 0, v9a }, |
1953 | f930d07e | blueswir1 | { "fmul8x16al", F3F(2, 0x36, 0x035), F3F(~2, ~0x36, ~0x035), "e,f,H", 0, v9a }, |
1954 | f930d07e | blueswir1 | { "fmul8sux16", F3F(2, 0x36, 0x036), F3F(~2, ~0x36, ~0x036), "v,B,H", 0, v9a }, |
1955 | f930d07e | blueswir1 | { "fmul8ulx16", F3F(2, 0x36, 0x037), F3F(~2, ~0x36, ~0x037), "v,B,H", 0, v9a }, |
1956 | f930d07e | blueswir1 | { "fmuld8sux16", F3F(2, 0x36, 0x038), F3F(~2, ~0x36, ~0x038), "e,f,H", 0, v9a }, |
1957 | f930d07e | blueswir1 | { "fmuld8ulx16", F3F(2, 0x36, 0x039), F3F(~2, ~0x36, ~0x039), "e,f,H", 0, v9a }, |
1958 | f930d07e | blueswir1 | |
1959 | f930d07e | blueswir1 | { "alignaddr", F3F(2, 0x36, 0x018), F3F(~2, ~0x36, ~0x018), "1,2,d", 0, v9a }, |
1960 | f930d07e | blueswir1 | { "alignaddrl", F3F(2, 0x36, 0x01a), F3F(~2, ~0x36, ~0x01a), "1,2,d", 0, v9a }, |
1961 | f930d07e | blueswir1 | { "faligndata", F3F(2, 0x36, 0x048), F3F(~2, ~0x36, ~0x048), "v,B,H", 0, v9a }, |
1962 | f930d07e | blueswir1 | |
1963 | f930d07e | blueswir1 | { "fzero", F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", 0, v9a }, |
1964 | f930d07e | blueswir1 | { "fzeros", F3F(2, 0x36, 0x061), F3F(~2, ~0x36, ~0x061), "g", 0, v9a }, |
1965 | f930d07e | blueswir1 | { "fone", F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", 0, v9a }, |
1966 | f930d07e | blueswir1 | { "fones", F3F(2, 0x36, 0x07f), F3F(~2, ~0x36, ~0x07f), "g", 0, v9a }, |
1967 | f930d07e | blueswir1 | { "fsrc1", F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", 0, v9a }, |
1968 | f930d07e | blueswir1 | { "fsrc1s", F3F(2, 0x36, 0x075), F3F(~2, ~0x36, ~0x075), "e,g", 0, v9a }, |
1969 | f930d07e | blueswir1 | { "fsrc2", F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", 0, v9a }, |
1970 | f930d07e | blueswir1 | { "fsrc2s", F3F(2, 0x36, 0x079), F3F(~2, ~0x36, ~0x079), "f,g", 0, v9a }, |
1971 | f930d07e | blueswir1 | { "fnot1", F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", 0, v9a }, |
1972 | f930d07e | blueswir1 | { "fnot1s", F3F(2, 0x36, 0x06b), F3F(~2, ~0x36, ~0x06b), "e,g", 0, v9a }, |
1973 | f930d07e | blueswir1 | { "fnot2", F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", 0, v9a }, |
1974 | f930d07e | blueswir1 | { "fnot2s", F3F(2, 0x36, 0x067), F3F(~2, ~0x36, ~0x067), "f,g", 0, v9a }, |
1975 | f930d07e | blueswir1 | { "for", F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", 0, v9a }, |
1976 | f930d07e | blueswir1 | { "fors", F3F(2, 0x36, 0x07d), F3F(~2, ~0x36, ~0x07d), "e,f,g", 0, v9a }, |
1977 | f930d07e | blueswir1 | { "fnor", F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", 0, v9a }, |
1978 | f930d07e | blueswir1 | { "fnors", F3F(2, 0x36, 0x063), F3F(~2, ~0x36, ~0x063), "e,f,g", 0, v9a }, |
1979 | f930d07e | blueswir1 | { "fand", F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", 0, v9a }, |
1980 | f930d07e | blueswir1 | { "fands", F3F(2, 0x36, 0x071), F3F(~2, ~0x36, ~0x071), "e,f,g", 0, v9a }, |
1981 | f930d07e | blueswir1 | { "fnand", F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", 0, v9a }, |
1982 | f930d07e | blueswir1 | { "fnands", F3F(2, 0x36, 0x06f), F3F(~2, ~0x36, ~0x06f), "e,f,g", 0, v9a }, |
1983 | f930d07e | blueswir1 | { "fxor", F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", 0, v9a }, |
1984 | f930d07e | blueswir1 | { "fxors", F3F(2, 0x36, 0x06d), F3F(~2, ~0x36, ~0x06d), "e,f,g", 0, v9a }, |
1985 | f930d07e | blueswir1 | { "fxnor", F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", 0, v9a }, |
1986 | f930d07e | blueswir1 | { "fxnors", F3F(2, 0x36, 0x073), F3F(~2, ~0x36, ~0x073), "e,f,g", 0, v9a }, |
1987 | f930d07e | blueswir1 | { "fornot1", F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", 0, v9a }, |
1988 | f930d07e | blueswir1 | { "fornot1s", F3F(2, 0x36, 0x07b), F3F(~2, ~0x36, ~0x07b), "e,f,g", 0, v9a }, |
1989 | f930d07e | blueswir1 | { "fornot2", F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", 0, v9a }, |
1990 | f930d07e | blueswir1 | { "fornot2s", F3F(2, 0x36, 0x077), F3F(~2, ~0x36, ~0x077), "e,f,g", 0, v9a }, |
1991 | f930d07e | blueswir1 | { "fandnot1", F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", 0, v9a }, |
1992 | f930d07e | blueswir1 | { "fandnot1s", F3F(2, 0x36, 0x069), F3F(~2, ~0x36, ~0x069), "e,f,g", 0, v9a }, |
1993 | f930d07e | blueswir1 | { "fandnot2", F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", 0, v9a }, |
1994 | f930d07e | blueswir1 | { "fandnot2s", F3F(2, 0x36, 0x065), F3F(~2, ~0x36, ~0x065), "e,f,g", 0, v9a }, |
1995 | f930d07e | blueswir1 | |
1996 | f930d07e | blueswir1 | { "fcmpgt16", F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", 0, v9a }, |
1997 | f930d07e | blueswir1 | { "fcmpgt32", F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", 0, v9a }, |
1998 | f930d07e | blueswir1 | { "fcmple16", F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", 0, v9a }, |
1999 | f930d07e | blueswir1 | { "fcmple32", F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", 0, v9a }, |
2000 | f930d07e | blueswir1 | { "fcmpne16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", 0, v9a }, |
2001 | f930d07e | blueswir1 | { "fcmpne32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", 0, v9a }, |
2002 | f930d07e | blueswir1 | { "fcmpeq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", 0, v9a }, |
2003 | f930d07e | blueswir1 | { "fcmpeq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", 0, v9a }, |
2004 | f930d07e | blueswir1 | |
2005 | f930d07e | blueswir1 | { "edge8", F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", 0, v9a }, |
2006 | f930d07e | blueswir1 | { "edge8l", F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", 0, v9a }, |
2007 | f930d07e | blueswir1 | { "edge16", F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", 0, v9a }, |
2008 | f930d07e | blueswir1 | { "edge16l", F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", 0, v9a }, |
2009 | f930d07e | blueswir1 | { "edge32", F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", 0, v9a }, |
2010 | f930d07e | blueswir1 | { "edge32l", F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", 0, v9a }, |
2011 | f930d07e | blueswir1 | |
2012 | f930d07e | blueswir1 | { "pdist", F3F(2, 0x36, 0x03e), F3F(~2, ~0x36, ~0x03e), "v,B,H", 0, v9a }, |
2013 | f930d07e | blueswir1 | |
2014 | f930d07e | blueswir1 | { "array8", F3F(2, 0x36, 0x010), F3F(~2, ~0x36, ~0x010), "1,2,d", 0, v9a }, |
2015 | f930d07e | blueswir1 | { "array16", F3F(2, 0x36, 0x012), F3F(~2, ~0x36, ~0x012), "1,2,d", 0, v9a }, |
2016 | f930d07e | blueswir1 | { "array32", F3F(2, 0x36, 0x014), F3F(~2, ~0x36, ~0x014), "1,2,d", 0, v9a }, |
2017 | aa0aa4fa | bellard | |
2018 | aa0aa4fa | bellard | /* Cheetah instructions */
|
2019 | aa0aa4fa | bellard | { "edge8n", F3F(2, 0x36, 0x001), F3F(~2, ~0x36, ~0x001), "1,2,d", 0, v9b }, |
2020 | aa0aa4fa | bellard | { "edge8ln", F3F(2, 0x36, 0x003), F3F(~2, ~0x36, ~0x003), "1,2,d", 0, v9b }, |
2021 | aa0aa4fa | bellard | { "edge16n", F3F(2, 0x36, 0x005), F3F(~2, ~0x36, ~0x005), "1,2,d", 0, v9b }, |
2022 | aa0aa4fa | bellard | { "edge16ln", F3F(2, 0x36, 0x007), F3F(~2, ~0x36, ~0x007), "1,2,d", 0, v9b }, |
2023 | aa0aa4fa | bellard | { "edge32n", F3F(2, 0x36, 0x009), F3F(~2, ~0x36, ~0x009), "1,2,d", 0, v9b }, |
2024 | aa0aa4fa | bellard | { "edge32ln", F3F(2, 0x36, 0x00b), F3F(~2, ~0x36, ~0x00b), "1,2,d", 0, v9b }, |
2025 | aa0aa4fa | bellard | |
2026 | aa0aa4fa | bellard | { "bmask", F3F(2, 0x36, 0x019), F3F(~2, ~0x36, ~0x019), "1,2,d", 0, v9b }, |
2027 | aa0aa4fa | bellard | { "bshuffle", F3F(2, 0x36, 0x04c), F3F(~2, ~0x36, ~0x04c), "v,B,H", 0, v9b }, |
2028 | aa0aa4fa | bellard | |
2029 | aa0aa4fa | bellard | { "siam", F3F(2, 0x36, 0x081), F3F(~2, ~0x36, ~0x081)|RD_G0|RS1_G0|RS2(~7), "3", 0, v9b }, |
2030 | aa0aa4fa | bellard | |
2031 | aa0aa4fa | bellard | /* More v9 specific insns, these need to come last so they do not clash
|
2032 | aa0aa4fa | bellard | with v9a instructions such as "edge8" which looks like impdep1. */
|
2033 | aa0aa4fa | bellard | |
2034 | aa0aa4fa | bellard | #define IMPDEP(name, code) \
|
2035 | f930d07e | blueswir1 | { name, F3(2, code, 0), F3(~2, ~code, ~0)|ASI(~0), "1,2,d", 0, v9notv9a }, \ |
2036 | f930d07e | blueswir1 | { name, F3(2, code, 1), F3(~2, ~code, ~1), "1,i,d", 0, v9notv9a }, \ |
2037 | aa0aa4fa | bellard | { name, F3(2, code, 0), F3(~2, ~code, ~0), "x,1,2,d", 0, v9notv9a }, \ |
2038 | aa0aa4fa | bellard | { name, F3(2, code, 0), F3(~2, ~code, ~0), "x,e,f,g", 0, v9notv9a } |
2039 | aa0aa4fa | bellard | |
2040 | aa0aa4fa | bellard | IMPDEP ("impdep1", 0x36), |
2041 | aa0aa4fa | bellard | IMPDEP ("impdep2", 0x37), |
2042 | aa0aa4fa | bellard | |
2043 | aa0aa4fa | bellard | #undef IMPDEP
|
2044 | aa0aa4fa | bellard | |
2045 | aa0aa4fa | bellard | }; |
2046 | aa0aa4fa | bellard | |
2047 | f82a3d48 | blueswir1 | static const int sparc_num_opcodes = ((sizeof sparc_opcodes)/(sizeof sparc_opcodes[0])); |
2048 | aa0aa4fa | bellard | |
2049 | aa0aa4fa | bellard | /* Utilities for argument parsing. */
|
2050 | aa0aa4fa | bellard | |
2051 | aa0aa4fa | bellard | typedef struct |
2052 | aa0aa4fa | bellard | { |
2053 | aa0aa4fa | bellard | int value;
|
2054 | aa0aa4fa | bellard | const char *name; |
2055 | aa0aa4fa | bellard | } arg; |
2056 | aa0aa4fa | bellard | |
2057 | aa0aa4fa | bellard | /* Look up VALUE in TABLE. */
|
2058 | aa0aa4fa | bellard | |
2059 | aa0aa4fa | bellard | static const char * |
2060 | 46f42f29 | blueswir1 | lookup_value (const arg *table, int value) |
2061 | aa0aa4fa | bellard | { |
2062 | aa0aa4fa | bellard | const arg *p;
|
2063 | aa0aa4fa | bellard | |
2064 | aa0aa4fa | bellard | for (p = table; p->name; ++p)
|
2065 | aa0aa4fa | bellard | if (value == p->value)
|
2066 | aa0aa4fa | bellard | return p->name;
|
2067 | aa0aa4fa | bellard | |
2068 | 46f42f29 | blueswir1 | return NULL; |
2069 | aa0aa4fa | bellard | } |
2070 | aa0aa4fa | bellard | |
2071 | aa0aa4fa | bellard | /* Handle ASI's. */
|
2072 | aa0aa4fa | bellard | |
2073 | 1983a395 | bellard | static const arg asi_table_v8[] = |
2074 | 1983a395 | bellard | { |
2075 | 1983a395 | bellard | { 0x00, "#ASI_M_RES00" }, |
2076 | 1983a395 | bellard | { 0x01, "#ASI_M_UNA01" }, |
2077 | 1983a395 | bellard | { 0x02, "#ASI_M_MXCC" }, |
2078 | 1983a395 | bellard | { 0x03, "#ASI_M_FLUSH_PROBE" }, |
2079 | 1983a395 | bellard | { 0x04, "#ASI_M_MMUREGS" }, |
2080 | 1983a395 | bellard | { 0x05, "#ASI_M_TLBDIAG" }, |
2081 | 1983a395 | bellard | { 0x06, "#ASI_M_DIAGS" }, |
2082 | 1983a395 | bellard | { 0x07, "#ASI_M_IODIAG" }, |
2083 | 1983a395 | bellard | { 0x08, "#ASI_M_USERTXT" }, |
2084 | 1983a395 | bellard | { 0x09, "#ASI_M_KERNELTXT" }, |
2085 | 1983a395 | bellard | { 0x0A, "#ASI_M_USERDATA" }, |
2086 | 1983a395 | bellard | { 0x0B, "#ASI_M_KERNELDATA" }, |
2087 | 1983a395 | bellard | { 0x0C, "#ASI_M_TXTC_TAG" }, |
2088 | 1983a395 | bellard | { 0x0D, "#ASI_M_TXTC_DATA" }, |
2089 | 1983a395 | bellard | { 0x0E, "#ASI_M_DATAC_TAG" }, |
2090 | 1983a395 | bellard | { 0x0F, "#ASI_M_DATAC_DATA" }, |
2091 | 1983a395 | bellard | { 0x10, "#ASI_M_FLUSH_PAGE" }, |
2092 | 1983a395 | bellard | { 0x11, "#ASI_M_FLUSH_SEG" }, |
2093 | 1983a395 | bellard | { 0x12, "#ASI_M_FLUSH_REGION" }, |
2094 | 1983a395 | bellard | { 0x13, "#ASI_M_FLUSH_CTX" }, |
2095 | 1983a395 | bellard | { 0x14, "#ASI_M_FLUSH_USER" }, |
2096 | 1983a395 | bellard | { 0x17, "#ASI_M_BCOPY" }, |
2097 | 1983a395 | bellard | { 0x18, "#ASI_M_IFLUSH_PAGE" }, |
2098 | 1983a395 | bellard | { 0x19, "#ASI_M_IFLUSH_SEG" }, |
2099 | 1983a395 | bellard | { 0x1A, "#ASI_M_IFLUSH_REGION" }, |
2100 | 1983a395 | bellard | { 0x1B, "#ASI_M_IFLUSH_CTX" }, |
2101 | 1983a395 | bellard | { 0x1C, "#ASI_M_IFLUSH_USER" }, |
2102 | 1983a395 | bellard | { 0x1F, "#ASI_M_BFILL" }, |
2103 | 1983a395 | bellard | { 0x20, "#ASI_M_BYPASS" }, |
2104 | 1983a395 | bellard | { 0x29, "#ASI_M_FBMEM" }, |
2105 | 1983a395 | bellard | { 0x2A, "#ASI_M_VMEUS" }, |
2106 | 1983a395 | bellard | { 0x2B, "#ASI_M_VMEPS" }, |
2107 | 1983a395 | bellard | { 0x2C, "#ASI_M_VMEUT" }, |
2108 | 1983a395 | bellard | { 0x2D, "#ASI_M_VMEPT" }, |
2109 | 1983a395 | bellard | { 0x2E, "#ASI_M_SBUS" }, |
2110 | 1983a395 | bellard | { 0x2F, "#ASI_M_CTL" }, |
2111 | 1983a395 | bellard | { 0x31, "#ASI_M_FLUSH_IWHOLE" }, |
2112 | 1983a395 | bellard | { 0x36, "#ASI_M_IC_FLCLEAR" }, |
2113 | 1983a395 | bellard | { 0x37, "#ASI_M_DC_FLCLEAR" }, |
2114 | 1983a395 | bellard | { 0x39, "#ASI_M_DCDR" }, |
2115 | 1983a395 | bellard | { 0x40, "#ASI_M_VIKING_TMP1" }, |
2116 | 1983a395 | bellard | { 0x41, "#ASI_M_VIKING_TMP2" }, |
2117 | 1983a395 | bellard | { 0x4c, "#ASI_M_ACTION" }, |
2118 | 660f11be | Blue Swirl | { 0, NULL } |
2119 | 1983a395 | bellard | }; |
2120 | 1983a395 | bellard | |
2121 | 1983a395 | bellard | static const arg asi_table_v9[] = |
2122 | aa0aa4fa | bellard | { |
2123 | aa0aa4fa | bellard | /* These are in the v9 architecture manual. */
|
2124 | aa0aa4fa | bellard | /* The shorter versions appear first, they're here because Sun's as has them.
|
2125 | aa0aa4fa | bellard | Sun's as uses #ASI_P_L instead of #ASI_PL (which appears in the
|
2126 | aa0aa4fa | bellard | UltraSPARC architecture manual). */
|
2127 | aa0aa4fa | bellard | { 0x04, "#ASI_N" }, |
2128 | aa0aa4fa | bellard | { 0x0c, "#ASI_N_L" }, |
2129 | aa0aa4fa | bellard | { 0x10, "#ASI_AIUP" }, |
2130 | aa0aa4fa | bellard | { 0x11, "#ASI_AIUS" }, |
2131 | aa0aa4fa | bellard | { 0x18, "#ASI_AIUP_L" }, |
2132 | aa0aa4fa | bellard | { 0x19, "#ASI_AIUS_L" }, |
2133 | aa0aa4fa | bellard | { 0x80, "#ASI_P" }, |
2134 | aa0aa4fa | bellard | { 0x81, "#ASI_S" }, |
2135 | aa0aa4fa | bellard | { 0x82, "#ASI_PNF" }, |
2136 | aa0aa4fa | bellard | { 0x83, "#ASI_SNF" }, |
2137 | aa0aa4fa | bellard | { 0x88, "#ASI_P_L" }, |
2138 | aa0aa4fa | bellard | { 0x89, "#ASI_S_L" }, |
2139 | aa0aa4fa | bellard | { 0x8a, "#ASI_PNF_L" }, |
2140 | aa0aa4fa | bellard | { 0x8b, "#ASI_SNF_L" }, |
2141 | aa0aa4fa | bellard | { 0x04, "#ASI_NUCLEUS" }, |
2142 | aa0aa4fa | bellard | { 0x0c, "#ASI_NUCLEUS_LITTLE" }, |
2143 | aa0aa4fa | bellard | { 0x10, "#ASI_AS_IF_USER_PRIMARY" }, |
2144 | aa0aa4fa | bellard | { 0x11, "#ASI_AS_IF_USER_SECONDARY" }, |
2145 | aa0aa4fa | bellard | { 0x18, "#ASI_AS_IF_USER_PRIMARY_LITTLE" }, |
2146 | aa0aa4fa | bellard | { 0x19, "#ASI_AS_IF_USER_SECONDARY_LITTLE" }, |
2147 | aa0aa4fa | bellard | { 0x80, "#ASI_PRIMARY" }, |
2148 | aa0aa4fa | bellard | { 0x81, "#ASI_SECONDARY" }, |
2149 | aa0aa4fa | bellard | { 0x82, "#ASI_PRIMARY_NOFAULT" }, |
2150 | aa0aa4fa | bellard | { 0x83, "#ASI_SECONDARY_NOFAULT" }, |
2151 | aa0aa4fa | bellard | { 0x88, "#ASI_PRIMARY_LITTLE" }, |
2152 | aa0aa4fa | bellard | { 0x89, "#ASI_SECONDARY_LITTLE" }, |
2153 | aa0aa4fa | bellard | { 0x8a, "#ASI_PRIMARY_NOFAULT_LITTLE" }, |
2154 | aa0aa4fa | bellard | { 0x8b, "#ASI_SECONDARY_NOFAULT_LITTLE" }, |
2155 | aa0aa4fa | bellard | /* These are UltraSPARC extensions. */
|
2156 | aa0aa4fa | bellard | /* FIXME: There are dozens of them. Not sure we want them all.
|
2157 | aa0aa4fa | bellard | Most are for kernel building but some are for vis type stuff. */
|
2158 | 660f11be | Blue Swirl | { 0, NULL } |
2159 | aa0aa4fa | bellard | }; |
2160 | aa0aa4fa | bellard | |
2161 | 1983a395 | bellard | /* Return the name for ASI value VALUE or NULL if not found. */
|
2162 | aa0aa4fa | bellard | |
2163 | 1983a395 | bellard | static const char * |
2164 | 1983a395 | bellard | sparc_decode_asi_v9 (int value)
|
2165 | aa0aa4fa | bellard | { |
2166 | 1983a395 | bellard | return lookup_value (asi_table_v9, value);
|
2167 | aa0aa4fa | bellard | } |
2168 | aa0aa4fa | bellard | |
2169 | 1983a395 | bellard | static const char * |
2170 | 1983a395 | bellard | sparc_decode_asi_v8 (int value)
|
2171 | aa0aa4fa | bellard | { |
2172 | 1983a395 | bellard | return lookup_value (asi_table_v8, value);
|
2173 | aa0aa4fa | bellard | } |
2174 | aa0aa4fa | bellard | |
2175 | aa0aa4fa | bellard | /* Handle membar masks. */
|
2176 | aa0aa4fa | bellard | |
2177 | d88bbf95 | blueswir1 | static const arg membar_table[] = |
2178 | aa0aa4fa | bellard | { |
2179 | aa0aa4fa | bellard | { 0x40, "#Sync" }, |
2180 | aa0aa4fa | bellard | { 0x20, "#MemIssue" }, |
2181 | aa0aa4fa | bellard | { 0x10, "#Lookaside" }, |
2182 | aa0aa4fa | bellard | { 0x08, "#StoreStore" }, |
2183 | aa0aa4fa | bellard | { 0x04, "#LoadStore" }, |
2184 | aa0aa4fa | bellard | { 0x02, "#StoreLoad" }, |
2185 | aa0aa4fa | bellard | { 0x01, "#LoadLoad" }, |
2186 | 660f11be | Blue Swirl | { 0, NULL } |
2187 | aa0aa4fa | bellard | }; |
2188 | aa0aa4fa | bellard | |
2189 | aa0aa4fa | bellard | /* Return the name for membar value VALUE or NULL if not found. */
|
2190 | aa0aa4fa | bellard | |
2191 | b1d8e52e | blueswir1 | static const char * |
2192 | 46f42f29 | blueswir1 | sparc_decode_membar (int value)
|
2193 | aa0aa4fa | bellard | { |
2194 | aa0aa4fa | bellard | return lookup_value (membar_table, value);
|
2195 | aa0aa4fa | bellard | } |
2196 | aa0aa4fa | bellard | |
2197 | aa0aa4fa | bellard | /* Handle prefetch args. */
|
2198 | aa0aa4fa | bellard | |
2199 | d88bbf95 | blueswir1 | static const arg prefetch_table[] = |
2200 | aa0aa4fa | bellard | { |
2201 | aa0aa4fa | bellard | { 0, "#n_reads" }, |
2202 | aa0aa4fa | bellard | { 1, "#one_read" }, |
2203 | aa0aa4fa | bellard | { 2, "#n_writes" }, |
2204 | aa0aa4fa | bellard | { 3, "#one_write" }, |
2205 | aa0aa4fa | bellard | { 4, "#page" }, |
2206 | aa0aa4fa | bellard | { 16, "#invalidate" }, |
2207 | 660f11be | Blue Swirl | { 0, NULL } |
2208 | aa0aa4fa | bellard | }; |
2209 | aa0aa4fa | bellard | |
2210 | aa0aa4fa | bellard | /* Return the name for prefetch value VALUE or NULL if not found. */
|
2211 | aa0aa4fa | bellard | |
2212 | b1d8e52e | blueswir1 | static const char * |
2213 | 46f42f29 | blueswir1 | sparc_decode_prefetch (int value)
|
2214 | aa0aa4fa | bellard | { |
2215 | aa0aa4fa | bellard | return lookup_value (prefetch_table, value);
|
2216 | aa0aa4fa | bellard | } |
2217 | aa0aa4fa | bellard | |
2218 | aa0aa4fa | bellard | /* Handle sparclet coprocessor registers. */
|
2219 | aa0aa4fa | bellard | |
2220 | d88bbf95 | blueswir1 | static const arg sparclet_cpreg_table[] = |
2221 | aa0aa4fa | bellard | { |
2222 | aa0aa4fa | bellard | { 0, "%ccsr" }, |
2223 | aa0aa4fa | bellard | { 1, "%ccfr" }, |
2224 | aa0aa4fa | bellard | { 2, "%cccrcr" }, |
2225 | aa0aa4fa | bellard | { 3, "%ccpr" }, |
2226 | aa0aa4fa | bellard | { 4, "%ccsr2" }, |
2227 | aa0aa4fa | bellard | { 5, "%cccrr" }, |
2228 | aa0aa4fa | bellard | { 6, "%ccrstr" }, |
2229 | 660f11be | Blue Swirl | { 0, NULL } |
2230 | aa0aa4fa | bellard | }; |
2231 | aa0aa4fa | bellard | |
2232 | aa0aa4fa | bellard | /* Return the name for sparclet cpreg value VALUE or NULL if not found. */
|
2233 | aa0aa4fa | bellard | |
2234 | b1d8e52e | blueswir1 | static const char * |
2235 | 46f42f29 | blueswir1 | sparc_decode_sparclet_cpreg (int value)
|
2236 | aa0aa4fa | bellard | { |
2237 | aa0aa4fa | bellard | return lookup_value (sparclet_cpreg_table, value);
|
2238 | aa0aa4fa | bellard | } |
2239 | aa0aa4fa | bellard | |
2240 | aa0aa4fa | bellard | #undef MASK_V9
|
2241 | aa0aa4fa | bellard | |
2242 | d4abd567 | blueswir1 | /* opcodes/sparc-dis.c */
|
2243 | d4abd567 | blueswir1 | |
2244 | 46f42f29 | blueswir1 | /* Print SPARC instructions.
|
2245 | 46f42f29 | blueswir1 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
|
2246 | 46f42f29 | blueswir1 | 2000, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
|
2247 | 46f42f29 | blueswir1 | |
2248 | 46f42f29 | blueswir1 | This program is free software; you can redistribute it and/or modify
|
2249 | 46f42f29 | blueswir1 | it under the terms of the GNU General Public License as published by
|
2250 | 46f42f29 | blueswir1 | the Free Software Foundation; either version 2 of the License, or
|
2251 | 46f42f29 | blueswir1 | (at your option) any later version.
|
2252 | 46f42f29 | blueswir1 | |
2253 | 46f42f29 | blueswir1 | This program is distributed in the hope that it will be useful,
|
2254 | 46f42f29 | blueswir1 | but WITHOUT ANY WARRANTY; without even the implied warranty of
|
2255 | 46f42f29 | blueswir1 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
2256 | 46f42f29 | blueswir1 | GNU General Public License for more details.
|
2257 | 46f42f29 | blueswir1 | |
2258 | 46f42f29 | blueswir1 | You should have received a copy of the GNU General Public License
|
2259 | 8167ee88 | Blue Swirl | along with this program; if not, see <http://www.gnu.org/licenses/>. */
|
2260 | 46f42f29 | blueswir1 | |
2261 | aa0aa4fa | bellard | /* Bitmask of v9 architectures. */
|
2262 | aa0aa4fa | bellard | #define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \ |
2263 | f930d07e | blueswir1 | | (1 << SPARC_OPCODE_ARCH_V9A) \
|
2264 | f930d07e | blueswir1 | | (1 << SPARC_OPCODE_ARCH_V9B))
|
2265 | aa0aa4fa | bellard | /* 1 if INSN is for v9 only. */
|
2266 | aa0aa4fa | bellard | #define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
|
2267 | aa0aa4fa | bellard | /* 1 if INSN is for v9. */
|
2268 | aa0aa4fa | bellard | #define V9_P(insn) (((insn)->architecture & MASK_V9) != 0) |
2269 | aa0aa4fa | bellard | |
2270 | aa0aa4fa | bellard | /* The sorted opcode table. */
|
2271 | 46f42f29 | blueswir1 | static const sparc_opcode **sorted_opcodes; |
2272 | aa0aa4fa | bellard | |
2273 | aa0aa4fa | bellard | /* For faster lookup, after insns are sorted they are hashed. */
|
2274 | aa0aa4fa | bellard | /* ??? I think there is room for even more improvement. */
|
2275 | aa0aa4fa | bellard | |
2276 | aa0aa4fa | bellard | #define HASH_SIZE 256 |
2277 | aa0aa4fa | bellard | /* It is important that we only look at insn code bits as that is how the
|
2278 | aa0aa4fa | bellard | opcode table is hashed. OPCODE_BITS is a table of valid bits for each
|
2279 | aa0aa4fa | bellard | of the main types (0,1,2,3). */
|
2280 | d88bbf95 | blueswir1 | static const int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 }; |
2281 | aa0aa4fa | bellard | #define HASH_INSN(INSN) \
|
2282 | aa0aa4fa | bellard | ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19)) |
2283 | 46f42f29 | blueswir1 | typedef struct sparc_opcode_hash |
2284 | 46f42f29 | blueswir1 | { |
2285 | 46f42f29 | blueswir1 | struct sparc_opcode_hash *next;
|
2286 | 46f42f29 | blueswir1 | const sparc_opcode *opcode;
|
2287 | 46f42f29 | blueswir1 | } sparc_opcode_hash; |
2288 | aa0aa4fa | bellard | |
2289 | 46f42f29 | blueswir1 | static sparc_opcode_hash *opcode_hash_table[HASH_SIZE];
|
2290 | aa0aa4fa | bellard | |
2291 | aa0aa4fa | bellard | /* Sign-extend a value which is N bits long. */
|
2292 | f930d07e | blueswir1 | #define SEX(value, bits) \
|
2293 | f930d07e | blueswir1 | ((((int)(value)) << ((8 * sizeof (int)) - bits)) \ |
2294 | f930d07e | blueswir1 | >> ((8 * sizeof (int)) - bits) ) |
2295 | aa0aa4fa | bellard | |
2296 | d88bbf95 | blueswir1 | static const char * const reg_names[] = |
2297 | 5fafdf24 | ths | { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", |
2298 | 5fafdf24 | ths | "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", |
2299 | 5fafdf24 | ths | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", |
2300 | 5fafdf24 | ths | "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", |
2301 | 5fafdf24 | ths | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
2302 | 5fafdf24 | ths | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
2303 | aa0aa4fa | bellard | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
2304 | aa0aa4fa | bellard | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", |
2305 | 5fafdf24 | ths | "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", |
2306 | 5fafdf24 | ths | "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", |
2307 | aa0aa4fa | bellard | "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55", |
2308 | aa0aa4fa | bellard | "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63", |
2309 | aa0aa4fa | bellard | /* psr, wim, tbr, fpsr, cpsr are v8 only. */
|
2310 | aa0aa4fa | bellard | "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr" |
2311 | aa0aa4fa | bellard | }; |
2312 | aa0aa4fa | bellard | |
2313 | f930d07e | blueswir1 | #define freg_names (®_names[4 * 8]) |
2314 | aa0aa4fa | bellard | |
2315 | aa0aa4fa | bellard | /* These are ordered according to there register number in
|
2316 | aa0aa4fa | bellard | rdpr and wrpr insns. */
|
2317 | d88bbf95 | blueswir1 | static const char * const v9_priv_reg_names[] = |
2318 | aa0aa4fa | bellard | { |
2319 | aa0aa4fa | bellard | "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl", |
2320 | aa0aa4fa | bellard | "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin", |
2321 | 46f42f29 | blueswir1 | "wstate", "fq", "gl" |
2322 | aa0aa4fa | bellard | /* "ver" - special cased */
|
2323 | aa0aa4fa | bellard | }; |
2324 | aa0aa4fa | bellard | |
2325 | aa0aa4fa | bellard | /* These are ordered according to there register number in
|
2326 | 46f42f29 | blueswir1 | rdhpr and wrhpr insns. */
|
2327 | 46f42f29 | blueswir1 | static const char * const v9_hpriv_reg_names[] = |
2328 | 46f42f29 | blueswir1 | { |
2329 | 46f42f29 | blueswir1 | "hpstate", "htstate", "resv2", "hintp", "resv4", "htba", "hver", |
2330 | 46f42f29 | blueswir1 | "resv7", "resv8", "resv9", "resv10", "resv11", "resv12", "resv13", |
2331 | 46f42f29 | blueswir1 | "resv14", "resv15", "resv16", "resv17", "resv18", "resv19", "resv20", |
2332 | 46f42f29 | blueswir1 | "resv21", "resv22", "resv23", "resv24", "resv25", "resv26", "resv27", |
2333 | 46f42f29 | blueswir1 | "resv28", "resv29", "resv30", "hstick_cmpr" |
2334 | 46f42f29 | blueswir1 | }; |
2335 | 46f42f29 | blueswir1 | |
2336 | 46f42f29 | blueswir1 | /* These are ordered according to there register number in
|
2337 | aa0aa4fa | bellard | rd and wr insns (-16). */
|
2338 | d88bbf95 | blueswir1 | static const char * const v9a_asr_reg_names[] = |
2339 | aa0aa4fa | bellard | { |
2340 | aa0aa4fa | bellard | "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint", |
2341 | aa0aa4fa | bellard | "softint", "tick_cmpr", "sys_tick", "sys_tick_cmpr" |
2342 | aa0aa4fa | bellard | }; |
2343 | aa0aa4fa | bellard | |
2344 | aa0aa4fa | bellard | /* Macros used to extract instruction fields. Not all fields have
|
2345 | aa0aa4fa | bellard | macros defined here, only those which are actually used. */
|
2346 | aa0aa4fa | bellard | |
2347 | 46f42f29 | blueswir1 | #define X_RD(i) (((i) >> 25) & 0x1f) |
2348 | 46f42f29 | blueswir1 | #define X_RS1(i) (((i) >> 14) & 0x1f) |
2349 | 46f42f29 | blueswir1 | #define X_LDST_I(i) (((i) >> 13) & 1) |
2350 | 46f42f29 | blueswir1 | #define X_ASI(i) (((i) >> 5) & 0xff) |
2351 | 46f42f29 | blueswir1 | #define X_RS2(i) (((i) >> 0) & 0x1f) |
2352 | 46f42f29 | blueswir1 | #define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1)) |
2353 | 46f42f29 | blueswir1 | #define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n))
|
2354 | 46f42f29 | blueswir1 | #define X_DISP22(i) (((i) >> 0) & 0x3fffff) |
2355 | 46f42f29 | blueswir1 | #define X_IMM22(i) X_DISP22 (i)
|
2356 | 46f42f29 | blueswir1 | #define X_DISP30(i) (((i) >> 0) & 0x3fffffff) |
2357 | aa0aa4fa | bellard | |
2358 | aa0aa4fa | bellard | /* These are for v9. */
|
2359 | 46f42f29 | blueswir1 | #define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff)) |
2360 | 46f42f29 | blueswir1 | #define X_DISP19(i) (((i) >> 0) & 0x7ffff) |
2361 | 46f42f29 | blueswir1 | #define X_MEMBAR(i) ((i) & 0x7f) |
2362 | aa0aa4fa | bellard | |
2363 | aa0aa4fa | bellard | /* Here is the union which was used to extract instruction fields
|
2364 | aa0aa4fa | bellard | before the shift and mask macros were written.
|
2365 | aa0aa4fa | bellard | |
2366 | aa0aa4fa | bellard | union sparc_insn
|
2367 | aa0aa4fa | bellard | {
|
2368 | aa0aa4fa | bellard | unsigned long int code;
|
2369 | aa0aa4fa | bellard | struct
|
2370 | f930d07e | blueswir1 | {
|
2371 | f930d07e | blueswir1 | unsigned int anop:2;
|
2372 | f930d07e | blueswir1 | #define op ldst.anop
|
2373 | f930d07e | blueswir1 | unsigned int anrd:5;
|
2374 | f930d07e | blueswir1 | #define rd ldst.anrd
|
2375 | f930d07e | blueswir1 | unsigned int op3:6;
|
2376 | f930d07e | blueswir1 | unsigned int anrs1:5;
|
2377 | f930d07e | blueswir1 | #define rs1 ldst.anrs1
|
2378 | f930d07e | blueswir1 | unsigned int i:1;
|
2379 | f930d07e | blueswir1 | unsigned int anasi:8;
|
2380 | f930d07e | blueswir1 | #define asi ldst.anasi
|
2381 | f930d07e | blueswir1 | unsigned int anrs2:5;
|
2382 | f930d07e | blueswir1 | #define rs2 ldst.anrs2
|
2383 | f930d07e | blueswir1 | #define shcnt rs2
|
2384 | f930d07e | blueswir1 | } ldst;
|
2385 | aa0aa4fa | bellard | struct
|
2386 | f930d07e | blueswir1 | {
|
2387 | f930d07e | blueswir1 | unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1;
|
2388 | f930d07e | blueswir1 | unsigned int IMM13:13;
|
2389 | f930d07e | blueswir1 | #define imm13 IMM13.IMM13
|
2390 | f930d07e | blueswir1 | } IMM13;
|
2391 | aa0aa4fa | bellard | struct
|
2392 | f930d07e | blueswir1 | {
|
2393 | f930d07e | blueswir1 | unsigned int anop:2;
|
2394 | f930d07e | blueswir1 | unsigned int a:1;
|
2395 | f930d07e | blueswir1 | unsigned int cond:4;
|
2396 | f930d07e | blueswir1 | unsigned int op2:3;
|
2397 | f930d07e | blueswir1 | unsigned int DISP22:22;
|
2398 | f930d07e | blueswir1 | #define disp22 branch.DISP22
|
2399 | f930d07e | blueswir1 | #define imm22 disp22
|
2400 | f930d07e | blueswir1 | } branch;
|
2401 | aa0aa4fa | bellard | struct
|
2402 | f930d07e | blueswir1 | {
|
2403 | f930d07e | blueswir1 | unsigned int anop:2;
|
2404 | f930d07e | blueswir1 | unsigned int a:1;
|
2405 | f930d07e | blueswir1 | unsigned int z:1;
|
2406 | f930d07e | blueswir1 | unsigned int rcond:3;
|
2407 | f930d07e | blueswir1 | unsigned int op2:3;
|
2408 | f930d07e | blueswir1 | unsigned int DISP16HI:2;
|
2409 | f930d07e | blueswir1 | unsigned int p:1;
|
2410 | f930d07e | blueswir1 | unsigned int _rs1:5;
|
2411 | f930d07e | blueswir1 | unsigned int DISP16LO:14;
|
2412 | f930d07e | blueswir1 | } branch16;
|
2413 | aa0aa4fa | bellard | struct
|
2414 | f930d07e | blueswir1 | {
|
2415 | f930d07e | blueswir1 | unsigned int anop:2;
|
2416 | f930d07e | blueswir1 | unsigned int adisp30:30;
|
2417 | f930d07e | blueswir1 | #define disp30 call.adisp30
|
2418 | f930d07e | blueswir1 | } call;
|
2419 | 46f42f29 | blueswir1 | }; */
|
2420 | aa0aa4fa | bellard | |
2421 | aa0aa4fa | bellard | /* Nonzero if INSN is the opcode for a delayed branch. */
|
2422 | 46f42f29 | blueswir1 | |
2423 | aa0aa4fa | bellard | static int |
2424 | 46f42f29 | blueswir1 | is_delayed_branch (unsigned long insn) |
2425 | aa0aa4fa | bellard | { |
2426 | 46f42f29 | blueswir1 | sparc_opcode_hash *op; |
2427 | aa0aa4fa | bellard | |
2428 | aa0aa4fa | bellard | for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
|
2429 | aa0aa4fa | bellard | { |
2430 | 46f42f29 | blueswir1 | const sparc_opcode *opcode = op->opcode;
|
2431 | 46f42f29 | blueswir1 | |
2432 | aa0aa4fa | bellard | if ((opcode->match & insn) == opcode->match
|
2433 | f930d07e | blueswir1 | && (opcode->lose & insn) == 0)
|
2434 | 46f42f29 | blueswir1 | return opcode->flags & F_DELAYED;
|
2435 | aa0aa4fa | bellard | } |
2436 | aa0aa4fa | bellard | return 0; |
2437 | aa0aa4fa | bellard | } |
2438 | aa0aa4fa | bellard | |
2439 | aa0aa4fa | bellard | /* extern void qsort (); */
|
2440 | aa0aa4fa | bellard | |
2441 | aa0aa4fa | bellard | /* Records current mask of SPARC_OPCODE_ARCH_FOO values, used to pass value
|
2442 | aa0aa4fa | bellard | to compare_opcodes. */
|
2443 | aa0aa4fa | bellard | static unsigned int current_arch_mask; |
2444 | aa0aa4fa | bellard | |
2445 | 46f42f29 | blueswir1 | /* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */
|
2446 | 46f42f29 | blueswir1 | |
2447 | 46f42f29 | blueswir1 | static int |
2448 | 46f42f29 | blueswir1 | compute_arch_mask (unsigned long mach) |
2449 | 46f42f29 | blueswir1 | { |
2450 | 46f42f29 | blueswir1 | switch (mach)
|
2451 | 46f42f29 | blueswir1 | { |
2452 | 46f42f29 | blueswir1 | case 0 : |
2453 | 46f42f29 | blueswir1 | case bfd_mach_sparc :
|
2454 | 46f42f29 | blueswir1 | return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8);
|
2455 | 46f42f29 | blueswir1 | case bfd_mach_sparc_sparclet :
|
2456 | 46f42f29 | blueswir1 | return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET);
|
2457 | 46f42f29 | blueswir1 | case bfd_mach_sparc_sparclite :
|
2458 | 46f42f29 | blueswir1 | case bfd_mach_sparc_sparclite_le :
|
2459 | 46f42f29 | blueswir1 | /* sparclites insns are recognized by default (because that's how
|
2460 | 46f42f29 | blueswir1 | they've always been treated, for better or worse). Kludge this by
|
2461 | 46f42f29 | blueswir1 | indicating generic v8 is also selected. */
|
2462 | 46f42f29 | blueswir1 | return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
|
2463 | 46f42f29 | blueswir1 | | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)); |
2464 | 46f42f29 | blueswir1 | case bfd_mach_sparc_v8plus :
|
2465 | 46f42f29 | blueswir1 | case bfd_mach_sparc_v9 :
|
2466 | 46f42f29 | blueswir1 | return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
|
2467 | 46f42f29 | blueswir1 | case bfd_mach_sparc_v8plusa :
|
2468 | 46f42f29 | blueswir1 | case bfd_mach_sparc_v9a :
|
2469 | 46f42f29 | blueswir1 | return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A);
|
2470 | 46f42f29 | blueswir1 | case bfd_mach_sparc_v8plusb :
|
2471 | 46f42f29 | blueswir1 | case bfd_mach_sparc_v9b :
|
2472 | 46f42f29 | blueswir1 | return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B);
|
2473 | 46f42f29 | blueswir1 | } |
2474 | 46f42f29 | blueswir1 | abort (); |
2475 | 46f42f29 | blueswir1 | } |
2476 | 46f42f29 | blueswir1 | |
2477 | 46f42f29 | blueswir1 | /* Compare opcodes A and B. */
|
2478 | 46f42f29 | blueswir1 | |
2479 | 46f42f29 | blueswir1 | static int |
2480 | 46f42f29 | blueswir1 | compare_opcodes (const void * a, const void * b) |
2481 | 46f42f29 | blueswir1 | { |
2482 | 46f42f29 | blueswir1 | sparc_opcode *op0 = * (sparc_opcode **) a; |
2483 | 46f42f29 | blueswir1 | sparc_opcode *op1 = * (sparc_opcode **) b; |
2484 | 46f42f29 | blueswir1 | unsigned long int match0 = op0->match, match1 = op1->match; |
2485 | 46f42f29 | blueswir1 | unsigned long int lose0 = op0->lose, lose1 = op1->lose; |
2486 | 46f42f29 | blueswir1 | register unsigned int i; |
2487 | 46f42f29 | blueswir1 | |
2488 | 46f42f29 | blueswir1 | /* If one (and only one) insn isn't supported by the current architecture,
|
2489 | 46f42f29 | blueswir1 | prefer the one that is. If neither are supported, but they're both for
|
2490 | 46f42f29 | blueswir1 | the same architecture, continue processing. Otherwise (both unsupported
|
2491 | 46f42f29 | blueswir1 | and for different architectures), prefer lower numbered arch's (fudged
|
2492 | 46f42f29 | blueswir1 | by comparing the bitmasks). */
|
2493 | 46f42f29 | blueswir1 | if (op0->architecture & current_arch_mask)
|
2494 | 46f42f29 | blueswir1 | { |
2495 | 46f42f29 | blueswir1 | if (! (op1->architecture & current_arch_mask))
|
2496 | 46f42f29 | blueswir1 | return -1; |
2497 | 46f42f29 | blueswir1 | } |
2498 | 46f42f29 | blueswir1 | else
|
2499 | 46f42f29 | blueswir1 | { |
2500 | 46f42f29 | blueswir1 | if (op1->architecture & current_arch_mask)
|
2501 | 46f42f29 | blueswir1 | return 1; |
2502 | 46f42f29 | blueswir1 | else if (op0->architecture != op1->architecture) |
2503 | 46f42f29 | blueswir1 | return op0->architecture - op1->architecture;
|
2504 | 46f42f29 | blueswir1 | } |
2505 | 46f42f29 | blueswir1 | |
2506 | 46f42f29 | blueswir1 | /* If a bit is set in both match and lose, there is something
|
2507 | 46f42f29 | blueswir1 | wrong with the opcode table. */
|
2508 | 46f42f29 | blueswir1 | if (match0 & lose0)
|
2509 | 46f42f29 | blueswir1 | { |
2510 | 46f42f29 | blueswir1 | fprintf |
2511 | 46f42f29 | blueswir1 | (stderr, |
2512 | 46f42f29 | blueswir1 | /* xgettext:c-format */
|
2513 | 46f42f29 | blueswir1 | _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
|
2514 | 46f42f29 | blueswir1 | op0->name, match0, lose0); |
2515 | 46f42f29 | blueswir1 | op0->lose &= ~op0->match; |
2516 | 46f42f29 | blueswir1 | lose0 = op0->lose; |
2517 | 46f42f29 | blueswir1 | } |
2518 | 46f42f29 | blueswir1 | |
2519 | 46f42f29 | blueswir1 | if (match1 & lose1)
|
2520 | 46f42f29 | blueswir1 | { |
2521 | 46f42f29 | blueswir1 | fprintf |
2522 | 46f42f29 | blueswir1 | (stderr, |
2523 | 46f42f29 | blueswir1 | /* xgettext:c-format */
|
2524 | 46f42f29 | blueswir1 | _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
|
2525 | 46f42f29 | blueswir1 | op1->name, match1, lose1); |
2526 | 46f42f29 | blueswir1 | op1->lose &= ~op1->match; |
2527 | 46f42f29 | blueswir1 | lose1 = op1->lose; |
2528 | 46f42f29 | blueswir1 | } |
2529 | 46f42f29 | blueswir1 | |
2530 | 46f42f29 | blueswir1 | /* Because the bits that are variable in one opcode are constant in
|
2531 | 46f42f29 | blueswir1 | another, it is important to order the opcodes in the right order. */
|
2532 | 46f42f29 | blueswir1 | for (i = 0; i < 32; ++i) |
2533 | 46f42f29 | blueswir1 | { |
2534 | 46f42f29 | blueswir1 | unsigned long int x = 1 << i; |
2535 | 46f42f29 | blueswir1 | int x0 = (match0 & x) != 0; |
2536 | 46f42f29 | blueswir1 | int x1 = (match1 & x) != 0; |
2537 | 46f42f29 | blueswir1 | |
2538 | 46f42f29 | blueswir1 | if (x0 != x1)
|
2539 | 46f42f29 | blueswir1 | return x1 - x0;
|
2540 | 46f42f29 | blueswir1 | } |
2541 | 46f42f29 | blueswir1 | |
2542 | 46f42f29 | blueswir1 | for (i = 0; i < 32; ++i) |
2543 | 46f42f29 | blueswir1 | { |
2544 | 46f42f29 | blueswir1 | unsigned long int x = 1 << i; |
2545 | 46f42f29 | blueswir1 | int x0 = (lose0 & x) != 0; |
2546 | 46f42f29 | blueswir1 | int x1 = (lose1 & x) != 0; |
2547 | 46f42f29 | blueswir1 | |
2548 | 46f42f29 | blueswir1 | if (x0 != x1)
|
2549 | 46f42f29 | blueswir1 | return x1 - x0;
|
2550 | 46f42f29 | blueswir1 | } |
2551 | 46f42f29 | blueswir1 | |
2552 | 46f42f29 | blueswir1 | /* They are functionally equal. So as long as the opcode table is
|
2553 | 46f42f29 | blueswir1 | valid, we can put whichever one first we want, on aesthetic grounds. */
|
2554 | 46f42f29 | blueswir1 | |
2555 | 46f42f29 | blueswir1 | /* Our first aesthetic ground is that aliases defer to real insns. */
|
2556 | 46f42f29 | blueswir1 | { |
2557 | 46f42f29 | blueswir1 | int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
|
2558 | 46f42f29 | blueswir1 | |
2559 | 46f42f29 | blueswir1 | if (alias_diff != 0) |
2560 | 46f42f29 | blueswir1 | /* Put the one that isn't an alias first. */
|
2561 | 46f42f29 | blueswir1 | return alias_diff;
|
2562 | 46f42f29 | blueswir1 | } |
2563 | 46f42f29 | blueswir1 | |
2564 | 46f42f29 | blueswir1 | /* Except for aliases, two "identical" instructions had
|
2565 | 46f42f29 | blueswir1 | better have the same opcode. This is a sanity check on the table. */
|
2566 | 46f42f29 | blueswir1 | i = strcmp (op0->name, op1->name); |
2567 | 46f42f29 | blueswir1 | if (i)
|
2568 | 46f42f29 | blueswir1 | { |
2569 | 46f42f29 | blueswir1 | if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */ |
2570 | 46f42f29 | blueswir1 | return i;
|
2571 | 46f42f29 | blueswir1 | else
|
2572 | 46f42f29 | blueswir1 | fprintf (stderr, |
2573 | 46f42f29 | blueswir1 | /* xgettext:c-format */
|
2574 | 46f42f29 | blueswir1 | _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"),
|
2575 | 46f42f29 | blueswir1 | op0->name, op1->name); |
2576 | 46f42f29 | blueswir1 | } |
2577 | 46f42f29 | blueswir1 | |
2578 | 46f42f29 | blueswir1 | /* Fewer arguments are preferred. */
|
2579 | 46f42f29 | blueswir1 | { |
2580 | 46f42f29 | blueswir1 | int length_diff = strlen (op0->args) - strlen (op1->args);
|
2581 | 46f42f29 | blueswir1 | |
2582 | 46f42f29 | blueswir1 | if (length_diff != 0) |
2583 | 46f42f29 | blueswir1 | /* Put the one with fewer arguments first. */
|
2584 | 46f42f29 | blueswir1 | return length_diff;
|
2585 | 46f42f29 | blueswir1 | } |
2586 | 46f42f29 | blueswir1 | |
2587 | 46f42f29 | blueswir1 | /* Put 1+i before i+1. */
|
2588 | 46f42f29 | blueswir1 | { |
2589 | 46f42f29 | blueswir1 | char *p0 = (char *) strchr (op0->args, '+'); |
2590 | 46f42f29 | blueswir1 | char *p1 = (char *) strchr (op1->args, '+'); |
2591 | 46f42f29 | blueswir1 | |
2592 | 46f42f29 | blueswir1 | if (p0 && p1)
|
2593 | 46f42f29 | blueswir1 | { |
2594 | 46f42f29 | blueswir1 | /* There is a plus in both operands. Note that a plus
|
2595 | 46f42f29 | blueswir1 | sign cannot be the first character in args,
|
2596 | 46f42f29 | blueswir1 | so the following [-1]'s are valid. */
|
2597 | 46f42f29 | blueswir1 | if (p0[-1] == 'i' && p1[1] == 'i') |
2598 | 46f42f29 | blueswir1 | /* op0 is i+1 and op1 is 1+i, so op1 goes first. */
|
2599 | 46f42f29 | blueswir1 | return 1; |
2600 | 46f42f29 | blueswir1 | if (p0[1] == 'i' && p1[-1] == 'i') |
2601 | 46f42f29 | blueswir1 | /* op0 is 1+i and op1 is i+1, so op0 goes first. */
|
2602 | 46f42f29 | blueswir1 | return -1; |
2603 | 46f42f29 | blueswir1 | } |
2604 | 46f42f29 | blueswir1 | } |
2605 | 46f42f29 | blueswir1 | |
2606 | 46f42f29 | blueswir1 | /* Put 1,i before i,1. */
|
2607 | 46f42f29 | blueswir1 | { |
2608 | 46f42f29 | blueswir1 | int i0 = strncmp (op0->args, "i,1", 3) == 0; |
2609 | 46f42f29 | blueswir1 | int i1 = strncmp (op1->args, "i,1", 3) == 0; |
2610 | 46f42f29 | blueswir1 | |
2611 | 46f42f29 | blueswir1 | if (i0 ^ i1)
|
2612 | 46f42f29 | blueswir1 | return i0 - i1;
|
2613 | 46f42f29 | blueswir1 | } |
2614 | 46f42f29 | blueswir1 | |
2615 | 46f42f29 | blueswir1 | /* They are, as far as we can tell, identical.
|
2616 | 46f42f29 | blueswir1 | Since qsort may have rearranged the table partially, there is
|
2617 | 46f42f29 | blueswir1 | no way to tell which one was first in the opcode table as
|
2618 | 46f42f29 | blueswir1 | written, so just say there are equal. */
|
2619 | 46f42f29 | blueswir1 | /* ??? This is no longer true now that we sort a vector of pointers,
|
2620 | 46f42f29 | blueswir1 | not the table itself. */
|
2621 | 46f42f29 | blueswir1 | return 0; |
2622 | 46f42f29 | blueswir1 | } |
2623 | 46f42f29 | blueswir1 | |
2624 | 46f42f29 | blueswir1 | /* Build a hash table from the opcode table.
|
2625 | 46f42f29 | blueswir1 | OPCODE_TABLE is a sorted list of pointers into the opcode table. */
|
2626 | 46f42f29 | blueswir1 | |
2627 | 46f42f29 | blueswir1 | static void |
2628 | 46f42f29 | blueswir1 | build_hash_table (const sparc_opcode **opcode_table,
|
2629 | 46f42f29 | blueswir1 | sparc_opcode_hash **hash_table, |
2630 | 46f42f29 | blueswir1 | int num_opcodes)
|
2631 | 46f42f29 | blueswir1 | { |
2632 | 46f42f29 | blueswir1 | int i;
|
2633 | 46f42f29 | blueswir1 | int hash_count[HASH_SIZE];
|
2634 | 46f42f29 | blueswir1 | static sparc_opcode_hash *hash_buf = NULL; |
2635 | 46f42f29 | blueswir1 | |
2636 | 46f42f29 | blueswir1 | /* Start at the end of the table and work backwards so that each
|
2637 | 46f42f29 | blueswir1 | chain is sorted. */
|
2638 | 46f42f29 | blueswir1 | |
2639 | 46f42f29 | blueswir1 | memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0])); |
2640 | 46f42f29 | blueswir1 | memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0])); |
2641 | 46f42f29 | blueswir1 | if (hash_buf != NULL) |
2642 | 46f42f29 | blueswir1 | free (hash_buf); |
2643 | 46f42f29 | blueswir1 | hash_buf = malloc (sizeof (* hash_buf) * num_opcodes);
|
2644 | 46f42f29 | blueswir1 | for (i = num_opcodes - 1; i >= 0; --i) |
2645 | 46f42f29 | blueswir1 | { |
2646 | 46f42f29 | blueswir1 | int hash = HASH_INSN (opcode_table[i]->match);
|
2647 | 46f42f29 | blueswir1 | sparc_opcode_hash *h = &hash_buf[i]; |
2648 | 46f42f29 | blueswir1 | |
2649 | 46f42f29 | blueswir1 | h->next = hash_table[hash]; |
2650 | 46f42f29 | blueswir1 | h->opcode = opcode_table[i]; |
2651 | 46f42f29 | blueswir1 | hash_table[hash] = h; |
2652 | 46f42f29 | blueswir1 | ++hash_count[hash]; |
2653 | 46f42f29 | blueswir1 | } |
2654 | 46f42f29 | blueswir1 | |
2655 | 46f42f29 | blueswir1 | #if 0 /* for debugging */
|
2656 | 46f42f29 | blueswir1 | {
|
2657 | 46f42f29 | blueswir1 | int min_count = num_opcodes, max_count = 0;
|
2658 | 46f42f29 | blueswir1 | int total;
|
2659 | 46f42f29 | blueswir1 | |
2660 | 46f42f29 | blueswir1 | for (i = 0; i < HASH_SIZE; ++i)
|
2661 | 46f42f29 | blueswir1 | {
|
2662 | 46f42f29 | blueswir1 | if (hash_count[i] < min_count)
|
2663 | 46f42f29 | blueswir1 | min_count = hash_count[i];
|
2664 | 46f42f29 | blueswir1 | if (hash_count[i] > max_count)
|
2665 | 46f42f29 | blueswir1 | max_count = hash_count[i];
|
2666 | 46f42f29 | blueswir1 | total += hash_count[i];
|
2667 | 46f42f29 | blueswir1 | }
|
2668 | 46f42f29 | blueswir1 | |
2669 | 46f42f29 | blueswir1 | printf ("Opcode hash table stats: min %d, max %d, ave %f\n",
|
2670 | 46f42f29 | blueswir1 | min_count, max_count, (double) total / HASH_SIZE);
|
2671 | 46f42f29 | blueswir1 | }
|
2672 | 46f42f29 | blueswir1 | #endif
|
2673 | 46f42f29 | blueswir1 | } |
2674 | 46f42f29 | blueswir1 | |
2675 | aa0aa4fa | bellard | /* Print one instruction from MEMADDR on INFO->STREAM.
|
2676 | aa0aa4fa | bellard | |
2677 | aa0aa4fa | bellard | We suffix the instruction with a comment that gives the absolute
|
2678 | aa0aa4fa | bellard | address involved, as well as its symbolic form, if the instruction
|
2679 | aa0aa4fa | bellard | is preceded by a findable `sethi' and it either adds an immediate
|
2680 | aa0aa4fa | bellard | displacement to that register, or it is an `add' or `or' instruction
|
2681 | aa0aa4fa | bellard | on that register. */
|
2682 | aa0aa4fa | bellard | |
2683 | aa0aa4fa | bellard | int
|
2684 | 46f42f29 | blueswir1 | print_insn_sparc (bfd_vma memaddr, disassemble_info *info) |
2685 | aa0aa4fa | bellard | { |
2686 | aa0aa4fa | bellard | FILE *stream = info->stream; |
2687 | aa0aa4fa | bellard | bfd_byte buffer[4];
|
2688 | aa0aa4fa | bellard | unsigned long insn; |
2689 | 46f42f29 | blueswir1 | sparc_opcode_hash *op; |
2690 | aa0aa4fa | bellard | /* Nonzero of opcode table has been initialized. */
|
2691 | aa0aa4fa | bellard | static int opcodes_initialized = 0; |
2692 | aa0aa4fa | bellard | /* bfd mach number of last call. */
|
2693 | aa0aa4fa | bellard | static unsigned long current_mach = 0; |
2694 | 46f42f29 | blueswir1 | bfd_vma (*getword) (const unsigned char *); |
2695 | aa0aa4fa | bellard | |
2696 | aa0aa4fa | bellard | if (!opcodes_initialized
|
2697 | aa0aa4fa | bellard | || info->mach != current_mach) |
2698 | aa0aa4fa | bellard | { |
2699 | aa0aa4fa | bellard | int i;
|
2700 | aa0aa4fa | bellard | |
2701 | aa0aa4fa | bellard | current_arch_mask = compute_arch_mask (info->mach); |
2702 | aa0aa4fa | bellard | |
2703 | aa0aa4fa | bellard | if (!opcodes_initialized)
|
2704 | 46f42f29 | blueswir1 | sorted_opcodes = |
2705 | 46f42f29 | blueswir1 | malloc (sparc_num_opcodes * sizeof (sparc_opcode *));
|
2706 | aa0aa4fa | bellard | /* Reset the sorted table so we can resort it. */
|
2707 | aa0aa4fa | bellard | for (i = 0; i < sparc_num_opcodes; ++i) |
2708 | f930d07e | blueswir1 | sorted_opcodes[i] = &sparc_opcodes[i]; |
2709 | aa0aa4fa | bellard | qsort ((char *) sorted_opcodes, sparc_num_opcodes,
|
2710 | f930d07e | blueswir1 | sizeof (sorted_opcodes[0]), compare_opcodes); |
2711 | aa0aa4fa | bellard | |
2712 | aa0aa4fa | bellard | build_hash_table (sorted_opcodes, opcode_hash_table, sparc_num_opcodes); |
2713 | aa0aa4fa | bellard | current_mach = info->mach; |
2714 | aa0aa4fa | bellard | opcodes_initialized = 1;
|
2715 | aa0aa4fa | bellard | } |
2716 | aa0aa4fa | bellard | |
2717 | aa0aa4fa | bellard | { |
2718 | aa0aa4fa | bellard | int status =
|
2719 | aa0aa4fa | bellard | (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
|
2720 | 46f42f29 | blueswir1 | |
2721 | aa0aa4fa | bellard | if (status != 0) |
2722 | aa0aa4fa | bellard | { |
2723 | f930d07e | blueswir1 | (*info->memory_error_func) (status, memaddr, info); |
2724 | f930d07e | blueswir1 | return -1; |
2725 | aa0aa4fa | bellard | } |
2726 | aa0aa4fa | bellard | } |
2727 | aa0aa4fa | bellard | |
2728 | aa0aa4fa | bellard | /* On SPARClite variants such as DANlite (sparc86x), instructions
|
2729 | 46f42f29 | blueswir1 | are always big-endian even when the machine is in little-endian mode. */
|
2730 | aa0aa4fa | bellard | if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite)
|
2731 | aa0aa4fa | bellard | getword = bfd_getb32; |
2732 | aa0aa4fa | bellard | else
|
2733 | aa0aa4fa | bellard | getword = bfd_getl32; |
2734 | aa0aa4fa | bellard | |
2735 | aa0aa4fa | bellard | insn = getword (buffer); |
2736 | aa0aa4fa | bellard | |
2737 | 46f42f29 | blueswir1 | info->insn_info_valid = 1; /* We do return this info. */ |
2738 | 46f42f29 | blueswir1 | info->insn_type = dis_nonbranch; /* Assume non branch insn. */
|
2739 | 46f42f29 | blueswir1 | info->branch_delay_insns = 0; /* Assume no delay. */ |
2740 | 46f42f29 | blueswir1 | info->target = 0; /* Assume no target known. */ |
2741 | aa0aa4fa | bellard | |
2742 | aa0aa4fa | bellard | for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
|
2743 | aa0aa4fa | bellard | { |
2744 | 46f42f29 | blueswir1 | const sparc_opcode *opcode = op->opcode;
|
2745 | aa0aa4fa | bellard | |
2746 | aa0aa4fa | bellard | /* If the insn isn't supported by the current architecture, skip it. */
|
2747 | aa0aa4fa | bellard | if (! (opcode->architecture & current_arch_mask))
|
2748 | f930d07e | blueswir1 | continue;
|
2749 | aa0aa4fa | bellard | |
2750 | aa0aa4fa | bellard | if ((opcode->match & insn) == opcode->match
|
2751 | f930d07e | blueswir1 | && (opcode->lose & insn) == 0)
|
2752 | f930d07e | blueswir1 | { |
2753 | f930d07e | blueswir1 | /* Nonzero means that we have found an instruction which has
|
2754 | f930d07e | blueswir1 | the effect of adding or or'ing the imm13 field to rs1. */
|
2755 | f930d07e | blueswir1 | int imm_added_to_rs1 = 0; |
2756 | f930d07e | blueswir1 | int imm_ored_to_rs1 = 0; |
2757 | aa0aa4fa | bellard | |
2758 | f930d07e | blueswir1 | /* Nonzero means that we have found a plus sign in the args
|
2759 | f930d07e | blueswir1 | field of the opcode table. */
|
2760 | f930d07e | blueswir1 | int found_plus = 0; |
2761 | 3b46e624 | ths | |
2762 | f930d07e | blueswir1 | /* Nonzero means we have an annulled branch. */
|
2763 | f930d07e | blueswir1 | int is_annulled = 0; |
2764 | aa0aa4fa | bellard | |
2765 | f930d07e | blueswir1 | /* Do we have an `add' or `or' instruction combining an
|
2766 | aa0aa4fa | bellard | immediate with rs1? */
|
2767 | f930d07e | blueswir1 | if (opcode->match == 0x80102000) /* or */ |
2768 | f930d07e | blueswir1 | imm_ored_to_rs1 = 1;
|
2769 | f930d07e | blueswir1 | if (opcode->match == 0x80002000) /* add */ |
2770 | f930d07e | blueswir1 | imm_added_to_rs1 = 1;
|
2771 | f930d07e | blueswir1 | |
2772 | f930d07e | blueswir1 | if (X_RS1 (insn) != X_RD (insn)
|
2773 | 660f11be | Blue Swirl | && strchr (opcode->args, 'r') != NULL) |
2774 | f930d07e | blueswir1 | /* Can't do simple format if source and dest are different. */
|
2775 | f930d07e | blueswir1 | continue;
|
2776 | f930d07e | blueswir1 | if (X_RS2 (insn) != X_RD (insn)
|
2777 | 660f11be | Blue Swirl | && strchr (opcode->args, 'O') != NULL) |
2778 | f930d07e | blueswir1 | /* Can't do simple format if source and dest are different. */
|
2779 | f930d07e | blueswir1 | continue;
|
2780 | f930d07e | blueswir1 | |
2781 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, opcode->name); |
2782 | f930d07e | blueswir1 | |
2783 | f930d07e | blueswir1 | { |
2784 | 46f42f29 | blueswir1 | const char *s; |
2785 | f930d07e | blueswir1 | |
2786 | f930d07e | blueswir1 | if (opcode->args[0] != ',') |
2787 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, " ");
|
2788 | 46f42f29 | blueswir1 | |
2789 | f930d07e | blueswir1 | for (s = opcode->args; *s != '\0'; ++s) |
2790 | f930d07e | blueswir1 | { |
2791 | f930d07e | blueswir1 | while (*s == ',') |
2792 | f930d07e | blueswir1 | { |
2793 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, ",");
|
2794 | f930d07e | blueswir1 | ++s; |
2795 | 46f42f29 | blueswir1 | switch (*s)
|
2796 | 46f42f29 | blueswir1 | { |
2797 | 46f42f29 | blueswir1 | case 'a': |
2798 | 46f42f29 | blueswir1 | (*info->fprintf_func) (stream, "a");
|
2799 | 46f42f29 | blueswir1 | is_annulled = 1;
|
2800 | 46f42f29 | blueswir1 | ++s; |
2801 | 46f42f29 | blueswir1 | continue;
|
2802 | 46f42f29 | blueswir1 | case 'N': |
2803 | 46f42f29 | blueswir1 | (*info->fprintf_func) (stream, "pn");
|
2804 | 46f42f29 | blueswir1 | ++s; |
2805 | 46f42f29 | blueswir1 | continue;
|
2806 | 46f42f29 | blueswir1 | |
2807 | 46f42f29 | blueswir1 | case 'T': |
2808 | 46f42f29 | blueswir1 | (*info->fprintf_func) (stream, "pt");
|
2809 | 46f42f29 | blueswir1 | ++s; |
2810 | 46f42f29 | blueswir1 | continue;
|
2811 | 46f42f29 | blueswir1 | |
2812 | 46f42f29 | blueswir1 | default:
|
2813 | 46f42f29 | blueswir1 | break;
|
2814 | 46f42f29 | blueswir1 | } |
2815 | 46f42f29 | blueswir1 | } |
2816 | f930d07e | blueswir1 | |
2817 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, " ");
|
2818 | f930d07e | blueswir1 | |
2819 | f930d07e | blueswir1 | switch (*s)
|
2820 | f930d07e | blueswir1 | { |
2821 | f930d07e | blueswir1 | case '+': |
2822 | f930d07e | blueswir1 | found_plus = 1;
|
2823 | 46f42f29 | blueswir1 | /* Fall through. */
|
2824 | f930d07e | blueswir1 | |
2825 | f930d07e | blueswir1 | default:
|
2826 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, "%c", *s);
|
2827 | f930d07e | blueswir1 | break;
|
2828 | f930d07e | blueswir1 | |
2829 | f930d07e | blueswir1 | case '#': |
2830 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, "0");
|
2831 | f930d07e | blueswir1 | break;
|
2832 | f930d07e | blueswir1 | |
2833 | f930d07e | blueswir1 | #define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n]) |
2834 | f930d07e | blueswir1 | case '1': |
2835 | f930d07e | blueswir1 | case 'r': |
2836 | f930d07e | blueswir1 | reg (X_RS1 (insn)); |
2837 | f930d07e | blueswir1 | break;
|
2838 | f930d07e | blueswir1 | |
2839 | f930d07e | blueswir1 | case '2': |
2840 | f930d07e | blueswir1 | case 'O': |
2841 | f930d07e | blueswir1 | reg (X_RS2 (insn)); |
2842 | f930d07e | blueswir1 | break;
|
2843 | f930d07e | blueswir1 | |
2844 | f930d07e | blueswir1 | case 'd': |
2845 | f930d07e | blueswir1 | reg (X_RD (insn)); |
2846 | f930d07e | blueswir1 | break;
|
2847 | f930d07e | blueswir1 | #undef reg
|
2848 | f930d07e | blueswir1 | |
2849 | f930d07e | blueswir1 | #define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n]) |
2850 | f930d07e | blueswir1 | #define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)]) |
2851 | f930d07e | blueswir1 | case 'e': |
2852 | f930d07e | blueswir1 | freg (X_RS1 (insn)); |
2853 | f930d07e | blueswir1 | break;
|
2854 | 46f42f29 | blueswir1 | case 'v': /* Double/even. */ |
2855 | 46f42f29 | blueswir1 | case 'V': /* Quad/multiple of 4. */ |
2856 | f930d07e | blueswir1 | fregx (X_RS1 (insn)); |
2857 | f930d07e | blueswir1 | break;
|
2858 | f930d07e | blueswir1 | |
2859 | f930d07e | blueswir1 | case 'f': |
2860 | f930d07e | blueswir1 | freg (X_RS2 (insn)); |
2861 | f930d07e | blueswir1 | break;
|
2862 | 46f42f29 | blueswir1 | case 'B': /* Double/even. */ |
2863 | 46f42f29 | blueswir1 | case 'R': /* Quad/multiple of 4. */ |
2864 | f930d07e | blueswir1 | fregx (X_RS2 (insn)); |
2865 | f930d07e | blueswir1 | break;
|
2866 | f930d07e | blueswir1 | |
2867 | f930d07e | blueswir1 | case 'g': |
2868 | f930d07e | blueswir1 | freg (X_RD (insn)); |
2869 | f930d07e | blueswir1 | break;
|
2870 | 46f42f29 | blueswir1 | case 'H': /* Double/even. */ |
2871 | 46f42f29 | blueswir1 | case 'J': /* Quad/multiple of 4. */ |
2872 | f930d07e | blueswir1 | fregx (X_RD (insn)); |
2873 | f930d07e | blueswir1 | break;
|
2874 | f930d07e | blueswir1 | #undef freg
|
2875 | f930d07e | blueswir1 | #undef fregx
|
2876 | f930d07e | blueswir1 | |
2877 | f930d07e | blueswir1 | #define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n)) |
2878 | f930d07e | blueswir1 | case 'b': |
2879 | f930d07e | blueswir1 | creg (X_RS1 (insn)); |
2880 | f930d07e | blueswir1 | break;
|
2881 | f930d07e | blueswir1 | |
2882 | f930d07e | blueswir1 | case 'c': |
2883 | f930d07e | blueswir1 | creg (X_RS2 (insn)); |
2884 | f930d07e | blueswir1 | break;
|
2885 | f930d07e | blueswir1 | |
2886 | f930d07e | blueswir1 | case 'D': |
2887 | f930d07e | blueswir1 | creg (X_RD (insn)); |
2888 | f930d07e | blueswir1 | break;
|
2889 | f930d07e | blueswir1 | #undef creg
|
2890 | f930d07e | blueswir1 | |
2891 | f930d07e | blueswir1 | case 'h': |
2892 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, "%%hi(%#x)",
|
2893 | f930d07e | blueswir1 | ((unsigned) 0xFFFFFFFF |
2894 | f930d07e | blueswir1 | & ((int) X_IMM22 (insn) << 10))); |
2895 | f930d07e | blueswir1 | break;
|
2896 | f930d07e | blueswir1 | |
2897 | 46f42f29 | blueswir1 | case 'i': /* 13 bit immediate. */ |
2898 | 46f42f29 | blueswir1 | case 'I': /* 11 bit immediate. */ |
2899 | 46f42f29 | blueswir1 | case 'j': /* 10 bit immediate. */ |
2900 | f930d07e | blueswir1 | { |
2901 | f930d07e | blueswir1 | int imm;
|
2902 | f930d07e | blueswir1 | |
2903 | f930d07e | blueswir1 | if (*s == 'i') |
2904 | f930d07e | blueswir1 | imm = X_SIMM (insn, 13);
|
2905 | f930d07e | blueswir1 | else if (*s == 'I') |
2906 | f930d07e | blueswir1 | imm = X_SIMM (insn, 11);
|
2907 | f930d07e | blueswir1 | else
|
2908 | f930d07e | blueswir1 | imm = X_SIMM (insn, 10);
|
2909 | f930d07e | blueswir1 | |
2910 | f930d07e | blueswir1 | /* Check to see whether we have a 1+i, and take
|
2911 | f930d07e | blueswir1 | note of that fact.
|
2912 | f930d07e | blueswir1 | |
2913 | f930d07e | blueswir1 | Note: because of the way we sort the table,
|
2914 | f930d07e | blueswir1 | we will be matching 1+i rather than i+1,
|
2915 | f930d07e | blueswir1 | so it is OK to assume that i is after +,
|
2916 | f930d07e | blueswir1 | not before it. */
|
2917 | f930d07e | blueswir1 | if (found_plus)
|
2918 | f930d07e | blueswir1 | imm_added_to_rs1 = 1;
|
2919 | f930d07e | blueswir1 | |
2920 | f930d07e | blueswir1 | if (imm <= 9) |
2921 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, "%d", imm);
|
2922 | f930d07e | blueswir1 | else
|
2923 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, "%#x", imm);
|
2924 | f930d07e | blueswir1 | } |
2925 | f930d07e | blueswir1 | break;
|
2926 | f930d07e | blueswir1 | |
2927 | 46f42f29 | blueswir1 | case 'X': /* 5 bit unsigned immediate. */ |
2928 | 46f42f29 | blueswir1 | case 'Y': /* 6 bit unsigned immediate. */ |
2929 | f930d07e | blueswir1 | { |
2930 | f930d07e | blueswir1 | int imm = X_IMM (insn, *s == 'X' ? 5 : 6); |
2931 | f930d07e | blueswir1 | |
2932 | f930d07e | blueswir1 | if (imm <= 9) |
2933 | f930d07e | blueswir1 | (info->fprintf_func) (stream, "%d", imm);
|
2934 | f930d07e | blueswir1 | else
|
2935 | f930d07e | blueswir1 | (info->fprintf_func) (stream, "%#x", (unsigned) imm); |
2936 | f930d07e | blueswir1 | } |
2937 | f930d07e | blueswir1 | break;
|
2938 | f930d07e | blueswir1 | |
2939 | f930d07e | blueswir1 | case '3': |
2940 | 46f42f29 | blueswir1 | (info->fprintf_func) (stream, "%ld", X_IMM (insn, 3)); |
2941 | f930d07e | blueswir1 | break;
|
2942 | f930d07e | blueswir1 | |
2943 | f930d07e | blueswir1 | case 'K': |
2944 | f930d07e | blueswir1 | { |
2945 | f930d07e | blueswir1 | int mask = X_MEMBAR (insn);
|
2946 | f930d07e | blueswir1 | int bit = 0x40, printed_one = 0; |
2947 | f930d07e | blueswir1 | const char *name; |
2948 | f930d07e | blueswir1 | |
2949 | f930d07e | blueswir1 | if (mask == 0) |
2950 | f930d07e | blueswir1 | (info->fprintf_func) (stream, "0");
|
2951 | f930d07e | blueswir1 | else
|
2952 | f930d07e | blueswir1 | while (bit)
|
2953 | f930d07e | blueswir1 | { |
2954 | f930d07e | blueswir1 | if (mask & bit)
|
2955 | f930d07e | blueswir1 | { |
2956 | f930d07e | blueswir1 | if (printed_one)
|
2957 | f930d07e | blueswir1 | (info->fprintf_func) (stream, "|");
|
2958 | f930d07e | blueswir1 | name = sparc_decode_membar (bit); |
2959 | f930d07e | blueswir1 | (info->fprintf_func) (stream, "%s", name);
|
2960 | f930d07e | blueswir1 | printed_one = 1;
|
2961 | f930d07e | blueswir1 | } |
2962 | f930d07e | blueswir1 | bit >>= 1;
|
2963 | f930d07e | blueswir1 | } |
2964 | f930d07e | blueswir1 | break;
|
2965 | f930d07e | blueswir1 | } |
2966 | f930d07e | blueswir1 | |
2967 | f930d07e | blueswir1 | case 'k': |
2968 | f930d07e | blueswir1 | info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4; |
2969 | f930d07e | blueswir1 | (*info->print_address_func) (info->target, info); |
2970 | f930d07e | blueswir1 | break;
|
2971 | f930d07e | blueswir1 | |
2972 | f930d07e | blueswir1 | case 'G': |
2973 | f930d07e | blueswir1 | info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4; |
2974 | f930d07e | blueswir1 | (*info->print_address_func) (info->target, info); |
2975 | f930d07e | blueswir1 | break;
|
2976 | f930d07e | blueswir1 | |
2977 | f930d07e | blueswir1 | case '6': |
2978 | f930d07e | blueswir1 | case '7': |
2979 | f930d07e | blueswir1 | case '8': |
2980 | f930d07e | blueswir1 | case '9': |
2981 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0'); |
2982 | f930d07e | blueswir1 | break;
|
2983 | f930d07e | blueswir1 | |
2984 | f930d07e | blueswir1 | case 'z': |
2985 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, "%%icc");
|
2986 | f930d07e | blueswir1 | break;
|
2987 | f930d07e | blueswir1 | |
2988 | f930d07e | blueswir1 | case 'Z': |
2989 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, "%%xcc");
|
2990 | f930d07e | blueswir1 | break;
|
2991 | f930d07e | blueswir1 | |
2992 | f930d07e | blueswir1 | case 'E': |
2993 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, "%%ccr");
|
2994 | f930d07e | blueswir1 | break;
|
2995 | f930d07e | blueswir1 | |
2996 | f930d07e | blueswir1 | case 's': |
2997 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, "%%fprs");
|
2998 | f930d07e | blueswir1 | break;
|
2999 | f930d07e | blueswir1 | |
3000 | f930d07e | blueswir1 | case 'o': |
3001 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, "%%asi");
|
3002 | f930d07e | blueswir1 | break;
|
3003 | f930d07e | blueswir1 | |
3004 | f930d07e | blueswir1 | case 'W': |
3005 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, "%%tick");
|
3006 | f930d07e | blueswir1 | break;
|
3007 | f930d07e | blueswir1 | |
3008 | f930d07e | blueswir1 | case 'P': |
3009 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, "%%pc");
|
3010 | f930d07e | blueswir1 | break;
|
3011 | f930d07e | blueswir1 | |
3012 | f930d07e | blueswir1 | case '?': |
3013 | f930d07e | blueswir1 | if (X_RS1 (insn) == 31) |
3014 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, "%%ver");
|
3015 | 46f42f29 | blueswir1 | else if ((unsigned) X_RS1 (insn) < 17) |
3016 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, "%%%s",
|
3017 | f930d07e | blueswir1 | v9_priv_reg_names[X_RS1 (insn)]); |
3018 | f930d07e | blueswir1 | else
|
3019 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, "%%reserved");
|
3020 | f930d07e | blueswir1 | break;
|
3021 | f930d07e | blueswir1 | |
3022 | f930d07e | blueswir1 | case '!': |
3023 | 46f42f29 | blueswir1 | if ((unsigned) X_RD (insn) < 17) |
3024 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, "%%%s",
|
3025 | f930d07e | blueswir1 | v9_priv_reg_names[X_RD (insn)]); |
3026 | f930d07e | blueswir1 | else
|
3027 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, "%%reserved");
|
3028 | f930d07e | blueswir1 | break;
|
3029 | f930d07e | blueswir1 | |
3030 | 46f42f29 | blueswir1 | case '$': |
3031 | 46f42f29 | blueswir1 | if ((unsigned) X_RS1 (insn) < 32) |
3032 | 46f42f29 | blueswir1 | (*info->fprintf_func) (stream, "%%%s",
|
3033 | 46f42f29 | blueswir1 | v9_hpriv_reg_names[X_RS1 (insn)]); |
3034 | 46f42f29 | blueswir1 | else
|
3035 | 46f42f29 | blueswir1 | (*info->fprintf_func) (stream, "%%reserved");
|
3036 | 46f42f29 | blueswir1 | break;
|
3037 | 46f42f29 | blueswir1 | |
3038 | 46f42f29 | blueswir1 | case '%': |
3039 | 46f42f29 | blueswir1 | if ((unsigned) X_RD (insn) < 32) |
3040 | 46f42f29 | blueswir1 | (*info->fprintf_func) (stream, "%%%s",
|
3041 | 46f42f29 | blueswir1 | v9_hpriv_reg_names[X_RD (insn)]); |
3042 | 46f42f29 | blueswir1 | else
|
3043 | 46f42f29 | blueswir1 | (*info->fprintf_func) (stream, "%%reserved");
|
3044 | 46f42f29 | blueswir1 | break;
|
3045 | 46f42f29 | blueswir1 | |
3046 | f930d07e | blueswir1 | case '/': |
3047 | f930d07e | blueswir1 | if (X_RS1 (insn) < 16 || X_RS1 (insn) > 25) |
3048 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, "%%reserved");
|
3049 | f930d07e | blueswir1 | else
|
3050 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, "%%%s",
|
3051 | f930d07e | blueswir1 | v9a_asr_reg_names[X_RS1 (insn)-16]);
|
3052 | f930d07e | blueswir1 | break;
|
3053 | f930d07e | blueswir1 | |
3054 | f930d07e | blueswir1 | case '_': |
3055 | f930d07e | blueswir1 | if (X_RD (insn) < 16 || X_RD (insn) > 25) |
3056 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, "%%reserved");
|
3057 | f930d07e | blueswir1 | else
|
3058 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, "%%%s",
|
3059 | f930d07e | blueswir1 | v9a_asr_reg_names[X_RD (insn)-16]);
|
3060 | f930d07e | blueswir1 | break;
|
3061 | f930d07e | blueswir1 | |
3062 | f930d07e | blueswir1 | case '*': |
3063 | f930d07e | blueswir1 | { |
3064 | f930d07e | blueswir1 | const char *name = sparc_decode_prefetch (X_RD (insn)); |
3065 | f930d07e | blueswir1 | |
3066 | f930d07e | blueswir1 | if (name)
|
3067 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, "%s", name);
|
3068 | f930d07e | blueswir1 | else
|
3069 | 46f42f29 | blueswir1 | (*info->fprintf_func) (stream, "%ld", X_RD (insn));
|
3070 | f930d07e | blueswir1 | break;
|
3071 | f930d07e | blueswir1 | } |
3072 | f930d07e | blueswir1 | |
3073 | f930d07e | blueswir1 | case 'M': |
3074 | 46f42f29 | blueswir1 | (*info->fprintf_func) (stream, "%%asr%ld", X_RS1 (insn));
|
3075 | f930d07e | blueswir1 | break;
|
3076 | f930d07e | blueswir1 | |
3077 | f930d07e | blueswir1 | case 'm': |
3078 | 46f42f29 | blueswir1 | (*info->fprintf_func) (stream, "%%asr%ld", X_RD (insn));
|
3079 | f930d07e | blueswir1 | break;
|
3080 | f930d07e | blueswir1 | |
3081 | f930d07e | blueswir1 | case 'L': |
3082 | f930d07e | blueswir1 | info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4; |
3083 | f930d07e | blueswir1 | (*info->print_address_func) (info->target, info); |
3084 | f930d07e | blueswir1 | break;
|
3085 | f930d07e | blueswir1 | |
3086 | f930d07e | blueswir1 | case 'n': |
3087 | f930d07e | blueswir1 | (*info->fprintf_func) |
3088 | f930d07e | blueswir1 | (stream, "%#x", SEX (X_DISP22 (insn), 22)); |
3089 | f930d07e | blueswir1 | break;
|
3090 | f930d07e | blueswir1 | |
3091 | f930d07e | blueswir1 | case 'l': |
3092 | f930d07e | blueswir1 | info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4; |
3093 | f930d07e | blueswir1 | (*info->print_address_func) (info->target, info); |
3094 | f930d07e | blueswir1 | break;
|
3095 | f930d07e | blueswir1 | |
3096 | f930d07e | blueswir1 | case 'A': |
3097 | f930d07e | blueswir1 | { |
3098 | f930d07e | blueswir1 | const char *name; |
3099 | f930d07e | blueswir1 | |
3100 | f930d07e | blueswir1 | if ((info->mach == bfd_mach_sparc_v8plusa) ||
|
3101 | 725cb90b | bellard | ((info->mach >= bfd_mach_sparc_v9) && |
3102 | 725cb90b | bellard | (info->mach <= bfd_mach_sparc_v9b))) |
3103 | f930d07e | blueswir1 | name = sparc_decode_asi_v9 (X_ASI (insn)); |
3104 | f930d07e | blueswir1 | else
|
3105 | f930d07e | blueswir1 | name = sparc_decode_asi_v8 (X_ASI (insn)); |
3106 | f930d07e | blueswir1 | |
3107 | f930d07e | blueswir1 | if (name)
|
3108 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, "%s", name);
|
3109 | f930d07e | blueswir1 | else
|
3110 | 46f42f29 | blueswir1 | (*info->fprintf_func) (stream, "(%ld)", X_ASI (insn));
|
3111 | f930d07e | blueswir1 | break;
|
3112 | f930d07e | blueswir1 | } |
3113 | f930d07e | blueswir1 | |
3114 | f930d07e | blueswir1 | case 'C': |
3115 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, "%%csr");
|
3116 | f930d07e | blueswir1 | break;
|
3117 | f930d07e | blueswir1 | |
3118 | f930d07e | blueswir1 | case 'F': |
3119 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, "%%fsr");
|
3120 | f930d07e | blueswir1 | break;
|
3121 | f930d07e | blueswir1 | |
3122 | f930d07e | blueswir1 | case 'p': |
3123 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, "%%psr");
|
3124 | f930d07e | blueswir1 | break;
|
3125 | f930d07e | blueswir1 | |
3126 | f930d07e | blueswir1 | case 'q': |
3127 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, "%%fq");
|
3128 | f930d07e | blueswir1 | break;
|
3129 | f930d07e | blueswir1 | |
3130 | f930d07e | blueswir1 | case 'Q': |
3131 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, "%%cq");
|
3132 | f930d07e | blueswir1 | break;
|
3133 | f930d07e | blueswir1 | |
3134 | f930d07e | blueswir1 | case 't': |
3135 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, "%%tbr");
|
3136 | f930d07e | blueswir1 | break;
|
3137 | f930d07e | blueswir1 | |
3138 | f930d07e | blueswir1 | case 'w': |
3139 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, "%%wim");
|
3140 | f930d07e | blueswir1 | break;
|
3141 | f930d07e | blueswir1 | |
3142 | f930d07e | blueswir1 | case 'x': |
3143 | 46f42f29 | blueswir1 | (*info->fprintf_func) (stream, "%ld",
|
3144 | f930d07e | blueswir1 | ((X_LDST_I (insn) << 8)
|
3145 | f930d07e | blueswir1 | + X_ASI (insn))); |
3146 | f930d07e | blueswir1 | break;
|
3147 | f930d07e | blueswir1 | |
3148 | f930d07e | blueswir1 | case 'y': |
3149 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, "%%y");
|
3150 | f930d07e | blueswir1 | break;
|
3151 | f930d07e | blueswir1 | |
3152 | f930d07e | blueswir1 | case 'u': |
3153 | f930d07e | blueswir1 | case 'U': |
3154 | f930d07e | blueswir1 | { |
3155 | f930d07e | blueswir1 | int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn); |
3156 | f930d07e | blueswir1 | const char *name = sparc_decode_sparclet_cpreg (val); |
3157 | f930d07e | blueswir1 | |
3158 | f930d07e | blueswir1 | if (name)
|
3159 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, "%s", name);
|
3160 | f930d07e | blueswir1 | else
|
3161 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, "%%cpreg(%d)", val);
|
3162 | f930d07e | blueswir1 | break;
|
3163 | f930d07e | blueswir1 | } |
3164 | f930d07e | blueswir1 | } |
3165 | f930d07e | blueswir1 | } |
3166 | f930d07e | blueswir1 | } |
3167 | f930d07e | blueswir1 | |
3168 | f930d07e | blueswir1 | /* If we are adding or or'ing something to rs1, then
|
3169 | f930d07e | blueswir1 | check to see whether the previous instruction was
|
3170 | f930d07e | blueswir1 | a sethi to the same register as in the sethi.
|
3171 | f930d07e | blueswir1 | If so, attempt to print the result of the add or
|
3172 | f930d07e | blueswir1 | or (in this context add and or do the same thing)
|
3173 | f930d07e | blueswir1 | and its symbolic value. */
|
3174 | f930d07e | blueswir1 | if (imm_ored_to_rs1 || imm_added_to_rs1)
|
3175 | f930d07e | blueswir1 | { |
3176 | f930d07e | blueswir1 | unsigned long prev_insn; |
3177 | f930d07e | blueswir1 | int errcode;
|
3178 | f930d07e | blueswir1 | |
3179 | 46f42f29 | blueswir1 | if (memaddr >= 4) |
3180 | 46f42f29 | blueswir1 | errcode = |
3181 | 46f42f29 | blueswir1 | (*info->read_memory_func) |
3182 | f930d07e | blueswir1 | (memaddr - 4, buffer, sizeof (buffer), info); |
3183 | 46f42f29 | blueswir1 | else
|
3184 | 46f42f29 | blueswir1 | errcode = 1;
|
3185 | 46f42f29 | blueswir1 | |
3186 | f930d07e | blueswir1 | prev_insn = getword (buffer); |
3187 | f930d07e | blueswir1 | |
3188 | f930d07e | blueswir1 | if (errcode == 0) |
3189 | f930d07e | blueswir1 | { |
3190 | f930d07e | blueswir1 | /* If it is a delayed branch, we need to look at the
|
3191 | f930d07e | blueswir1 | instruction before the delayed branch. This handles
|
3192 | 46f42f29 | blueswir1 | sequences such as:
|
3193 | f930d07e | blueswir1 | |
3194 | f930d07e | blueswir1 | sethi %o1, %hi(_foo), %o1
|
3195 | f930d07e | blueswir1 | call _printf
|
3196 | 46f42f29 | blueswir1 | or %o1, %lo(_foo), %o1 */
|
3197 | f930d07e | blueswir1 | |
3198 | f930d07e | blueswir1 | if (is_delayed_branch (prev_insn))
|
3199 | f930d07e | blueswir1 | { |
3200 | 46f42f29 | blueswir1 | if (memaddr >= 8) |
3201 | 46f42f29 | blueswir1 | errcode = (*info->read_memory_func) |
3202 | 46f42f29 | blueswir1 | (memaddr - 8, buffer, sizeof (buffer), info); |
3203 | 46f42f29 | blueswir1 | else
|
3204 | 46f42f29 | blueswir1 | errcode = 1;
|
3205 | 46f42f29 | blueswir1 | |
3206 | f930d07e | blueswir1 | prev_insn = getword (buffer); |
3207 | f930d07e | blueswir1 | } |
3208 | f930d07e | blueswir1 | } |
3209 | f930d07e | blueswir1 | |
3210 | f930d07e | blueswir1 | /* If there was a problem reading memory, then assume
|
3211 | f930d07e | blueswir1 | the previous instruction was not sethi. */
|
3212 | f930d07e | blueswir1 | if (errcode == 0) |
3213 | f930d07e | blueswir1 | { |
3214 | f930d07e | blueswir1 | /* Is it sethi to the same register? */
|
3215 | f930d07e | blueswir1 | if ((prev_insn & 0xc1c00000) == 0x01000000 |
3216 | f930d07e | blueswir1 | && X_RD (prev_insn) == X_RS1 (insn)) |
3217 | f930d07e | blueswir1 | { |
3218 | f930d07e | blueswir1 | (*info->fprintf_func) (stream, "\t! ");
|
3219 | f930d07e | blueswir1 | info->target = |
3220 | f930d07e | blueswir1 | ((unsigned) 0xFFFFFFFF |
3221 | f930d07e | blueswir1 | & ((int) X_IMM22 (prev_insn) << 10)); |
3222 | f930d07e | blueswir1 | if (imm_added_to_rs1)
|
3223 | f930d07e | blueswir1 | info->target += X_SIMM (insn, 13);
|
3224 | f930d07e | blueswir1 | else
|
3225 | f930d07e | blueswir1 | info->target |= X_SIMM (insn, 13);
|
3226 | f930d07e | blueswir1 | (*info->print_address_func) (info->target, info); |
3227 | f930d07e | blueswir1 | info->insn_type = dis_dref; |
3228 | f930d07e | blueswir1 | info->data_size = 4; /* FIXME!!! */ |
3229 | f930d07e | blueswir1 | } |
3230 | f930d07e | blueswir1 | } |
3231 | f930d07e | blueswir1 | } |
3232 | f930d07e | blueswir1 | |
3233 | f930d07e | blueswir1 | if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR))
|
3234 | f930d07e | blueswir1 | { |
3235 | 46f42f29 | blueswir1 | /* FIXME -- check is_annulled flag. */
|
3236 | f930d07e | blueswir1 | if (opcode->flags & F_UNBR)
|
3237 | f930d07e | blueswir1 | info->insn_type = dis_branch; |
3238 | f930d07e | blueswir1 | if (opcode->flags & F_CONDBR)
|
3239 | f930d07e | blueswir1 | info->insn_type = dis_condbranch; |
3240 | f930d07e | blueswir1 | if (opcode->flags & F_JSR)
|
3241 | f930d07e | blueswir1 | info->insn_type = dis_jsr; |
3242 | f930d07e | blueswir1 | if (opcode->flags & F_DELAYED)
|
3243 | f930d07e | blueswir1 | info->branch_delay_insns = 1;
|
3244 | f930d07e | blueswir1 | } |
3245 | f930d07e | blueswir1 | |
3246 | f930d07e | blueswir1 | return sizeof (buffer); |
3247 | f930d07e | blueswir1 | } |
3248 | aa0aa4fa | bellard | } |
3249 | aa0aa4fa | bellard | |
3250 | 46f42f29 | blueswir1 | info->insn_type = dis_noninsn; /* Mark as non-valid instruction. */
|
3251 | aa0aa4fa | bellard | (*info->fprintf_func) (stream, _("unknown"));
|
3252 | aa0aa4fa | bellard | return sizeof (buffer); |
3253 | aa0aa4fa | bellard | } |