Revision 65ce8c2f target-sparc/op_helper.c
| b/target-sparc/op_helper.c | ||
|---|---|---|
| 12 | 12 |
#ifdef USE_INT_TO_FLOAT_HELPERS |
| 13 | 13 |
void do_fitos(void) |
| 14 | 14 |
{
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FT0 = (float) *((int32_t *)&FT1);
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FT0 = int32_to_float32(*((int32_t *)&FT1));
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|
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} |
| 17 | 17 |
|
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void do_fitod(void) |
| 19 | 19 |
{
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DT0 = (double) *((int32_t *)&FT1);
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|
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DT0 = int32_to_float64(*((int32_t *)&FT1));
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|
| 21 | 21 |
} |
| 22 | 22 |
#endif |
| 23 | 23 |
|
| ... | ... | |
| 43 | 43 |
DT0 = float64_sqrt(DT1, &env->fp_status); |
| 44 | 44 |
} |
| 45 | 45 |
|
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#define FS 0 |
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void do_fcmps (void) |
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{
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); |
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if (isnan(FT0) || isnan(FT1)) {
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T0 = (FSR_FCC1 | FSR_FCC0) << FS; |
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if (env->fsr & FSR_NVM) {
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env->fsr |= T0; |
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raise_exception(TT_FP_EXCP); |
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} else {
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env->fsr |= FSR_NVA; |
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} |
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} else if (FT0 < FT1) {
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T0 = FSR_FCC0 << FS; |
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} else if (FT0 > FT1) {
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T0 = FSR_FCC1 << FS; |
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} else {
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T0 = 0; |
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#define GEN_FCMP(name, size, reg1, reg2, FS) \ |
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void glue(do_, name) (void) \ |
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{ \
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ |
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switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
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case float_relation_unordered: \ |
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T0 = (FSR_FCC1 | FSR_FCC0) << FS; \ |
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if (env->fsr & FSR_NVM) { \
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env->fsr |= T0; \ |
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raise_exception(TT_FP_EXCP); \ |
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} else { \
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env->fsr |= FSR_NVA; \ |
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} \ |
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break; \ |
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case float_relation_less: \ |
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T0 = FSR_FCC0 << FS; \ |
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break; \ |
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case float_relation_greater: \ |
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T0 = FSR_FCC1 << FS; \ |
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break; \ |
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default: \ |
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T0 = 0; \ |
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break; \ |
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} \ |
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env->fsr |= T0; \ |
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} |
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env->fsr |= T0; |
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} |
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void do_fcmpd (void) |
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{
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); |
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if (isnan(DT0) || isnan(DT1)) {
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T0 = (FSR_FCC1 | FSR_FCC0) << FS; |
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if (env->fsr & FSR_NVM) {
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env->fsr |= T0; |
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raise_exception(TT_FP_EXCP); |
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} else {
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env->fsr |= FSR_NVA; |
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} |
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} else if (DT0 < DT1) {
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T0 = FSR_FCC0 << FS; |
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} else if (DT0 > DT1) {
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T0 = FSR_FCC1 << FS; |
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} else {
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T0 = 0; |
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} |
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env->fsr |= T0; |
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} |
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GEN_FCMP(fcmps, float32, FT0, FT1, 0); |
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GEN_FCMP(fcmpd, float64, DT0, DT1, 0); |
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|
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#ifdef TARGET_SPARC64 |
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#undef FS |
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#define FS 22 |
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void do_fcmps_fcc1 (void) |
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{
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); |
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if (isnan(FT0) || isnan(FT1)) {
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T0 = (FSR_FCC1 | FSR_FCC0) << FS; |
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if (env->fsr & FSR_NVM) {
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env->fsr |= T0; |
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raise_exception(TT_FP_EXCP); |
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} else {
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env->fsr |= FSR_NVA; |
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} |
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} else if (FT0 < FT1) {
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T0 = FSR_FCC0 << FS; |
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} else if (FT0 > FT1) {
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T0 = FSR_FCC1 << FS; |
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} else {
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T0 = 0; |
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} |
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env->fsr |= T0; |
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} |
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void do_fcmpd_fcc1 (void) |
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{
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); |
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if (isnan(DT0) || isnan(DT1)) {
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T0 = (FSR_FCC1 | FSR_FCC0) << FS; |
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if (env->fsr & FSR_NVM) {
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env->fsr |= T0; |
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raise_exception(TT_FP_EXCP); |
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} else {
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env->fsr |= FSR_NVA; |
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} |
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} else if (DT0 < DT1) {
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T0 = FSR_FCC0 << FS; |
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} else if (DT0 > DT1) {
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T0 = FSR_FCC1 << FS; |
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} else {
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T0 = 0; |
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} |
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env->fsr |= T0; |
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} |
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GEN_FCMP(fcmps_fcc1, float32, FT0, FT1, 22); |
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GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22); |
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#undef FS |
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#define FS 24 |
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void do_fcmps_fcc2 (void) |
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{
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); |
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if (isnan(FT0) || isnan(FT1)) {
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T0 = (FSR_FCC1 | FSR_FCC0) << FS; |
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if (env->fsr & FSR_NVM) {
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env->fsr |= T0; |
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raise_exception(TT_FP_EXCP); |
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} else {
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env->fsr |= FSR_NVA; |
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} |
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} else if (FT0 < FT1) {
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T0 = FSR_FCC0 << FS; |
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} else if (FT0 > FT1) {
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T0 = FSR_FCC1 << FS; |
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} else {
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T0 = 0; |
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} |
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env->fsr |= T0; |
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} |
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GEN_FCMP(fcmps_fcc2, float32, FT0, FT1, 24); |
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GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24); |
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void do_fcmpd_fcc2 (void) |
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{
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); |
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if (isnan(DT0) || isnan(DT1)) {
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T0 = (FSR_FCC1 | FSR_FCC0) << FS; |
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if (env->fsr & FSR_NVM) {
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env->fsr |= T0; |
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raise_exception(TT_FP_EXCP); |
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} else {
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env->fsr |= FSR_NVA; |
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} |
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} else if (DT0 < DT1) {
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T0 = FSR_FCC0 << FS; |
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} else if (DT0 > DT1) {
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T0 = FSR_FCC1 << FS; |
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} else {
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T0 = 0; |
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} |
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env->fsr |= T0; |
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} |
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#undef FS |
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#define FS 26 |
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void do_fcmps_fcc3 (void) |
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{
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); |
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if (isnan(FT0) || isnan(FT1)) {
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T0 = (FSR_FCC1 | FSR_FCC0) << FS; |
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if (env->fsr & FSR_NVM) {
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env->fsr |= T0; |
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raise_exception(TT_FP_EXCP); |
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} else {
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env->fsr |= FSR_NVA; |
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} |
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} else if (FT0 < FT1) {
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T0 = FSR_FCC0 << FS; |
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} else if (FT0 > FT1) {
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T0 = FSR_FCC1 << FS; |
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} else {
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T0 = 0; |
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} |
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env->fsr |= T0; |
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} |
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|
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void do_fcmpd_fcc3 (void) |
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{
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); |
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if (isnan(DT0) || isnan(DT1)) {
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T0 = (FSR_FCC1 | FSR_FCC0) << FS; |
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if (env->fsr & FSR_NVM) {
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env->fsr |= T0; |
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raise_exception(TT_FP_EXCP); |
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} else {
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env->fsr |= FSR_NVA; |
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} |
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} else if (DT0 < DT1) {
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T0 = FSR_FCC0 << FS; |
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} else if (DT0 > DT1) {
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T0 = FSR_FCC1 << FS; |
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} else {
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T0 = 0; |
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} |
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env->fsr |= T0; |
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} |
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#undef FS |
|
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GEN_FCMP(fcmps_fcc3, float32, FT0, FT1, 26); |
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GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26); |
|
| 222 | 85 |
#endif |
| 223 | 86 |
|
| 224 | 87 |
#if defined(CONFIG_USER_ONLY) |
| ... | ... | |
| 783 | 646 |
set_float_rounding_mode(rnd_mode, &env->fp_status); |
| 784 | 647 |
} |
| 785 | 648 |
|
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void cpu_get_fp64(uint64_t *pmant, uint16_t *pexp, double f) |
|
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{
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int exptemp; |
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| 789 |
|
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*pmant = ldexp(frexp(f, &exptemp), 53); |
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*pexp = exptemp; |
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} |
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|
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double cpu_put_fp64(uint64_t mant, uint16_t exp) |
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| 795 |
{
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return ldexp((double) mant, exp - 53); |
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} |
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| 798 |
|
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| 799 | 649 |
void helper_debug() |
| 800 | 650 |
{
|
| 801 | 651 |
env->exception_index = EXCP_DEBUG; |
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