root / hw / grlib_apbuart.c @ 6618f909
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1 | 8b1e1320 | Fabien Chouteau | /*
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2 | 8b1e1320 | Fabien Chouteau | * QEMU GRLIB APB UART Emulator
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3 | 8b1e1320 | Fabien Chouteau | *
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4 | 8b1e1320 | Fabien Chouteau | * Copyright (c) 2010-2011 AdaCore
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5 | 8b1e1320 | Fabien Chouteau | *
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6 | 8b1e1320 | Fabien Chouteau | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 8b1e1320 | Fabien Chouteau | * of this software and associated documentation files (the "Software"), to deal
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8 | 8b1e1320 | Fabien Chouteau | * in the Software without restriction, including without limitation the rights
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9 | 8b1e1320 | Fabien Chouteau | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 8b1e1320 | Fabien Chouteau | * copies of the Software, and to permit persons to whom the Software is
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11 | 8b1e1320 | Fabien Chouteau | * furnished to do so, subject to the following conditions:
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12 | 8b1e1320 | Fabien Chouteau | *
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13 | 8b1e1320 | Fabien Chouteau | * The above copyright notice and this permission notice shall be included in
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14 | 8b1e1320 | Fabien Chouteau | * all copies or substantial portions of the Software.
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15 | 8b1e1320 | Fabien Chouteau | *
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16 | 8b1e1320 | Fabien Chouteau | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 8b1e1320 | Fabien Chouteau | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 8b1e1320 | Fabien Chouteau | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 8b1e1320 | Fabien Chouteau | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 8b1e1320 | Fabien Chouteau | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 8b1e1320 | Fabien Chouteau | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 8b1e1320 | Fabien Chouteau | * THE SOFTWARE.
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23 | 8b1e1320 | Fabien Chouteau | */
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24 | 8b1e1320 | Fabien Chouteau | |
25 | 8b1e1320 | Fabien Chouteau | #include "sysbus.h" |
26 | 8b1e1320 | Fabien Chouteau | #include "qemu-char.h" |
27 | 49d4d9b6 | Paolo Bonzini | #include "ptimer.h" |
28 | 8b1e1320 | Fabien Chouteau | |
29 | 8b1e1320 | Fabien Chouteau | #include "trace.h" |
30 | 8b1e1320 | Fabien Chouteau | |
31 | 8b1e1320 | Fabien Chouteau | #define UART_REG_SIZE 20 /* Size of memory mapped registers */ |
32 | 8b1e1320 | Fabien Chouteau | |
33 | 8b1e1320 | Fabien Chouteau | /* UART status register fields */
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34 | 8b1e1320 | Fabien Chouteau | #define UART_DATA_READY (1 << 0) |
35 | 8b1e1320 | Fabien Chouteau | #define UART_TRANSMIT_SHIFT_EMPTY (1 << 1) |
36 | 8b1e1320 | Fabien Chouteau | #define UART_TRANSMIT_FIFO_EMPTY (1 << 2) |
37 | 8b1e1320 | Fabien Chouteau | #define UART_BREAK_RECEIVED (1 << 3) |
38 | 8b1e1320 | Fabien Chouteau | #define UART_OVERRUN (1 << 4) |
39 | 8b1e1320 | Fabien Chouteau | #define UART_PARITY_ERROR (1 << 5) |
40 | 8b1e1320 | Fabien Chouteau | #define UART_FRAMING_ERROR (1 << 6) |
41 | 8b1e1320 | Fabien Chouteau | #define UART_TRANSMIT_FIFO_HALF (1 << 7) |
42 | 8b1e1320 | Fabien Chouteau | #define UART_RECEIVE_FIFO_HALF (1 << 8) |
43 | 8b1e1320 | Fabien Chouteau | #define UART_TRANSMIT_FIFO_FULL (1 << 9) |
44 | 8b1e1320 | Fabien Chouteau | #define UART_RECEIVE_FIFO_FULL (1 << 10) |
45 | 8b1e1320 | Fabien Chouteau | |
46 | 8b1e1320 | Fabien Chouteau | /* UART control register fields */
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47 | 8b1e1320 | Fabien Chouteau | #define UART_RECEIVE_ENABLE (1 << 0) |
48 | 8b1e1320 | Fabien Chouteau | #define UART_TRANSMIT_ENABLE (1 << 1) |
49 | 8b1e1320 | Fabien Chouteau | #define UART_RECEIVE_INTERRUPT (1 << 2) |
50 | 8b1e1320 | Fabien Chouteau | #define UART_TRANSMIT_INTERRUPT (1 << 3) |
51 | 8b1e1320 | Fabien Chouteau | #define UART_PARITY_SELECT (1 << 4) |
52 | 8b1e1320 | Fabien Chouteau | #define UART_PARITY_ENABLE (1 << 5) |
53 | 8b1e1320 | Fabien Chouteau | #define UART_FLOW_CONTROL (1 << 6) |
54 | 8b1e1320 | Fabien Chouteau | #define UART_LOOPBACK (1 << 7) |
55 | 8b1e1320 | Fabien Chouteau | #define UART_EXTERNAL_CLOCK (1 << 8) |
56 | 8b1e1320 | Fabien Chouteau | #define UART_RECEIVE_FIFO_INTERRUPT (1 << 9) |
57 | 8b1e1320 | Fabien Chouteau | #define UART_TRANSMIT_FIFO_INTERRUPT (1 << 10) |
58 | 8b1e1320 | Fabien Chouteau | #define UART_FIFO_DEBUG_MODE (1 << 11) |
59 | 8b1e1320 | Fabien Chouteau | #define UART_OUTPUT_ENABLE (1 << 12) |
60 | 8b1e1320 | Fabien Chouteau | #define UART_FIFO_AVAILABLE (1 << 31) |
61 | 8b1e1320 | Fabien Chouteau | |
62 | 8b1e1320 | Fabien Chouteau | /* Memory mapped register offsets */
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63 | 8b1e1320 | Fabien Chouteau | #define DATA_OFFSET 0x00 |
64 | 8b1e1320 | Fabien Chouteau | #define STATUS_OFFSET 0x04 |
65 | 8b1e1320 | Fabien Chouteau | #define CONTROL_OFFSET 0x08 |
66 | 8b1e1320 | Fabien Chouteau | #define SCALER_OFFSET 0x0C /* not supported */ |
67 | 8b1e1320 | Fabien Chouteau | #define FIFO_DEBUG_OFFSET 0x10 /* not supported */ |
68 | 8b1e1320 | Fabien Chouteau | |
69 | 8b1e1320 | Fabien Chouteau | typedef struct UART { |
70 | 8b1e1320 | Fabien Chouteau | SysBusDevice busdev; |
71 | 6281f7d1 | Avi Kivity | MemoryRegion iomem; |
72 | 8b1e1320 | Fabien Chouteau | qemu_irq irq; |
73 | 8b1e1320 | Fabien Chouteau | |
74 | 8b1e1320 | Fabien Chouteau | CharDriverState *chr; |
75 | 8b1e1320 | Fabien Chouteau | |
76 | 8b1e1320 | Fabien Chouteau | /* registers */
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77 | 8b1e1320 | Fabien Chouteau | uint32_t receive; |
78 | 8b1e1320 | Fabien Chouteau | uint32_t status; |
79 | 8b1e1320 | Fabien Chouteau | uint32_t control; |
80 | 8b1e1320 | Fabien Chouteau | } UART; |
81 | 8b1e1320 | Fabien Chouteau | |
82 | 8b1e1320 | Fabien Chouteau | static int grlib_apbuart_can_receive(void *opaque) |
83 | 8b1e1320 | Fabien Chouteau | { |
84 | 8b1e1320 | Fabien Chouteau | UART *uart = opaque; |
85 | 8b1e1320 | Fabien Chouteau | |
86 | 8b1e1320 | Fabien Chouteau | return !!(uart->status & UART_DATA_READY);
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87 | 8b1e1320 | Fabien Chouteau | } |
88 | 8b1e1320 | Fabien Chouteau | |
89 | 8b1e1320 | Fabien Chouteau | static void grlib_apbuart_receive(void *opaque, const uint8_t *buf, int size) |
90 | 8b1e1320 | Fabien Chouteau | { |
91 | 8b1e1320 | Fabien Chouteau | UART *uart = opaque; |
92 | 8b1e1320 | Fabien Chouteau | |
93 | 8b1e1320 | Fabien Chouteau | uart->receive = *buf; |
94 | 8b1e1320 | Fabien Chouteau | uart->status |= UART_DATA_READY; |
95 | 8b1e1320 | Fabien Chouteau | |
96 | 8b1e1320 | Fabien Chouteau | if (uart->control & UART_RECEIVE_INTERRUPT) {
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97 | 8b1e1320 | Fabien Chouteau | qemu_irq_pulse(uart->irq); |
98 | 8b1e1320 | Fabien Chouteau | } |
99 | 8b1e1320 | Fabien Chouteau | } |
100 | 8b1e1320 | Fabien Chouteau | |
101 | 8b1e1320 | Fabien Chouteau | static void grlib_apbuart_event(void *opaque, int event) |
102 | 8b1e1320 | Fabien Chouteau | { |
103 | 8b1e1320 | Fabien Chouteau | trace_grlib_apbuart_event(event); |
104 | 8b1e1320 | Fabien Chouteau | } |
105 | 8b1e1320 | Fabien Chouteau | |
106 | 8b1e1320 | Fabien Chouteau | static void |
107 | 6281f7d1 | Avi Kivity | grlib_apbuart_write(void *opaque, target_phys_addr_t addr,
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108 | 6281f7d1 | Avi Kivity | uint64_t value, unsigned size)
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109 | 8b1e1320 | Fabien Chouteau | { |
110 | 8b1e1320 | Fabien Chouteau | UART *uart = opaque; |
111 | 8b1e1320 | Fabien Chouteau | unsigned char c = 0; |
112 | 8b1e1320 | Fabien Chouteau | |
113 | 8b1e1320 | Fabien Chouteau | addr &= 0xff;
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114 | 8b1e1320 | Fabien Chouteau | |
115 | 8b1e1320 | Fabien Chouteau | /* Unit registers */
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116 | 8b1e1320 | Fabien Chouteau | switch (addr) {
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117 | 8b1e1320 | Fabien Chouteau | case DATA_OFFSET:
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118 | 8b1e1320 | Fabien Chouteau | c = value & 0xFF;
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119 | 2cc6e0a1 | Anthony Liguori | qemu_chr_fe_write(uart->chr, &c, 1);
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120 | 8b1e1320 | Fabien Chouteau | return;
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121 | 8b1e1320 | Fabien Chouteau | |
122 | 8b1e1320 | Fabien Chouteau | case STATUS_OFFSET:
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123 | 8b1e1320 | Fabien Chouteau | /* Read Only */
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124 | 8b1e1320 | Fabien Chouteau | return;
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125 | 8b1e1320 | Fabien Chouteau | |
126 | 8b1e1320 | Fabien Chouteau | case CONTROL_OFFSET:
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127 | 8b1e1320 | Fabien Chouteau | /* Not supported */
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128 | 8b1e1320 | Fabien Chouteau | return;
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129 | 8b1e1320 | Fabien Chouteau | |
130 | 8b1e1320 | Fabien Chouteau | case SCALER_OFFSET:
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131 | 8b1e1320 | Fabien Chouteau | /* Not supported */
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132 | 8b1e1320 | Fabien Chouteau | return;
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133 | 8b1e1320 | Fabien Chouteau | |
134 | 8b1e1320 | Fabien Chouteau | default:
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135 | 8b1e1320 | Fabien Chouteau | break;
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136 | 8b1e1320 | Fabien Chouteau | } |
137 | 8b1e1320 | Fabien Chouteau | |
138 | b4548fcc | Stefan Hajnoczi | trace_grlib_apbuart_writel_unknown(addr, value); |
139 | 8b1e1320 | Fabien Chouteau | } |
140 | 8b1e1320 | Fabien Chouteau | |
141 | 6281f7d1 | Avi Kivity | static bool grlib_apbuart_accepts(void *opaque, target_phys_addr_t addr, |
142 | 6281f7d1 | Avi Kivity | unsigned size, bool is_write) |
143 | 6281f7d1 | Avi Kivity | { |
144 | 6281f7d1 | Avi Kivity | return is_write && size == 4; |
145 | 6281f7d1 | Avi Kivity | } |
146 | 8b1e1320 | Fabien Chouteau | |
147 | 6281f7d1 | Avi Kivity | static const MemoryRegionOps grlib_apbuart_ops = { |
148 | 6281f7d1 | Avi Kivity | .write = grlib_apbuart_write, |
149 | 6281f7d1 | Avi Kivity | .valid.accepts = grlib_apbuart_accepts, |
150 | 6281f7d1 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
151 | 8b1e1320 | Fabien Chouteau | }; |
152 | 8b1e1320 | Fabien Chouteau | |
153 | 8b1e1320 | Fabien Chouteau | static int grlib_apbuart_init(SysBusDevice *dev) |
154 | 8b1e1320 | Fabien Chouteau | { |
155 | 8b1e1320 | Fabien Chouteau | UART *uart = FROM_SYSBUS(typeof(*uart), dev); |
156 | 8b1e1320 | Fabien Chouteau | |
157 | 8b1e1320 | Fabien Chouteau | qemu_chr_add_handlers(uart->chr, |
158 | 8b1e1320 | Fabien Chouteau | grlib_apbuart_can_receive, |
159 | 8b1e1320 | Fabien Chouteau | grlib_apbuart_receive, |
160 | 8b1e1320 | Fabien Chouteau | grlib_apbuart_event, |
161 | 8b1e1320 | Fabien Chouteau | uart); |
162 | 8b1e1320 | Fabien Chouteau | |
163 | 8b1e1320 | Fabien Chouteau | sysbus_init_irq(dev, &uart->irq); |
164 | 8b1e1320 | Fabien Chouteau | |
165 | 6281f7d1 | Avi Kivity | memory_region_init_io(&uart->iomem, &grlib_apbuart_ops, uart, |
166 | 6281f7d1 | Avi Kivity | "uart", UART_REG_SIZE);
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167 | 8b1e1320 | Fabien Chouteau | |
168 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, &uart->iomem); |
169 | 8b1e1320 | Fabien Chouteau | |
170 | 8b1e1320 | Fabien Chouteau | return 0; |
171 | 8b1e1320 | Fabien Chouteau | } |
172 | 8b1e1320 | Fabien Chouteau | |
173 | 8b1e1320 | Fabien Chouteau | static SysBusDeviceInfo grlib_gptimer_info = {
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174 | 8b1e1320 | Fabien Chouteau | .init = grlib_apbuart_init, |
175 | 8b1e1320 | Fabien Chouteau | .qdev.name = "grlib,apbuart",
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176 | 8b1e1320 | Fabien Chouteau | .qdev.size = sizeof(UART),
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177 | 8b1e1320 | Fabien Chouteau | .qdev.props = (Property[]) { |
178 | 8b1e1320 | Fabien Chouteau | DEFINE_PROP_CHR("chrdev", UART, chr),
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179 | 8b1e1320 | Fabien Chouteau | DEFINE_PROP_END_OF_LIST() |
180 | 8b1e1320 | Fabien Chouteau | } |
181 | 8b1e1320 | Fabien Chouteau | }; |
182 | 8b1e1320 | Fabien Chouteau | |
183 | 8b1e1320 | Fabien Chouteau | static void grlib_gptimer_register(void) |
184 | 8b1e1320 | Fabien Chouteau | { |
185 | 8b1e1320 | Fabien Chouteau | sysbus_register_withprop(&grlib_gptimer_info); |
186 | 8b1e1320 | Fabien Chouteau | } |
187 | 8b1e1320 | Fabien Chouteau | |
188 | 8b1e1320 | Fabien Chouteau | device_init(grlib_gptimer_register) |