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1 | 4c9649a9 | j_mayer | /*
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2 | 4c9649a9 | j_mayer | * Alpha emulation cpu translation for qemu.
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3 | 5fafdf24 | ths | *
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4 | 4c9649a9 | j_mayer | * Copyright (c) 2007 Jocelyn Mayer
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5 | 4c9649a9 | j_mayer | *
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6 | 4c9649a9 | j_mayer | * This library is free software; you can redistribute it and/or
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7 | 4c9649a9 | j_mayer | * modify it under the terms of the GNU Lesser General Public
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8 | 4c9649a9 | j_mayer | * License as published by the Free Software Foundation; either
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9 | 4c9649a9 | j_mayer | * version 2 of the License, or (at your option) any later version.
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10 | 4c9649a9 | j_mayer | *
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11 | 4c9649a9 | j_mayer | * This library is distributed in the hope that it will be useful,
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12 | 4c9649a9 | j_mayer | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 4c9649a9 | j_mayer | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 4c9649a9 | j_mayer | * Lesser General Public License for more details.
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15 | 4c9649a9 | j_mayer | *
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16 | 4c9649a9 | j_mayer | * You should have received a copy of the GNU Lesser General Public
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17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | 4c9649a9 | j_mayer | */
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19 | 4c9649a9 | j_mayer | |
20 | 4c9649a9 | j_mayer | #include <stdint.h> |
21 | 4c9649a9 | j_mayer | #include <stdlib.h> |
22 | 4c9649a9 | j_mayer | #include <stdio.h> |
23 | 4c9649a9 | j_mayer | |
24 | 4c9649a9 | j_mayer | #include "cpu.h" |
25 | 4c9649a9 | j_mayer | #include "exec-all.h" |
26 | 4c9649a9 | j_mayer | #include "disas.h" |
27 | ae8ecd42 | aurel32 | #include "host-utils.h" |
28 | 57fec1fe | bellard | #include "tcg-op.h" |
29 | ca10f867 | aurel32 | #include "qemu-common.h" |
30 | 4c9649a9 | j_mayer | |
31 | a7812ae4 | pbrook | #include "helper.h" |
32 | a7812ae4 | pbrook | #define GEN_HELPER 1 |
33 | a7812ae4 | pbrook | #include "helper.h" |
34 | a7812ae4 | pbrook | |
35 | 19188121 | Richard Henderson | #undef ALPHA_DEBUG_DISAS
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36 | f24518b5 | Richard Henderson | #define CONFIG_SOFTFLOAT_INLINE
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37 | d12d51d5 | aliguori | |
38 | d12d51d5 | aliguori | #ifdef ALPHA_DEBUG_DISAS
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39 | 806991da | Richard Henderson | # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) |
40 | d12d51d5 | aliguori | #else
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41 | d12d51d5 | aliguori | # define LOG_DISAS(...) do { } while (0) |
42 | d12d51d5 | aliguori | #endif
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43 | d12d51d5 | aliguori | |
44 | 4c9649a9 | j_mayer | typedef struct DisasContext DisasContext; |
45 | 4c9649a9 | j_mayer | struct DisasContext {
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46 | 4c9649a9 | j_mayer | uint64_t pc; |
47 | 4c9649a9 | j_mayer | int mem_idx;
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48 | 4c9649a9 | j_mayer | #if !defined (CONFIG_USER_ONLY)
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49 | 4c9649a9 | j_mayer | int pal_mode;
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50 | 4c9649a9 | j_mayer | #endif
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51 | 8579095b | aurel32 | CPUAlphaState *env; |
52 | 4c9649a9 | j_mayer | uint32_t amask; |
53 | f24518b5 | Richard Henderson | |
54 | f24518b5 | Richard Henderson | /* Current rounding mode for this TB. */
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55 | f24518b5 | Richard Henderson | int tb_rm;
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56 | f24518b5 | Richard Henderson | /* Current flush-to-zero setting for this TB. */
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57 | f24518b5 | Richard Henderson | int tb_ftz;
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58 | 4c9649a9 | j_mayer | }; |
59 | 4c9649a9 | j_mayer | |
60 | 3761035f | aurel32 | /* global register indexes */
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61 | a7812ae4 | pbrook | static TCGv_ptr cpu_env;
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62 | 496cb5b9 | aurel32 | static TCGv cpu_ir[31]; |
63 | f18cd223 | aurel32 | static TCGv cpu_fir[31]; |
64 | 496cb5b9 | aurel32 | static TCGv cpu_pc;
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65 | f4ed8679 | aurel32 | static TCGv cpu_lock;
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66 | ab471ade | Richard Henderson | #ifdef CONFIG_USER_ONLY
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67 | ab471ade | Richard Henderson | static TCGv cpu_uniq;
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68 | ab471ade | Richard Henderson | #endif
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69 | 496cb5b9 | aurel32 | |
70 | 3761035f | aurel32 | /* register names */
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71 | f18cd223 | aurel32 | static char cpu_reg_names[10*4+21*5 + 10*5+21*6]; |
72 | 2e70f6ef | pbrook | |
73 | 2e70f6ef | pbrook | #include "gen-icount.h" |
74 | 2e70f6ef | pbrook | |
75 | a5f1b965 | blueswir1 | static void alpha_translate_init(void) |
76 | 2e70f6ef | pbrook | { |
77 | 496cb5b9 | aurel32 | int i;
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78 | 496cb5b9 | aurel32 | char *p;
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79 | 2e70f6ef | pbrook | static int done_init = 0; |
80 | 496cb5b9 | aurel32 | |
81 | 2e70f6ef | pbrook | if (done_init)
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82 | 2e70f6ef | pbrook | return;
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83 | 496cb5b9 | aurel32 | |
84 | a7812ae4 | pbrook | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
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85 | 496cb5b9 | aurel32 | |
86 | 496cb5b9 | aurel32 | p = cpu_reg_names; |
87 | 496cb5b9 | aurel32 | for (i = 0; i < 31; i++) { |
88 | 496cb5b9 | aurel32 | sprintf(p, "ir%d", i);
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89 | a7812ae4 | pbrook | cpu_ir[i] = tcg_global_mem_new_i64(TCG_AREG0, |
90 | a7812ae4 | pbrook | offsetof(CPUState, ir[i]), p); |
91 | 6ba8dcd7 | aurel32 | p += (i < 10) ? 4 : 5; |
92 | f18cd223 | aurel32 | |
93 | f18cd223 | aurel32 | sprintf(p, "fir%d", i);
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94 | a7812ae4 | pbrook | cpu_fir[i] = tcg_global_mem_new_i64(TCG_AREG0, |
95 | a7812ae4 | pbrook | offsetof(CPUState, fir[i]), p); |
96 | f18cd223 | aurel32 | p += (i < 10) ? 5 : 6; |
97 | 496cb5b9 | aurel32 | } |
98 | 496cb5b9 | aurel32 | |
99 | a7812ae4 | pbrook | cpu_pc = tcg_global_mem_new_i64(TCG_AREG0, |
100 | a7812ae4 | pbrook | offsetof(CPUState, pc), "pc");
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101 | 496cb5b9 | aurel32 | |
102 | a7812ae4 | pbrook | cpu_lock = tcg_global_mem_new_i64(TCG_AREG0, |
103 | a7812ae4 | pbrook | offsetof(CPUState, lock), "lock");
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104 | f4ed8679 | aurel32 | |
105 | ab471ade | Richard Henderson | #ifdef CONFIG_USER_ONLY
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106 | ab471ade | Richard Henderson | cpu_uniq = tcg_global_mem_new_i64(TCG_AREG0, |
107 | ab471ade | Richard Henderson | offsetof(CPUState, unique), "uniq");
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108 | ab471ade | Richard Henderson | #endif
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109 | ab471ade | Richard Henderson | |
110 | 496cb5b9 | aurel32 | /* register helpers */
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111 | a7812ae4 | pbrook | #define GEN_HELPER 2 |
112 | 496cb5b9 | aurel32 | #include "helper.h" |
113 | 496cb5b9 | aurel32 | |
114 | 2e70f6ef | pbrook | done_init = 1;
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115 | 2e70f6ef | pbrook | } |
116 | 2e70f6ef | pbrook | |
117 | 636aa200 | Blue Swirl | static inline void gen_excp(DisasContext *ctx, int exception, int error_code) |
118 | 4c9649a9 | j_mayer | { |
119 | a7812ae4 | pbrook | TCGv_i32 tmp1, tmp2; |
120 | 6ad02592 | aurel32 | |
121 | 496cb5b9 | aurel32 | tcg_gen_movi_i64(cpu_pc, ctx->pc); |
122 | 6ad02592 | aurel32 | tmp1 = tcg_const_i32(exception); |
123 | 6ad02592 | aurel32 | tmp2 = tcg_const_i32(error_code); |
124 | a7812ae4 | pbrook | gen_helper_excp(tmp1, tmp2); |
125 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp2); |
126 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp1); |
127 | 4c9649a9 | j_mayer | } |
128 | 4c9649a9 | j_mayer | |
129 | 636aa200 | Blue Swirl | static inline void gen_invalid(DisasContext *ctx) |
130 | 4c9649a9 | j_mayer | { |
131 | 4c9649a9 | j_mayer | gen_excp(ctx, EXCP_OPCDEC, 0);
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132 | 4c9649a9 | j_mayer | } |
133 | 4c9649a9 | j_mayer | |
134 | 636aa200 | Blue Swirl | static inline void gen_qemu_ldf(TCGv t0, TCGv t1, int flags) |
135 | f18cd223 | aurel32 | { |
136 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
137 | a7812ae4 | pbrook | TCGv_i32 tmp32 = tcg_temp_new_i32(); |
138 | f18cd223 | aurel32 | tcg_gen_qemu_ld32u(tmp, t1, flags); |
139 | a7812ae4 | pbrook | tcg_gen_trunc_i64_i32(tmp32, tmp); |
140 | a7812ae4 | pbrook | gen_helper_memory_to_f(t0, tmp32); |
141 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp32); |
142 | f18cd223 | aurel32 | tcg_temp_free(tmp); |
143 | f18cd223 | aurel32 | } |
144 | f18cd223 | aurel32 | |
145 | 636aa200 | Blue Swirl | static inline void gen_qemu_ldg(TCGv t0, TCGv t1, int flags) |
146 | f18cd223 | aurel32 | { |
147 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
148 | f18cd223 | aurel32 | tcg_gen_qemu_ld64(tmp, t1, flags); |
149 | a7812ae4 | pbrook | gen_helper_memory_to_g(t0, tmp); |
150 | f18cd223 | aurel32 | tcg_temp_free(tmp); |
151 | f18cd223 | aurel32 | } |
152 | f18cd223 | aurel32 | |
153 | 636aa200 | Blue Swirl | static inline void gen_qemu_lds(TCGv t0, TCGv t1, int flags) |
154 | f18cd223 | aurel32 | { |
155 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
156 | a7812ae4 | pbrook | TCGv_i32 tmp32 = tcg_temp_new_i32(); |
157 | f18cd223 | aurel32 | tcg_gen_qemu_ld32u(tmp, t1, flags); |
158 | a7812ae4 | pbrook | tcg_gen_trunc_i64_i32(tmp32, tmp); |
159 | a7812ae4 | pbrook | gen_helper_memory_to_s(t0, tmp32); |
160 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp32); |
161 | f18cd223 | aurel32 | tcg_temp_free(tmp); |
162 | f18cd223 | aurel32 | } |
163 | f18cd223 | aurel32 | |
164 | 636aa200 | Blue Swirl | static inline void gen_qemu_ldl_l(TCGv t0, TCGv t1, int flags) |
165 | f4ed8679 | aurel32 | { |
166 | f4ed8679 | aurel32 | tcg_gen_mov_i64(cpu_lock, t1); |
167 | f4ed8679 | aurel32 | tcg_gen_qemu_ld32s(t0, t1, flags); |
168 | f4ed8679 | aurel32 | } |
169 | f4ed8679 | aurel32 | |
170 | 636aa200 | Blue Swirl | static inline void gen_qemu_ldq_l(TCGv t0, TCGv t1, int flags) |
171 | f4ed8679 | aurel32 | { |
172 | f4ed8679 | aurel32 | tcg_gen_mov_i64(cpu_lock, t1); |
173 | f4ed8679 | aurel32 | tcg_gen_qemu_ld64(t0, t1, flags); |
174 | f4ed8679 | aurel32 | } |
175 | f4ed8679 | aurel32 | |
176 | 636aa200 | Blue Swirl | static inline void gen_load_mem(DisasContext *ctx, |
177 | 636aa200 | Blue Swirl | void (*tcg_gen_qemu_load)(TCGv t0, TCGv t1,
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178 | 636aa200 | Blue Swirl | int flags),
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179 | 636aa200 | Blue Swirl | int ra, int rb, int32_t disp16, int fp, |
180 | 636aa200 | Blue Swirl | int clear)
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181 | 023d8ca2 | aurel32 | { |
182 | 023d8ca2 | aurel32 | TCGv addr; |
183 | 023d8ca2 | aurel32 | |
184 | 023d8ca2 | aurel32 | if (unlikely(ra == 31)) |
185 | 023d8ca2 | aurel32 | return;
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186 | 023d8ca2 | aurel32 | |
187 | a7812ae4 | pbrook | addr = tcg_temp_new(); |
188 | 023d8ca2 | aurel32 | if (rb != 31) { |
189 | 023d8ca2 | aurel32 | tcg_gen_addi_i64(addr, cpu_ir[rb], disp16); |
190 | 023d8ca2 | aurel32 | if (clear)
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191 | 023d8ca2 | aurel32 | tcg_gen_andi_i64(addr, addr, ~0x7);
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192 | 023d8ca2 | aurel32 | } else {
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193 | 023d8ca2 | aurel32 | if (clear)
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194 | 023d8ca2 | aurel32 | disp16 &= ~0x7;
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195 | 023d8ca2 | aurel32 | tcg_gen_movi_i64(addr, disp16); |
196 | 023d8ca2 | aurel32 | } |
197 | f18cd223 | aurel32 | if (fp)
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198 | f18cd223 | aurel32 | tcg_gen_qemu_load(cpu_fir[ra], addr, ctx->mem_idx); |
199 | f18cd223 | aurel32 | else
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200 | f18cd223 | aurel32 | tcg_gen_qemu_load(cpu_ir[ra], addr, ctx->mem_idx); |
201 | 023d8ca2 | aurel32 | tcg_temp_free(addr); |
202 | 023d8ca2 | aurel32 | } |
203 | 023d8ca2 | aurel32 | |
204 | 636aa200 | Blue Swirl | static inline void gen_qemu_stf(TCGv t0, TCGv t1, int flags) |
205 | f18cd223 | aurel32 | { |
206 | a7812ae4 | pbrook | TCGv_i32 tmp32 = tcg_temp_new_i32(); |
207 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
208 | a7812ae4 | pbrook | gen_helper_f_to_memory(tmp32, t0); |
209 | a7812ae4 | pbrook | tcg_gen_extu_i32_i64(tmp, tmp32); |
210 | f18cd223 | aurel32 | tcg_gen_qemu_st32(tmp, t1, flags); |
211 | f18cd223 | aurel32 | tcg_temp_free(tmp); |
212 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp32); |
213 | f18cd223 | aurel32 | } |
214 | f18cd223 | aurel32 | |
215 | 636aa200 | Blue Swirl | static inline void gen_qemu_stg(TCGv t0, TCGv t1, int flags) |
216 | f18cd223 | aurel32 | { |
217 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
218 | a7812ae4 | pbrook | gen_helper_g_to_memory(tmp, t0); |
219 | f18cd223 | aurel32 | tcg_gen_qemu_st64(tmp, t1, flags); |
220 | f18cd223 | aurel32 | tcg_temp_free(tmp); |
221 | f18cd223 | aurel32 | } |
222 | f18cd223 | aurel32 | |
223 | 636aa200 | Blue Swirl | static inline void gen_qemu_sts(TCGv t0, TCGv t1, int flags) |
224 | f18cd223 | aurel32 | { |
225 | a7812ae4 | pbrook | TCGv_i32 tmp32 = tcg_temp_new_i32(); |
226 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
227 | a7812ae4 | pbrook | gen_helper_s_to_memory(tmp32, t0); |
228 | a7812ae4 | pbrook | tcg_gen_extu_i32_i64(tmp, tmp32); |
229 | f18cd223 | aurel32 | tcg_gen_qemu_st32(tmp, t1, flags); |
230 | f18cd223 | aurel32 | tcg_temp_free(tmp); |
231 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp32); |
232 | f18cd223 | aurel32 | } |
233 | f18cd223 | aurel32 | |
234 | 636aa200 | Blue Swirl | static inline void gen_qemu_stl_c(TCGv t0, TCGv t1, int flags) |
235 | f4ed8679 | aurel32 | { |
236 | f4ed8679 | aurel32 | int l1, l2;
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237 | f4ed8679 | aurel32 | |
238 | f4ed8679 | aurel32 | l1 = gen_new_label(); |
239 | f4ed8679 | aurel32 | l2 = gen_new_label(); |
240 | f4ed8679 | aurel32 | tcg_gen_brcond_i64(TCG_COND_NE, cpu_lock, t1, l1); |
241 | f4ed8679 | aurel32 | tcg_gen_qemu_st32(t0, t1, flags); |
242 | 6223246a | aurel32 | tcg_gen_movi_i64(t0, 1);
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243 | f4ed8679 | aurel32 | tcg_gen_br(l2); |
244 | f4ed8679 | aurel32 | gen_set_label(l1); |
245 | 6223246a | aurel32 | tcg_gen_movi_i64(t0, 0);
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246 | f4ed8679 | aurel32 | gen_set_label(l2); |
247 | f4ed8679 | aurel32 | tcg_gen_movi_i64(cpu_lock, -1);
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248 | f4ed8679 | aurel32 | } |
249 | f4ed8679 | aurel32 | |
250 | 636aa200 | Blue Swirl | static inline void gen_qemu_stq_c(TCGv t0, TCGv t1, int flags) |
251 | f4ed8679 | aurel32 | { |
252 | f4ed8679 | aurel32 | int l1, l2;
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253 | f4ed8679 | aurel32 | |
254 | f4ed8679 | aurel32 | l1 = gen_new_label(); |
255 | f4ed8679 | aurel32 | l2 = gen_new_label(); |
256 | f4ed8679 | aurel32 | tcg_gen_brcond_i64(TCG_COND_NE, cpu_lock, t1, l1); |
257 | f4ed8679 | aurel32 | tcg_gen_qemu_st64(t0, t1, flags); |
258 | 6223246a | aurel32 | tcg_gen_movi_i64(t0, 1);
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259 | f4ed8679 | aurel32 | tcg_gen_br(l2); |
260 | f4ed8679 | aurel32 | gen_set_label(l1); |
261 | 6223246a | aurel32 | tcg_gen_movi_i64(t0, 0);
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262 | f4ed8679 | aurel32 | gen_set_label(l2); |
263 | f4ed8679 | aurel32 | tcg_gen_movi_i64(cpu_lock, -1);
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264 | f4ed8679 | aurel32 | } |
265 | f4ed8679 | aurel32 | |
266 | 636aa200 | Blue Swirl | static inline void gen_store_mem(DisasContext *ctx, |
267 | 636aa200 | Blue Swirl | void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1,
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268 | 636aa200 | Blue Swirl | int flags),
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269 | 636aa200 | Blue Swirl | int ra, int rb, int32_t disp16, int fp, |
270 | 636aa200 | Blue Swirl | int clear, int local) |
271 | 023d8ca2 | aurel32 | { |
272 | 9cd38c23 | aurel32 | TCGv addr; |
273 | 57a92c8e | aurel32 | if (local)
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274 | a7812ae4 | pbrook | addr = tcg_temp_local_new(); |
275 | 57a92c8e | aurel32 | else
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276 | a7812ae4 | pbrook | addr = tcg_temp_new(); |
277 | 023d8ca2 | aurel32 | if (rb != 31) { |
278 | 023d8ca2 | aurel32 | tcg_gen_addi_i64(addr, cpu_ir[rb], disp16); |
279 | 023d8ca2 | aurel32 | if (clear)
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280 | 023d8ca2 | aurel32 | tcg_gen_andi_i64(addr, addr, ~0x7);
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281 | 023d8ca2 | aurel32 | } else {
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282 | 023d8ca2 | aurel32 | if (clear)
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283 | 023d8ca2 | aurel32 | disp16 &= ~0x7;
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284 | 023d8ca2 | aurel32 | tcg_gen_movi_i64(addr, disp16); |
285 | 023d8ca2 | aurel32 | } |
286 | f18cd223 | aurel32 | if (ra != 31) { |
287 | f18cd223 | aurel32 | if (fp)
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288 | f18cd223 | aurel32 | tcg_gen_qemu_store(cpu_fir[ra], addr, ctx->mem_idx); |
289 | f18cd223 | aurel32 | else
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290 | f18cd223 | aurel32 | tcg_gen_qemu_store(cpu_ir[ra], addr, ctx->mem_idx); |
291 | f18cd223 | aurel32 | } else {
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292 | 57a92c8e | aurel32 | TCGv zero; |
293 | 57a92c8e | aurel32 | if (local)
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294 | 57a92c8e | aurel32 | zero = tcg_const_local_i64(0);
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295 | 57a92c8e | aurel32 | else
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296 | 57a92c8e | aurel32 | zero = tcg_const_i64(0);
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297 | 023d8ca2 | aurel32 | tcg_gen_qemu_store(zero, addr, ctx->mem_idx); |
298 | 023d8ca2 | aurel32 | tcg_temp_free(zero); |
299 | 023d8ca2 | aurel32 | } |
300 | 023d8ca2 | aurel32 | tcg_temp_free(addr); |
301 | 023d8ca2 | aurel32 | } |
302 | 023d8ca2 | aurel32 | |
303 | dbb30fe6 | Richard Henderson | static void gen_bcond_pcload(DisasContext *ctx, int32_t disp, int lab_true) |
304 | 4c9649a9 | j_mayer | { |
305 | dbb30fe6 | Richard Henderson | int lab_over = gen_new_label();
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306 | dbb30fe6 | Richard Henderson | |
307 | dbb30fe6 | Richard Henderson | tcg_gen_movi_i64(cpu_pc, ctx->pc); |
308 | dbb30fe6 | Richard Henderson | tcg_gen_br(lab_over); |
309 | dbb30fe6 | Richard Henderson | gen_set_label(lab_true); |
310 | dbb30fe6 | Richard Henderson | tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp << 2));
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311 | dbb30fe6 | Richard Henderson | gen_set_label(lab_over); |
312 | dbb30fe6 | Richard Henderson | } |
313 | dbb30fe6 | Richard Henderson | |
314 | dbb30fe6 | Richard Henderson | static void gen_bcond(DisasContext *ctx, TCGCond cond, int ra, |
315 | dbb30fe6 | Richard Henderson | int32_t disp, int mask)
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316 | dbb30fe6 | Richard Henderson | { |
317 | dbb30fe6 | Richard Henderson | int lab_true = gen_new_label();
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318 | 9c29504e | aurel32 | |
319 | 9c29504e | aurel32 | if (likely(ra != 31)) { |
320 | 9c29504e | aurel32 | if (mask) {
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321 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
322 | 9c29504e | aurel32 | tcg_gen_andi_i64(tmp, cpu_ir[ra], 1);
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323 | dbb30fe6 | Richard Henderson | tcg_gen_brcondi_i64(cond, tmp, 0, lab_true);
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324 | 9c29504e | aurel32 | tcg_temp_free(tmp); |
325 | dbb30fe6 | Richard Henderson | } else {
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326 | dbb30fe6 | Richard Henderson | tcg_gen_brcondi_i64(cond, cpu_ir[ra], 0, lab_true);
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327 | dbb30fe6 | Richard Henderson | } |
328 | 9c29504e | aurel32 | } else {
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329 | 9c29504e | aurel32 | /* Very uncommon case - Do not bother to optimize. */
|
330 | 9c29504e | aurel32 | TCGv tmp = tcg_const_i64(0);
|
331 | dbb30fe6 | Richard Henderson | tcg_gen_brcondi_i64(cond, tmp, 0, lab_true);
|
332 | 9c29504e | aurel32 | tcg_temp_free(tmp); |
333 | 9c29504e | aurel32 | } |
334 | dbb30fe6 | Richard Henderson | gen_bcond_pcload(ctx, disp, lab_true); |
335 | 4c9649a9 | j_mayer | } |
336 | 4c9649a9 | j_mayer | |
337 | dbb30fe6 | Richard Henderson | /* Generate a forward TCG branch to LAB_TRUE if RA cmp 0.0.
|
338 | dbb30fe6 | Richard Henderson | This is complicated by the fact that -0.0 compares the same as +0.0. */
|
339 | dbb30fe6 | Richard Henderson | |
340 | dbb30fe6 | Richard Henderson | static void gen_fbcond_internal(TCGCond cond, TCGv src, int lab_true) |
341 | 4c9649a9 | j_mayer | { |
342 | dbb30fe6 | Richard Henderson | int lab_false = -1; |
343 | dbb30fe6 | Richard Henderson | uint64_t mzero = 1ull << 63; |
344 | f18cd223 | aurel32 | TCGv tmp; |
345 | f18cd223 | aurel32 | |
346 | dbb30fe6 | Richard Henderson | switch (cond) {
|
347 | dbb30fe6 | Richard Henderson | case TCG_COND_LE:
|
348 | dbb30fe6 | Richard Henderson | case TCG_COND_GT:
|
349 | dbb30fe6 | Richard Henderson | /* For <= or >, the -0.0 value directly compares the way we want. */
|
350 | dbb30fe6 | Richard Henderson | tcg_gen_brcondi_i64(cond, src, 0, lab_true);
|
351 | a7812ae4 | pbrook | break;
|
352 | dbb30fe6 | Richard Henderson | |
353 | dbb30fe6 | Richard Henderson | case TCG_COND_EQ:
|
354 | dbb30fe6 | Richard Henderson | case TCG_COND_NE:
|
355 | dbb30fe6 | Richard Henderson | /* For == or !=, we can simply mask off the sign bit and compare. */
|
356 | dbb30fe6 | Richard Henderson | /* ??? Assume that the temporary is reclaimed at the branch. */
|
357 | dbb30fe6 | Richard Henderson | tmp = tcg_temp_new(); |
358 | dbb30fe6 | Richard Henderson | tcg_gen_andi_i64(tmp, src, mzero - 1);
|
359 | dbb30fe6 | Richard Henderson | tcg_gen_brcondi_i64(cond, tmp, 0, lab_true);
|
360 | a7812ae4 | pbrook | break;
|
361 | dbb30fe6 | Richard Henderson | |
362 | dbb30fe6 | Richard Henderson | case TCG_COND_GE:
|
363 | dbb30fe6 | Richard Henderson | /* For >=, emit two branches to the destination. */
|
364 | dbb30fe6 | Richard Henderson | tcg_gen_brcondi_i64(cond, src, 0, lab_true);
|
365 | dbb30fe6 | Richard Henderson | tcg_gen_brcondi_i64(TCG_COND_EQ, src, mzero, lab_true); |
366 | a7812ae4 | pbrook | break;
|
367 | dbb30fe6 | Richard Henderson | |
368 | dbb30fe6 | Richard Henderson | case TCG_COND_LT:
|
369 | dbb30fe6 | Richard Henderson | /* For <, first filter out -0.0 to what will be the fallthru. */
|
370 | dbb30fe6 | Richard Henderson | lab_false = gen_new_label(); |
371 | dbb30fe6 | Richard Henderson | tcg_gen_brcondi_i64(TCG_COND_EQ, src, mzero, lab_false); |
372 | dbb30fe6 | Richard Henderson | tcg_gen_brcondi_i64(cond, src, 0, lab_true);
|
373 | dbb30fe6 | Richard Henderson | gen_set_label(lab_false); |
374 | a7812ae4 | pbrook | break;
|
375 | dbb30fe6 | Richard Henderson | |
376 | a7812ae4 | pbrook | default:
|
377 | a7812ae4 | pbrook | abort(); |
378 | f18cd223 | aurel32 | } |
379 | dbb30fe6 | Richard Henderson | } |
380 | dbb30fe6 | Richard Henderson | |
381 | dbb30fe6 | Richard Henderson | static void gen_fbcond(DisasContext *ctx, TCGCond cond, int ra, int32_t disp) |
382 | dbb30fe6 | Richard Henderson | { |
383 | dbb30fe6 | Richard Henderson | int lab_true;
|
384 | dbb30fe6 | Richard Henderson | |
385 | dbb30fe6 | Richard Henderson | if (unlikely(ra == 31)) { |
386 | dbb30fe6 | Richard Henderson | /* Very uncommon case, but easier to optimize it to an integer
|
387 | dbb30fe6 | Richard Henderson | comparison than continuing with the floating point comparison. */
|
388 | dbb30fe6 | Richard Henderson | gen_bcond(ctx, cond, ra, disp, 0);
|
389 | dbb30fe6 | Richard Henderson | return;
|
390 | dbb30fe6 | Richard Henderson | } |
391 | dbb30fe6 | Richard Henderson | |
392 | dbb30fe6 | Richard Henderson | lab_true = gen_new_label(); |
393 | dbb30fe6 | Richard Henderson | gen_fbcond_internal(cond, cpu_fir[ra], lab_true); |
394 | dbb30fe6 | Richard Henderson | gen_bcond_pcload(ctx, disp, lab_true); |
395 | 4c9649a9 | j_mayer | } |
396 | 4c9649a9 | j_mayer | |
397 | 636aa200 | Blue Swirl | static inline void gen_cmov(TCGCond inv_cond, int ra, int rb, int rc, |
398 | 636aa200 | Blue Swirl | int islit, uint8_t lit, int mask) |
399 | 4c9649a9 | j_mayer | { |
400 | 9c29504e | aurel32 | int l1;
|
401 | 9c29504e | aurel32 | |
402 | 9c29504e | aurel32 | if (unlikely(rc == 31)) |
403 | 9c29504e | aurel32 | return;
|
404 | 9c29504e | aurel32 | |
405 | 9c29504e | aurel32 | l1 = gen_new_label(); |
406 | 9c29504e | aurel32 | |
407 | 9c29504e | aurel32 | if (ra != 31) { |
408 | 9c29504e | aurel32 | if (mask) {
|
409 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
410 | 9c29504e | aurel32 | tcg_gen_andi_i64(tmp, cpu_ir[ra], 1);
|
411 | 9c29504e | aurel32 | tcg_gen_brcondi_i64(inv_cond, tmp, 0, l1);
|
412 | 9c29504e | aurel32 | tcg_temp_free(tmp); |
413 | 9c29504e | aurel32 | } else
|
414 | 9c29504e | aurel32 | tcg_gen_brcondi_i64(inv_cond, cpu_ir[ra], 0, l1);
|
415 | 9c29504e | aurel32 | } else {
|
416 | 9c29504e | aurel32 | /* Very uncommon case - Do not bother to optimize. */
|
417 | 9c29504e | aurel32 | TCGv tmp = tcg_const_i64(0);
|
418 | 9c29504e | aurel32 | tcg_gen_brcondi_i64(inv_cond, tmp, 0, l1);
|
419 | 9c29504e | aurel32 | tcg_temp_free(tmp); |
420 | 9c29504e | aurel32 | } |
421 | 9c29504e | aurel32 | |
422 | 4c9649a9 | j_mayer | if (islit)
|
423 | 9c29504e | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
424 | 4c9649a9 | j_mayer | else
|
425 | dfaa8583 | aurel32 | tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
426 | 9c29504e | aurel32 | gen_set_label(l1); |
427 | 4c9649a9 | j_mayer | } |
428 | 4c9649a9 | j_mayer | |
429 | dbb30fe6 | Richard Henderson | static void gen_fcmov(TCGCond inv_cond, int ra, int rb, int rc) |
430 | dbb30fe6 | Richard Henderson | { |
431 | dbb30fe6 | Richard Henderson | TCGv va = cpu_fir[ra]; |
432 | dbb30fe6 | Richard Henderson | int l1;
|
433 | dbb30fe6 | Richard Henderson | |
434 | dbb30fe6 | Richard Henderson | if (unlikely(rc == 31)) |
435 | dbb30fe6 | Richard Henderson | return;
|
436 | dbb30fe6 | Richard Henderson | if (unlikely(ra == 31)) { |
437 | dbb30fe6 | Richard Henderson | /* ??? Assume that the temporary is reclaimed at the branch. */
|
438 | dbb30fe6 | Richard Henderson | va = tcg_const_i64(0);
|
439 | dbb30fe6 | Richard Henderson | } |
440 | dbb30fe6 | Richard Henderson | |
441 | dbb30fe6 | Richard Henderson | l1 = gen_new_label(); |
442 | dbb30fe6 | Richard Henderson | gen_fbcond_internal(inv_cond, va, l1); |
443 | dbb30fe6 | Richard Henderson | |
444 | dbb30fe6 | Richard Henderson | if (rb != 31) |
445 | dbb30fe6 | Richard Henderson | tcg_gen_mov_i64(cpu_fir[rc], cpu_fir[rb]); |
446 | dbb30fe6 | Richard Henderson | else
|
447 | dbb30fe6 | Richard Henderson | tcg_gen_movi_i64(cpu_fir[rc], 0);
|
448 | dbb30fe6 | Richard Henderson | gen_set_label(l1); |
449 | dbb30fe6 | Richard Henderson | } |
450 | dbb30fe6 | Richard Henderson | |
451 | f24518b5 | Richard Henderson | #define QUAL_RM_N 0x080 /* Round mode nearest even */ |
452 | f24518b5 | Richard Henderson | #define QUAL_RM_C 0x000 /* Round mode chopped */ |
453 | f24518b5 | Richard Henderson | #define QUAL_RM_M 0x040 /* Round mode minus infinity */ |
454 | f24518b5 | Richard Henderson | #define QUAL_RM_D 0x0c0 /* Round mode dynamic */ |
455 | f24518b5 | Richard Henderson | #define QUAL_RM_MASK 0x0c0 |
456 | f24518b5 | Richard Henderson | |
457 | f24518b5 | Richard Henderson | #define QUAL_U 0x100 /* Underflow enable (fp output) */ |
458 | f24518b5 | Richard Henderson | #define QUAL_V 0x100 /* Overflow enable (int output) */ |
459 | f24518b5 | Richard Henderson | #define QUAL_S 0x400 /* Software completion enable */ |
460 | f24518b5 | Richard Henderson | #define QUAL_I 0x200 /* Inexact detection enable */ |
461 | f24518b5 | Richard Henderson | |
462 | f24518b5 | Richard Henderson | static void gen_qual_roundmode(DisasContext *ctx, int fn11) |
463 | f24518b5 | Richard Henderson | { |
464 | f24518b5 | Richard Henderson | TCGv_i32 tmp; |
465 | f24518b5 | Richard Henderson | |
466 | f24518b5 | Richard Henderson | fn11 &= QUAL_RM_MASK; |
467 | f24518b5 | Richard Henderson | if (fn11 == ctx->tb_rm) {
|
468 | f24518b5 | Richard Henderson | return;
|
469 | f24518b5 | Richard Henderson | } |
470 | f24518b5 | Richard Henderson | ctx->tb_rm = fn11; |
471 | f24518b5 | Richard Henderson | |
472 | f24518b5 | Richard Henderson | tmp = tcg_temp_new_i32(); |
473 | f24518b5 | Richard Henderson | switch (fn11) {
|
474 | f24518b5 | Richard Henderson | case QUAL_RM_N:
|
475 | f24518b5 | Richard Henderson | tcg_gen_movi_i32(tmp, float_round_nearest_even); |
476 | f24518b5 | Richard Henderson | break;
|
477 | f24518b5 | Richard Henderson | case QUAL_RM_C:
|
478 | f24518b5 | Richard Henderson | tcg_gen_movi_i32(tmp, float_round_to_zero); |
479 | f24518b5 | Richard Henderson | break;
|
480 | f24518b5 | Richard Henderson | case QUAL_RM_M:
|
481 | f24518b5 | Richard Henderson | tcg_gen_movi_i32(tmp, float_round_down); |
482 | f24518b5 | Richard Henderson | break;
|
483 | f24518b5 | Richard Henderson | case QUAL_RM_D:
|
484 | f24518b5 | Richard Henderson | tcg_gen_ld8u_i32(tmp, cpu_env, offsetof(CPUState, fpcr_dyn_round)); |
485 | f24518b5 | Richard Henderson | break;
|
486 | f24518b5 | Richard Henderson | } |
487 | f24518b5 | Richard Henderson | |
488 | f24518b5 | Richard Henderson | #if defined(CONFIG_SOFTFLOAT_INLINE)
|
489 | f24518b5 | Richard Henderson | /* ??? The "softfloat.h" interface is to call set_float_rounding_mode.
|
490 | f24518b5 | Richard Henderson | With CONFIG_SOFTFLOAT that expands to an out-of-line call that just
|
491 | f24518b5 | Richard Henderson | sets the one field. */
|
492 | f24518b5 | Richard Henderson | tcg_gen_st8_i32(tmp, cpu_env, |
493 | f24518b5 | Richard Henderson | offsetof(CPUState, fp_status.float_rounding_mode)); |
494 | f24518b5 | Richard Henderson | #else
|
495 | f24518b5 | Richard Henderson | gen_helper_setroundmode(tmp); |
496 | f24518b5 | Richard Henderson | #endif
|
497 | f24518b5 | Richard Henderson | |
498 | f24518b5 | Richard Henderson | tcg_temp_free_i32(tmp); |
499 | f24518b5 | Richard Henderson | } |
500 | f24518b5 | Richard Henderson | |
501 | f24518b5 | Richard Henderson | static void gen_qual_flushzero(DisasContext *ctx, int fn11) |
502 | f24518b5 | Richard Henderson | { |
503 | f24518b5 | Richard Henderson | TCGv_i32 tmp; |
504 | f24518b5 | Richard Henderson | |
505 | f24518b5 | Richard Henderson | fn11 &= QUAL_U; |
506 | f24518b5 | Richard Henderson | if (fn11 == ctx->tb_ftz) {
|
507 | f24518b5 | Richard Henderson | return;
|
508 | f24518b5 | Richard Henderson | } |
509 | f24518b5 | Richard Henderson | ctx->tb_ftz = fn11; |
510 | f24518b5 | Richard Henderson | |
511 | f24518b5 | Richard Henderson | tmp = tcg_temp_new_i32(); |
512 | f24518b5 | Richard Henderson | if (fn11) {
|
513 | f24518b5 | Richard Henderson | /* Underflow is enabled, use the FPCR setting. */
|
514 | f24518b5 | Richard Henderson | tcg_gen_ld8u_i32(tmp, cpu_env, offsetof(CPUState, fpcr_flush_to_zero)); |
515 | f24518b5 | Richard Henderson | } else {
|
516 | f24518b5 | Richard Henderson | /* Underflow is disabled, force flush-to-zero. */
|
517 | f24518b5 | Richard Henderson | tcg_gen_movi_i32(tmp, 1);
|
518 | f24518b5 | Richard Henderson | } |
519 | f24518b5 | Richard Henderson | |
520 | f24518b5 | Richard Henderson | #if defined(CONFIG_SOFTFLOAT_INLINE)
|
521 | f24518b5 | Richard Henderson | tcg_gen_st8_i32(tmp, cpu_env, |
522 | f24518b5 | Richard Henderson | offsetof(CPUState, fp_status.flush_to_zero)); |
523 | f24518b5 | Richard Henderson | #else
|
524 | f24518b5 | Richard Henderson | gen_helper_setflushzero(tmp); |
525 | f24518b5 | Richard Henderson | #endif
|
526 | f24518b5 | Richard Henderson | |
527 | f24518b5 | Richard Henderson | tcg_temp_free_i32(tmp); |
528 | f24518b5 | Richard Henderson | } |
529 | f24518b5 | Richard Henderson | |
530 | f24518b5 | Richard Henderson | static TCGv gen_ieee_input(int reg, int fn11, int is_cmp) |
531 | f24518b5 | Richard Henderson | { |
532 | f24518b5 | Richard Henderson | TCGv val = tcg_temp_new(); |
533 | f24518b5 | Richard Henderson | if (reg == 31) { |
534 | f24518b5 | Richard Henderson | tcg_gen_movi_i64(val, 0);
|
535 | f24518b5 | Richard Henderson | } else if (fn11 & QUAL_S) { |
536 | f24518b5 | Richard Henderson | gen_helper_ieee_input_s(val, cpu_fir[reg]); |
537 | f24518b5 | Richard Henderson | } else if (is_cmp) { |
538 | f24518b5 | Richard Henderson | gen_helper_ieee_input_cmp(val, cpu_fir[reg]); |
539 | f24518b5 | Richard Henderson | } else {
|
540 | f24518b5 | Richard Henderson | gen_helper_ieee_input(val, cpu_fir[reg]); |
541 | f24518b5 | Richard Henderson | } |
542 | f24518b5 | Richard Henderson | return val;
|
543 | f24518b5 | Richard Henderson | } |
544 | f24518b5 | Richard Henderson | |
545 | f24518b5 | Richard Henderson | static void gen_fp_exc_clear(void) |
546 | f24518b5 | Richard Henderson | { |
547 | f24518b5 | Richard Henderson | #if defined(CONFIG_SOFTFLOAT_INLINE)
|
548 | f24518b5 | Richard Henderson | TCGv_i32 zero = tcg_const_i32(0);
|
549 | f24518b5 | Richard Henderson | tcg_gen_st8_i32(zero, cpu_env, |
550 | f24518b5 | Richard Henderson | offsetof(CPUState, fp_status.float_exception_flags)); |
551 | f24518b5 | Richard Henderson | tcg_temp_free_i32(zero); |
552 | f24518b5 | Richard Henderson | #else
|
553 | f24518b5 | Richard Henderson | gen_helper_fp_exc_clear(); |
554 | f24518b5 | Richard Henderson | #endif
|
555 | f24518b5 | Richard Henderson | } |
556 | f24518b5 | Richard Henderson | |
557 | f24518b5 | Richard Henderson | static void gen_fp_exc_raise_ignore(int rc, int fn11, int ignore) |
558 | f24518b5 | Richard Henderson | { |
559 | f24518b5 | Richard Henderson | /* ??? We ought to be able to do something with imprecise exceptions.
|
560 | f24518b5 | Richard Henderson | E.g. notice we're still in the trap shadow of something within the
|
561 | f24518b5 | Richard Henderson | TB and do not generate the code to signal the exception; end the TB
|
562 | f24518b5 | Richard Henderson | when an exception is forced to arrive, either by consumption of a
|
563 | f24518b5 | Richard Henderson | register value or TRAPB or EXCB. */
|
564 | f24518b5 | Richard Henderson | TCGv_i32 exc = tcg_temp_new_i32(); |
565 | f24518b5 | Richard Henderson | TCGv_i32 reg; |
566 | f24518b5 | Richard Henderson | |
567 | f24518b5 | Richard Henderson | #if defined(CONFIG_SOFTFLOAT_INLINE)
|
568 | f24518b5 | Richard Henderson | tcg_gen_ld8u_i32(exc, cpu_env, |
569 | f24518b5 | Richard Henderson | offsetof(CPUState, fp_status.float_exception_flags)); |
570 | f24518b5 | Richard Henderson | #else
|
571 | f24518b5 | Richard Henderson | gen_helper_fp_exc_get(exc); |
572 | f24518b5 | Richard Henderson | #endif
|
573 | f24518b5 | Richard Henderson | |
574 | f24518b5 | Richard Henderson | if (ignore) {
|
575 | f24518b5 | Richard Henderson | tcg_gen_andi_i32(exc, exc, ~ignore); |
576 | f24518b5 | Richard Henderson | } |
577 | f24518b5 | Richard Henderson | |
578 | f24518b5 | Richard Henderson | /* ??? Pass in the regno of the destination so that the helper can
|
579 | f24518b5 | Richard Henderson | set EXC_MASK, which contains a bitmask of destination registers
|
580 | f24518b5 | Richard Henderson | that have caused arithmetic traps. A simple userspace emulation
|
581 | f24518b5 | Richard Henderson | does not require this. We do need it for a guest kernel's entArith,
|
582 | f24518b5 | Richard Henderson | or if we were to do something clever with imprecise exceptions. */
|
583 | f24518b5 | Richard Henderson | reg = tcg_const_i32(rc + 32);
|
584 | f24518b5 | Richard Henderson | |
585 | f24518b5 | Richard Henderson | if (fn11 & QUAL_S) {
|
586 | f24518b5 | Richard Henderson | gen_helper_fp_exc_raise_s(exc, reg); |
587 | f24518b5 | Richard Henderson | } else {
|
588 | f24518b5 | Richard Henderson | gen_helper_fp_exc_raise(exc, reg); |
589 | f24518b5 | Richard Henderson | } |
590 | f24518b5 | Richard Henderson | |
591 | f24518b5 | Richard Henderson | tcg_temp_free_i32(reg); |
592 | f24518b5 | Richard Henderson | tcg_temp_free_i32(exc); |
593 | f24518b5 | Richard Henderson | } |
594 | f24518b5 | Richard Henderson | |
595 | f24518b5 | Richard Henderson | static inline void gen_fp_exc_raise(int rc, int fn11) |
596 | f24518b5 | Richard Henderson | { |
597 | f24518b5 | Richard Henderson | gen_fp_exc_raise_ignore(rc, fn11, fn11 & QUAL_I ? 0 : float_flag_inexact);
|
598 | 4c9649a9 | j_mayer | } |
599 | f24518b5 | Richard Henderson | |
600 | f24518b5 | Richard Henderson | #define FARITH2(name) \
|
601 | f24518b5 | Richard Henderson | static inline void glue(gen_f, name)(int rb, int rc) \ |
602 | f24518b5 | Richard Henderson | { \ |
603 | f24518b5 | Richard Henderson | if (unlikely(rc == 31)) { \ |
604 | f24518b5 | Richard Henderson | return; \
|
605 | f24518b5 | Richard Henderson | } \ |
606 | f24518b5 | Richard Henderson | if (rb != 31) { \ |
607 | f24518b5 | Richard Henderson | gen_helper_ ## name (cpu_fir[rc], cpu_fir[rb]); \ |
608 | f24518b5 | Richard Henderson | } else { \
|
609 | f24518b5 | Richard Henderson | TCGv tmp = tcg_const_i64(0); \
|
610 | f24518b5 | Richard Henderson | gen_helper_ ## name (cpu_fir[rc], tmp); \ |
611 | f24518b5 | Richard Henderson | tcg_temp_free(tmp); \ |
612 | f24518b5 | Richard Henderson | } \ |
613 | f24518b5 | Richard Henderson | } |
614 | f24518b5 | Richard Henderson | FARITH2(cvtlq) |
615 | f24518b5 | Richard Henderson | FARITH2(cvtql) |
616 | f24518b5 | Richard Henderson | FARITH2(cvtql_v) |
617 | f24518b5 | Richard Henderson | FARITH2(cvtql_sv) |
618 | f24518b5 | Richard Henderson | |
619 | f24518b5 | Richard Henderson | /* ??? VAX instruction qualifiers ignored. */
|
620 | a7812ae4 | pbrook | FARITH2(sqrtf) |
621 | a7812ae4 | pbrook | FARITH2(sqrtg) |
622 | a7812ae4 | pbrook | FARITH2(cvtgf) |
623 | a7812ae4 | pbrook | FARITH2(cvtgq) |
624 | a7812ae4 | pbrook | FARITH2(cvtqf) |
625 | a7812ae4 | pbrook | FARITH2(cvtqg) |
626 | f24518b5 | Richard Henderson | |
627 | f24518b5 | Richard Henderson | static void gen_ieee_arith2(DisasContext *ctx, void (*helper)(TCGv, TCGv), |
628 | f24518b5 | Richard Henderson | int rb, int rc, int fn11) |
629 | f24518b5 | Richard Henderson | { |
630 | f24518b5 | Richard Henderson | TCGv vb; |
631 | f24518b5 | Richard Henderson | |
632 | f24518b5 | Richard Henderson | /* ??? This is wrong: the instruction is not a nop, it still may
|
633 | f24518b5 | Richard Henderson | raise exceptions. */
|
634 | f24518b5 | Richard Henderson | if (unlikely(rc == 31)) { |
635 | f24518b5 | Richard Henderson | return;
|
636 | f24518b5 | Richard Henderson | } |
637 | f24518b5 | Richard Henderson | |
638 | f24518b5 | Richard Henderson | gen_qual_roundmode(ctx, fn11); |
639 | f24518b5 | Richard Henderson | gen_qual_flushzero(ctx, fn11); |
640 | f24518b5 | Richard Henderson | gen_fp_exc_clear(); |
641 | f24518b5 | Richard Henderson | |
642 | f24518b5 | Richard Henderson | vb = gen_ieee_input(rb, fn11, 0);
|
643 | f24518b5 | Richard Henderson | helper(cpu_fir[rc], vb); |
644 | f24518b5 | Richard Henderson | tcg_temp_free(vb); |
645 | f24518b5 | Richard Henderson | |
646 | f24518b5 | Richard Henderson | gen_fp_exc_raise(rc, fn11); |
647 | f24518b5 | Richard Henderson | } |
648 | f24518b5 | Richard Henderson | |
649 | f24518b5 | Richard Henderson | #define IEEE_ARITH2(name) \
|
650 | f24518b5 | Richard Henderson | static inline void glue(gen_f, name)(DisasContext *ctx, \ |
651 | f24518b5 | Richard Henderson | int rb, int rc, int fn11) \ |
652 | f24518b5 | Richard Henderson | { \ |
653 | f24518b5 | Richard Henderson | gen_ieee_arith2(ctx, gen_helper_##name, rb, rc, fn11); \ |
654 | f24518b5 | Richard Henderson | } |
655 | f24518b5 | Richard Henderson | IEEE_ARITH2(sqrts) |
656 | f24518b5 | Richard Henderson | IEEE_ARITH2(sqrtt) |
657 | f24518b5 | Richard Henderson | IEEE_ARITH2(cvtst) |
658 | f24518b5 | Richard Henderson | IEEE_ARITH2(cvtts) |
659 | f24518b5 | Richard Henderson | |
660 | f24518b5 | Richard Henderson | static void gen_fcvttq(DisasContext *ctx, int rb, int rc, int fn11) |
661 | f24518b5 | Richard Henderson | { |
662 | f24518b5 | Richard Henderson | TCGv vb; |
663 | f24518b5 | Richard Henderson | int ignore = 0; |
664 | f24518b5 | Richard Henderson | |
665 | f24518b5 | Richard Henderson | /* ??? This is wrong: the instruction is not a nop, it still may
|
666 | f24518b5 | Richard Henderson | raise exceptions. */
|
667 | f24518b5 | Richard Henderson | if (unlikely(rc == 31)) { |
668 | f24518b5 | Richard Henderson | return;
|
669 | f24518b5 | Richard Henderson | } |
670 | f24518b5 | Richard Henderson | |
671 | f24518b5 | Richard Henderson | /* No need to set flushzero, since we have an integer output. */
|
672 | f24518b5 | Richard Henderson | gen_fp_exc_clear(); |
673 | f24518b5 | Richard Henderson | vb = gen_ieee_input(rb, fn11, 0);
|
674 | f24518b5 | Richard Henderson | |
675 | f24518b5 | Richard Henderson | /* Almost all integer conversions use cropped rounding, and most
|
676 | f24518b5 | Richard Henderson | also do not have integer overflow enabled. Special case that. */
|
677 | f24518b5 | Richard Henderson | switch (fn11) {
|
678 | f24518b5 | Richard Henderson | case QUAL_RM_C:
|
679 | f24518b5 | Richard Henderson | gen_helper_cvttq_c(cpu_fir[rc], vb); |
680 | f24518b5 | Richard Henderson | break;
|
681 | f24518b5 | Richard Henderson | case QUAL_V | QUAL_RM_C:
|
682 | f24518b5 | Richard Henderson | case QUAL_S | QUAL_V | QUAL_RM_C:
|
683 | f24518b5 | Richard Henderson | ignore = float_flag_inexact; |
684 | f24518b5 | Richard Henderson | /* FALLTHRU */
|
685 | f24518b5 | Richard Henderson | case QUAL_S | QUAL_V | QUAL_I | QUAL_RM_C:
|
686 | f24518b5 | Richard Henderson | gen_helper_cvttq_svic(cpu_fir[rc], vb); |
687 | f24518b5 | Richard Henderson | break;
|
688 | f24518b5 | Richard Henderson | default:
|
689 | f24518b5 | Richard Henderson | gen_qual_roundmode(ctx, fn11); |
690 | f24518b5 | Richard Henderson | gen_helper_cvttq(cpu_fir[rc], vb); |
691 | f24518b5 | Richard Henderson | ignore |= (fn11 & QUAL_V ? 0 : float_flag_overflow);
|
692 | f24518b5 | Richard Henderson | ignore |= (fn11 & QUAL_I ? 0 : float_flag_inexact);
|
693 | f24518b5 | Richard Henderson | break;
|
694 | f24518b5 | Richard Henderson | } |
695 | f24518b5 | Richard Henderson | tcg_temp_free(vb); |
696 | f24518b5 | Richard Henderson | |
697 | f24518b5 | Richard Henderson | gen_fp_exc_raise_ignore(rc, fn11, ignore); |
698 | 4c9649a9 | j_mayer | } |
699 | 4c9649a9 | j_mayer | |
700 | f24518b5 | Richard Henderson | static void gen_ieee_intcvt(DisasContext *ctx, void (*helper)(TCGv, TCGv), |
701 | f24518b5 | Richard Henderson | int rb, int rc, int fn11) |
702 | f24518b5 | Richard Henderson | { |
703 | f24518b5 | Richard Henderson | TCGv vb; |
704 | f24518b5 | Richard Henderson | |
705 | f24518b5 | Richard Henderson | /* ??? This is wrong: the instruction is not a nop, it still may
|
706 | f24518b5 | Richard Henderson | raise exceptions. */
|
707 | f24518b5 | Richard Henderson | if (unlikely(rc == 31)) { |
708 | f24518b5 | Richard Henderson | return;
|
709 | f24518b5 | Richard Henderson | } |
710 | f24518b5 | Richard Henderson | |
711 | f24518b5 | Richard Henderson | gen_qual_roundmode(ctx, fn11); |
712 | f24518b5 | Richard Henderson | |
713 | f24518b5 | Richard Henderson | if (rb == 31) { |
714 | f24518b5 | Richard Henderson | vb = tcg_const_i64(0);
|
715 | f24518b5 | Richard Henderson | } else {
|
716 | f24518b5 | Richard Henderson | vb = cpu_fir[rb]; |
717 | f24518b5 | Richard Henderson | } |
718 | f24518b5 | Richard Henderson | |
719 | f24518b5 | Richard Henderson | /* The only exception that can be raised by integer conversion
|
720 | f24518b5 | Richard Henderson | is inexact. Thus we only need to worry about exceptions when
|
721 | f24518b5 | Richard Henderson | inexact handling is requested. */
|
722 | f24518b5 | Richard Henderson | if (fn11 & QUAL_I) {
|
723 | f24518b5 | Richard Henderson | gen_fp_exc_clear(); |
724 | f24518b5 | Richard Henderson | helper(cpu_fir[rc], vb); |
725 | f24518b5 | Richard Henderson | gen_fp_exc_raise(rc, fn11); |
726 | f24518b5 | Richard Henderson | } else {
|
727 | f24518b5 | Richard Henderson | helper(cpu_fir[rc], vb); |
728 | f24518b5 | Richard Henderson | } |
729 | f24518b5 | Richard Henderson | |
730 | f24518b5 | Richard Henderson | if (rb == 31) { |
731 | f24518b5 | Richard Henderson | tcg_temp_free(vb); |
732 | f24518b5 | Richard Henderson | } |
733 | f24518b5 | Richard Henderson | } |
734 | f24518b5 | Richard Henderson | |
735 | f24518b5 | Richard Henderson | #define IEEE_INTCVT(name) \
|
736 | f24518b5 | Richard Henderson | static inline void glue(gen_f, name)(DisasContext *ctx, \ |
737 | f24518b5 | Richard Henderson | int rb, int rc, int fn11) \ |
738 | f24518b5 | Richard Henderson | { \ |
739 | f24518b5 | Richard Henderson | gen_ieee_intcvt(ctx, gen_helper_##name, rb, rc, fn11); \ |
740 | f24518b5 | Richard Henderson | } |
741 | f24518b5 | Richard Henderson | IEEE_INTCVT(cvtqs) |
742 | f24518b5 | Richard Henderson | IEEE_INTCVT(cvtqt) |
743 | f24518b5 | Richard Henderson | |
744 | f24518b5 | Richard Henderson | #define FARITH3(name) \
|
745 | f24518b5 | Richard Henderson | static inline void glue(gen_f, name)(int ra, int rb, int rc) \ |
746 | f24518b5 | Richard Henderson | { \ |
747 | f24518b5 | Richard Henderson | TCGv va, vb; \ |
748 | f24518b5 | Richard Henderson | \ |
749 | f24518b5 | Richard Henderson | if (unlikely(rc == 31)) { \ |
750 | f24518b5 | Richard Henderson | return; \
|
751 | f24518b5 | Richard Henderson | } \ |
752 | f24518b5 | Richard Henderson | if (ra == 31) { \ |
753 | f24518b5 | Richard Henderson | va = tcg_const_i64(0); \
|
754 | f24518b5 | Richard Henderson | } else { \
|
755 | f24518b5 | Richard Henderson | va = cpu_fir[ra]; \ |
756 | f24518b5 | Richard Henderson | } \ |
757 | f24518b5 | Richard Henderson | if (rb == 31) { \ |
758 | f24518b5 | Richard Henderson | vb = tcg_const_i64(0); \
|
759 | f24518b5 | Richard Henderson | } else { \
|
760 | f24518b5 | Richard Henderson | vb = cpu_fir[rb]; \ |
761 | f24518b5 | Richard Henderson | } \ |
762 | f24518b5 | Richard Henderson | \ |
763 | f24518b5 | Richard Henderson | gen_helper_ ## name (cpu_fir[rc], va, vb); \ |
764 | f24518b5 | Richard Henderson | \ |
765 | f24518b5 | Richard Henderson | if (ra == 31) { \ |
766 | f24518b5 | Richard Henderson | tcg_temp_free(va); \ |
767 | f24518b5 | Richard Henderson | } \ |
768 | f24518b5 | Richard Henderson | if (rb == 31) { \ |
769 | f24518b5 | Richard Henderson | tcg_temp_free(vb); \ |
770 | f24518b5 | Richard Henderson | } \ |
771 | f24518b5 | Richard Henderson | } |
772 | f24518b5 | Richard Henderson | /* ??? Ought to expand these inline; simple masking operations. */
|
773 | f24518b5 | Richard Henderson | FARITH3(cpys) |
774 | f24518b5 | Richard Henderson | FARITH3(cpysn) |
775 | f24518b5 | Richard Henderson | FARITH3(cpyse) |
776 | f24518b5 | Richard Henderson | |
777 | f24518b5 | Richard Henderson | /* ??? VAX instruction qualifiers ignored. */
|
778 | a7812ae4 | pbrook | FARITH3(addf) |
779 | a7812ae4 | pbrook | FARITH3(subf) |
780 | a7812ae4 | pbrook | FARITH3(mulf) |
781 | a7812ae4 | pbrook | FARITH3(divf) |
782 | a7812ae4 | pbrook | FARITH3(addg) |
783 | a7812ae4 | pbrook | FARITH3(subg) |
784 | a7812ae4 | pbrook | FARITH3(mulg) |
785 | a7812ae4 | pbrook | FARITH3(divg) |
786 | a7812ae4 | pbrook | FARITH3(cmpgeq) |
787 | a7812ae4 | pbrook | FARITH3(cmpglt) |
788 | a7812ae4 | pbrook | FARITH3(cmpgle) |
789 | f24518b5 | Richard Henderson | |
790 | f24518b5 | Richard Henderson | static void gen_ieee_arith3(DisasContext *ctx, |
791 | f24518b5 | Richard Henderson | void (*helper)(TCGv, TCGv, TCGv),
|
792 | f24518b5 | Richard Henderson | int ra, int rb, int rc, int fn11) |
793 | f24518b5 | Richard Henderson | { |
794 | f24518b5 | Richard Henderson | TCGv va, vb; |
795 | f24518b5 | Richard Henderson | |
796 | f24518b5 | Richard Henderson | /* ??? This is wrong: the instruction is not a nop, it still may
|
797 | f24518b5 | Richard Henderson | raise exceptions. */
|
798 | f24518b5 | Richard Henderson | if (unlikely(rc == 31)) { |
799 | f24518b5 | Richard Henderson | return;
|
800 | f24518b5 | Richard Henderson | } |
801 | f24518b5 | Richard Henderson | |
802 | f24518b5 | Richard Henderson | gen_qual_roundmode(ctx, fn11); |
803 | f24518b5 | Richard Henderson | gen_qual_flushzero(ctx, fn11); |
804 | f24518b5 | Richard Henderson | gen_fp_exc_clear(); |
805 | f24518b5 | Richard Henderson | |
806 | f24518b5 | Richard Henderson | va = gen_ieee_input(ra, fn11, 0);
|
807 | f24518b5 | Richard Henderson | vb = gen_ieee_input(rb, fn11, 0);
|
808 | f24518b5 | Richard Henderson | helper(cpu_fir[rc], va, vb); |
809 | f24518b5 | Richard Henderson | tcg_temp_free(va); |
810 | f24518b5 | Richard Henderson | tcg_temp_free(vb); |
811 | f24518b5 | Richard Henderson | |
812 | f24518b5 | Richard Henderson | gen_fp_exc_raise(rc, fn11); |
813 | f24518b5 | Richard Henderson | } |
814 | f24518b5 | Richard Henderson | |
815 | f24518b5 | Richard Henderson | #define IEEE_ARITH3(name) \
|
816 | f24518b5 | Richard Henderson | static inline void glue(gen_f, name)(DisasContext *ctx, \ |
817 | f24518b5 | Richard Henderson | int ra, int rb, int rc, int fn11) \ |
818 | f24518b5 | Richard Henderson | { \ |
819 | f24518b5 | Richard Henderson | gen_ieee_arith3(ctx, gen_helper_##name, ra, rb, rc, fn11); \ |
820 | f24518b5 | Richard Henderson | } |
821 | f24518b5 | Richard Henderson | IEEE_ARITH3(adds) |
822 | f24518b5 | Richard Henderson | IEEE_ARITH3(subs) |
823 | f24518b5 | Richard Henderson | IEEE_ARITH3(muls) |
824 | f24518b5 | Richard Henderson | IEEE_ARITH3(divs) |
825 | f24518b5 | Richard Henderson | IEEE_ARITH3(addt) |
826 | f24518b5 | Richard Henderson | IEEE_ARITH3(subt) |
827 | f24518b5 | Richard Henderson | IEEE_ARITH3(mult) |
828 | f24518b5 | Richard Henderson | IEEE_ARITH3(divt) |
829 | f24518b5 | Richard Henderson | |
830 | f24518b5 | Richard Henderson | static void gen_ieee_compare(DisasContext *ctx, |
831 | f24518b5 | Richard Henderson | void (*helper)(TCGv, TCGv, TCGv),
|
832 | f24518b5 | Richard Henderson | int ra, int rb, int rc, int fn11) |
833 | f24518b5 | Richard Henderson | { |
834 | f24518b5 | Richard Henderson | TCGv va, vb; |
835 | f24518b5 | Richard Henderson | |
836 | f24518b5 | Richard Henderson | /* ??? This is wrong: the instruction is not a nop, it still may
|
837 | f24518b5 | Richard Henderson | raise exceptions. */
|
838 | f24518b5 | Richard Henderson | if (unlikely(rc == 31)) { |
839 | f24518b5 | Richard Henderson | return;
|
840 | f24518b5 | Richard Henderson | } |
841 | f24518b5 | Richard Henderson | |
842 | f24518b5 | Richard Henderson | gen_fp_exc_clear(); |
843 | f24518b5 | Richard Henderson | |
844 | f24518b5 | Richard Henderson | va = gen_ieee_input(ra, fn11, 1);
|
845 | f24518b5 | Richard Henderson | vb = gen_ieee_input(rb, fn11, 1);
|
846 | f24518b5 | Richard Henderson | helper(cpu_fir[rc], va, vb); |
847 | f24518b5 | Richard Henderson | tcg_temp_free(va); |
848 | f24518b5 | Richard Henderson | tcg_temp_free(vb); |
849 | f24518b5 | Richard Henderson | |
850 | f24518b5 | Richard Henderson | gen_fp_exc_raise(rc, fn11); |
851 | f24518b5 | Richard Henderson | } |
852 | f24518b5 | Richard Henderson | |
853 | f24518b5 | Richard Henderson | #define IEEE_CMP3(name) \
|
854 | f24518b5 | Richard Henderson | static inline void glue(gen_f, name)(DisasContext *ctx, \ |
855 | f24518b5 | Richard Henderson | int ra, int rb, int rc, int fn11) \ |
856 | f24518b5 | Richard Henderson | { \ |
857 | f24518b5 | Richard Henderson | gen_ieee_compare(ctx, gen_helper_##name, ra, rb, rc, fn11); \ |
858 | f24518b5 | Richard Henderson | } |
859 | f24518b5 | Richard Henderson | IEEE_CMP3(cmptun) |
860 | f24518b5 | Richard Henderson | IEEE_CMP3(cmpteq) |
861 | f24518b5 | Richard Henderson | IEEE_CMP3(cmptlt) |
862 | f24518b5 | Richard Henderson | IEEE_CMP3(cmptle) |
863 | a7812ae4 | pbrook | |
864 | 248c42f3 | Richard Henderson | static inline uint64_t zapnot_mask(uint8_t lit) |
865 | 248c42f3 | Richard Henderson | { |
866 | 248c42f3 | Richard Henderson | uint64_t mask = 0;
|
867 | 248c42f3 | Richard Henderson | int i;
|
868 | 248c42f3 | Richard Henderson | |
869 | 248c42f3 | Richard Henderson | for (i = 0; i < 8; ++i) { |
870 | 248c42f3 | Richard Henderson | if ((lit >> i) & 1) |
871 | 248c42f3 | Richard Henderson | mask |= 0xffull << (i * 8); |
872 | 248c42f3 | Richard Henderson | } |
873 | 248c42f3 | Richard Henderson | return mask;
|
874 | 248c42f3 | Richard Henderson | } |
875 | 248c42f3 | Richard Henderson | |
876 | 87d98f95 | Richard Henderson | /* Implement zapnot with an immediate operand, which expands to some
|
877 | 87d98f95 | Richard Henderson | form of immediate AND. This is a basic building block in the
|
878 | 87d98f95 | Richard Henderson | definition of many of the other byte manipulation instructions. */
|
879 | 248c42f3 | Richard Henderson | static void gen_zapnoti(TCGv dest, TCGv src, uint8_t lit) |
880 | 87d98f95 | Richard Henderson | { |
881 | 87d98f95 | Richard Henderson | switch (lit) {
|
882 | 87d98f95 | Richard Henderson | case 0x00: |
883 | 248c42f3 | Richard Henderson | tcg_gen_movi_i64(dest, 0);
|
884 | 87d98f95 | Richard Henderson | break;
|
885 | 87d98f95 | Richard Henderson | case 0x01: |
886 | 248c42f3 | Richard Henderson | tcg_gen_ext8u_i64(dest, src); |
887 | 87d98f95 | Richard Henderson | break;
|
888 | 87d98f95 | Richard Henderson | case 0x03: |
889 | 248c42f3 | Richard Henderson | tcg_gen_ext16u_i64(dest, src); |
890 | 87d98f95 | Richard Henderson | break;
|
891 | 87d98f95 | Richard Henderson | case 0x0f: |
892 | 248c42f3 | Richard Henderson | tcg_gen_ext32u_i64(dest, src); |
893 | 87d98f95 | Richard Henderson | break;
|
894 | 87d98f95 | Richard Henderson | case 0xff: |
895 | 248c42f3 | Richard Henderson | tcg_gen_mov_i64(dest, src); |
896 | 87d98f95 | Richard Henderson | break;
|
897 | 87d98f95 | Richard Henderson | default:
|
898 | 248c42f3 | Richard Henderson | tcg_gen_andi_i64 (dest, src, zapnot_mask (lit)); |
899 | 87d98f95 | Richard Henderson | break;
|
900 | 87d98f95 | Richard Henderson | } |
901 | 87d98f95 | Richard Henderson | } |
902 | 87d98f95 | Richard Henderson | |
903 | 87d98f95 | Richard Henderson | static inline void gen_zapnot(int ra, int rb, int rc, int islit, uint8_t lit) |
904 | 87d98f95 | Richard Henderson | { |
905 | 87d98f95 | Richard Henderson | if (unlikely(rc == 31)) |
906 | 87d98f95 | Richard Henderson | return;
|
907 | 87d98f95 | Richard Henderson | else if (unlikely(ra == 31)) |
908 | 87d98f95 | Richard Henderson | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
909 | 87d98f95 | Richard Henderson | else if (islit) |
910 | 248c42f3 | Richard Henderson | gen_zapnoti(cpu_ir[rc], cpu_ir[ra], lit); |
911 | 87d98f95 | Richard Henderson | else
|
912 | 87d98f95 | Richard Henderson | gen_helper_zapnot (cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
913 | 87d98f95 | Richard Henderson | } |
914 | 87d98f95 | Richard Henderson | |
915 | 87d98f95 | Richard Henderson | static inline void gen_zap(int ra, int rb, int rc, int islit, uint8_t lit) |
916 | 87d98f95 | Richard Henderson | { |
917 | 87d98f95 | Richard Henderson | if (unlikely(rc == 31)) |
918 | 87d98f95 | Richard Henderson | return;
|
919 | 87d98f95 | Richard Henderson | else if (unlikely(ra == 31)) |
920 | 87d98f95 | Richard Henderson | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
921 | 87d98f95 | Richard Henderson | else if (islit) |
922 | 248c42f3 | Richard Henderson | gen_zapnoti(cpu_ir[rc], cpu_ir[ra], ~lit); |
923 | 87d98f95 | Richard Henderson | else
|
924 | 87d98f95 | Richard Henderson | gen_helper_zap (cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
925 | 87d98f95 | Richard Henderson | } |
926 | 87d98f95 | Richard Henderson | |
927 | 87d98f95 | Richard Henderson | |
928 | 248c42f3 | Richard Henderson | /* EXTWH, EXTLH, EXTQH */
|
929 | ffec44f1 | Richard Henderson | static void gen_ext_h(int ra, int rb, int rc, int islit, |
930 | ffec44f1 | Richard Henderson | uint8_t lit, uint8_t byte_mask) |
931 | b3249f63 | aurel32 | { |
932 | b3249f63 | aurel32 | if (unlikely(rc == 31)) |
933 | b3249f63 | aurel32 | return;
|
934 | 377a43b6 | Richard Henderson | else if (unlikely(ra == 31)) |
935 | 377a43b6 | Richard Henderson | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
936 | 377a43b6 | Richard Henderson | else {
|
937 | dfaa8583 | aurel32 | if (islit) {
|
938 | 377a43b6 | Richard Henderson | lit = (64 - (lit & 7) * 8) & 0x3f; |
939 | 377a43b6 | Richard Henderson | tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], lit); |
940 | fe2b269a | aurel32 | } else {
|
941 | 377a43b6 | Richard Henderson | TCGv tmp1 = tcg_temp_new(); |
942 | b3249f63 | aurel32 | tcg_gen_andi_i64(tmp1, cpu_ir[rb], 7);
|
943 | b3249f63 | aurel32 | tcg_gen_shli_i64(tmp1, tmp1, 3);
|
944 | dbf95805 | Vince Weaver | tcg_gen_neg_i64(tmp1, tmp1); |
945 | dbf95805 | Vince Weaver | tcg_gen_andi_i64(tmp1, tmp1, 0x3f);
|
946 | dfaa8583 | aurel32 | tcg_gen_shl_i64(cpu_ir[rc], cpu_ir[ra], tmp1); |
947 | b3249f63 | aurel32 | tcg_temp_free(tmp1); |
948 | dfaa8583 | aurel32 | } |
949 | 248c42f3 | Richard Henderson | gen_zapnoti(cpu_ir[rc], cpu_ir[rc], byte_mask); |
950 | 377a43b6 | Richard Henderson | } |
951 | b3249f63 | aurel32 | } |
952 | b3249f63 | aurel32 | |
953 | 248c42f3 | Richard Henderson | /* EXTBL, EXTWL, EXTLL, EXTQL */
|
954 | ffec44f1 | Richard Henderson | static void gen_ext_l(int ra, int rb, int rc, int islit, |
955 | ffec44f1 | Richard Henderson | uint8_t lit, uint8_t byte_mask) |
956 | b3249f63 | aurel32 | { |
957 | b3249f63 | aurel32 | if (unlikely(rc == 31)) |
958 | b3249f63 | aurel32 | return;
|
959 | 377a43b6 | Richard Henderson | else if (unlikely(ra == 31)) |
960 | 377a43b6 | Richard Henderson | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
961 | 377a43b6 | Richard Henderson | else {
|
962 | dfaa8583 | aurel32 | if (islit) {
|
963 | 377a43b6 | Richard Henderson | tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[ra], (lit & 7) * 8); |
964 | dfaa8583 | aurel32 | } else {
|
965 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
966 | b3249f63 | aurel32 | tcg_gen_andi_i64(tmp, cpu_ir[rb], 7);
|
967 | b3249f63 | aurel32 | tcg_gen_shli_i64(tmp, tmp, 3);
|
968 | dfaa8583 | aurel32 | tcg_gen_shr_i64(cpu_ir[rc], cpu_ir[ra], tmp); |
969 | b3249f63 | aurel32 | tcg_temp_free(tmp); |
970 | fe2b269a | aurel32 | } |
971 | 248c42f3 | Richard Henderson | gen_zapnoti(cpu_ir[rc], cpu_ir[rc], byte_mask); |
972 | 248c42f3 | Richard Henderson | } |
973 | 248c42f3 | Richard Henderson | } |
974 | 248c42f3 | Richard Henderson | |
975 | 50eb6e5c | Richard Henderson | /* INSWH, INSLH, INSQH */
|
976 | 50eb6e5c | Richard Henderson | static void gen_ins_h(int ra, int rb, int rc, int islit, |
977 | 50eb6e5c | Richard Henderson | uint8_t lit, uint8_t byte_mask) |
978 | 50eb6e5c | Richard Henderson | { |
979 | 50eb6e5c | Richard Henderson | if (unlikely(rc == 31)) |
980 | 50eb6e5c | Richard Henderson | return;
|
981 | 50eb6e5c | Richard Henderson | else if (unlikely(ra == 31) || (islit && (lit & 7) == 0)) |
982 | 50eb6e5c | Richard Henderson | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
983 | 50eb6e5c | Richard Henderson | else {
|
984 | 50eb6e5c | Richard Henderson | TCGv tmp = tcg_temp_new(); |
985 | 50eb6e5c | Richard Henderson | |
986 | 50eb6e5c | Richard Henderson | /* The instruction description has us left-shift the byte mask
|
987 | 50eb6e5c | Richard Henderson | and extract bits <15:8> and apply that zap at the end. This
|
988 | 50eb6e5c | Richard Henderson | is equivalent to simply performing the zap first and shifting
|
989 | 50eb6e5c | Richard Henderson | afterward. */
|
990 | 50eb6e5c | Richard Henderson | gen_zapnoti (tmp, cpu_ir[ra], byte_mask); |
991 | 50eb6e5c | Richard Henderson | |
992 | 50eb6e5c | Richard Henderson | if (islit) {
|
993 | 50eb6e5c | Richard Henderson | /* Note that we have handled the lit==0 case above. */
|
994 | 50eb6e5c | Richard Henderson | tcg_gen_shri_i64 (cpu_ir[rc], tmp, 64 - (lit & 7) * 8); |
995 | 50eb6e5c | Richard Henderson | } else {
|
996 | 50eb6e5c | Richard Henderson | TCGv shift = tcg_temp_new(); |
997 | 50eb6e5c | Richard Henderson | |
998 | 50eb6e5c | Richard Henderson | /* If (B & 7) == 0, we need to shift by 64 and leave a zero.
|
999 | 50eb6e5c | Richard Henderson | Do this portably by splitting the shift into two parts:
|
1000 | 50eb6e5c | Richard Henderson | shift_count-1 and 1. Arrange for the -1 by using
|
1001 | 50eb6e5c | Richard Henderson | ones-complement instead of twos-complement in the negation:
|
1002 | 50eb6e5c | Richard Henderson | ~((B & 7) * 8) & 63. */
|
1003 | 50eb6e5c | Richard Henderson | |
1004 | 50eb6e5c | Richard Henderson | tcg_gen_andi_i64(shift, cpu_ir[rb], 7);
|
1005 | 50eb6e5c | Richard Henderson | tcg_gen_shli_i64(shift, shift, 3);
|
1006 | 50eb6e5c | Richard Henderson | tcg_gen_not_i64(shift, shift); |
1007 | 50eb6e5c | Richard Henderson | tcg_gen_andi_i64(shift, shift, 0x3f);
|
1008 | 50eb6e5c | Richard Henderson | |
1009 | 50eb6e5c | Richard Henderson | tcg_gen_shr_i64(cpu_ir[rc], tmp, shift); |
1010 | 50eb6e5c | Richard Henderson | tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[rc], 1);
|
1011 | 50eb6e5c | Richard Henderson | tcg_temp_free(shift); |
1012 | 50eb6e5c | Richard Henderson | } |
1013 | 50eb6e5c | Richard Henderson | tcg_temp_free(tmp); |
1014 | 50eb6e5c | Richard Henderson | } |
1015 | 50eb6e5c | Richard Henderson | } |
1016 | 50eb6e5c | Richard Henderson | |
1017 | 248c42f3 | Richard Henderson | /* INSBL, INSWL, INSLL, INSQL */
|
1018 | ffec44f1 | Richard Henderson | static void gen_ins_l(int ra, int rb, int rc, int islit, |
1019 | ffec44f1 | Richard Henderson | uint8_t lit, uint8_t byte_mask) |
1020 | 248c42f3 | Richard Henderson | { |
1021 | 248c42f3 | Richard Henderson | if (unlikely(rc == 31)) |
1022 | 248c42f3 | Richard Henderson | return;
|
1023 | 248c42f3 | Richard Henderson | else if (unlikely(ra == 31)) |
1024 | 248c42f3 | Richard Henderson | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
1025 | 248c42f3 | Richard Henderson | else {
|
1026 | 248c42f3 | Richard Henderson | TCGv tmp = tcg_temp_new(); |
1027 | 248c42f3 | Richard Henderson | |
1028 | 248c42f3 | Richard Henderson | /* The instruction description has us left-shift the byte mask
|
1029 | 248c42f3 | Richard Henderson | the same number of byte slots as the data and apply the zap
|
1030 | 248c42f3 | Richard Henderson | at the end. This is equivalent to simply performing the zap
|
1031 | 248c42f3 | Richard Henderson | first and shifting afterward. */
|
1032 | 248c42f3 | Richard Henderson | gen_zapnoti (tmp, cpu_ir[ra], byte_mask); |
1033 | 248c42f3 | Richard Henderson | |
1034 | 248c42f3 | Richard Henderson | if (islit) {
|
1035 | 248c42f3 | Richard Henderson | tcg_gen_shli_i64(cpu_ir[rc], tmp, (lit & 7) * 8); |
1036 | 248c42f3 | Richard Henderson | } else {
|
1037 | 248c42f3 | Richard Henderson | TCGv shift = tcg_temp_new(); |
1038 | 248c42f3 | Richard Henderson | tcg_gen_andi_i64(shift, cpu_ir[rb], 7);
|
1039 | 248c42f3 | Richard Henderson | tcg_gen_shli_i64(shift, shift, 3);
|
1040 | 248c42f3 | Richard Henderson | tcg_gen_shl_i64(cpu_ir[rc], tmp, shift); |
1041 | 248c42f3 | Richard Henderson | tcg_temp_free(shift); |
1042 | 248c42f3 | Richard Henderson | } |
1043 | 248c42f3 | Richard Henderson | tcg_temp_free(tmp); |
1044 | 377a43b6 | Richard Henderson | } |
1045 | b3249f63 | aurel32 | } |
1046 | b3249f63 | aurel32 | |
1047 | ffec44f1 | Richard Henderson | /* MSKWH, MSKLH, MSKQH */
|
1048 | ffec44f1 | Richard Henderson | static void gen_msk_h(int ra, int rb, int rc, int islit, |
1049 | ffec44f1 | Richard Henderson | uint8_t lit, uint8_t byte_mask) |
1050 | ffec44f1 | Richard Henderson | { |
1051 | ffec44f1 | Richard Henderson | if (unlikely(rc == 31)) |
1052 | ffec44f1 | Richard Henderson | return;
|
1053 | ffec44f1 | Richard Henderson | else if (unlikely(ra == 31)) |
1054 | ffec44f1 | Richard Henderson | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
1055 | ffec44f1 | Richard Henderson | else if (islit) { |
1056 | ffec44f1 | Richard Henderson | gen_zapnoti (cpu_ir[rc], cpu_ir[ra], ~((byte_mask << (lit & 7)) >> 8)); |
1057 | ffec44f1 | Richard Henderson | } else {
|
1058 | ffec44f1 | Richard Henderson | TCGv shift = tcg_temp_new(); |
1059 | ffec44f1 | Richard Henderson | TCGv mask = tcg_temp_new(); |
1060 | ffec44f1 | Richard Henderson | |
1061 | ffec44f1 | Richard Henderson | /* The instruction description is as above, where the byte_mask
|
1062 | ffec44f1 | Richard Henderson | is shifted left, and then we extract bits <15:8>. This can be
|
1063 | ffec44f1 | Richard Henderson | emulated with a right-shift on the expanded byte mask. This
|
1064 | ffec44f1 | Richard Henderson | requires extra care because for an input <2:0> == 0 we need a
|
1065 | ffec44f1 | Richard Henderson | shift of 64 bits in order to generate a zero. This is done by
|
1066 | ffec44f1 | Richard Henderson | splitting the shift into two parts, the variable shift - 1
|
1067 | ffec44f1 | Richard Henderson | followed by a constant 1 shift. The code we expand below is
|
1068 | ffec44f1 | Richard Henderson | equivalent to ~((B & 7) * 8) & 63. */
|
1069 | ffec44f1 | Richard Henderson | |
1070 | ffec44f1 | Richard Henderson | tcg_gen_andi_i64(shift, cpu_ir[rb], 7);
|
1071 | ffec44f1 | Richard Henderson | tcg_gen_shli_i64(shift, shift, 3);
|
1072 | ffec44f1 | Richard Henderson | tcg_gen_not_i64(shift, shift); |
1073 | ffec44f1 | Richard Henderson | tcg_gen_andi_i64(shift, shift, 0x3f);
|
1074 | ffec44f1 | Richard Henderson | tcg_gen_movi_i64(mask, zapnot_mask (byte_mask)); |
1075 | ffec44f1 | Richard Henderson | tcg_gen_shr_i64(mask, mask, shift); |
1076 | ffec44f1 | Richard Henderson | tcg_gen_shri_i64(mask, mask, 1);
|
1077 | ffec44f1 | Richard Henderson | |
1078 | ffec44f1 | Richard Henderson | tcg_gen_andc_i64(cpu_ir[rc], cpu_ir[ra], mask); |
1079 | ffec44f1 | Richard Henderson | |
1080 | ffec44f1 | Richard Henderson | tcg_temp_free(mask); |
1081 | ffec44f1 | Richard Henderson | tcg_temp_free(shift); |
1082 | ffec44f1 | Richard Henderson | } |
1083 | ffec44f1 | Richard Henderson | } |
1084 | ffec44f1 | Richard Henderson | |
1085 | 14ab1634 | Richard Henderson | /* MSKBL, MSKWL, MSKLL, MSKQL */
|
1086 | ffec44f1 | Richard Henderson | static void gen_msk_l(int ra, int rb, int rc, int islit, |
1087 | ffec44f1 | Richard Henderson | uint8_t lit, uint8_t byte_mask) |
1088 | 14ab1634 | Richard Henderson | { |
1089 | 14ab1634 | Richard Henderson | if (unlikely(rc == 31)) |
1090 | 14ab1634 | Richard Henderson | return;
|
1091 | 14ab1634 | Richard Henderson | else if (unlikely(ra == 31)) |
1092 | 14ab1634 | Richard Henderson | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
1093 | 14ab1634 | Richard Henderson | else if (islit) { |
1094 | 14ab1634 | Richard Henderson | gen_zapnoti (cpu_ir[rc], cpu_ir[ra], ~(byte_mask << (lit & 7)));
|
1095 | 14ab1634 | Richard Henderson | } else {
|
1096 | 14ab1634 | Richard Henderson | TCGv shift = tcg_temp_new(); |
1097 | 14ab1634 | Richard Henderson | TCGv mask = tcg_temp_new(); |
1098 | 14ab1634 | Richard Henderson | |
1099 | 14ab1634 | Richard Henderson | tcg_gen_andi_i64(shift, cpu_ir[rb], 7);
|
1100 | 14ab1634 | Richard Henderson | tcg_gen_shli_i64(shift, shift, 3);
|
1101 | 14ab1634 | Richard Henderson | tcg_gen_movi_i64(mask, zapnot_mask (byte_mask)); |
1102 | 14ab1634 | Richard Henderson | tcg_gen_shl_i64(mask, mask, shift); |
1103 | 14ab1634 | Richard Henderson | |
1104 | 14ab1634 | Richard Henderson | tcg_gen_andc_i64(cpu_ir[rc], cpu_ir[ra], mask); |
1105 | 14ab1634 | Richard Henderson | |
1106 | 14ab1634 | Richard Henderson | tcg_temp_free(mask); |
1107 | 14ab1634 | Richard Henderson | tcg_temp_free(shift); |
1108 | 14ab1634 | Richard Henderson | } |
1109 | 14ab1634 | Richard Henderson | } |
1110 | 14ab1634 | Richard Henderson | |
1111 | 04acd307 | aurel32 | /* Code to call arith3 helpers */
|
1112 | a7812ae4 | pbrook | #define ARITH3(name) \
|
1113 | 636aa200 | Blue Swirl | static inline void glue(gen_, name)(int ra, int rb, int rc, int islit,\ |
1114 | 636aa200 | Blue Swirl | uint8_t lit) \ |
1115 | a7812ae4 | pbrook | { \ |
1116 | a7812ae4 | pbrook | if (unlikely(rc == 31)) \ |
1117 | a7812ae4 | pbrook | return; \
|
1118 | a7812ae4 | pbrook | \ |
1119 | a7812ae4 | pbrook | if (ra != 31) { \ |
1120 | a7812ae4 | pbrook | if (islit) { \
|
1121 | a7812ae4 | pbrook | TCGv tmp = tcg_const_i64(lit); \ |
1122 | a7812ae4 | pbrook | gen_helper_ ## name(cpu_ir[rc], cpu_ir[ra], tmp); \ |
1123 | a7812ae4 | pbrook | tcg_temp_free(tmp); \ |
1124 | a7812ae4 | pbrook | } else \
|
1125 | a7812ae4 | pbrook | gen_helper_ ## name (cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); \ |
1126 | a7812ae4 | pbrook | } else { \
|
1127 | a7812ae4 | pbrook | TCGv tmp1 = tcg_const_i64(0); \
|
1128 | a7812ae4 | pbrook | if (islit) { \
|
1129 | a7812ae4 | pbrook | TCGv tmp2 = tcg_const_i64(lit); \ |
1130 | a7812ae4 | pbrook | gen_helper_ ## name (cpu_ir[rc], tmp1, tmp2); \ |
1131 | a7812ae4 | pbrook | tcg_temp_free(tmp2); \ |
1132 | a7812ae4 | pbrook | } else \
|
1133 | a7812ae4 | pbrook | gen_helper_ ## name (cpu_ir[rc], tmp1, cpu_ir[rb]); \ |
1134 | a7812ae4 | pbrook | tcg_temp_free(tmp1); \ |
1135 | a7812ae4 | pbrook | } \ |
1136 | b3249f63 | aurel32 | } |
1137 | a7812ae4 | pbrook | ARITH3(cmpbge) |
1138 | a7812ae4 | pbrook | ARITH3(addlv) |
1139 | a7812ae4 | pbrook | ARITH3(sublv) |
1140 | a7812ae4 | pbrook | ARITH3(addqv) |
1141 | a7812ae4 | pbrook | ARITH3(subqv) |
1142 | a7812ae4 | pbrook | ARITH3(umulh) |
1143 | a7812ae4 | pbrook | ARITH3(mullv) |
1144 | a7812ae4 | pbrook | ARITH3(mulqv) |
1145 | 13e4df99 | Richard Henderson | ARITH3(minub8) |
1146 | 13e4df99 | Richard Henderson | ARITH3(minsb8) |
1147 | 13e4df99 | Richard Henderson | ARITH3(minuw4) |
1148 | 13e4df99 | Richard Henderson | ARITH3(minsw4) |
1149 | 13e4df99 | Richard Henderson | ARITH3(maxub8) |
1150 | 13e4df99 | Richard Henderson | ARITH3(maxsb8) |
1151 | 13e4df99 | Richard Henderson | ARITH3(maxuw4) |
1152 | 13e4df99 | Richard Henderson | ARITH3(maxsw4) |
1153 | 13e4df99 | Richard Henderson | ARITH3(perr) |
1154 | 13e4df99 | Richard Henderson | |
1155 | 13e4df99 | Richard Henderson | #define MVIOP2(name) \
|
1156 | 13e4df99 | Richard Henderson | static inline void glue(gen_, name)(int rb, int rc) \ |
1157 | 13e4df99 | Richard Henderson | { \ |
1158 | 13e4df99 | Richard Henderson | if (unlikely(rc == 31)) \ |
1159 | 13e4df99 | Richard Henderson | return; \
|
1160 | 13e4df99 | Richard Henderson | if (unlikely(rb == 31)) \ |
1161 | 13e4df99 | Richard Henderson | tcg_gen_movi_i64(cpu_ir[rc], 0); \
|
1162 | 13e4df99 | Richard Henderson | else \
|
1163 | 13e4df99 | Richard Henderson | gen_helper_ ## name (cpu_ir[rc], cpu_ir[rb]); \ |
1164 | 13e4df99 | Richard Henderson | } |
1165 | 13e4df99 | Richard Henderson | MVIOP2(pklb) |
1166 | 13e4df99 | Richard Henderson | MVIOP2(pkwb) |
1167 | 13e4df99 | Richard Henderson | MVIOP2(unpkbl) |
1168 | 13e4df99 | Richard Henderson | MVIOP2(unpkbw) |
1169 | b3249f63 | aurel32 | |
1170 | 636aa200 | Blue Swirl | static inline void gen_cmp(TCGCond cond, int ra, int rb, int rc, int islit, |
1171 | 636aa200 | Blue Swirl | uint8_t lit) |
1172 | 01ff9cc8 | aurel32 | { |
1173 | 01ff9cc8 | aurel32 | int l1, l2;
|
1174 | 01ff9cc8 | aurel32 | TCGv tmp; |
1175 | 01ff9cc8 | aurel32 | |
1176 | 01ff9cc8 | aurel32 | if (unlikely(rc == 31)) |
1177 | 13e4df99 | Richard Henderson | return;
|
1178 | 01ff9cc8 | aurel32 | |
1179 | 01ff9cc8 | aurel32 | l1 = gen_new_label(); |
1180 | 01ff9cc8 | aurel32 | l2 = gen_new_label(); |
1181 | 01ff9cc8 | aurel32 | |
1182 | 01ff9cc8 | aurel32 | if (ra != 31) { |
1183 | a7812ae4 | pbrook | tmp = tcg_temp_new(); |
1184 | 01ff9cc8 | aurel32 | tcg_gen_mov_i64(tmp, cpu_ir[ra]); |
1185 | 01ff9cc8 | aurel32 | } else
|
1186 | 01ff9cc8 | aurel32 | tmp = tcg_const_i64(0);
|
1187 | 01ff9cc8 | aurel32 | if (islit)
|
1188 | 01ff9cc8 | aurel32 | tcg_gen_brcondi_i64(cond, tmp, lit, l1); |
1189 | 01ff9cc8 | aurel32 | else
|
1190 | dfaa8583 | aurel32 | tcg_gen_brcond_i64(cond, tmp, cpu_ir[rb], l1); |
1191 | 01ff9cc8 | aurel32 | |
1192 | 01ff9cc8 | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
1193 | 01ff9cc8 | aurel32 | tcg_gen_br(l2); |
1194 | 01ff9cc8 | aurel32 | gen_set_label(l1); |
1195 | 01ff9cc8 | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 1);
|
1196 | 01ff9cc8 | aurel32 | gen_set_label(l2); |
1197 | 01ff9cc8 | aurel32 | } |
1198 | 01ff9cc8 | aurel32 | |
1199 | 636aa200 | Blue Swirl | static inline int translate_one(DisasContext *ctx, uint32_t insn) |
1200 | 4c9649a9 | j_mayer | { |
1201 | 4c9649a9 | j_mayer | uint32_t palcode; |
1202 | 4c9649a9 | j_mayer | int32_t disp21, disp16, disp12; |
1203 | 4c9649a9 | j_mayer | uint16_t fn11, fn16; |
1204 | 13e4df99 | Richard Henderson | uint8_t opc, ra, rb, rc, sbz, fpfn, fn7, fn2, islit, real_islit; |
1205 | adf3c8b6 | aurel32 | uint8_t lit; |
1206 | 4c9649a9 | j_mayer | int ret;
|
1207 | 4c9649a9 | j_mayer | |
1208 | 4c9649a9 | j_mayer | /* Decode all instruction fields */
|
1209 | 4c9649a9 | j_mayer | opc = insn >> 26;
|
1210 | 4c9649a9 | j_mayer | ra = (insn >> 21) & 0x1F; |
1211 | 4c9649a9 | j_mayer | rb = (insn >> 16) & 0x1F; |
1212 | 4c9649a9 | j_mayer | rc = insn & 0x1F;
|
1213 | 4c9649a9 | j_mayer | sbz = (insn >> 13) & 0x07; |
1214 | 13e4df99 | Richard Henderson | real_islit = islit = (insn >> 12) & 1; |
1215 | dfaa8583 | aurel32 | if (rb == 31 && !islit) { |
1216 | dfaa8583 | aurel32 | islit = 1;
|
1217 | dfaa8583 | aurel32 | lit = 0;
|
1218 | dfaa8583 | aurel32 | } else
|
1219 | dfaa8583 | aurel32 | lit = (insn >> 13) & 0xFF; |
1220 | 4c9649a9 | j_mayer | palcode = insn & 0x03FFFFFF;
|
1221 | 4c9649a9 | j_mayer | disp21 = ((int32_t)((insn & 0x001FFFFF) << 11)) >> 11; |
1222 | 4c9649a9 | j_mayer | disp16 = (int16_t)(insn & 0x0000FFFF);
|
1223 | 4c9649a9 | j_mayer | disp12 = (int32_t)((insn & 0x00000FFF) << 20) >> 20; |
1224 | 4c9649a9 | j_mayer | fn16 = insn & 0x0000FFFF;
|
1225 | 4c9649a9 | j_mayer | fn11 = (insn >> 5) & 0x000007FF; |
1226 | 4c9649a9 | j_mayer | fpfn = fn11 & 0x3F;
|
1227 | 4c9649a9 | j_mayer | fn7 = (insn >> 5) & 0x0000007F; |
1228 | 4c9649a9 | j_mayer | fn2 = (insn >> 5) & 0x00000003; |
1229 | 4c9649a9 | j_mayer | ret = 0;
|
1230 | 806991da | Richard Henderson | LOG_DISAS("opc %02x ra %2d rb %2d rc %2d disp16 %6d\n",
|
1231 | d12d51d5 | aliguori | opc, ra, rb, rc, disp16); |
1232 | 806991da | Richard Henderson | |
1233 | 4c9649a9 | j_mayer | switch (opc) {
|
1234 | 4c9649a9 | j_mayer | case 0x00: |
1235 | 4c9649a9 | j_mayer | /* CALL_PAL */
|
1236 | ab471ade | Richard Henderson | #ifdef CONFIG_USER_ONLY
|
1237 | ab471ade | Richard Henderson | if (palcode == 0x9E) { |
1238 | ab471ade | Richard Henderson | /* RDUNIQUE */
|
1239 | ab471ade | Richard Henderson | tcg_gen_mov_i64(cpu_ir[IR_V0], cpu_uniq); |
1240 | ab471ade | Richard Henderson | break;
|
1241 | ab471ade | Richard Henderson | } else if (palcode == 0x9F) { |
1242 | ab471ade | Richard Henderson | /* WRUNIQUE */
|
1243 | ab471ade | Richard Henderson | tcg_gen_mov_i64(cpu_uniq, cpu_ir[IR_A0]); |
1244 | ab471ade | Richard Henderson | break;
|
1245 | ab471ade | Richard Henderson | } |
1246 | ab471ade | Richard Henderson | #endif
|
1247 | 4c9649a9 | j_mayer | if (palcode >= 0x80 && palcode < 0xC0) { |
1248 | 4c9649a9 | j_mayer | /* Unprivileged PAL call */
|
1249 | 31a877f2 | aurel32 | gen_excp(ctx, EXCP_CALL_PAL + ((palcode & 0x3F) << 6), 0); |
1250 | ab471ade | Richard Henderson | ret = 3;
|
1251 | ab471ade | Richard Henderson | break;
|
1252 | ab471ade | Richard Henderson | } |
1253 | ab471ade | Richard Henderson | #ifndef CONFIG_USER_ONLY
|
1254 | ab471ade | Richard Henderson | if (palcode < 0x40) { |
1255 | 4c9649a9 | j_mayer | /* Privileged PAL code */
|
1256 | 4c9649a9 | j_mayer | if (ctx->mem_idx & 1) |
1257 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1258 | ab471ade | Richard Henderson | gen_excp(ctx, EXCP_CALL_PALP + ((palcode & 0x3F) << 6), 0); |
1259 | ab471ade | Richard Henderson | ret = 3;
|
1260 | 4c9649a9 | j_mayer | } |
1261 | ab471ade | Richard Henderson | #endif
|
1262 | ab471ade | Richard Henderson | /* Invalid PAL call */
|
1263 | ab471ade | Richard Henderson | goto invalid_opc;
|
1264 | 4c9649a9 | j_mayer | case 0x01: |
1265 | 4c9649a9 | j_mayer | /* OPC01 */
|
1266 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1267 | 4c9649a9 | j_mayer | case 0x02: |
1268 | 4c9649a9 | j_mayer | /* OPC02 */
|
1269 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1270 | 4c9649a9 | j_mayer | case 0x03: |
1271 | 4c9649a9 | j_mayer | /* OPC03 */
|
1272 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1273 | 4c9649a9 | j_mayer | case 0x04: |
1274 | 4c9649a9 | j_mayer | /* OPC04 */
|
1275 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1276 | 4c9649a9 | j_mayer | case 0x05: |
1277 | 4c9649a9 | j_mayer | /* OPC05 */
|
1278 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1279 | 4c9649a9 | j_mayer | case 0x06: |
1280 | 4c9649a9 | j_mayer | /* OPC06 */
|
1281 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1282 | 4c9649a9 | j_mayer | case 0x07: |
1283 | 4c9649a9 | j_mayer | /* OPC07 */
|
1284 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1285 | 4c9649a9 | j_mayer | case 0x08: |
1286 | 4c9649a9 | j_mayer | /* LDA */
|
1287 | 1ef4ef4e | aurel32 | if (likely(ra != 31)) { |
1288 | 496cb5b9 | aurel32 | if (rb != 31) |
1289 | 3761035f | aurel32 | tcg_gen_addi_i64(cpu_ir[ra], cpu_ir[rb], disp16); |
1290 | 3761035f | aurel32 | else
|
1291 | 3761035f | aurel32 | tcg_gen_movi_i64(cpu_ir[ra], disp16); |
1292 | 496cb5b9 | aurel32 | } |
1293 | 4c9649a9 | j_mayer | break;
|
1294 | 4c9649a9 | j_mayer | case 0x09: |
1295 | 4c9649a9 | j_mayer | /* LDAH */
|
1296 | 1ef4ef4e | aurel32 | if (likely(ra != 31)) { |
1297 | 496cb5b9 | aurel32 | if (rb != 31) |
1298 | 3761035f | aurel32 | tcg_gen_addi_i64(cpu_ir[ra], cpu_ir[rb], disp16 << 16);
|
1299 | 3761035f | aurel32 | else
|
1300 | 3761035f | aurel32 | tcg_gen_movi_i64(cpu_ir[ra], disp16 << 16);
|
1301 | 496cb5b9 | aurel32 | } |
1302 | 4c9649a9 | j_mayer | break;
|
1303 | 4c9649a9 | j_mayer | case 0x0A: |
1304 | 4c9649a9 | j_mayer | /* LDBU */
|
1305 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_BWX))
|
1306 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1307 | f18cd223 | aurel32 | gen_load_mem(ctx, &tcg_gen_qemu_ld8u, ra, rb, disp16, 0, 0); |
1308 | 4c9649a9 | j_mayer | break;
|
1309 | 4c9649a9 | j_mayer | case 0x0B: |
1310 | 4c9649a9 | j_mayer | /* LDQ_U */
|
1311 | f18cd223 | aurel32 | gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 1); |
1312 | 4c9649a9 | j_mayer | break;
|
1313 | 4c9649a9 | j_mayer | case 0x0C: |
1314 | 4c9649a9 | j_mayer | /* LDWU */
|
1315 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_BWX))
|
1316 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1317 | 577d5e7f | aurel32 | gen_load_mem(ctx, &tcg_gen_qemu_ld16u, ra, rb, disp16, 0, 0); |
1318 | 4c9649a9 | j_mayer | break;
|
1319 | 4c9649a9 | j_mayer | case 0x0D: |
1320 | 4c9649a9 | j_mayer | /* STW */
|
1321 | 57a92c8e | aurel32 | gen_store_mem(ctx, &tcg_gen_qemu_st16, ra, rb, disp16, 0, 0, 0); |
1322 | 4c9649a9 | j_mayer | break;
|
1323 | 4c9649a9 | j_mayer | case 0x0E: |
1324 | 4c9649a9 | j_mayer | /* STB */
|
1325 | 57a92c8e | aurel32 | gen_store_mem(ctx, &tcg_gen_qemu_st8, ra, rb, disp16, 0, 0, 0); |
1326 | 4c9649a9 | j_mayer | break;
|
1327 | 4c9649a9 | j_mayer | case 0x0F: |
1328 | 4c9649a9 | j_mayer | /* STQ_U */
|
1329 | 57a92c8e | aurel32 | gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 1, 0); |
1330 | 4c9649a9 | j_mayer | break;
|
1331 | 4c9649a9 | j_mayer | case 0x10: |
1332 | 4c9649a9 | j_mayer | switch (fn7) {
|
1333 | 4c9649a9 | j_mayer | case 0x00: |
1334 | 4c9649a9 | j_mayer | /* ADDL */
|
1335 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1336 | 30c7183b | aurel32 | if (ra != 31) { |
1337 | 30c7183b | aurel32 | if (islit) {
|
1338 | 30c7183b | aurel32 | tcg_gen_addi_i64(cpu_ir[rc], cpu_ir[ra], lit); |
1339 | 30c7183b | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); |
1340 | dfaa8583 | aurel32 | } else {
|
1341 | 30c7183b | aurel32 | tcg_gen_add_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
1342 | 30c7183b | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); |
1343 | dfaa8583 | aurel32 | } |
1344 | 30c7183b | aurel32 | } else {
|
1345 | 30c7183b | aurel32 | if (islit)
|
1346 | dfaa8583 | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
1347 | 30c7183b | aurel32 | else
|
1348 | dfaa8583 | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]); |
1349 | 30c7183b | aurel32 | } |
1350 | 30c7183b | aurel32 | } |
1351 | 4c9649a9 | j_mayer | break;
|
1352 | 4c9649a9 | j_mayer | case 0x02: |
1353 | 4c9649a9 | j_mayer | /* S4ADDL */
|
1354 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1355 | 30c7183b | aurel32 | if (ra != 31) { |
1356 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
1357 | dfaa8583 | aurel32 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
|
1358 | dfaa8583 | aurel32 | if (islit)
|
1359 | dfaa8583 | aurel32 | tcg_gen_addi_i64(tmp, tmp, lit); |
1360 | dfaa8583 | aurel32 | else
|
1361 | dfaa8583 | aurel32 | tcg_gen_add_i64(tmp, tmp, cpu_ir[rb]); |
1362 | dfaa8583 | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], tmp); |
1363 | dfaa8583 | aurel32 | tcg_temp_free(tmp); |
1364 | 30c7183b | aurel32 | } else {
|
1365 | 30c7183b | aurel32 | if (islit)
|
1366 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
1367 | 30c7183b | aurel32 | else
|
1368 | dfaa8583 | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]); |
1369 | 30c7183b | aurel32 | } |
1370 | 30c7183b | aurel32 | } |
1371 | 4c9649a9 | j_mayer | break;
|
1372 | 4c9649a9 | j_mayer | case 0x09: |
1373 | 4c9649a9 | j_mayer | /* SUBL */
|
1374 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1375 | 30c7183b | aurel32 | if (ra != 31) { |
1376 | dfaa8583 | aurel32 | if (islit)
|
1377 | 30c7183b | aurel32 | tcg_gen_subi_i64(cpu_ir[rc], cpu_ir[ra], lit); |
1378 | dfaa8583 | aurel32 | else
|
1379 | 30c7183b | aurel32 | tcg_gen_sub_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
1380 | dfaa8583 | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); |
1381 | 30c7183b | aurel32 | } else {
|
1382 | 30c7183b | aurel32 | if (islit)
|
1383 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], -lit); |
1384 | dfaa8583 | aurel32 | else {
|
1385 | 30c7183b | aurel32 | tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); |
1386 | 30c7183b | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); |
1387 | 30c7183b | aurel32 | } |
1388 | 30c7183b | aurel32 | } |
1389 | 4c9649a9 | j_mayer | break;
|
1390 | 4c9649a9 | j_mayer | case 0x0B: |
1391 | 4c9649a9 | j_mayer | /* S4SUBL */
|
1392 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1393 | 30c7183b | aurel32 | if (ra != 31) { |
1394 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
1395 | dfaa8583 | aurel32 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
|
1396 | dfaa8583 | aurel32 | if (islit)
|
1397 | dfaa8583 | aurel32 | tcg_gen_subi_i64(tmp, tmp, lit); |
1398 | dfaa8583 | aurel32 | else
|
1399 | dfaa8583 | aurel32 | tcg_gen_sub_i64(tmp, tmp, cpu_ir[rb]); |
1400 | dfaa8583 | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], tmp); |
1401 | dfaa8583 | aurel32 | tcg_temp_free(tmp); |
1402 | 30c7183b | aurel32 | } else {
|
1403 | 30c7183b | aurel32 | if (islit)
|
1404 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], -lit); |
1405 | dfaa8583 | aurel32 | else {
|
1406 | 30c7183b | aurel32 | tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); |
1407 | 30c7183b | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); |
1408 | dfaa8583 | aurel32 | } |
1409 | 30c7183b | aurel32 | } |
1410 | 30c7183b | aurel32 | } |
1411 | 4c9649a9 | j_mayer | break;
|
1412 | 4c9649a9 | j_mayer | case 0x0F: |
1413 | 4c9649a9 | j_mayer | /* CMPBGE */
|
1414 | a7812ae4 | pbrook | gen_cmpbge(ra, rb, rc, islit, lit); |
1415 | 4c9649a9 | j_mayer | break;
|
1416 | 4c9649a9 | j_mayer | case 0x12: |
1417 | 4c9649a9 | j_mayer | /* S8ADDL */
|
1418 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1419 | 30c7183b | aurel32 | if (ra != 31) { |
1420 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
1421 | dfaa8583 | aurel32 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
|
1422 | dfaa8583 | aurel32 | if (islit)
|
1423 | dfaa8583 | aurel32 | tcg_gen_addi_i64(tmp, tmp, lit); |
1424 | dfaa8583 | aurel32 | else
|
1425 | dfaa8583 | aurel32 | tcg_gen_add_i64(tmp, tmp, cpu_ir[rb]); |
1426 | dfaa8583 | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], tmp); |
1427 | dfaa8583 | aurel32 | tcg_temp_free(tmp); |
1428 | 30c7183b | aurel32 | } else {
|
1429 | 30c7183b | aurel32 | if (islit)
|
1430 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
1431 | 30c7183b | aurel32 | else
|
1432 | dfaa8583 | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]); |
1433 | 30c7183b | aurel32 | } |
1434 | 30c7183b | aurel32 | } |
1435 | 4c9649a9 | j_mayer | break;
|
1436 | 4c9649a9 | j_mayer | case 0x1B: |
1437 | 4c9649a9 | j_mayer | /* S8SUBL */
|
1438 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1439 | 30c7183b | aurel32 | if (ra != 31) { |
1440 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
1441 | dfaa8583 | aurel32 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
|
1442 | dfaa8583 | aurel32 | if (islit)
|
1443 | dfaa8583 | aurel32 | tcg_gen_subi_i64(tmp, tmp, lit); |
1444 | dfaa8583 | aurel32 | else
|
1445 | dfaa8583 | aurel32 | tcg_gen_sub_i64(tmp, tmp, cpu_ir[rb]); |
1446 | dfaa8583 | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], tmp); |
1447 | dfaa8583 | aurel32 | tcg_temp_free(tmp); |
1448 | 30c7183b | aurel32 | } else {
|
1449 | 30c7183b | aurel32 | if (islit)
|
1450 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], -lit); |
1451 | dfaa8583 | aurel32 | else
|
1452 | 30c7183b | aurel32 | tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); |
1453 | 30c7183b | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); |
1454 | dfaa8583 | aurel32 | } |
1455 | 30c7183b | aurel32 | } |
1456 | 30c7183b | aurel32 | } |
1457 | 4c9649a9 | j_mayer | break;
|
1458 | 4c9649a9 | j_mayer | case 0x1D: |
1459 | 4c9649a9 | j_mayer | /* CMPULT */
|
1460 | 01ff9cc8 | aurel32 | gen_cmp(TCG_COND_LTU, ra, rb, rc, islit, lit); |
1461 | 4c9649a9 | j_mayer | break;
|
1462 | 4c9649a9 | j_mayer | case 0x20: |
1463 | 4c9649a9 | j_mayer | /* ADDQ */
|
1464 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1465 | 30c7183b | aurel32 | if (ra != 31) { |
1466 | 30c7183b | aurel32 | if (islit)
|
1467 | 30c7183b | aurel32 | tcg_gen_addi_i64(cpu_ir[rc], cpu_ir[ra], lit); |
1468 | 30c7183b | aurel32 | else
|
1469 | dfaa8583 | aurel32 | tcg_gen_add_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
1470 | 30c7183b | aurel32 | } else {
|
1471 | 30c7183b | aurel32 | if (islit)
|
1472 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
1473 | 30c7183b | aurel32 | else
|
1474 | dfaa8583 | aurel32 | tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
1475 | 30c7183b | aurel32 | } |
1476 | 30c7183b | aurel32 | } |
1477 | 4c9649a9 | j_mayer | break;
|
1478 | 4c9649a9 | j_mayer | case 0x22: |
1479 | 4c9649a9 | j_mayer | /* S4ADDQ */
|
1480 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1481 | 30c7183b | aurel32 | if (ra != 31) { |
1482 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
1483 | dfaa8583 | aurel32 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
|
1484 | dfaa8583 | aurel32 | if (islit)
|
1485 | dfaa8583 | aurel32 | tcg_gen_addi_i64(cpu_ir[rc], tmp, lit); |
1486 | dfaa8583 | aurel32 | else
|
1487 | dfaa8583 | aurel32 | tcg_gen_add_i64(cpu_ir[rc], tmp, cpu_ir[rb]); |
1488 | dfaa8583 | aurel32 | tcg_temp_free(tmp); |
1489 | 30c7183b | aurel32 | } else {
|
1490 | 30c7183b | aurel32 | if (islit)
|
1491 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
1492 | 30c7183b | aurel32 | else
|
1493 | dfaa8583 | aurel32 | tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
1494 | 30c7183b | aurel32 | } |
1495 | 30c7183b | aurel32 | } |
1496 | 4c9649a9 | j_mayer | break;
|
1497 | 4c9649a9 | j_mayer | case 0x29: |
1498 | 4c9649a9 | j_mayer | /* SUBQ */
|
1499 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1500 | 30c7183b | aurel32 | if (ra != 31) { |
1501 | 30c7183b | aurel32 | if (islit)
|
1502 | 30c7183b | aurel32 | tcg_gen_subi_i64(cpu_ir[rc], cpu_ir[ra], lit); |
1503 | 30c7183b | aurel32 | else
|
1504 | dfaa8583 | aurel32 | tcg_gen_sub_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
1505 | 30c7183b | aurel32 | } else {
|
1506 | 30c7183b | aurel32 | if (islit)
|
1507 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], -lit); |
1508 | 30c7183b | aurel32 | else
|
1509 | dfaa8583 | aurel32 | tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); |
1510 | 30c7183b | aurel32 | } |
1511 | 30c7183b | aurel32 | } |
1512 | 4c9649a9 | j_mayer | break;
|
1513 | 4c9649a9 | j_mayer | case 0x2B: |
1514 | 4c9649a9 | j_mayer | /* S4SUBQ */
|
1515 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1516 | 30c7183b | aurel32 | if (ra != 31) { |
1517 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
1518 | dfaa8583 | aurel32 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
|
1519 | dfaa8583 | aurel32 | if (islit)
|
1520 | dfaa8583 | aurel32 | tcg_gen_subi_i64(cpu_ir[rc], tmp, lit); |
1521 | dfaa8583 | aurel32 | else
|
1522 | dfaa8583 | aurel32 | tcg_gen_sub_i64(cpu_ir[rc], tmp, cpu_ir[rb]); |
1523 | dfaa8583 | aurel32 | tcg_temp_free(tmp); |
1524 | 30c7183b | aurel32 | } else {
|
1525 | 30c7183b | aurel32 | if (islit)
|
1526 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], -lit); |
1527 | 30c7183b | aurel32 | else
|
1528 | dfaa8583 | aurel32 | tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); |
1529 | 30c7183b | aurel32 | } |
1530 | 30c7183b | aurel32 | } |
1531 | 4c9649a9 | j_mayer | break;
|
1532 | 4c9649a9 | j_mayer | case 0x2D: |
1533 | 4c9649a9 | j_mayer | /* CMPEQ */
|
1534 | 01ff9cc8 | aurel32 | gen_cmp(TCG_COND_EQ, ra, rb, rc, islit, lit); |
1535 | 4c9649a9 | j_mayer | break;
|
1536 | 4c9649a9 | j_mayer | case 0x32: |
1537 | 4c9649a9 | j_mayer | /* S8ADDQ */
|
1538 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1539 | 30c7183b | aurel32 | if (ra != 31) { |
1540 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
1541 | dfaa8583 | aurel32 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
|
1542 | dfaa8583 | aurel32 | if (islit)
|
1543 | dfaa8583 | aurel32 | tcg_gen_addi_i64(cpu_ir[rc], tmp, lit); |
1544 | dfaa8583 | aurel32 | else
|
1545 | dfaa8583 | aurel32 | tcg_gen_add_i64(cpu_ir[rc], tmp, cpu_ir[rb]); |
1546 | dfaa8583 | aurel32 | tcg_temp_free(tmp); |
1547 | 30c7183b | aurel32 | } else {
|
1548 | 30c7183b | aurel32 | if (islit)
|
1549 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
1550 | 30c7183b | aurel32 | else
|
1551 | dfaa8583 | aurel32 | tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
1552 | 30c7183b | aurel32 | } |
1553 | 30c7183b | aurel32 | } |
1554 | 4c9649a9 | j_mayer | break;
|
1555 | 4c9649a9 | j_mayer | case 0x3B: |
1556 | 4c9649a9 | j_mayer | /* S8SUBQ */
|
1557 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1558 | 30c7183b | aurel32 | if (ra != 31) { |
1559 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
1560 | dfaa8583 | aurel32 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
|
1561 | dfaa8583 | aurel32 | if (islit)
|
1562 | dfaa8583 | aurel32 | tcg_gen_subi_i64(cpu_ir[rc], tmp, lit); |
1563 | dfaa8583 | aurel32 | else
|
1564 | dfaa8583 | aurel32 | tcg_gen_sub_i64(cpu_ir[rc], tmp, cpu_ir[rb]); |
1565 | dfaa8583 | aurel32 | tcg_temp_free(tmp); |
1566 | 30c7183b | aurel32 | } else {
|
1567 | 30c7183b | aurel32 | if (islit)
|
1568 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], -lit); |
1569 | 30c7183b | aurel32 | else
|
1570 | dfaa8583 | aurel32 | tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); |
1571 | 30c7183b | aurel32 | } |
1572 | 30c7183b | aurel32 | } |
1573 | 4c9649a9 | j_mayer | break;
|
1574 | 4c9649a9 | j_mayer | case 0x3D: |
1575 | 4c9649a9 | j_mayer | /* CMPULE */
|
1576 | 01ff9cc8 | aurel32 | gen_cmp(TCG_COND_LEU, ra, rb, rc, islit, lit); |
1577 | 4c9649a9 | j_mayer | break;
|
1578 | 4c9649a9 | j_mayer | case 0x40: |
1579 | 4c9649a9 | j_mayer | /* ADDL/V */
|
1580 | a7812ae4 | pbrook | gen_addlv(ra, rb, rc, islit, lit); |
1581 | 4c9649a9 | j_mayer | break;
|
1582 | 4c9649a9 | j_mayer | case 0x49: |
1583 | 4c9649a9 | j_mayer | /* SUBL/V */
|
1584 | a7812ae4 | pbrook | gen_sublv(ra, rb, rc, islit, lit); |
1585 | 4c9649a9 | j_mayer | break;
|
1586 | 4c9649a9 | j_mayer | case 0x4D: |
1587 | 4c9649a9 | j_mayer | /* CMPLT */
|
1588 | 01ff9cc8 | aurel32 | gen_cmp(TCG_COND_LT, ra, rb, rc, islit, lit); |
1589 | 4c9649a9 | j_mayer | break;
|
1590 | 4c9649a9 | j_mayer | case 0x60: |
1591 | 4c9649a9 | j_mayer | /* ADDQ/V */
|
1592 | a7812ae4 | pbrook | gen_addqv(ra, rb, rc, islit, lit); |
1593 | 4c9649a9 | j_mayer | break;
|
1594 | 4c9649a9 | j_mayer | case 0x69: |
1595 | 4c9649a9 | j_mayer | /* SUBQ/V */
|
1596 | a7812ae4 | pbrook | gen_subqv(ra, rb, rc, islit, lit); |
1597 | 4c9649a9 | j_mayer | break;
|
1598 | 4c9649a9 | j_mayer | case 0x6D: |
1599 | 4c9649a9 | j_mayer | /* CMPLE */
|
1600 | 01ff9cc8 | aurel32 | gen_cmp(TCG_COND_LE, ra, rb, rc, islit, lit); |
1601 | 4c9649a9 | j_mayer | break;
|
1602 | 4c9649a9 | j_mayer | default:
|
1603 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1604 | 4c9649a9 | j_mayer | } |
1605 | 4c9649a9 | j_mayer | break;
|
1606 | 4c9649a9 | j_mayer | case 0x11: |
1607 | 4c9649a9 | j_mayer | switch (fn7) {
|
1608 | 4c9649a9 | j_mayer | case 0x00: |
1609 | 4c9649a9 | j_mayer | /* AND */
|
1610 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1611 | dfaa8583 | aurel32 | if (ra == 31) |
1612 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
1613 | 30c7183b | aurel32 | else if (islit) |
1614 | 30c7183b | aurel32 | tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[ra], lit); |
1615 | 30c7183b | aurel32 | else
|
1616 | 30c7183b | aurel32 | tcg_gen_and_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
1617 | 30c7183b | aurel32 | } |
1618 | 4c9649a9 | j_mayer | break;
|
1619 | 4c9649a9 | j_mayer | case 0x08: |
1620 | 4c9649a9 | j_mayer | /* BIC */
|
1621 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1622 | 30c7183b | aurel32 | if (ra != 31) { |
1623 | 30c7183b | aurel32 | if (islit)
|
1624 | 30c7183b | aurel32 | tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[ra], ~lit); |
1625 | 1b581c44 | aurel32 | else
|
1626 | 1b581c44 | aurel32 | tcg_gen_andc_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
1627 | 30c7183b | aurel32 | } else
|
1628 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
1629 | 30c7183b | aurel32 | } |
1630 | 4c9649a9 | j_mayer | break;
|
1631 | 4c9649a9 | j_mayer | case 0x14: |
1632 | 4c9649a9 | j_mayer | /* CMOVLBS */
|
1633 | fe2b269a | aurel32 | gen_cmov(TCG_COND_EQ, ra, rb, rc, islit, lit, 1);
|
1634 | 4c9649a9 | j_mayer | break;
|
1635 | 4c9649a9 | j_mayer | case 0x16: |
1636 | 4c9649a9 | j_mayer | /* CMOVLBC */
|
1637 | fe2b269a | aurel32 | gen_cmov(TCG_COND_NE, ra, rb, rc, islit, lit, 1);
|
1638 | 4c9649a9 | j_mayer | break;
|
1639 | 4c9649a9 | j_mayer | case 0x20: |
1640 | 4c9649a9 | j_mayer | /* BIS */
|
1641 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1642 | 30c7183b | aurel32 | if (ra != 31) { |
1643 | 30c7183b | aurel32 | if (islit)
|
1644 | 30c7183b | aurel32 | tcg_gen_ori_i64(cpu_ir[rc], cpu_ir[ra], lit); |
1645 | 8bb6e981 | aurel32 | else
|
1646 | 30c7183b | aurel32 | tcg_gen_or_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
1647 | 4c9649a9 | j_mayer | } else {
|
1648 | 30c7183b | aurel32 | if (islit)
|
1649 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
1650 | 30c7183b | aurel32 | else
|
1651 | dfaa8583 | aurel32 | tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
1652 | 4c9649a9 | j_mayer | } |
1653 | 4c9649a9 | j_mayer | } |
1654 | 4c9649a9 | j_mayer | break;
|
1655 | 4c9649a9 | j_mayer | case 0x24: |
1656 | 4c9649a9 | j_mayer | /* CMOVEQ */
|
1657 | fe2b269a | aurel32 | gen_cmov(TCG_COND_NE, ra, rb, rc, islit, lit, 0);
|
1658 | 4c9649a9 | j_mayer | break;
|
1659 | 4c9649a9 | j_mayer | case 0x26: |
1660 | 4c9649a9 | j_mayer | /* CMOVNE */
|
1661 | fe2b269a | aurel32 | gen_cmov(TCG_COND_EQ, ra, rb, rc, islit, lit, 0);
|
1662 | 4c9649a9 | j_mayer | break;
|
1663 | 4c9649a9 | j_mayer | case 0x28: |
1664 | 4c9649a9 | j_mayer | /* ORNOT */
|
1665 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1666 | dfaa8583 | aurel32 | if (ra != 31) { |
1667 | 30c7183b | aurel32 | if (islit)
|
1668 | 30c7183b | aurel32 | tcg_gen_ori_i64(cpu_ir[rc], cpu_ir[ra], ~lit); |
1669 | 1b581c44 | aurel32 | else
|
1670 | 1b581c44 | aurel32 | tcg_gen_orc_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
1671 | 30c7183b | aurel32 | } else {
|
1672 | 30c7183b | aurel32 | if (islit)
|
1673 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], ~lit); |
1674 | 30c7183b | aurel32 | else
|
1675 | 30c7183b | aurel32 | tcg_gen_not_i64(cpu_ir[rc], cpu_ir[rb]); |
1676 | 30c7183b | aurel32 | } |
1677 | 30c7183b | aurel32 | } |
1678 | 4c9649a9 | j_mayer | break;
|
1679 | 4c9649a9 | j_mayer | case 0x40: |
1680 | 4c9649a9 | j_mayer | /* XOR */
|
1681 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1682 | 30c7183b | aurel32 | if (ra != 31) { |
1683 | 30c7183b | aurel32 | if (islit)
|
1684 | 30c7183b | aurel32 | tcg_gen_xori_i64(cpu_ir[rc], cpu_ir[ra], lit); |
1685 | 30c7183b | aurel32 | else
|
1686 | dfaa8583 | aurel32 | tcg_gen_xor_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
1687 | 30c7183b | aurel32 | } else {
|
1688 | 30c7183b | aurel32 | if (islit)
|
1689 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
1690 | 30c7183b | aurel32 | else
|
1691 | dfaa8583 | aurel32 | tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
1692 | 30c7183b | aurel32 | } |
1693 | 30c7183b | aurel32 | } |
1694 | 4c9649a9 | j_mayer | break;
|
1695 | 4c9649a9 | j_mayer | case 0x44: |
1696 | 4c9649a9 | j_mayer | /* CMOVLT */
|
1697 | fe2b269a | aurel32 | gen_cmov(TCG_COND_GE, ra, rb, rc, islit, lit, 0);
|
1698 | 4c9649a9 | j_mayer | break;
|
1699 | 4c9649a9 | j_mayer | case 0x46: |
1700 | 4c9649a9 | j_mayer | /* CMOVGE */
|
1701 | fe2b269a | aurel32 | gen_cmov(TCG_COND_LT, ra, rb, rc, islit, lit, 0);
|
1702 | 4c9649a9 | j_mayer | break;
|
1703 | 4c9649a9 | j_mayer | case 0x48: |
1704 | 4c9649a9 | j_mayer | /* EQV */
|
1705 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1706 | 30c7183b | aurel32 | if (ra != 31) { |
1707 | 30c7183b | aurel32 | if (islit)
|
1708 | 30c7183b | aurel32 | tcg_gen_xori_i64(cpu_ir[rc], cpu_ir[ra], ~lit); |
1709 | 1b581c44 | aurel32 | else
|
1710 | 1b581c44 | aurel32 | tcg_gen_eqv_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
1711 | 30c7183b | aurel32 | } else {
|
1712 | 30c7183b | aurel32 | if (islit)
|
1713 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], ~lit); |
1714 | 30c7183b | aurel32 | else
|
1715 | dfaa8583 | aurel32 | tcg_gen_not_i64(cpu_ir[rc], cpu_ir[rb]); |
1716 | 30c7183b | aurel32 | } |
1717 | 30c7183b | aurel32 | } |
1718 | 4c9649a9 | j_mayer | break;
|
1719 | 4c9649a9 | j_mayer | case 0x61: |
1720 | 4c9649a9 | j_mayer | /* AMASK */
|
1721 | ae8ecd42 | aurel32 | if (likely(rc != 31)) { |
1722 | ae8ecd42 | aurel32 | if (islit)
|
1723 | 1a1f7dbc | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
1724 | ae8ecd42 | aurel32 | else
|
1725 | 1a1f7dbc | aurel32 | tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
1726 | 1a1f7dbc | aurel32 | switch (ctx->env->implver) {
|
1727 | 1a1f7dbc | aurel32 | case IMPLVER_2106x:
|
1728 | 1a1f7dbc | aurel32 | /* EV4, EV45, LCA, LCA45 & EV5 */
|
1729 | 1a1f7dbc | aurel32 | break;
|
1730 | 1a1f7dbc | aurel32 | case IMPLVER_21164:
|
1731 | 1a1f7dbc | aurel32 | case IMPLVER_21264:
|
1732 | 1a1f7dbc | aurel32 | case IMPLVER_21364:
|
1733 | 1a1f7dbc | aurel32 | tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[rc], |
1734 | 1a1f7dbc | aurel32 | ~(uint64_t)ctx->amask); |
1735 | 1a1f7dbc | aurel32 | break;
|
1736 | 1a1f7dbc | aurel32 | } |
1737 | ae8ecd42 | aurel32 | } |
1738 | 4c9649a9 | j_mayer | break;
|
1739 | 4c9649a9 | j_mayer | case 0x64: |
1740 | 4c9649a9 | j_mayer | /* CMOVLE */
|
1741 | fe2b269a | aurel32 | gen_cmov(TCG_COND_GT, ra, rb, rc, islit, lit, 0);
|
1742 | 4c9649a9 | j_mayer | break;
|
1743 | 4c9649a9 | j_mayer | case 0x66: |
1744 | 4c9649a9 | j_mayer | /* CMOVGT */
|
1745 | fe2b269a | aurel32 | gen_cmov(TCG_COND_LE, ra, rb, rc, islit, lit, 0);
|
1746 | 4c9649a9 | j_mayer | break;
|
1747 | 4c9649a9 | j_mayer | case 0x6C: |
1748 | 4c9649a9 | j_mayer | /* IMPLVER */
|
1749 | 3761035f | aurel32 | if (rc != 31) |
1750 | 8579095b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], ctx->env->implver); |
1751 | 4c9649a9 | j_mayer | break;
|
1752 | 4c9649a9 | j_mayer | default:
|
1753 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1754 | 4c9649a9 | j_mayer | } |
1755 | 4c9649a9 | j_mayer | break;
|
1756 | 4c9649a9 | j_mayer | case 0x12: |
1757 | 4c9649a9 | j_mayer | switch (fn7) {
|
1758 | 4c9649a9 | j_mayer | case 0x02: |
1759 | 4c9649a9 | j_mayer | /* MSKBL */
|
1760 | 14ab1634 | Richard Henderson | gen_msk_l(ra, rb, rc, islit, lit, 0x01);
|
1761 | 4c9649a9 | j_mayer | break;
|
1762 | 4c9649a9 | j_mayer | case 0x06: |
1763 | 4c9649a9 | j_mayer | /* EXTBL */
|
1764 | 377a43b6 | Richard Henderson | gen_ext_l(ra, rb, rc, islit, lit, 0x01);
|
1765 | 4c9649a9 | j_mayer | break;
|
1766 | 4c9649a9 | j_mayer | case 0x0B: |
1767 | 4c9649a9 | j_mayer | /* INSBL */
|
1768 | 248c42f3 | Richard Henderson | gen_ins_l(ra, rb, rc, islit, lit, 0x01);
|
1769 | 4c9649a9 | j_mayer | break;
|
1770 | 4c9649a9 | j_mayer | case 0x12: |
1771 | 4c9649a9 | j_mayer | /* MSKWL */
|
1772 | 14ab1634 | Richard Henderson | gen_msk_l(ra, rb, rc, islit, lit, 0x03);
|
1773 | 4c9649a9 | j_mayer | break;
|
1774 | 4c9649a9 | j_mayer | case 0x16: |
1775 | 4c9649a9 | j_mayer | /* EXTWL */
|
1776 | 377a43b6 | Richard Henderson | gen_ext_l(ra, rb, rc, islit, lit, 0x03);
|
1777 | 4c9649a9 | j_mayer | break;
|
1778 | 4c9649a9 | j_mayer | case 0x1B: |
1779 | 4c9649a9 | j_mayer | /* INSWL */
|
1780 | 248c42f3 | Richard Henderson | gen_ins_l(ra, rb, rc, islit, lit, 0x03);
|
1781 | 4c9649a9 | j_mayer | break;
|
1782 | 4c9649a9 | j_mayer | case 0x22: |
1783 | 4c9649a9 | j_mayer | /* MSKLL */
|
1784 | 14ab1634 | Richard Henderson | gen_msk_l(ra, rb, rc, islit, lit, 0x0f);
|
1785 | 4c9649a9 | j_mayer | break;
|
1786 | 4c9649a9 | j_mayer | case 0x26: |
1787 | 4c9649a9 | j_mayer | /* EXTLL */
|
1788 | 377a43b6 | Richard Henderson | gen_ext_l(ra, rb, rc, islit, lit, 0x0f);
|
1789 | 4c9649a9 | j_mayer | break;
|
1790 | 4c9649a9 | j_mayer | case 0x2B: |
1791 | 4c9649a9 | j_mayer | /* INSLL */
|
1792 | 248c42f3 | Richard Henderson | gen_ins_l(ra, rb, rc, islit, lit, 0x0f);
|
1793 | 4c9649a9 | j_mayer | break;
|
1794 | 4c9649a9 | j_mayer | case 0x30: |
1795 | 4c9649a9 | j_mayer | /* ZAP */
|
1796 | a7812ae4 | pbrook | gen_zap(ra, rb, rc, islit, lit); |
1797 | 4c9649a9 | j_mayer | break;
|
1798 | 4c9649a9 | j_mayer | case 0x31: |
1799 | 4c9649a9 | j_mayer | /* ZAPNOT */
|
1800 | a7812ae4 | pbrook | gen_zapnot(ra, rb, rc, islit, lit); |
1801 | 4c9649a9 | j_mayer | break;
|
1802 | 4c9649a9 | j_mayer | case 0x32: |
1803 | 4c9649a9 | j_mayer | /* MSKQL */
|
1804 | 14ab1634 | Richard Henderson | gen_msk_l(ra, rb, rc, islit, lit, 0xff);
|
1805 | 4c9649a9 | j_mayer | break;
|
1806 | 4c9649a9 | j_mayer | case 0x34: |
1807 | 4c9649a9 | j_mayer | /* SRL */
|
1808 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1809 | 30c7183b | aurel32 | if (ra != 31) { |
1810 | 30c7183b | aurel32 | if (islit)
|
1811 | 30c7183b | aurel32 | tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f);
|
1812 | dfaa8583 | aurel32 | else {
|
1813 | a7812ae4 | pbrook | TCGv shift = tcg_temp_new(); |
1814 | 30c7183b | aurel32 | tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f);
|
1815 | 30c7183b | aurel32 | tcg_gen_shr_i64(cpu_ir[rc], cpu_ir[ra], shift); |
1816 | 30c7183b | aurel32 | tcg_temp_free(shift); |
1817 | dfaa8583 | aurel32 | } |
1818 | 30c7183b | aurel32 | } else
|
1819 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
1820 | 30c7183b | aurel32 | } |
1821 | 4c9649a9 | j_mayer | break;
|
1822 | 4c9649a9 | j_mayer | case 0x36: |
1823 | 4c9649a9 | j_mayer | /* EXTQL */
|
1824 | 377a43b6 | Richard Henderson | gen_ext_l(ra, rb, rc, islit, lit, 0xff);
|
1825 | 4c9649a9 | j_mayer | break;
|
1826 | 4c9649a9 | j_mayer | case 0x39: |
1827 | 4c9649a9 | j_mayer | /* SLL */
|
1828 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1829 | 30c7183b | aurel32 | if (ra != 31) { |
1830 | 30c7183b | aurel32 | if (islit)
|
1831 | 30c7183b | aurel32 | tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f);
|
1832 | dfaa8583 | aurel32 | else {
|
1833 | a7812ae4 | pbrook | TCGv shift = tcg_temp_new(); |
1834 | 30c7183b | aurel32 | tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f);
|
1835 | 30c7183b | aurel32 | tcg_gen_shl_i64(cpu_ir[rc], cpu_ir[ra], shift); |
1836 | 30c7183b | aurel32 | tcg_temp_free(shift); |
1837 | dfaa8583 | aurel32 | } |
1838 | 30c7183b | aurel32 | } else
|
1839 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
1840 | 30c7183b | aurel32 | } |
1841 | 4c9649a9 | j_mayer | break;
|
1842 | 4c9649a9 | j_mayer | case 0x3B: |
1843 | 4c9649a9 | j_mayer | /* INSQL */
|
1844 | 248c42f3 | Richard Henderson | gen_ins_l(ra, rb, rc, islit, lit, 0xff);
|
1845 | 4c9649a9 | j_mayer | break;
|
1846 | 4c9649a9 | j_mayer | case 0x3C: |
1847 | 4c9649a9 | j_mayer | /* SRA */
|
1848 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1849 | 30c7183b | aurel32 | if (ra != 31) { |
1850 | 30c7183b | aurel32 | if (islit)
|
1851 | 30c7183b | aurel32 | tcg_gen_sari_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f);
|
1852 | dfaa8583 | aurel32 | else {
|
1853 | a7812ae4 | pbrook | TCGv shift = tcg_temp_new(); |
1854 | 30c7183b | aurel32 | tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f);
|
1855 | 30c7183b | aurel32 | tcg_gen_sar_i64(cpu_ir[rc], cpu_ir[ra], shift); |
1856 | 30c7183b | aurel32 | tcg_temp_free(shift); |
1857 | dfaa8583 | aurel32 | } |
1858 | 30c7183b | aurel32 | } else
|
1859 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
1860 | 30c7183b | aurel32 | } |
1861 | 4c9649a9 | j_mayer | break;
|
1862 | 4c9649a9 | j_mayer | case 0x52: |
1863 | 4c9649a9 | j_mayer | /* MSKWH */
|
1864 | ffec44f1 | Richard Henderson | gen_msk_h(ra, rb, rc, islit, lit, 0x03);
|
1865 | 4c9649a9 | j_mayer | break;
|
1866 | 4c9649a9 | j_mayer | case 0x57: |
1867 | 4c9649a9 | j_mayer | /* INSWH */
|
1868 | 50eb6e5c | Richard Henderson | gen_ins_h(ra, rb, rc, islit, lit, 0x03);
|
1869 | 4c9649a9 | j_mayer | break;
|
1870 | 4c9649a9 | j_mayer | case 0x5A: |
1871 | 4c9649a9 | j_mayer | /* EXTWH */
|
1872 | 377a43b6 | Richard Henderson | gen_ext_h(ra, rb, rc, islit, lit, 0x03);
|
1873 | 4c9649a9 | j_mayer | break;
|
1874 | 4c9649a9 | j_mayer | case 0x62: |
1875 | 4c9649a9 | j_mayer | /* MSKLH */
|
1876 | ffec44f1 | Richard Henderson | gen_msk_h(ra, rb, rc, islit, lit, 0x0f);
|
1877 | 4c9649a9 | j_mayer | break;
|
1878 | 4c9649a9 | j_mayer | case 0x67: |
1879 | 4c9649a9 | j_mayer | /* INSLH */
|
1880 | 50eb6e5c | Richard Henderson | gen_ins_h(ra, rb, rc, islit, lit, 0x0f);
|
1881 | 4c9649a9 | j_mayer | break;
|
1882 | 4c9649a9 | j_mayer | case 0x6A: |
1883 | 4c9649a9 | j_mayer | /* EXTLH */
|
1884 | 377a43b6 | Richard Henderson | gen_ext_h(ra, rb, rc, islit, lit, 0x0f);
|
1885 | 4c9649a9 | j_mayer | break;
|
1886 | 4c9649a9 | j_mayer | case 0x72: |
1887 | 4c9649a9 | j_mayer | /* MSKQH */
|
1888 | ffec44f1 | Richard Henderson | gen_msk_h(ra, rb, rc, islit, lit, 0xff);
|
1889 | 4c9649a9 | j_mayer | break;
|
1890 | 4c9649a9 | j_mayer | case 0x77: |
1891 | 4c9649a9 | j_mayer | /* INSQH */
|
1892 | 50eb6e5c | Richard Henderson | gen_ins_h(ra, rb, rc, islit, lit, 0xff);
|
1893 | 4c9649a9 | j_mayer | break;
|
1894 | 4c9649a9 | j_mayer | case 0x7A: |
1895 | 4c9649a9 | j_mayer | /* EXTQH */
|
1896 | 377a43b6 | Richard Henderson | gen_ext_h(ra, rb, rc, islit, lit, 0xff);
|
1897 | 4c9649a9 | j_mayer | break;
|
1898 | 4c9649a9 | j_mayer | default:
|
1899 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1900 | 4c9649a9 | j_mayer | } |
1901 | 4c9649a9 | j_mayer | break;
|
1902 | 4c9649a9 | j_mayer | case 0x13: |
1903 | 4c9649a9 | j_mayer | switch (fn7) {
|
1904 | 4c9649a9 | j_mayer | case 0x00: |
1905 | 4c9649a9 | j_mayer | /* MULL */
|
1906 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1907 | dfaa8583 | aurel32 | if (ra == 31) |
1908 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
1909 | 30c7183b | aurel32 | else {
|
1910 | 30c7183b | aurel32 | if (islit)
|
1911 | 30c7183b | aurel32 | tcg_gen_muli_i64(cpu_ir[rc], cpu_ir[ra], lit); |
1912 | 30c7183b | aurel32 | else
|
1913 | 30c7183b | aurel32 | tcg_gen_mul_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
1914 | 30c7183b | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); |
1915 | 30c7183b | aurel32 | } |
1916 | 30c7183b | aurel32 | } |
1917 | 4c9649a9 | j_mayer | break;
|
1918 | 4c9649a9 | j_mayer | case 0x20: |
1919 | 4c9649a9 | j_mayer | /* MULQ */
|
1920 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
1921 | dfaa8583 | aurel32 | if (ra == 31) |
1922 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
1923 | 30c7183b | aurel32 | else if (islit) |
1924 | 30c7183b | aurel32 | tcg_gen_muli_i64(cpu_ir[rc], cpu_ir[ra], lit); |
1925 | 30c7183b | aurel32 | else
|
1926 | 30c7183b | aurel32 | tcg_gen_mul_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
1927 | 30c7183b | aurel32 | } |
1928 | 4c9649a9 | j_mayer | break;
|
1929 | 4c9649a9 | j_mayer | case 0x30: |
1930 | 4c9649a9 | j_mayer | /* UMULH */
|
1931 | a7812ae4 | pbrook | gen_umulh(ra, rb, rc, islit, lit); |
1932 | 4c9649a9 | j_mayer | break;
|
1933 | 4c9649a9 | j_mayer | case 0x40: |
1934 | 4c9649a9 | j_mayer | /* MULL/V */
|
1935 | a7812ae4 | pbrook | gen_mullv(ra, rb, rc, islit, lit); |
1936 | 4c9649a9 | j_mayer | break;
|
1937 | 4c9649a9 | j_mayer | case 0x60: |
1938 | 4c9649a9 | j_mayer | /* MULQ/V */
|
1939 | a7812ae4 | pbrook | gen_mulqv(ra, rb, rc, islit, lit); |
1940 | 4c9649a9 | j_mayer | break;
|
1941 | 4c9649a9 | j_mayer | default:
|
1942 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1943 | 4c9649a9 | j_mayer | } |
1944 | 4c9649a9 | j_mayer | break;
|
1945 | 4c9649a9 | j_mayer | case 0x14: |
1946 | f24518b5 | Richard Henderson | switch (fpfn) { /* fn11 & 0x3F */ |
1947 | 4c9649a9 | j_mayer | case 0x04: |
1948 | 4c9649a9 | j_mayer | /* ITOFS */
|
1949 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_FIX))
|
1950 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1951 | f18cd223 | aurel32 | if (likely(rc != 31)) { |
1952 | f18cd223 | aurel32 | if (ra != 31) { |
1953 | a7812ae4 | pbrook | TCGv_i32 tmp = tcg_temp_new_i32(); |
1954 | f18cd223 | aurel32 | tcg_gen_trunc_i64_i32(tmp, cpu_ir[ra]); |
1955 | a7812ae4 | pbrook | gen_helper_memory_to_s(cpu_fir[rc], tmp); |
1956 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp); |
1957 | f18cd223 | aurel32 | } else
|
1958 | f18cd223 | aurel32 | tcg_gen_movi_i64(cpu_fir[rc], 0);
|
1959 | f18cd223 | aurel32 | } |
1960 | 4c9649a9 | j_mayer | break;
|
1961 | 4c9649a9 | j_mayer | case 0x0A: |
1962 | 4c9649a9 | j_mayer | /* SQRTF */
|
1963 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_FIX))
|
1964 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1965 | a7812ae4 | pbrook | gen_fsqrtf(rb, rc); |
1966 | 4c9649a9 | j_mayer | break;
|
1967 | 4c9649a9 | j_mayer | case 0x0B: |
1968 | 4c9649a9 | j_mayer | /* SQRTS */
|
1969 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_FIX))
|
1970 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1971 | f24518b5 | Richard Henderson | gen_fsqrts(ctx, rb, rc, fn11); |
1972 | 4c9649a9 | j_mayer | break;
|
1973 | 4c9649a9 | j_mayer | case 0x14: |
1974 | 4c9649a9 | j_mayer | /* ITOFF */
|
1975 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_FIX))
|
1976 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1977 | f18cd223 | aurel32 | if (likely(rc != 31)) { |
1978 | f18cd223 | aurel32 | if (ra != 31) { |
1979 | a7812ae4 | pbrook | TCGv_i32 tmp = tcg_temp_new_i32(); |
1980 | f18cd223 | aurel32 | tcg_gen_trunc_i64_i32(tmp, cpu_ir[ra]); |
1981 | a7812ae4 | pbrook | gen_helper_memory_to_f(cpu_fir[rc], tmp); |
1982 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp); |
1983 | f18cd223 | aurel32 | } else
|
1984 | f18cd223 | aurel32 | tcg_gen_movi_i64(cpu_fir[rc], 0);
|
1985 | f18cd223 | aurel32 | } |
1986 | 4c9649a9 | j_mayer | break;
|
1987 | 4c9649a9 | j_mayer | case 0x24: |
1988 | 4c9649a9 | j_mayer | /* ITOFT */
|
1989 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_FIX))
|
1990 | 4c9649a9 | j_mayer | goto invalid_opc;
|
1991 | f18cd223 | aurel32 | if (likely(rc != 31)) { |
1992 | f18cd223 | aurel32 | if (ra != 31) |
1993 | f18cd223 | aurel32 | tcg_gen_mov_i64(cpu_fir[rc], cpu_ir[ra]); |
1994 | f18cd223 | aurel32 | else
|
1995 | f18cd223 | aurel32 | tcg_gen_movi_i64(cpu_fir[rc], 0);
|
1996 | f18cd223 | aurel32 | } |
1997 | 4c9649a9 | j_mayer | break;
|
1998 | 4c9649a9 | j_mayer | case 0x2A: |
1999 | 4c9649a9 | j_mayer | /* SQRTG */
|
2000 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_FIX))
|
2001 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2002 | a7812ae4 | pbrook | gen_fsqrtg(rb, rc); |
2003 | 4c9649a9 | j_mayer | break;
|
2004 | 4c9649a9 | j_mayer | case 0x02B: |
2005 | 4c9649a9 | j_mayer | /* SQRTT */
|
2006 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_FIX))
|
2007 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2008 | f24518b5 | Richard Henderson | gen_fsqrtt(ctx, rb, rc, fn11); |
2009 | 4c9649a9 | j_mayer | break;
|
2010 | 4c9649a9 | j_mayer | default:
|
2011 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2012 | 4c9649a9 | j_mayer | } |
2013 | 4c9649a9 | j_mayer | break;
|
2014 | 4c9649a9 | j_mayer | case 0x15: |
2015 | 4c9649a9 | j_mayer | /* VAX floating point */
|
2016 | 4c9649a9 | j_mayer | /* XXX: rounding mode and trap are ignored (!) */
|
2017 | f24518b5 | Richard Henderson | switch (fpfn) { /* fn11 & 0x3F */ |
2018 | 4c9649a9 | j_mayer | case 0x00: |
2019 | 4c9649a9 | j_mayer | /* ADDF */
|
2020 | a7812ae4 | pbrook | gen_faddf(ra, rb, rc); |
2021 | 4c9649a9 | j_mayer | break;
|
2022 | 4c9649a9 | j_mayer | case 0x01: |
2023 | 4c9649a9 | j_mayer | /* SUBF */
|
2024 | a7812ae4 | pbrook | gen_fsubf(ra, rb, rc); |
2025 | 4c9649a9 | j_mayer | break;
|
2026 | 4c9649a9 | j_mayer | case 0x02: |
2027 | 4c9649a9 | j_mayer | /* MULF */
|
2028 | a7812ae4 | pbrook | gen_fmulf(ra, rb, rc); |
2029 | 4c9649a9 | j_mayer | break;
|
2030 | 4c9649a9 | j_mayer | case 0x03: |
2031 | 4c9649a9 | j_mayer | /* DIVF */
|
2032 | a7812ae4 | pbrook | gen_fdivf(ra, rb, rc); |
2033 | 4c9649a9 | j_mayer | break;
|
2034 | 4c9649a9 | j_mayer | case 0x1E: |
2035 | 4c9649a9 | j_mayer | /* CVTDG */
|
2036 | 4c9649a9 | j_mayer | #if 0 // TODO
|
2037 | a7812ae4 | pbrook | gen_fcvtdg(rb, rc);
|
2038 | 4c9649a9 | j_mayer | #else
|
2039 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2040 | 4c9649a9 | j_mayer | #endif
|
2041 | 4c9649a9 | j_mayer | break;
|
2042 | 4c9649a9 | j_mayer | case 0x20: |
2043 | 4c9649a9 | j_mayer | /* ADDG */
|
2044 | a7812ae4 | pbrook | gen_faddg(ra, rb, rc); |
2045 | 4c9649a9 | j_mayer | break;
|
2046 | 4c9649a9 | j_mayer | case 0x21: |
2047 | 4c9649a9 | j_mayer | /* SUBG */
|
2048 | a7812ae4 | pbrook | gen_fsubg(ra, rb, rc); |
2049 | 4c9649a9 | j_mayer | break;
|
2050 | 4c9649a9 | j_mayer | case 0x22: |
2051 | 4c9649a9 | j_mayer | /* MULG */
|
2052 | a7812ae4 | pbrook | gen_fmulg(ra, rb, rc); |
2053 | 4c9649a9 | j_mayer | break;
|
2054 | 4c9649a9 | j_mayer | case 0x23: |
2055 | 4c9649a9 | j_mayer | /* DIVG */
|
2056 | a7812ae4 | pbrook | gen_fdivg(ra, rb, rc); |
2057 | 4c9649a9 | j_mayer | break;
|
2058 | 4c9649a9 | j_mayer | case 0x25: |
2059 | 4c9649a9 | j_mayer | /* CMPGEQ */
|
2060 | a7812ae4 | pbrook | gen_fcmpgeq(ra, rb, rc); |
2061 | 4c9649a9 | j_mayer | break;
|
2062 | 4c9649a9 | j_mayer | case 0x26: |
2063 | 4c9649a9 | j_mayer | /* CMPGLT */
|
2064 | a7812ae4 | pbrook | gen_fcmpglt(ra, rb, rc); |
2065 | 4c9649a9 | j_mayer | break;
|
2066 | 4c9649a9 | j_mayer | case 0x27: |
2067 | 4c9649a9 | j_mayer | /* CMPGLE */
|
2068 | a7812ae4 | pbrook | gen_fcmpgle(ra, rb, rc); |
2069 | 4c9649a9 | j_mayer | break;
|
2070 | 4c9649a9 | j_mayer | case 0x2C: |
2071 | 4c9649a9 | j_mayer | /* CVTGF */
|
2072 | a7812ae4 | pbrook | gen_fcvtgf(rb, rc); |
2073 | 4c9649a9 | j_mayer | break;
|
2074 | 4c9649a9 | j_mayer | case 0x2D: |
2075 | 4c9649a9 | j_mayer | /* CVTGD */
|
2076 | 4c9649a9 | j_mayer | #if 0 // TODO
|
2077 | a7812ae4 | pbrook | gen_fcvtgd(rb, rc);
|
2078 | 4c9649a9 | j_mayer | #else
|
2079 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2080 | 4c9649a9 | j_mayer | #endif
|
2081 | 4c9649a9 | j_mayer | break;
|
2082 | 4c9649a9 | j_mayer | case 0x2F: |
2083 | 4c9649a9 | j_mayer | /* CVTGQ */
|
2084 | a7812ae4 | pbrook | gen_fcvtgq(rb, rc); |
2085 | 4c9649a9 | j_mayer | break;
|
2086 | 4c9649a9 | j_mayer | case 0x3C: |
2087 | 4c9649a9 | j_mayer | /* CVTQF */
|
2088 | a7812ae4 | pbrook | gen_fcvtqf(rb, rc); |
2089 | 4c9649a9 | j_mayer | break;
|
2090 | 4c9649a9 | j_mayer | case 0x3E: |
2091 | 4c9649a9 | j_mayer | /* CVTQG */
|
2092 | a7812ae4 | pbrook | gen_fcvtqg(rb, rc); |
2093 | 4c9649a9 | j_mayer | break;
|
2094 | 4c9649a9 | j_mayer | default:
|
2095 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2096 | 4c9649a9 | j_mayer | } |
2097 | 4c9649a9 | j_mayer | break;
|
2098 | 4c9649a9 | j_mayer | case 0x16: |
2099 | 4c9649a9 | j_mayer | /* IEEE floating-point */
|
2100 | f24518b5 | Richard Henderson | switch (fpfn) { /* fn11 & 0x3F */ |
2101 | 4c9649a9 | j_mayer | case 0x00: |
2102 | 4c9649a9 | j_mayer | /* ADDS */
|
2103 | f24518b5 | Richard Henderson | gen_fadds(ctx, ra, rb, rc, fn11); |
2104 | 4c9649a9 | j_mayer | break;
|
2105 | 4c9649a9 | j_mayer | case 0x01: |
2106 | 4c9649a9 | j_mayer | /* SUBS */
|
2107 | f24518b5 | Richard Henderson | gen_fsubs(ctx, ra, rb, rc, fn11); |
2108 | 4c9649a9 | j_mayer | break;
|
2109 | 4c9649a9 | j_mayer | case 0x02: |
2110 | 4c9649a9 | j_mayer | /* MULS */
|
2111 | f24518b5 | Richard Henderson | gen_fmuls(ctx, ra, rb, rc, fn11); |
2112 | 4c9649a9 | j_mayer | break;
|
2113 | 4c9649a9 | j_mayer | case 0x03: |
2114 | 4c9649a9 | j_mayer | /* DIVS */
|
2115 | f24518b5 | Richard Henderson | gen_fdivs(ctx, ra, rb, rc, fn11); |
2116 | 4c9649a9 | j_mayer | break;
|
2117 | 4c9649a9 | j_mayer | case 0x20: |
2118 | 4c9649a9 | j_mayer | /* ADDT */
|
2119 | f24518b5 | Richard Henderson | gen_faddt(ctx, ra, rb, rc, fn11); |
2120 | 4c9649a9 | j_mayer | break;
|
2121 | 4c9649a9 | j_mayer | case 0x21: |
2122 | 4c9649a9 | j_mayer | /* SUBT */
|
2123 | f24518b5 | Richard Henderson | gen_fsubt(ctx, ra, rb, rc, fn11); |
2124 | 4c9649a9 | j_mayer | break;
|
2125 | 4c9649a9 | j_mayer | case 0x22: |
2126 | 4c9649a9 | j_mayer | /* MULT */
|
2127 | f24518b5 | Richard Henderson | gen_fmult(ctx, ra, rb, rc, fn11); |
2128 | 4c9649a9 | j_mayer | break;
|
2129 | 4c9649a9 | j_mayer | case 0x23: |
2130 | 4c9649a9 | j_mayer | /* DIVT */
|
2131 | f24518b5 | Richard Henderson | gen_fdivt(ctx, ra, rb, rc, fn11); |
2132 | 4c9649a9 | j_mayer | break;
|
2133 | 4c9649a9 | j_mayer | case 0x24: |
2134 | 4c9649a9 | j_mayer | /* CMPTUN */
|
2135 | f24518b5 | Richard Henderson | gen_fcmptun(ctx, ra, rb, rc, fn11); |
2136 | 4c9649a9 | j_mayer | break;
|
2137 | 4c9649a9 | j_mayer | case 0x25: |
2138 | 4c9649a9 | j_mayer | /* CMPTEQ */
|
2139 | f24518b5 | Richard Henderson | gen_fcmpteq(ctx, ra, rb, rc, fn11); |
2140 | 4c9649a9 | j_mayer | break;
|
2141 | 4c9649a9 | j_mayer | case 0x26: |
2142 | 4c9649a9 | j_mayer | /* CMPTLT */
|
2143 | f24518b5 | Richard Henderson | gen_fcmptlt(ctx, ra, rb, rc, fn11); |
2144 | 4c9649a9 | j_mayer | break;
|
2145 | 4c9649a9 | j_mayer | case 0x27: |
2146 | 4c9649a9 | j_mayer | /* CMPTLE */
|
2147 | f24518b5 | Richard Henderson | gen_fcmptle(ctx, ra, rb, rc, fn11); |
2148 | 4c9649a9 | j_mayer | break;
|
2149 | 4c9649a9 | j_mayer | case 0x2C: |
2150 | a74b4d2c | aurel32 | if (fn11 == 0x2AC || fn11 == 0x6AC) { |
2151 | 4c9649a9 | j_mayer | /* CVTST */
|
2152 | f24518b5 | Richard Henderson | gen_fcvtst(ctx, rb, rc, fn11); |
2153 | 4c9649a9 | j_mayer | } else {
|
2154 | 4c9649a9 | j_mayer | /* CVTTS */
|
2155 | f24518b5 | Richard Henderson | gen_fcvtts(ctx, rb, rc, fn11); |
2156 | 4c9649a9 | j_mayer | } |
2157 | 4c9649a9 | j_mayer | break;
|
2158 | 4c9649a9 | j_mayer | case 0x2F: |
2159 | 4c9649a9 | j_mayer | /* CVTTQ */
|
2160 | f24518b5 | Richard Henderson | gen_fcvttq(ctx, rb, rc, fn11); |
2161 | 4c9649a9 | j_mayer | break;
|
2162 | 4c9649a9 | j_mayer | case 0x3C: |
2163 | 4c9649a9 | j_mayer | /* CVTQS */
|
2164 | f24518b5 | Richard Henderson | gen_fcvtqs(ctx, rb, rc, fn11); |
2165 | 4c9649a9 | j_mayer | break;
|
2166 | 4c9649a9 | j_mayer | case 0x3E: |
2167 | 4c9649a9 | j_mayer | /* CVTQT */
|
2168 | f24518b5 | Richard Henderson | gen_fcvtqt(ctx, rb, rc, fn11); |
2169 | 4c9649a9 | j_mayer | break;
|
2170 | 4c9649a9 | j_mayer | default:
|
2171 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2172 | 4c9649a9 | j_mayer | } |
2173 | 4c9649a9 | j_mayer | break;
|
2174 | 4c9649a9 | j_mayer | case 0x17: |
2175 | 4c9649a9 | j_mayer | switch (fn11) {
|
2176 | 4c9649a9 | j_mayer | case 0x010: |
2177 | 4c9649a9 | j_mayer | /* CVTLQ */
|
2178 | a7812ae4 | pbrook | gen_fcvtlq(rb, rc); |
2179 | 4c9649a9 | j_mayer | break;
|
2180 | 4c9649a9 | j_mayer | case 0x020: |
2181 | f18cd223 | aurel32 | if (likely(rc != 31)) { |
2182 | a06d48d9 | Richard Henderson | if (ra == rb) {
|
2183 | 4c9649a9 | j_mayer | /* FMOV */
|
2184 | a06d48d9 | Richard Henderson | if (ra == 31) |
2185 | a06d48d9 | Richard Henderson | tcg_gen_movi_i64(cpu_fir[rc], 0);
|
2186 | a06d48d9 | Richard Henderson | else
|
2187 | a06d48d9 | Richard Henderson | tcg_gen_mov_i64(cpu_fir[rc], cpu_fir[ra]); |
2188 | a06d48d9 | Richard Henderson | } else {
|
2189 | f18cd223 | aurel32 | /* CPYS */
|
2190 | a7812ae4 | pbrook | gen_fcpys(ra, rb, rc); |
2191 | a06d48d9 | Richard Henderson | } |
2192 | 4c9649a9 | j_mayer | } |
2193 | 4c9649a9 | j_mayer | break;
|
2194 | 4c9649a9 | j_mayer | case 0x021: |
2195 | 4c9649a9 | j_mayer | /* CPYSN */
|
2196 | a7812ae4 | pbrook | gen_fcpysn(ra, rb, rc); |
2197 | 4c9649a9 | j_mayer | break;
|
2198 | 4c9649a9 | j_mayer | case 0x022: |
2199 | 4c9649a9 | j_mayer | /* CPYSE */
|
2200 | a7812ae4 | pbrook | gen_fcpyse(ra, rb, rc); |
2201 | 4c9649a9 | j_mayer | break;
|
2202 | 4c9649a9 | j_mayer | case 0x024: |
2203 | 4c9649a9 | j_mayer | /* MT_FPCR */
|
2204 | f18cd223 | aurel32 | if (likely(ra != 31)) |
2205 | a7812ae4 | pbrook | gen_helper_store_fpcr(cpu_fir[ra]); |
2206 | f18cd223 | aurel32 | else {
|
2207 | f18cd223 | aurel32 | TCGv tmp = tcg_const_i64(0);
|
2208 | a7812ae4 | pbrook | gen_helper_store_fpcr(tmp); |
2209 | f18cd223 | aurel32 | tcg_temp_free(tmp); |
2210 | f18cd223 | aurel32 | } |
2211 | 4c9649a9 | j_mayer | break;
|
2212 | 4c9649a9 | j_mayer | case 0x025: |
2213 | 4c9649a9 | j_mayer | /* MF_FPCR */
|
2214 | f18cd223 | aurel32 | if (likely(ra != 31)) |
2215 | a7812ae4 | pbrook | gen_helper_load_fpcr(cpu_fir[ra]); |
2216 | 4c9649a9 | j_mayer | break;
|
2217 | 4c9649a9 | j_mayer | case 0x02A: |
2218 | 4c9649a9 | j_mayer | /* FCMOVEQ */
|
2219 | dbb30fe6 | Richard Henderson | gen_fcmov(TCG_COND_NE, ra, rb, rc); |
2220 | 4c9649a9 | j_mayer | break;
|
2221 | 4c9649a9 | j_mayer | case 0x02B: |
2222 | 4c9649a9 | j_mayer | /* FCMOVNE */
|
2223 | dbb30fe6 | Richard Henderson | gen_fcmov(TCG_COND_EQ, ra, rb, rc); |
2224 | 4c9649a9 | j_mayer | break;
|
2225 | 4c9649a9 | j_mayer | case 0x02C: |
2226 | 4c9649a9 | j_mayer | /* FCMOVLT */
|
2227 | dbb30fe6 | Richard Henderson | gen_fcmov(TCG_COND_GE, ra, rb, rc); |
2228 | 4c9649a9 | j_mayer | break;
|
2229 | 4c9649a9 | j_mayer | case 0x02D: |
2230 | 4c9649a9 | j_mayer | /* FCMOVGE */
|
2231 | dbb30fe6 | Richard Henderson | gen_fcmov(TCG_COND_LT, ra, rb, rc); |
2232 | 4c9649a9 | j_mayer | break;
|
2233 | 4c9649a9 | j_mayer | case 0x02E: |
2234 | 4c9649a9 | j_mayer | /* FCMOVLE */
|
2235 | dbb30fe6 | Richard Henderson | gen_fcmov(TCG_COND_GT, ra, rb, rc); |
2236 | 4c9649a9 | j_mayer | break;
|
2237 | 4c9649a9 | j_mayer | case 0x02F: |
2238 | 4c9649a9 | j_mayer | /* FCMOVGT */
|
2239 | dbb30fe6 | Richard Henderson | gen_fcmov(TCG_COND_LE, ra, rb, rc); |
2240 | 4c9649a9 | j_mayer | break;
|
2241 | 4c9649a9 | j_mayer | case 0x030: |
2242 | 4c9649a9 | j_mayer | /* CVTQL */
|
2243 | a7812ae4 | pbrook | gen_fcvtql(rb, rc); |
2244 | 4c9649a9 | j_mayer | break;
|
2245 | 4c9649a9 | j_mayer | case 0x130: |
2246 | 4c9649a9 | j_mayer | /* CVTQL/V */
|
2247 | f24518b5 | Richard Henderson | gen_fcvtql_v(rb, rc); |
2248 | 4c9649a9 | j_mayer | break;
|
2249 | 4c9649a9 | j_mayer | case 0x530: |
2250 | 4c9649a9 | j_mayer | /* CVTQL/SV */
|
2251 | f24518b5 | Richard Henderson | gen_fcvtql_sv(rb, rc); |
2252 | 4c9649a9 | j_mayer | break;
|
2253 | 4c9649a9 | j_mayer | default:
|
2254 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2255 | 4c9649a9 | j_mayer | } |
2256 | 4c9649a9 | j_mayer | break;
|
2257 | 4c9649a9 | j_mayer | case 0x18: |
2258 | 4c9649a9 | j_mayer | switch ((uint16_t)disp16) {
|
2259 | 4c9649a9 | j_mayer | case 0x0000: |
2260 | 4c9649a9 | j_mayer | /* TRAPB */
|
2261 | 4c9649a9 | j_mayer | /* No-op. Just exit from the current tb */
|
2262 | 4c9649a9 | j_mayer | ret = 2;
|
2263 | 4c9649a9 | j_mayer | break;
|
2264 | 4c9649a9 | j_mayer | case 0x0400: |
2265 | 4c9649a9 | j_mayer | /* EXCB */
|
2266 | 4c9649a9 | j_mayer | /* No-op. Just exit from the current tb */
|
2267 | 4c9649a9 | j_mayer | ret = 2;
|
2268 | 4c9649a9 | j_mayer | break;
|
2269 | 4c9649a9 | j_mayer | case 0x4000: |
2270 | 4c9649a9 | j_mayer | /* MB */
|
2271 | 4c9649a9 | j_mayer | /* No-op */
|
2272 | 4c9649a9 | j_mayer | break;
|
2273 | 4c9649a9 | j_mayer | case 0x4400: |
2274 | 4c9649a9 | j_mayer | /* WMB */
|
2275 | 4c9649a9 | j_mayer | /* No-op */
|
2276 | 4c9649a9 | j_mayer | break;
|
2277 | 4c9649a9 | j_mayer | case 0x8000: |
2278 | 4c9649a9 | j_mayer | /* FETCH */
|
2279 | 4c9649a9 | j_mayer | /* No-op */
|
2280 | 4c9649a9 | j_mayer | break;
|
2281 | 4c9649a9 | j_mayer | case 0xA000: |
2282 | 4c9649a9 | j_mayer | /* FETCH_M */
|
2283 | 4c9649a9 | j_mayer | /* No-op */
|
2284 | 4c9649a9 | j_mayer | break;
|
2285 | 4c9649a9 | j_mayer | case 0xC000: |
2286 | 4c9649a9 | j_mayer | /* RPCC */
|
2287 | 3761035f | aurel32 | if (ra != 31) |
2288 | a7812ae4 | pbrook | gen_helper_load_pcc(cpu_ir[ra]); |
2289 | 4c9649a9 | j_mayer | break;
|
2290 | 4c9649a9 | j_mayer | case 0xE000: |
2291 | 4c9649a9 | j_mayer | /* RC */
|
2292 | 3761035f | aurel32 | if (ra != 31) |
2293 | a7812ae4 | pbrook | gen_helper_rc(cpu_ir[ra]); |
2294 | 4c9649a9 | j_mayer | break;
|
2295 | 4c9649a9 | j_mayer | case 0xE800: |
2296 | 4c9649a9 | j_mayer | /* ECB */
|
2297 | 4c9649a9 | j_mayer | break;
|
2298 | 4c9649a9 | j_mayer | case 0xF000: |
2299 | 4c9649a9 | j_mayer | /* RS */
|
2300 | 3761035f | aurel32 | if (ra != 31) |
2301 | a7812ae4 | pbrook | gen_helper_rs(cpu_ir[ra]); |
2302 | 4c9649a9 | j_mayer | break;
|
2303 | 4c9649a9 | j_mayer | case 0xF800: |
2304 | 4c9649a9 | j_mayer | /* WH64 */
|
2305 | 4c9649a9 | j_mayer | /* No-op */
|
2306 | 4c9649a9 | j_mayer | break;
|
2307 | 4c9649a9 | j_mayer | default:
|
2308 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2309 | 4c9649a9 | j_mayer | } |
2310 | 4c9649a9 | j_mayer | break;
|
2311 | 4c9649a9 | j_mayer | case 0x19: |
2312 | 4c9649a9 | j_mayer | /* HW_MFPR (PALcode) */
|
2313 | 4c9649a9 | j_mayer | #if defined (CONFIG_USER_ONLY)
|
2314 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2315 | 4c9649a9 | j_mayer | #else
|
2316 | 4c9649a9 | j_mayer | if (!ctx->pal_mode)
|
2317 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2318 | 8bb6e981 | aurel32 | if (ra != 31) { |
2319 | 8bb6e981 | aurel32 | TCGv tmp = tcg_const_i32(insn & 0xFF);
|
2320 | a7812ae4 | pbrook | gen_helper_mfpr(cpu_ir[ra], tmp, cpu_ir[ra]); |
2321 | 8bb6e981 | aurel32 | tcg_temp_free(tmp); |
2322 | 8bb6e981 | aurel32 | } |
2323 | 4c9649a9 | j_mayer | break;
|
2324 | 4c9649a9 | j_mayer | #endif
|
2325 | 4c9649a9 | j_mayer | case 0x1A: |
2326 | 3761035f | aurel32 | if (rb != 31) |
2327 | 3761035f | aurel32 | tcg_gen_andi_i64(cpu_pc, cpu_ir[rb], ~3);
|
2328 | 3761035f | aurel32 | else
|
2329 | 3761035f | aurel32 | tcg_gen_movi_i64(cpu_pc, 0);
|
2330 | 1304ca87 | aurel32 | if (ra != 31) |
2331 | 1304ca87 | aurel32 | tcg_gen_movi_i64(cpu_ir[ra], ctx->pc); |
2332 | 4c9649a9 | j_mayer | /* Those four jumps only differ by the branch prediction hint */
|
2333 | 4c9649a9 | j_mayer | switch (fn2) {
|
2334 | 4c9649a9 | j_mayer | case 0x0: |
2335 | 4c9649a9 | j_mayer | /* JMP */
|
2336 | 4c9649a9 | j_mayer | break;
|
2337 | 4c9649a9 | j_mayer | case 0x1: |
2338 | 4c9649a9 | j_mayer | /* JSR */
|
2339 | 4c9649a9 | j_mayer | break;
|
2340 | 4c9649a9 | j_mayer | case 0x2: |
2341 | 4c9649a9 | j_mayer | /* RET */
|
2342 | 4c9649a9 | j_mayer | break;
|
2343 | 4c9649a9 | j_mayer | case 0x3: |
2344 | 4c9649a9 | j_mayer | /* JSR_COROUTINE */
|
2345 | 4c9649a9 | j_mayer | break;
|
2346 | 4c9649a9 | j_mayer | } |
2347 | 4c9649a9 | j_mayer | ret = 1;
|
2348 | 4c9649a9 | j_mayer | break;
|
2349 | 4c9649a9 | j_mayer | case 0x1B: |
2350 | 4c9649a9 | j_mayer | /* HW_LD (PALcode) */
|
2351 | 4c9649a9 | j_mayer | #if defined (CONFIG_USER_ONLY)
|
2352 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2353 | 4c9649a9 | j_mayer | #else
|
2354 | 4c9649a9 | j_mayer | if (!ctx->pal_mode)
|
2355 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2356 | 8bb6e981 | aurel32 | if (ra != 31) { |
2357 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
2358 | 8bb6e981 | aurel32 | if (rb != 31) |
2359 | 8bb6e981 | aurel32 | tcg_gen_addi_i64(addr, cpu_ir[rb], disp12); |
2360 | 8bb6e981 | aurel32 | else
|
2361 | 8bb6e981 | aurel32 | tcg_gen_movi_i64(addr, disp12); |
2362 | 8bb6e981 | aurel32 | switch ((insn >> 12) & 0xF) { |
2363 | 8bb6e981 | aurel32 | case 0x0: |
2364 | b5d51029 | aurel32 | /* Longword physical access (hw_ldl/p) */
|
2365 | a7812ae4 | pbrook | gen_helper_ldl_raw(cpu_ir[ra], addr); |
2366 | 8bb6e981 | aurel32 | break;
|
2367 | 8bb6e981 | aurel32 | case 0x1: |
2368 | b5d51029 | aurel32 | /* Quadword physical access (hw_ldq/p) */
|
2369 | a7812ae4 | pbrook | gen_helper_ldq_raw(cpu_ir[ra], addr); |
2370 | 8bb6e981 | aurel32 | break;
|
2371 | 8bb6e981 | aurel32 | case 0x2: |
2372 | b5d51029 | aurel32 | /* Longword physical access with lock (hw_ldl_l/p) */
|
2373 | a7812ae4 | pbrook | gen_helper_ldl_l_raw(cpu_ir[ra], addr); |
2374 | 8bb6e981 | aurel32 | break;
|
2375 | 8bb6e981 | aurel32 | case 0x3: |
2376 | b5d51029 | aurel32 | /* Quadword physical access with lock (hw_ldq_l/p) */
|
2377 | a7812ae4 | pbrook | gen_helper_ldq_l_raw(cpu_ir[ra], addr); |
2378 | 8bb6e981 | aurel32 | break;
|
2379 | 8bb6e981 | aurel32 | case 0x4: |
2380 | b5d51029 | aurel32 | /* Longword virtual PTE fetch (hw_ldl/v) */
|
2381 | b5d51029 | aurel32 | tcg_gen_qemu_ld32s(cpu_ir[ra], addr, 0);
|
2382 | 8bb6e981 | aurel32 | break;
|
2383 | 8bb6e981 | aurel32 | case 0x5: |
2384 | b5d51029 | aurel32 | /* Quadword virtual PTE fetch (hw_ldq/v) */
|
2385 | b5d51029 | aurel32 | tcg_gen_qemu_ld64(cpu_ir[ra], addr, 0);
|
2386 | 8bb6e981 | aurel32 | break;
|
2387 | 8bb6e981 | aurel32 | case 0x6: |
2388 | 8bb6e981 | aurel32 | /* Incpu_ir[ra]id */
|
2389 | b5d51029 | aurel32 | goto invalid_opc;
|
2390 | 8bb6e981 | aurel32 | case 0x7: |
2391 | 8bb6e981 | aurel32 | /* Incpu_ir[ra]id */
|
2392 | b5d51029 | aurel32 | goto invalid_opc;
|
2393 | 8bb6e981 | aurel32 | case 0x8: |
2394 | b5d51029 | aurel32 | /* Longword virtual access (hw_ldl) */
|
2395 | a7812ae4 | pbrook | gen_helper_st_virt_to_phys(addr, addr); |
2396 | a7812ae4 | pbrook | gen_helper_ldl_raw(cpu_ir[ra], addr); |
2397 | 8bb6e981 | aurel32 | break;
|
2398 | 8bb6e981 | aurel32 | case 0x9: |
2399 | b5d51029 | aurel32 | /* Quadword virtual access (hw_ldq) */
|
2400 | a7812ae4 | pbrook | gen_helper_st_virt_to_phys(addr, addr); |
2401 | a7812ae4 | pbrook | gen_helper_ldq_raw(cpu_ir[ra], addr); |
2402 | 8bb6e981 | aurel32 | break;
|
2403 | 8bb6e981 | aurel32 | case 0xA: |
2404 | b5d51029 | aurel32 | /* Longword virtual access with protection check (hw_ldl/w) */
|
2405 | b5d51029 | aurel32 | tcg_gen_qemu_ld32s(cpu_ir[ra], addr, 0);
|
2406 | 8bb6e981 | aurel32 | break;
|
2407 | 8bb6e981 | aurel32 | case 0xB: |
2408 | b5d51029 | aurel32 | /* Quadword virtual access with protection check (hw_ldq/w) */
|
2409 | b5d51029 | aurel32 | tcg_gen_qemu_ld64(cpu_ir[ra], addr, 0);
|
2410 | 8bb6e981 | aurel32 | break;
|
2411 | 8bb6e981 | aurel32 | case 0xC: |
2412 | b5d51029 | aurel32 | /* Longword virtual access with alt access mode (hw_ldl/a)*/
|
2413 | a7812ae4 | pbrook | gen_helper_set_alt_mode(); |
2414 | a7812ae4 | pbrook | gen_helper_st_virt_to_phys(addr, addr); |
2415 | a7812ae4 | pbrook | gen_helper_ldl_raw(cpu_ir[ra], addr); |
2416 | a7812ae4 | pbrook | gen_helper_restore_mode(); |
2417 | 8bb6e981 | aurel32 | break;
|
2418 | 8bb6e981 | aurel32 | case 0xD: |
2419 | b5d51029 | aurel32 | /* Quadword virtual access with alt access mode (hw_ldq/a) */
|
2420 | a7812ae4 | pbrook | gen_helper_set_alt_mode(); |
2421 | a7812ae4 | pbrook | gen_helper_st_virt_to_phys(addr, addr); |
2422 | a7812ae4 | pbrook | gen_helper_ldq_raw(cpu_ir[ra], addr); |
2423 | a7812ae4 | pbrook | gen_helper_restore_mode(); |
2424 | 8bb6e981 | aurel32 | break;
|
2425 | 8bb6e981 | aurel32 | case 0xE: |
2426 | 8bb6e981 | aurel32 | /* Longword virtual access with alternate access mode and
|
2427 | b5d51029 | aurel32 | * protection checks (hw_ldl/wa)
|
2428 | 8bb6e981 | aurel32 | */
|
2429 | a7812ae4 | pbrook | gen_helper_set_alt_mode(); |
2430 | a7812ae4 | pbrook | gen_helper_ldl_data(cpu_ir[ra], addr); |
2431 | a7812ae4 | pbrook | gen_helper_restore_mode(); |
2432 | 8bb6e981 | aurel32 | break;
|
2433 | 8bb6e981 | aurel32 | case 0xF: |
2434 | 8bb6e981 | aurel32 | /* Quadword virtual access with alternate access mode and
|
2435 | b5d51029 | aurel32 | * protection checks (hw_ldq/wa)
|
2436 | 8bb6e981 | aurel32 | */
|
2437 | a7812ae4 | pbrook | gen_helper_set_alt_mode(); |
2438 | a7812ae4 | pbrook | gen_helper_ldq_data(cpu_ir[ra], addr); |
2439 | a7812ae4 | pbrook | gen_helper_restore_mode(); |
2440 | 8bb6e981 | aurel32 | break;
|
2441 | 8bb6e981 | aurel32 | } |
2442 | 8bb6e981 | aurel32 | tcg_temp_free(addr); |
2443 | 4c9649a9 | j_mayer | } |
2444 | 4c9649a9 | j_mayer | break;
|
2445 | 4c9649a9 | j_mayer | #endif
|
2446 | 4c9649a9 | j_mayer | case 0x1C: |
2447 | 4c9649a9 | j_mayer | switch (fn7) {
|
2448 | 4c9649a9 | j_mayer | case 0x00: |
2449 | 4c9649a9 | j_mayer | /* SEXTB */
|
2450 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_BWX))
|
2451 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2452 | ae8ecd42 | aurel32 | if (likely(rc != 31)) { |
2453 | ae8ecd42 | aurel32 | if (islit)
|
2454 | ae8ecd42 | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], (int64_t)((int8_t)lit)); |
2455 | ae8ecd42 | aurel32 | else
|
2456 | dfaa8583 | aurel32 | tcg_gen_ext8s_i64(cpu_ir[rc], cpu_ir[rb]); |
2457 | ae8ecd42 | aurel32 | } |
2458 | 4c9649a9 | j_mayer | break;
|
2459 | 4c9649a9 | j_mayer | case 0x01: |
2460 | 4c9649a9 | j_mayer | /* SEXTW */
|
2461 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_BWX))
|
2462 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2463 | ae8ecd42 | aurel32 | if (likely(rc != 31)) { |
2464 | ae8ecd42 | aurel32 | if (islit)
|
2465 | ae8ecd42 | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], (int64_t)((int16_t)lit)); |
2466 | ae8ecd42 | aurel32 | else
|
2467 | dfaa8583 | aurel32 | tcg_gen_ext16s_i64(cpu_ir[rc], cpu_ir[rb]); |
2468 | ae8ecd42 | aurel32 | } |
2469 | 4c9649a9 | j_mayer | break;
|
2470 | 4c9649a9 | j_mayer | case 0x30: |
2471 | 4c9649a9 | j_mayer | /* CTPOP */
|
2472 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_CIX))
|
2473 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2474 | ae8ecd42 | aurel32 | if (likely(rc != 31)) { |
2475 | ae8ecd42 | aurel32 | if (islit)
|
2476 | ae8ecd42 | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], ctpop64(lit)); |
2477 | ae8ecd42 | aurel32 | else
|
2478 | a7812ae4 | pbrook | gen_helper_ctpop(cpu_ir[rc], cpu_ir[rb]); |
2479 | ae8ecd42 | aurel32 | } |
2480 | 4c9649a9 | j_mayer | break;
|
2481 | 4c9649a9 | j_mayer | case 0x31: |
2482 | 4c9649a9 | j_mayer | /* PERR */
|
2483 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
2484 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2485 | 13e4df99 | Richard Henderson | gen_perr(ra, rb, rc, islit, lit); |
2486 | 4c9649a9 | j_mayer | break;
|
2487 | 4c9649a9 | j_mayer | case 0x32: |
2488 | 4c9649a9 | j_mayer | /* CTLZ */
|
2489 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_CIX))
|
2490 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2491 | ae8ecd42 | aurel32 | if (likely(rc != 31)) { |
2492 | ae8ecd42 | aurel32 | if (islit)
|
2493 | ae8ecd42 | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], clz64(lit)); |
2494 | ae8ecd42 | aurel32 | else
|
2495 | a7812ae4 | pbrook | gen_helper_ctlz(cpu_ir[rc], cpu_ir[rb]); |
2496 | ae8ecd42 | aurel32 | } |
2497 | 4c9649a9 | j_mayer | break;
|
2498 | 4c9649a9 | j_mayer | case 0x33: |
2499 | 4c9649a9 | j_mayer | /* CTTZ */
|
2500 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_CIX))
|
2501 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2502 | ae8ecd42 | aurel32 | if (likely(rc != 31)) { |
2503 | ae8ecd42 | aurel32 | if (islit)
|
2504 | ae8ecd42 | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], ctz64(lit)); |
2505 | ae8ecd42 | aurel32 | else
|
2506 | a7812ae4 | pbrook | gen_helper_cttz(cpu_ir[rc], cpu_ir[rb]); |
2507 | ae8ecd42 | aurel32 | } |
2508 | 4c9649a9 | j_mayer | break;
|
2509 | 4c9649a9 | j_mayer | case 0x34: |
2510 | 4c9649a9 | j_mayer | /* UNPKBW */
|
2511 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
2512 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2513 | 13e4df99 | Richard Henderson | if (real_islit || ra != 31) |
2514 | 13e4df99 | Richard Henderson | goto invalid_opc;
|
2515 | 13e4df99 | Richard Henderson | gen_unpkbw (rb, rc); |
2516 | 4c9649a9 | j_mayer | break;
|
2517 | 4c9649a9 | j_mayer | case 0x35: |
2518 | 13e4df99 | Richard Henderson | /* UNPKBL */
|
2519 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
2520 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2521 | 13e4df99 | Richard Henderson | if (real_islit || ra != 31) |
2522 | 13e4df99 | Richard Henderson | goto invalid_opc;
|
2523 | 13e4df99 | Richard Henderson | gen_unpkbl (rb, rc); |
2524 | 4c9649a9 | j_mayer | break;
|
2525 | 4c9649a9 | j_mayer | case 0x36: |
2526 | 4c9649a9 | j_mayer | /* PKWB */
|
2527 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
2528 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2529 | 13e4df99 | Richard Henderson | if (real_islit || ra != 31) |
2530 | 13e4df99 | Richard Henderson | goto invalid_opc;
|
2531 | 13e4df99 | Richard Henderson | gen_pkwb (rb, rc); |
2532 | 4c9649a9 | j_mayer | break;
|
2533 | 4c9649a9 | j_mayer | case 0x37: |
2534 | 4c9649a9 | j_mayer | /* PKLB */
|
2535 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
2536 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2537 | 13e4df99 | Richard Henderson | if (real_islit || ra != 31) |
2538 | 13e4df99 | Richard Henderson | goto invalid_opc;
|
2539 | 13e4df99 | Richard Henderson | gen_pklb (rb, rc); |
2540 | 4c9649a9 | j_mayer | break;
|
2541 | 4c9649a9 | j_mayer | case 0x38: |
2542 | 4c9649a9 | j_mayer | /* MINSB8 */
|
2543 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
2544 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2545 | 13e4df99 | Richard Henderson | gen_minsb8 (ra, rb, rc, islit, lit); |
2546 | 4c9649a9 | j_mayer | break;
|
2547 | 4c9649a9 | j_mayer | case 0x39: |
2548 | 4c9649a9 | j_mayer | /* MINSW4 */
|
2549 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
2550 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2551 | 13e4df99 | Richard Henderson | gen_minsw4 (ra, rb, rc, islit, lit); |
2552 | 4c9649a9 | j_mayer | break;
|
2553 | 4c9649a9 | j_mayer | case 0x3A: |
2554 | 4c9649a9 | j_mayer | /* MINUB8 */
|
2555 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
2556 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2557 | 13e4df99 | Richard Henderson | gen_minub8 (ra, rb, rc, islit, lit); |
2558 | 4c9649a9 | j_mayer | break;
|
2559 | 4c9649a9 | j_mayer | case 0x3B: |
2560 | 4c9649a9 | j_mayer | /* MINUW4 */
|
2561 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
2562 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2563 | 13e4df99 | Richard Henderson | gen_minuw4 (ra, rb, rc, islit, lit); |
2564 | 4c9649a9 | j_mayer | break;
|
2565 | 4c9649a9 | j_mayer | case 0x3C: |
2566 | 4c9649a9 | j_mayer | /* MAXUB8 */
|
2567 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
2568 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2569 | 13e4df99 | Richard Henderson | gen_maxub8 (ra, rb, rc, islit, lit); |
2570 | 4c9649a9 | j_mayer | break;
|
2571 | 4c9649a9 | j_mayer | case 0x3D: |
2572 | 4c9649a9 | j_mayer | /* MAXUW4 */
|
2573 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
2574 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2575 | 13e4df99 | Richard Henderson | gen_maxuw4 (ra, rb, rc, islit, lit); |
2576 | 4c9649a9 | j_mayer | break;
|
2577 | 4c9649a9 | j_mayer | case 0x3E: |
2578 | 4c9649a9 | j_mayer | /* MAXSB8 */
|
2579 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
2580 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2581 | 13e4df99 | Richard Henderson | gen_maxsb8 (ra, rb, rc, islit, lit); |
2582 | 4c9649a9 | j_mayer | break;
|
2583 | 4c9649a9 | j_mayer | case 0x3F: |
2584 | 4c9649a9 | j_mayer | /* MAXSW4 */
|
2585 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
2586 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2587 | 13e4df99 | Richard Henderson | gen_maxsw4 (ra, rb, rc, islit, lit); |
2588 | 4c9649a9 | j_mayer | break;
|
2589 | 4c9649a9 | j_mayer | case 0x70: |
2590 | 4c9649a9 | j_mayer | /* FTOIT */
|
2591 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_FIX))
|
2592 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2593 | f18cd223 | aurel32 | if (likely(rc != 31)) { |
2594 | f18cd223 | aurel32 | if (ra != 31) |
2595 | f18cd223 | aurel32 | tcg_gen_mov_i64(cpu_ir[rc], cpu_fir[ra]); |
2596 | f18cd223 | aurel32 | else
|
2597 | f18cd223 | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
2598 | f18cd223 | aurel32 | } |
2599 | 4c9649a9 | j_mayer | break;
|
2600 | 4c9649a9 | j_mayer | case 0x78: |
2601 | 4c9649a9 | j_mayer | /* FTOIS */
|
2602 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_FIX))
|
2603 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2604 | f18cd223 | aurel32 | if (rc != 31) { |
2605 | a7812ae4 | pbrook | TCGv_i32 tmp1 = tcg_temp_new_i32(); |
2606 | f18cd223 | aurel32 | if (ra != 31) |
2607 | a7812ae4 | pbrook | gen_helper_s_to_memory(tmp1, cpu_fir[ra]); |
2608 | f18cd223 | aurel32 | else {
|
2609 | f18cd223 | aurel32 | TCGv tmp2 = tcg_const_i64(0);
|
2610 | a7812ae4 | pbrook | gen_helper_s_to_memory(tmp1, tmp2); |
2611 | f18cd223 | aurel32 | tcg_temp_free(tmp2); |
2612 | f18cd223 | aurel32 | } |
2613 | f18cd223 | aurel32 | tcg_gen_ext_i32_i64(cpu_ir[rc], tmp1); |
2614 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp1); |
2615 | f18cd223 | aurel32 | } |
2616 | 4c9649a9 | j_mayer | break;
|
2617 | 4c9649a9 | j_mayer | default:
|
2618 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2619 | 4c9649a9 | j_mayer | } |
2620 | 4c9649a9 | j_mayer | break;
|
2621 | 4c9649a9 | j_mayer | case 0x1D: |
2622 | 4c9649a9 | j_mayer | /* HW_MTPR (PALcode) */
|
2623 | 4c9649a9 | j_mayer | #if defined (CONFIG_USER_ONLY)
|
2624 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2625 | 4c9649a9 | j_mayer | #else
|
2626 | 4c9649a9 | j_mayer | if (!ctx->pal_mode)
|
2627 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2628 | 8bb6e981 | aurel32 | else {
|
2629 | 8bb6e981 | aurel32 | TCGv tmp1 = tcg_const_i32(insn & 0xFF);
|
2630 | 8bb6e981 | aurel32 | if (ra != 31) |
2631 | a7812ae4 | pbrook | gen_helper_mtpr(tmp1, cpu_ir[ra]); |
2632 | 8bb6e981 | aurel32 | else {
|
2633 | 8bb6e981 | aurel32 | TCGv tmp2 = tcg_const_i64(0);
|
2634 | a7812ae4 | pbrook | gen_helper_mtpr(tmp1, tmp2); |
2635 | 8bb6e981 | aurel32 | tcg_temp_free(tmp2); |
2636 | 8bb6e981 | aurel32 | } |
2637 | 8bb6e981 | aurel32 | tcg_temp_free(tmp1); |
2638 | 8bb6e981 | aurel32 | ret = 2;
|
2639 | 8bb6e981 | aurel32 | } |
2640 | 4c9649a9 | j_mayer | break;
|
2641 | 4c9649a9 | j_mayer | #endif
|
2642 | 4c9649a9 | j_mayer | case 0x1E: |
2643 | 4c9649a9 | j_mayer | /* HW_REI (PALcode) */
|
2644 | 4c9649a9 | j_mayer | #if defined (CONFIG_USER_ONLY)
|
2645 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2646 | 4c9649a9 | j_mayer | #else
|
2647 | 4c9649a9 | j_mayer | if (!ctx->pal_mode)
|
2648 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2649 | 4c9649a9 | j_mayer | if (rb == 31) { |
2650 | 4c9649a9 | j_mayer | /* "Old" alpha */
|
2651 | a7812ae4 | pbrook | gen_helper_hw_rei(); |
2652 | 4c9649a9 | j_mayer | } else {
|
2653 | 8bb6e981 | aurel32 | TCGv tmp; |
2654 | 8bb6e981 | aurel32 | |
2655 | 8bb6e981 | aurel32 | if (ra != 31) { |
2656 | a7812ae4 | pbrook | tmp = tcg_temp_new(); |
2657 | 8bb6e981 | aurel32 | tcg_gen_addi_i64(tmp, cpu_ir[rb], (((int64_t)insn << 51) >> 51)); |
2658 | 8bb6e981 | aurel32 | } else
|
2659 | 8bb6e981 | aurel32 | tmp = tcg_const_i64(((int64_t)insn << 51) >> 51); |
2660 | a7812ae4 | pbrook | gen_helper_hw_ret(tmp); |
2661 | 8bb6e981 | aurel32 | tcg_temp_free(tmp); |
2662 | 4c9649a9 | j_mayer | } |
2663 | 4c9649a9 | j_mayer | ret = 2;
|
2664 | 4c9649a9 | j_mayer | break;
|
2665 | 4c9649a9 | j_mayer | #endif
|
2666 | 4c9649a9 | j_mayer | case 0x1F: |
2667 | 4c9649a9 | j_mayer | /* HW_ST (PALcode) */
|
2668 | 4c9649a9 | j_mayer | #if defined (CONFIG_USER_ONLY)
|
2669 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2670 | 4c9649a9 | j_mayer | #else
|
2671 | 4c9649a9 | j_mayer | if (!ctx->pal_mode)
|
2672 | 4c9649a9 | j_mayer | goto invalid_opc;
|
2673 | 8bb6e981 | aurel32 | else {
|
2674 | 8bb6e981 | aurel32 | TCGv addr, val; |
2675 | a7812ae4 | pbrook | addr = tcg_temp_new(); |
2676 | 8bb6e981 | aurel32 | if (rb != 31) |
2677 | 8bb6e981 | aurel32 | tcg_gen_addi_i64(addr, cpu_ir[rb], disp12); |
2678 | 8bb6e981 | aurel32 | else
|
2679 | 8bb6e981 | aurel32 | tcg_gen_movi_i64(addr, disp12); |
2680 | 8bb6e981 | aurel32 | if (ra != 31) |
2681 | 8bb6e981 | aurel32 | val = cpu_ir[ra]; |
2682 | 8bb6e981 | aurel32 | else {
|
2683 | a7812ae4 | pbrook | val = tcg_temp_new(); |
2684 | 8bb6e981 | aurel32 | tcg_gen_movi_i64(val, 0);
|
2685 | 8bb6e981 | aurel32 | } |
2686 | 8bb6e981 | aurel32 | switch ((insn >> 12) & 0xF) { |
2687 | 8bb6e981 | aurel32 | case 0x0: |
2688 | 8bb6e981 | aurel32 | /* Longword physical access */
|
2689 | a7812ae4 | pbrook | gen_helper_stl_raw(val, addr); |
2690 | 8bb6e981 | aurel32 | break;
|
2691 | 8bb6e981 | aurel32 | case 0x1: |
2692 | 8bb6e981 | aurel32 | /* Quadword physical access */
|
2693 | a7812ae4 | pbrook | gen_helper_stq_raw(val, addr); |
2694 | 8bb6e981 | aurel32 | break;
|
2695 | 8bb6e981 | aurel32 | case 0x2: |
2696 | 8bb6e981 | aurel32 | /* Longword physical access with lock */
|
2697 | a7812ae4 | pbrook | gen_helper_stl_c_raw(val, val, addr); |
2698 | 8bb6e981 | aurel32 | break;
|
2699 | 8bb6e981 | aurel32 | case 0x3: |
2700 | 8bb6e981 | aurel32 | /* Quadword physical access with lock */
|
2701 | a7812ae4 | pbrook | gen_helper_stq_c_raw(val, val, addr); |
2702 | 8bb6e981 | aurel32 | break;
|
2703 | 8bb6e981 | aurel32 | case 0x4: |
2704 | 8bb6e981 | aurel32 | /* Longword virtual access */
|
2705 | a7812ae4 | pbrook | gen_helper_st_virt_to_phys(addr, addr); |
2706 | a7812ae4 | pbrook | gen_helper_stl_raw(val, addr); |
2707 | 8bb6e981 | aurel32 | break;
|
2708 | 8bb6e981 | aurel32 | case 0x5: |
2709 | 8bb6e981 | aurel32 | /* Quadword virtual access */
|
2710 | a7812ae4 | pbrook | gen_helper_st_virt_to_phys(addr, addr); |
2711 | a7812ae4 | pbrook | gen_helper_stq_raw(val, addr); |
2712 | 8bb6e981 | aurel32 | break;
|
2713 | 8bb6e981 | aurel32 | case 0x6: |
2714 | 8bb6e981 | aurel32 | /* Invalid */
|
2715 | 8bb6e981 | aurel32 | goto invalid_opc;
|
2716 | 8bb6e981 | aurel32 | case 0x7: |
2717 | 8bb6e981 | aurel32 | /* Invalid */
|
2718 | 8bb6e981 | aurel32 | goto invalid_opc;
|
2719 | 8bb6e981 | aurel32 | case 0x8: |
2720 | 8bb6e981 | aurel32 | /* Invalid */
|
2721 | 8bb6e981 | aurel32 | goto invalid_opc;
|
2722 | 8bb6e981 | aurel32 | case 0x9: |
2723 | 8bb6e981 | aurel32 | /* Invalid */
|
2724 | 8bb6e981 | aurel32 | goto invalid_opc;
|
2725 | 8bb6e981 | aurel32 | case 0xA: |
2726 | 8bb6e981 | aurel32 | /* Invalid */
|
2727 | 8bb6e981 | aurel32 | goto invalid_opc;
|
2728 | 8bb6e981 | aurel32 | case 0xB: |
2729 | 8bb6e981 | aurel32 | /* Invalid */
|
2730 | 8bb6e981 | aurel32 | goto invalid_opc;
|
2731 | 8bb6e981 | aurel32 | case 0xC: |
2732 | 8bb6e981 | aurel32 | /* Longword virtual access with alternate access mode */
|
2733 | a7812ae4 | pbrook | gen_helper_set_alt_mode(); |
2734 | a7812ae4 | pbrook | gen_helper_st_virt_to_phys(addr, addr); |
2735 | a7812ae4 | pbrook | gen_helper_stl_raw(val, addr); |
2736 | a7812ae4 | pbrook | gen_helper_restore_mode(); |
2737 | 8bb6e981 | aurel32 | break;
|
2738 | 8bb6e981 | aurel32 | case 0xD: |
2739 | 8bb6e981 | aurel32 | /* Quadword virtual access with alternate access mode */
|
2740 | a7812ae4 | pbrook | gen_helper_set_alt_mode(); |
2741 | a7812ae4 | pbrook | gen_helper_st_virt_to_phys(addr, addr); |
2742 | a7812ae4 | pbrook | gen_helper_stl_raw(val, addr); |
2743 | a7812ae4 | pbrook | gen_helper_restore_mode(); |
2744 | 8bb6e981 | aurel32 | break;
|
2745 | 8bb6e981 | aurel32 | case 0xE: |
2746 | 8bb6e981 | aurel32 | /* Invalid */
|
2747 | 8bb6e981 | aurel32 | goto invalid_opc;
|
2748 | 8bb6e981 | aurel32 | case 0xF: |
2749 | 8bb6e981 | aurel32 | /* Invalid */
|
2750 | 8bb6e981 | aurel32 | goto invalid_opc;
|
2751 | 8bb6e981 | aurel32 | } |
2752 | 45d46ce8 | aurel32 | if (ra == 31) |
2753 | 8bb6e981 | aurel32 | tcg_temp_free(val); |
2754 | 8bb6e981 | aurel32 | tcg_temp_free(addr); |
2755 | 4c9649a9 | j_mayer | } |
2756 | 4c9649a9 | j_mayer | break;
|
2757 | 4c9649a9 | j_mayer | #endif
|
2758 | 4c9649a9 | j_mayer | case 0x20: |
2759 | 4c9649a9 | j_mayer | /* LDF */
|
2760 | f18cd223 | aurel32 | gen_load_mem(ctx, &gen_qemu_ldf, ra, rb, disp16, 1, 0); |
2761 | 4c9649a9 | j_mayer | break;
|
2762 | 4c9649a9 | j_mayer | case 0x21: |
2763 | 4c9649a9 | j_mayer | /* LDG */
|
2764 | f18cd223 | aurel32 | gen_load_mem(ctx, &gen_qemu_ldg, ra, rb, disp16, 1, 0); |
2765 | 4c9649a9 | j_mayer | break;
|
2766 | 4c9649a9 | j_mayer | case 0x22: |
2767 | 4c9649a9 | j_mayer | /* LDS */
|
2768 | f18cd223 | aurel32 | gen_load_mem(ctx, &gen_qemu_lds, ra, rb, disp16, 1, 0); |
2769 | 4c9649a9 | j_mayer | break;
|
2770 | 4c9649a9 | j_mayer | case 0x23: |
2771 | 4c9649a9 | j_mayer | /* LDT */
|
2772 | f18cd223 | aurel32 | gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 1, 0); |
2773 | 4c9649a9 | j_mayer | break;
|
2774 | 4c9649a9 | j_mayer | case 0x24: |
2775 | 4c9649a9 | j_mayer | /* STF */
|
2776 | 57a92c8e | aurel32 | gen_store_mem(ctx, &gen_qemu_stf, ra, rb, disp16, 1, 0, 0); |
2777 | 4c9649a9 | j_mayer | break;
|
2778 | 4c9649a9 | j_mayer | case 0x25: |
2779 | 4c9649a9 | j_mayer | /* STG */
|
2780 | 57a92c8e | aurel32 | gen_store_mem(ctx, &gen_qemu_stg, ra, rb, disp16, 1, 0, 0); |
2781 | 4c9649a9 | j_mayer | break;
|
2782 | 4c9649a9 | j_mayer | case 0x26: |
2783 | 4c9649a9 | j_mayer | /* STS */
|
2784 | 57a92c8e | aurel32 | gen_store_mem(ctx, &gen_qemu_sts, ra, rb, disp16, 1, 0, 0); |
2785 | 4c9649a9 | j_mayer | break;
|
2786 | 4c9649a9 | j_mayer | case 0x27: |
2787 | 4c9649a9 | j_mayer | /* STT */
|
2788 | 57a92c8e | aurel32 | gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 1, 0, 0); |
2789 | 4c9649a9 | j_mayer | break;
|
2790 | 4c9649a9 | j_mayer | case 0x28: |
2791 | 4c9649a9 | j_mayer | /* LDL */
|
2792 | f18cd223 | aurel32 | gen_load_mem(ctx, &tcg_gen_qemu_ld32s, ra, rb, disp16, 0, 0); |
2793 | 4c9649a9 | j_mayer | break;
|
2794 | 4c9649a9 | j_mayer | case 0x29: |
2795 | 4c9649a9 | j_mayer | /* LDQ */
|
2796 | f18cd223 | aurel32 | gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 0); |
2797 | 4c9649a9 | j_mayer | break;
|
2798 | 4c9649a9 | j_mayer | case 0x2A: |
2799 | 4c9649a9 | j_mayer | /* LDL_L */
|
2800 | f4ed8679 | aurel32 | gen_load_mem(ctx, &gen_qemu_ldl_l, ra, rb, disp16, 0, 0); |
2801 | 4c9649a9 | j_mayer | break;
|
2802 | 4c9649a9 | j_mayer | case 0x2B: |
2803 | 4c9649a9 | j_mayer | /* LDQ_L */
|
2804 | f4ed8679 | aurel32 | gen_load_mem(ctx, &gen_qemu_ldq_l, ra, rb, disp16, 0, 0); |
2805 | 4c9649a9 | j_mayer | break;
|
2806 | 4c9649a9 | j_mayer | case 0x2C: |
2807 | 4c9649a9 | j_mayer | /* STL */
|
2808 | 57a92c8e | aurel32 | gen_store_mem(ctx, &tcg_gen_qemu_st32, ra, rb, disp16, 0, 0, 0); |
2809 | 4c9649a9 | j_mayer | break;
|
2810 | 4c9649a9 | j_mayer | case 0x2D: |
2811 | 4c9649a9 | j_mayer | /* STQ */
|
2812 | 57a92c8e | aurel32 | gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 0, 0); |
2813 | 4c9649a9 | j_mayer | break;
|
2814 | 4c9649a9 | j_mayer | case 0x2E: |
2815 | 4c9649a9 | j_mayer | /* STL_C */
|
2816 | 57a92c8e | aurel32 | gen_store_mem(ctx, &gen_qemu_stl_c, ra, rb, disp16, 0, 0, 1); |
2817 | 4c9649a9 | j_mayer | break;
|
2818 | 4c9649a9 | j_mayer | case 0x2F: |
2819 | 4c9649a9 | j_mayer | /* STQ_C */
|
2820 | 57a92c8e | aurel32 | gen_store_mem(ctx, &gen_qemu_stq_c, ra, rb, disp16, 0, 0, 1); |
2821 | 4c9649a9 | j_mayer | break;
|
2822 | 4c9649a9 | j_mayer | case 0x30: |
2823 | 4c9649a9 | j_mayer | /* BR */
|
2824 | 3761035f | aurel32 | if (ra != 31) |
2825 | 3761035f | aurel32 | tcg_gen_movi_i64(cpu_ir[ra], ctx->pc); |
2826 | 3761035f | aurel32 | tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp21 << 2));
|
2827 | 4c9649a9 | j_mayer | ret = 1;
|
2828 | 4c9649a9 | j_mayer | break;
|
2829 | a7812ae4 | pbrook | case 0x31: /* FBEQ */ |
2830 | dbb30fe6 | Richard Henderson | gen_fbcond(ctx, TCG_COND_EQ, ra, disp21); |
2831 | dbb30fe6 | Richard Henderson | ret = 1;
|
2832 | dbb30fe6 | Richard Henderson | break;
|
2833 | a7812ae4 | pbrook | case 0x32: /* FBLT */ |
2834 | dbb30fe6 | Richard Henderson | gen_fbcond(ctx, TCG_COND_LT, ra, disp21); |
2835 | dbb30fe6 | Richard Henderson | ret = 1;
|
2836 | dbb30fe6 | Richard Henderson | break;
|
2837 | a7812ae4 | pbrook | case 0x33: /* FBLE */ |
2838 | dbb30fe6 | Richard Henderson | gen_fbcond(ctx, TCG_COND_LE, ra, disp21); |
2839 | 4c9649a9 | j_mayer | ret = 1;
|
2840 | 4c9649a9 | j_mayer | break;
|
2841 | 4c9649a9 | j_mayer | case 0x34: |
2842 | 4c9649a9 | j_mayer | /* BSR */
|
2843 | 3761035f | aurel32 | if (ra != 31) |
2844 | 3761035f | aurel32 | tcg_gen_movi_i64(cpu_ir[ra], ctx->pc); |
2845 | 3761035f | aurel32 | tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp21 << 2));
|
2846 | 4c9649a9 | j_mayer | ret = 1;
|
2847 | 4c9649a9 | j_mayer | break;
|
2848 | a7812ae4 | pbrook | case 0x35: /* FBNE */ |
2849 | dbb30fe6 | Richard Henderson | gen_fbcond(ctx, TCG_COND_NE, ra, disp21); |
2850 | dbb30fe6 | Richard Henderson | ret = 1;
|
2851 | dbb30fe6 | Richard Henderson | break;
|
2852 | a7812ae4 | pbrook | case 0x36: /* FBGE */ |
2853 | dbb30fe6 | Richard Henderson | gen_fbcond(ctx, TCG_COND_GE, ra, disp21); |
2854 | dbb30fe6 | Richard Henderson | ret = 1;
|
2855 | dbb30fe6 | Richard Henderson | break;
|
2856 | a7812ae4 | pbrook | case 0x37: /* FBGT */ |
2857 | dbb30fe6 | Richard Henderson | gen_fbcond(ctx, TCG_COND_GT, ra, disp21); |
2858 | 4c9649a9 | j_mayer | ret = 1;
|
2859 | 4c9649a9 | j_mayer | break;
|
2860 | 4c9649a9 | j_mayer | case 0x38: |
2861 | 4c9649a9 | j_mayer | /* BLBC */
|
2862 | a1516744 | aurel32 | gen_bcond(ctx, TCG_COND_EQ, ra, disp21, 1);
|
2863 | 4c9649a9 | j_mayer | ret = 1;
|
2864 | 4c9649a9 | j_mayer | break;
|
2865 | 4c9649a9 | j_mayer | case 0x39: |
2866 | 4c9649a9 | j_mayer | /* BEQ */
|
2867 | a1516744 | aurel32 | gen_bcond(ctx, TCG_COND_EQ, ra, disp21, 0);
|
2868 | 4c9649a9 | j_mayer | ret = 1;
|
2869 | 4c9649a9 | j_mayer | break;
|
2870 | 4c9649a9 | j_mayer | case 0x3A: |
2871 | 4c9649a9 | j_mayer | /* BLT */
|
2872 | a1516744 | aurel32 | gen_bcond(ctx, TCG_COND_LT, ra, disp21, 0);
|
2873 | 4c9649a9 | j_mayer | ret = 1;
|
2874 | 4c9649a9 | j_mayer | break;
|
2875 | 4c9649a9 | j_mayer | case 0x3B: |
2876 | 4c9649a9 | j_mayer | /* BLE */
|
2877 | a1516744 | aurel32 | gen_bcond(ctx, TCG_COND_LE, ra, disp21, 0);
|
2878 | 4c9649a9 | j_mayer | ret = 1;
|
2879 | 4c9649a9 | j_mayer | break;
|
2880 | 4c9649a9 | j_mayer | case 0x3C: |
2881 | 4c9649a9 | j_mayer | /* BLBS */
|
2882 | a1516744 | aurel32 | gen_bcond(ctx, TCG_COND_NE, ra, disp21, 1);
|
2883 | 4c9649a9 | j_mayer | ret = 1;
|
2884 | 4c9649a9 | j_mayer | break;
|
2885 | 4c9649a9 | j_mayer | case 0x3D: |
2886 | 4c9649a9 | j_mayer | /* BNE */
|
2887 | a1516744 | aurel32 | gen_bcond(ctx, TCG_COND_NE, ra, disp21, 0);
|
2888 | 4c9649a9 | j_mayer | ret = 1;
|
2889 | 4c9649a9 | j_mayer | break;
|
2890 | 4c9649a9 | j_mayer | case 0x3E: |
2891 | 4c9649a9 | j_mayer | /* BGE */
|
2892 | a1516744 | aurel32 | gen_bcond(ctx, TCG_COND_GE, ra, disp21, 0);
|
2893 | 4c9649a9 | j_mayer | ret = 1;
|
2894 | 4c9649a9 | j_mayer | break;
|
2895 | 4c9649a9 | j_mayer | case 0x3F: |
2896 | 4c9649a9 | j_mayer | /* BGT */
|
2897 | a1516744 | aurel32 | gen_bcond(ctx, TCG_COND_GT, ra, disp21, 0);
|
2898 | 4c9649a9 | j_mayer | ret = 1;
|
2899 | 4c9649a9 | j_mayer | break;
|
2900 | 4c9649a9 | j_mayer | invalid_opc:
|
2901 | 4c9649a9 | j_mayer | gen_invalid(ctx); |
2902 | 4c9649a9 | j_mayer | ret = 3;
|
2903 | 4c9649a9 | j_mayer | break;
|
2904 | 4c9649a9 | j_mayer | } |
2905 | 4c9649a9 | j_mayer | |
2906 | 4c9649a9 | j_mayer | return ret;
|
2907 | 4c9649a9 | j_mayer | } |
2908 | 4c9649a9 | j_mayer | |
2909 | 636aa200 | Blue Swirl | static inline void gen_intermediate_code_internal(CPUState *env, |
2910 | 636aa200 | Blue Swirl | TranslationBlock *tb, |
2911 | 636aa200 | Blue Swirl | int search_pc)
|
2912 | 4c9649a9 | j_mayer | { |
2913 | 4c9649a9 | j_mayer | DisasContext ctx, *ctxp = &ctx; |
2914 | 4c9649a9 | j_mayer | target_ulong pc_start; |
2915 | 4c9649a9 | j_mayer | uint32_t insn; |
2916 | 4c9649a9 | j_mayer | uint16_t *gen_opc_end; |
2917 | a1d1bb31 | aliguori | CPUBreakpoint *bp; |
2918 | 4c9649a9 | j_mayer | int j, lj = -1; |
2919 | 4c9649a9 | j_mayer | int ret;
|
2920 | 2e70f6ef | pbrook | int num_insns;
|
2921 | 2e70f6ef | pbrook | int max_insns;
|
2922 | 4c9649a9 | j_mayer | |
2923 | 4c9649a9 | j_mayer | pc_start = tb->pc; |
2924 | 4c9649a9 | j_mayer | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
2925 | 4c9649a9 | j_mayer | ctx.pc = pc_start; |
2926 | 4c9649a9 | j_mayer | ctx.amask = env->amask; |
2927 | 8579095b | aurel32 | ctx.env = env; |
2928 | 4c9649a9 | j_mayer | #if defined (CONFIG_USER_ONLY)
|
2929 | 4c9649a9 | j_mayer | ctx.mem_idx = 0;
|
2930 | 4c9649a9 | j_mayer | #else
|
2931 | 4c9649a9 | j_mayer | ctx.mem_idx = ((env->ps >> 3) & 3); |
2932 | 4c9649a9 | j_mayer | ctx.pal_mode = env->ipr[IPR_EXC_ADDR] & 1;
|
2933 | 4c9649a9 | j_mayer | #endif
|
2934 | f24518b5 | Richard Henderson | |
2935 | f24518b5 | Richard Henderson | /* ??? Every TB begins with unset rounding mode, to be initialized on
|
2936 | f24518b5 | Richard Henderson | the first fp insn of the TB. Alternately we could define a proper
|
2937 | f24518b5 | Richard Henderson | default for every TB (e.g. QUAL_RM_N or QUAL_RM_D) and make sure
|
2938 | f24518b5 | Richard Henderson | to reset the FP_STATUS to that default at the end of any TB that
|
2939 | f24518b5 | Richard Henderson | changes the default. We could even (gasp) dynamiclly figure out
|
2940 | f24518b5 | Richard Henderson | what default would be most efficient given the running program. */
|
2941 | f24518b5 | Richard Henderson | ctx.tb_rm = -1;
|
2942 | f24518b5 | Richard Henderson | /* Similarly for flush-to-zero. */
|
2943 | f24518b5 | Richard Henderson | ctx.tb_ftz = -1;
|
2944 | f24518b5 | Richard Henderson | |
2945 | 2e70f6ef | pbrook | num_insns = 0;
|
2946 | 2e70f6ef | pbrook | max_insns = tb->cflags & CF_COUNT_MASK; |
2947 | 2e70f6ef | pbrook | if (max_insns == 0) |
2948 | 2e70f6ef | pbrook | max_insns = CF_COUNT_MASK; |
2949 | 2e70f6ef | pbrook | |
2950 | 2e70f6ef | pbrook | gen_icount_start(); |
2951 | 4c9649a9 | j_mayer | for (ret = 0; ret == 0;) { |
2952 | 72cf2d4f | Blue Swirl | if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
|
2953 | 72cf2d4f | Blue Swirl | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
2954 | a1d1bb31 | aliguori | if (bp->pc == ctx.pc) {
|
2955 | 4c9649a9 | j_mayer | gen_excp(&ctx, EXCP_DEBUG, 0);
|
2956 | 4c9649a9 | j_mayer | break;
|
2957 | 4c9649a9 | j_mayer | } |
2958 | 4c9649a9 | j_mayer | } |
2959 | 4c9649a9 | j_mayer | } |
2960 | 4c9649a9 | j_mayer | if (search_pc) {
|
2961 | 4c9649a9 | j_mayer | j = gen_opc_ptr - gen_opc_buf; |
2962 | 4c9649a9 | j_mayer | if (lj < j) {
|
2963 | 4c9649a9 | j_mayer | lj++; |
2964 | 4c9649a9 | j_mayer | while (lj < j)
|
2965 | 4c9649a9 | j_mayer | gen_opc_instr_start[lj++] = 0;
|
2966 | 4c9649a9 | j_mayer | } |
2967 | ed1dda53 | aurel32 | gen_opc_pc[lj] = ctx.pc; |
2968 | ed1dda53 | aurel32 | gen_opc_instr_start[lj] = 1;
|
2969 | ed1dda53 | aurel32 | gen_opc_icount[lj] = num_insns; |
2970 | 4c9649a9 | j_mayer | } |
2971 | 2e70f6ef | pbrook | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
2972 | 2e70f6ef | pbrook | gen_io_start(); |
2973 | 4c9649a9 | j_mayer | insn = ldl_code(ctx.pc); |
2974 | 2e70f6ef | pbrook | num_insns++; |
2975 | c4b3be39 | Richard Henderson | |
2976 | c4b3be39 | Richard Henderson | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
|
2977 | c4b3be39 | Richard Henderson | tcg_gen_debug_insn_start(ctx.pc); |
2978 | c4b3be39 | Richard Henderson | } |
2979 | c4b3be39 | Richard Henderson | |
2980 | 4c9649a9 | j_mayer | ctx.pc += 4;
|
2981 | 4c9649a9 | j_mayer | ret = translate_one(ctxp, insn); |
2982 | 4c9649a9 | j_mayer | if (ret != 0) |
2983 | 4c9649a9 | j_mayer | break;
|
2984 | 4c9649a9 | j_mayer | /* if we reach a page boundary or are single stepping, stop
|
2985 | 4c9649a9 | j_mayer | * generation
|
2986 | 4c9649a9 | j_mayer | */
|
2987 | 19bf517b | aurel32 | if (env->singlestep_enabled) {
|
2988 | 19bf517b | aurel32 | gen_excp(&ctx, EXCP_DEBUG, 0);
|
2989 | 19bf517b | aurel32 | break;
|
2990 | 1b530a6d | aurel32 | } |
2991 | 19bf517b | aurel32 | |
2992 | 8fcc55f9 | aurel32 | if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) |
2993 | 8fcc55f9 | aurel32 | break;
|
2994 | 8fcc55f9 | aurel32 | |
2995 | 8fcc55f9 | aurel32 | if (gen_opc_ptr >= gen_opc_end)
|
2996 | 8fcc55f9 | aurel32 | break;
|
2997 | 8fcc55f9 | aurel32 | |
2998 | 8fcc55f9 | aurel32 | if (num_insns >= max_insns)
|
2999 | 8fcc55f9 | aurel32 | break;
|
3000 | 8fcc55f9 | aurel32 | |
3001 | 1b530a6d | aurel32 | if (singlestep) {
|
3002 | 1b530a6d | aurel32 | break;
|
3003 | 1b530a6d | aurel32 | } |
3004 | 4c9649a9 | j_mayer | } |
3005 | 4c9649a9 | j_mayer | if (ret != 1 && ret != 3) { |
3006 | 496cb5b9 | aurel32 | tcg_gen_movi_i64(cpu_pc, ctx.pc); |
3007 | 4c9649a9 | j_mayer | } |
3008 | 2e70f6ef | pbrook | if (tb->cflags & CF_LAST_IO)
|
3009 | 2e70f6ef | pbrook | gen_io_end(); |
3010 | 4c9649a9 | j_mayer | /* Generate the return instruction */
|
3011 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3012 | 2e70f6ef | pbrook | gen_icount_end(tb, num_insns); |
3013 | 4c9649a9 | j_mayer | *gen_opc_ptr = INDEX_op_end; |
3014 | 4c9649a9 | j_mayer | if (search_pc) {
|
3015 | 4c9649a9 | j_mayer | j = gen_opc_ptr - gen_opc_buf; |
3016 | 4c9649a9 | j_mayer | lj++; |
3017 | 4c9649a9 | j_mayer | while (lj <= j)
|
3018 | 4c9649a9 | j_mayer | gen_opc_instr_start[lj++] = 0;
|
3019 | 4c9649a9 | j_mayer | } else {
|
3020 | 4c9649a9 | j_mayer | tb->size = ctx.pc - pc_start; |
3021 | 2e70f6ef | pbrook | tb->icount = num_insns; |
3022 | 4c9649a9 | j_mayer | } |
3023 | 806991da | Richard Henderson | #ifdef DEBUG_DISAS
|
3024 | 8fec2b8c | aliguori | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
3025 | 93fcfe39 | aliguori | qemu_log("IN: %s\n", lookup_symbol(pc_start));
|
3026 | 93fcfe39 | aliguori | log_target_disas(pc_start, ctx.pc - pc_start, 1);
|
3027 | 93fcfe39 | aliguori | qemu_log("\n");
|
3028 | 4c9649a9 | j_mayer | } |
3029 | 4c9649a9 | j_mayer | #endif
|
3030 | 4c9649a9 | j_mayer | } |
3031 | 4c9649a9 | j_mayer | |
3032 | 2cfc5f17 | ths | void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb) |
3033 | 4c9649a9 | j_mayer | { |
3034 | 2cfc5f17 | ths | gen_intermediate_code_internal(env, tb, 0);
|
3035 | 4c9649a9 | j_mayer | } |
3036 | 4c9649a9 | j_mayer | |
3037 | 2cfc5f17 | ths | void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb) |
3038 | 4c9649a9 | j_mayer | { |
3039 | 2cfc5f17 | ths | gen_intermediate_code_internal(env, tb, 1);
|
3040 | 4c9649a9 | j_mayer | } |
3041 | 4c9649a9 | j_mayer | |
3042 | a964acc6 | Richard Henderson | struct cpu_def_t {
|
3043 | a964acc6 | Richard Henderson | const char *name; |
3044 | a964acc6 | Richard Henderson | int implver, amask;
|
3045 | a964acc6 | Richard Henderson | }; |
3046 | a964acc6 | Richard Henderson | |
3047 | a964acc6 | Richard Henderson | static const struct cpu_def_t cpu_defs[] = { |
3048 | a964acc6 | Richard Henderson | { "ev4", IMPLVER_2106x, 0 }, |
3049 | a964acc6 | Richard Henderson | { "ev5", IMPLVER_21164, 0 }, |
3050 | a964acc6 | Richard Henderson | { "ev56", IMPLVER_21164, AMASK_BWX },
|
3051 | a964acc6 | Richard Henderson | { "pca56", IMPLVER_21164, AMASK_BWX | AMASK_MVI },
|
3052 | a964acc6 | Richard Henderson | { "ev6", IMPLVER_21264, AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_TRAP },
|
3053 | a964acc6 | Richard Henderson | { "ev67", IMPLVER_21264, (AMASK_BWX | AMASK_FIX | AMASK_CIX
|
3054 | a964acc6 | Richard Henderson | | AMASK_MVI | AMASK_TRAP | AMASK_PREFETCH), }, |
3055 | a964acc6 | Richard Henderson | { "ev68", IMPLVER_21264, (AMASK_BWX | AMASK_FIX | AMASK_CIX
|
3056 | a964acc6 | Richard Henderson | | AMASK_MVI | AMASK_TRAP | AMASK_PREFETCH), }, |
3057 | a964acc6 | Richard Henderson | { "21064", IMPLVER_2106x, 0 }, |
3058 | a964acc6 | Richard Henderson | { "21164", IMPLVER_21164, 0 }, |
3059 | a964acc6 | Richard Henderson | { "21164a", IMPLVER_21164, AMASK_BWX },
|
3060 | a964acc6 | Richard Henderson | { "21164pc", IMPLVER_21164, AMASK_BWX | AMASK_MVI },
|
3061 | a964acc6 | Richard Henderson | { "21264", IMPLVER_21264, AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_TRAP },
|
3062 | a964acc6 | Richard Henderson | { "21264a", IMPLVER_21264, (AMASK_BWX | AMASK_FIX | AMASK_CIX
|
3063 | a964acc6 | Richard Henderson | | AMASK_MVI | AMASK_TRAP | AMASK_PREFETCH), } |
3064 | a964acc6 | Richard Henderson | }; |
3065 | a964acc6 | Richard Henderson | |
3066 | aaed909a | bellard | CPUAlphaState * cpu_alpha_init (const char *cpu_model) |
3067 | 4c9649a9 | j_mayer | { |
3068 | 4c9649a9 | j_mayer | CPUAlphaState *env; |
3069 | a964acc6 | Richard Henderson | int implver, amask, i, max;
|
3070 | 4c9649a9 | j_mayer | |
3071 | 4c9649a9 | j_mayer | env = qemu_mallocz(sizeof(CPUAlphaState));
|
3072 | 4c9649a9 | j_mayer | cpu_exec_init(env); |
3073 | 2e70f6ef | pbrook | alpha_translate_init(); |
3074 | 4c9649a9 | j_mayer | tlb_flush(env, 1);
|
3075 | a964acc6 | Richard Henderson | |
3076 | a964acc6 | Richard Henderson | /* Default to ev67; no reason not to emulate insns by default. */
|
3077 | a964acc6 | Richard Henderson | implver = IMPLVER_21264; |
3078 | a964acc6 | Richard Henderson | amask = (AMASK_BWX | AMASK_FIX | AMASK_CIX | AMASK_MVI |
3079 | a964acc6 | Richard Henderson | | AMASK_TRAP | AMASK_PREFETCH); |
3080 | a964acc6 | Richard Henderson | |
3081 | a964acc6 | Richard Henderson | max = ARRAY_SIZE(cpu_defs); |
3082 | a964acc6 | Richard Henderson | for (i = 0; i < max; i++) { |
3083 | a964acc6 | Richard Henderson | if (strcmp (cpu_model, cpu_defs[i].name) == 0) { |
3084 | a964acc6 | Richard Henderson | implver = cpu_defs[i].implver; |
3085 | a964acc6 | Richard Henderson | amask = cpu_defs[i].amask; |
3086 | a964acc6 | Richard Henderson | break;
|
3087 | a964acc6 | Richard Henderson | } |
3088 | a964acc6 | Richard Henderson | } |
3089 | a964acc6 | Richard Henderson | env->implver = implver; |
3090 | a964acc6 | Richard Henderson | env->amask = amask; |
3091 | a964acc6 | Richard Henderson | |
3092 | 4c9649a9 | j_mayer | env->ps = 0x1F00;
|
3093 | 4c9649a9 | j_mayer | #if defined (CONFIG_USER_ONLY)
|
3094 | 4c9649a9 | j_mayer | env->ps |= 1 << 3; |
3095 | 2edd07ef | Richard Henderson | cpu_alpha_store_fpcr(env, (FPCR_INVD | FPCR_DZED | FPCR_OVFD |
3096 | 2edd07ef | Richard Henderson | | FPCR_UNFD | FPCR_INED | FPCR_DNOD)); |
3097 | 6049f4f8 | Richard Henderson | #else
|
3098 | 4c9649a9 | j_mayer | pal_init(env); |
3099 | 6049f4f8 | Richard Henderson | #endif
|
3100 | dad081ee | Richard Henderson | |
3101 | 4c9649a9 | j_mayer | /* Initialize IPR */
|
3102 | dad081ee | Richard Henderson | #if defined (CONFIG_USER_ONLY)
|
3103 | dad081ee | Richard Henderson | env->ipr[IPR_EXC_ADDR] = 0;
|
3104 | dad081ee | Richard Henderson | env->ipr[IPR_EXC_SUM] = 0;
|
3105 | dad081ee | Richard Henderson | env->ipr[IPR_EXC_MASK] = 0;
|
3106 | dad081ee | Richard Henderson | #else
|
3107 | dad081ee | Richard Henderson | { |
3108 | dad081ee | Richard Henderson | uint64_t hwpcb; |
3109 | dad081ee | Richard Henderson | hwpcb = env->ipr[IPR_PCBB]; |
3110 | dad081ee | Richard Henderson | env->ipr[IPR_ASN] = 0;
|
3111 | dad081ee | Richard Henderson | env->ipr[IPR_ASTEN] = 0;
|
3112 | dad081ee | Richard Henderson | env->ipr[IPR_ASTSR] = 0;
|
3113 | dad081ee | Richard Henderson | env->ipr[IPR_DATFX] = 0;
|
3114 | dad081ee | Richard Henderson | /* XXX: fix this */
|
3115 | dad081ee | Richard Henderson | // env->ipr[IPR_ESP] = ldq_raw(hwpcb + 8);
|
3116 | dad081ee | Richard Henderson | // env->ipr[IPR_KSP] = ldq_raw(hwpcb + 0);
|
3117 | dad081ee | Richard Henderson | // env->ipr[IPR_SSP] = ldq_raw(hwpcb + 16);
|
3118 | dad081ee | Richard Henderson | // env->ipr[IPR_USP] = ldq_raw(hwpcb + 24);
|
3119 | dad081ee | Richard Henderson | env->ipr[IPR_FEN] = 0;
|
3120 | dad081ee | Richard Henderson | env->ipr[IPR_IPL] = 31;
|
3121 | dad081ee | Richard Henderson | env->ipr[IPR_MCES] = 0;
|
3122 | dad081ee | Richard Henderson | env->ipr[IPR_PERFMON] = 0; /* Implementation specific */ |
3123 | dad081ee | Richard Henderson | // env->ipr[IPR_PTBR] = ldq_raw(hwpcb + 32);
|
3124 | dad081ee | Richard Henderson | env->ipr[IPR_SISR] = 0;
|
3125 | dad081ee | Richard Henderson | env->ipr[IPR_VIRBND] = -1ULL;
|
3126 | dad081ee | Richard Henderson | } |
3127 | dad081ee | Richard Henderson | #endif
|
3128 | 4c9649a9 | j_mayer | |
3129 | 0bf46a40 | aliguori | qemu_init_vcpu(env); |
3130 | 4c9649a9 | j_mayer | return env;
|
3131 | 4c9649a9 | j_mayer | } |
3132 | aaed909a | bellard | |
3133 | d2856f1a | aurel32 | void gen_pc_load(CPUState *env, TranslationBlock *tb,
|
3134 | d2856f1a | aurel32 | unsigned long searched_pc, int pc_pos, void *puc) |
3135 | d2856f1a | aurel32 | { |
3136 | d2856f1a | aurel32 | env->pc = gen_opc_pc[pc_pos]; |
3137 | d2856f1a | aurel32 | } |