root / hw / mc146818rtc.c @ 663447d4
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/*
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* QEMU MC146818 RTC emulation
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "qemu-timer.h" |
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#include "sysemu.h" |
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#include "pc.h" |
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#include "apic.h" |
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#include "isa.h" |
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#include "mc146818rtc.h" |
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//#define DEBUG_CMOS
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//#define DEBUG_COALESCED
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#ifdef DEBUG_CMOS
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# define CMOS_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) |
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#else
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# define CMOS_DPRINTF(format, ...) do { } while (0) |
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#endif
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#ifdef DEBUG_COALESCED
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# define DPRINTF_C(format, ...) printf(format, ## __VA_ARGS__) |
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#else
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# define DPRINTF_C(format, ...) do { } while (0) |
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#endif
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|
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#define RTC_REINJECT_ON_ACK_COUNT 20 |
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#define RTC_SECONDS 0 |
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#define RTC_SECONDS_ALARM 1 |
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#define RTC_MINUTES 2 |
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#define RTC_MINUTES_ALARM 3 |
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#define RTC_HOURS 4 |
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#define RTC_HOURS_ALARM 5 |
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#define RTC_ALARM_DONT_CARE 0xC0 |
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|
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#define RTC_DAY_OF_WEEK 6 |
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#define RTC_DAY_OF_MONTH 7 |
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#define RTC_MONTH 8 |
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#define RTC_YEAR 9 |
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|
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#define RTC_REG_A 10 |
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#define RTC_REG_B 11 |
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#define RTC_REG_C 12 |
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#define RTC_REG_D 13 |
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|
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#define REG_A_UIP 0x80 |
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#define REG_B_SET 0x80 |
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#define REG_B_PIE 0x40 |
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#define REG_B_AIE 0x20 |
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#define REG_B_UIE 0x10 |
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#define REG_B_SQWE 0x08 |
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#define REG_B_DM 0x04 |
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#define REG_B_24H 0x02 |
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#define REG_C_UF 0x10 |
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#define REG_C_IRQF 0x80 |
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#define REG_C_PF 0x40 |
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#define REG_C_AF 0x20 |
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typedef struct RTCState { |
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ISADevice dev; |
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MemoryRegion io; |
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uint8_t cmos_data[128];
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uint8_t cmos_index; |
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struct tm current_tm;
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int32_t base_year; |
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qemu_irq irq; |
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qemu_irq sqw_irq; |
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int it_shift;
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/* periodic timer */
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QEMUTimer *periodic_timer; |
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int64_t next_periodic_time; |
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/* second update */
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int64_t next_second_time; |
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uint16_t irq_reinject_on_ack_count; |
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uint32_t irq_coalesced; |
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uint32_t period; |
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QEMUTimer *coalesced_timer; |
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QEMUTimer *second_timer; |
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QEMUTimer *second_timer2; |
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Notifier clock_reset_notifier; |
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} RTCState; |
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|
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static void rtc_set_time(RTCState *s); |
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static void rtc_copy_date(RTCState *s); |
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#ifdef TARGET_I386
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static void rtc_coalesced_timer_update(RTCState *s) |
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{ |
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if (s->irq_coalesced == 0) { |
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qemu_del_timer(s->coalesced_timer); |
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} else {
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/* divide each RTC interval to 2 - 8 smaller intervals */
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int c = MIN(s->irq_coalesced, 7) + 1; |
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int64_t next_clock = qemu_get_clock_ns(rtc_clock) + |
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muldiv64(s->period / c, get_ticks_per_sec(), 32768);
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qemu_mod_timer(s->coalesced_timer, next_clock); |
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} |
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} |
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static void rtc_coalesced_timer(void *opaque) |
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{ |
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RTCState *s = opaque; |
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if (s->irq_coalesced != 0) { |
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apic_reset_irq_delivered(); |
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s->cmos_data[RTC_REG_C] |= 0xc0;
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DPRINTF_C("cmos: injecting from timer\n");
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qemu_irq_raise(s->irq); |
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if (apic_get_irq_delivered()) {
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s->irq_coalesced--; |
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DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
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s->irq_coalesced); |
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} |
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} |
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rtc_coalesced_timer_update(s); |
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} |
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#endif
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static void rtc_timer_update(RTCState *s, int64_t current_time) |
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{ |
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int period_code, period;
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int64_t cur_clock, next_irq_clock; |
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period_code = s->cmos_data[RTC_REG_A] & 0x0f;
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if (period_code != 0 |
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&& ((s->cmos_data[RTC_REG_B] & REG_B_PIE) |
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|| ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) { |
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if (period_code <= 2) |
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period_code += 7;
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/* period in 32 Khz cycles */
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period = 1 << (period_code - 1); |
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#ifdef TARGET_I386
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if (period != s->period) {
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s->irq_coalesced = (s->irq_coalesced * s->period) / period; |
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DPRINTF_C("cmos: coalesced irqs scaled to %d\n", s->irq_coalesced);
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} |
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s->period = period; |
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#endif
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/* compute 32 khz clock */
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cur_clock = muldiv64(current_time, 32768, get_ticks_per_sec());
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next_irq_clock = (cur_clock & ~(period - 1)) + period;
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s->next_periodic_time = |
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muldiv64(next_irq_clock, get_ticks_per_sec(), 32768) + 1; |
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qemu_mod_timer(s->periodic_timer, s->next_periodic_time); |
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} else {
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#ifdef TARGET_I386
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s->irq_coalesced = 0;
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#endif
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qemu_del_timer(s->periodic_timer); |
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} |
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} |
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static void rtc_periodic_timer(void *opaque) |
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{ |
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RTCState *s = opaque; |
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rtc_timer_update(s, s->next_periodic_time); |
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s->cmos_data[RTC_REG_C] |= REG_C_PF; |
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if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
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s->cmos_data[RTC_REG_C] |= REG_C_IRQF; |
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#ifdef TARGET_I386
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if(rtc_td_hack) {
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if (s->irq_reinject_on_ack_count >= RTC_REINJECT_ON_ACK_COUNT)
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s->irq_reinject_on_ack_count = 0;
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apic_reset_irq_delivered(); |
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qemu_irq_raise(s->irq); |
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if (!apic_get_irq_delivered()) {
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s->irq_coalesced++; |
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rtc_coalesced_timer_update(s); |
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DPRINTF_C("cmos: coalesced irqs increased to %d\n",
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s->irq_coalesced); |
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} |
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} else
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#endif
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qemu_irq_raise(s->irq); |
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} |
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if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) {
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/* Not square wave at all but we don't want 2048Hz interrupts!
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Must be seen as a pulse. */
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qemu_irq_raise(s->sqw_irq); |
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} |
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} |
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static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) |
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{ |
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RTCState *s = opaque; |
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if ((addr & 1) == 0) { |
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s->cmos_index = data & 0x7f;
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} else {
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CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02x\n",
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s->cmos_index, data); |
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switch(s->cmos_index) {
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case RTC_SECONDS_ALARM:
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case RTC_MINUTES_ALARM:
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case RTC_HOURS_ALARM:
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s->cmos_data[s->cmos_index] = data; |
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break;
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case RTC_SECONDS:
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case RTC_MINUTES:
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case RTC_HOURS:
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case RTC_DAY_OF_WEEK:
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case RTC_DAY_OF_MONTH:
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case RTC_MONTH:
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case RTC_YEAR:
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s->cmos_data[s->cmos_index] = data; |
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/* if in set mode, do not update the time */
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if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
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rtc_set_time(s); |
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} |
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break;
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case RTC_REG_A:
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/* UIP bit is read only */
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s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) | |
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(s->cmos_data[RTC_REG_A] & REG_A_UIP); |
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rtc_timer_update(s, qemu_get_clock_ns(rtc_clock)); |
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break;
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case RTC_REG_B:
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if (data & REG_B_SET) {
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/* set mode: reset UIP mode */
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s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; |
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data &= ~REG_B_UIE; |
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} else {
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/* if disabling set mode, update the time */
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if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
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rtc_set_time(s); |
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} |
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} |
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if (((s->cmos_data[RTC_REG_B] ^ data) & (REG_B_DM | REG_B_24H)) &&
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!(data & REG_B_SET)) { |
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/* If the time format has changed and not in set mode,
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update the registers immediately. */
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s->cmos_data[RTC_REG_B] = data; |
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rtc_copy_date(s); |
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} else {
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s->cmos_data[RTC_REG_B] = data; |
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} |
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rtc_timer_update(s, qemu_get_clock_ns(rtc_clock)); |
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break;
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case RTC_REG_C:
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case RTC_REG_D:
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/* cannot write to them */
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break;
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default:
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s->cmos_data[s->cmos_index] = data; |
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break;
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} |
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} |
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} |
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static inline int rtc_to_bcd(RTCState *s, int a) |
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{ |
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if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
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return a;
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} else {
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return ((a / 10) << 4) | (a % 10); |
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} |
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} |
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|
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static inline int rtc_from_bcd(RTCState *s, int a) |
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{ |
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if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
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return a;
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} else {
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return ((a >> 4) * 10) + (a & 0x0f); |
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} |
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} |
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static void rtc_set_time(RTCState *s) |
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{ |
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struct tm *tm = &s->current_tm;
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tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]); |
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tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]); |
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tm->tm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
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if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) {
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tm->tm_hour %= 12;
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if (s->cmos_data[RTC_HOURS] & 0x80) { |
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tm->tm_hour += 12;
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} |
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} |
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tm->tm_wday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
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tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]); |
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tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
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tm->tm_year = rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year - 1900;
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rtc_change_mon_event(tm); |
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} |
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|
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static void rtc_copy_date(RTCState *s) |
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{ |
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const struct tm *tm = &s->current_tm; |
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int year;
|
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|
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s->cmos_data[RTC_SECONDS] = rtc_to_bcd(s, tm->tm_sec); |
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s->cmos_data[RTC_MINUTES] = rtc_to_bcd(s, tm->tm_min); |
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if (s->cmos_data[RTC_REG_B] & REG_B_24H) {
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/* 24 hour format */
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s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour); |
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} else {
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/* 12 hour format */
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int h = (tm->tm_hour % 12) ? tm->tm_hour % 12 : 12; |
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s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, h); |
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if (tm->tm_hour >= 12) |
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s->cmos_data[RTC_HOURS] |= 0x80;
|
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} |
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s->cmos_data[RTC_DAY_OF_WEEK] = rtc_to_bcd(s, tm->tm_wday + 1);
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s->cmos_data[RTC_DAY_OF_MONTH] = rtc_to_bcd(s, tm->tm_mday); |
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s->cmos_data[RTC_MONTH] = rtc_to_bcd(s, tm->tm_mon + 1);
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year = (tm->tm_year - s->base_year) % 100;
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if (year < 0) |
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year += 100;
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s->cmos_data[RTC_YEAR] = rtc_to_bcd(s, year); |
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} |
339 |
|
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/* month is between 0 and 11. */
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static int get_days_in_month(int month, int year) |
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{ |
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static const int days_tab[12] = { |
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31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 |
345 |
}; |
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int d;
|
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if ((unsigned )month >= 12) |
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return 31; |
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d = days_tab[month]; |
350 |
if (month == 1) { |
351 |
if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0)) |
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d++; |
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} |
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return d;
|
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} |
356 |
|
357 |
/* update 'tm' to the next second */
|
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static void rtc_next_second(struct tm *tm) |
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{ |
360 |
int days_in_month;
|
361 |
|
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tm->tm_sec++; |
363 |
if ((unsigned)tm->tm_sec >= 60) { |
364 |
tm->tm_sec = 0;
|
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tm->tm_min++; |
366 |
if ((unsigned)tm->tm_min >= 60) { |
367 |
tm->tm_min = 0;
|
368 |
tm->tm_hour++; |
369 |
if ((unsigned)tm->tm_hour >= 24) { |
370 |
tm->tm_hour = 0;
|
371 |
/* next day */
|
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tm->tm_wday++; |
373 |
if ((unsigned)tm->tm_wday >= 7) |
374 |
tm->tm_wday = 0;
|
375 |
days_in_month = get_days_in_month(tm->tm_mon, |
376 |
tm->tm_year + 1900);
|
377 |
tm->tm_mday++; |
378 |
if (tm->tm_mday < 1) { |
379 |
tm->tm_mday = 1;
|
380 |
} else if (tm->tm_mday > days_in_month) { |
381 |
tm->tm_mday = 1;
|
382 |
tm->tm_mon++; |
383 |
if (tm->tm_mon >= 12) { |
384 |
tm->tm_mon = 0;
|
385 |
tm->tm_year++; |
386 |
} |
387 |
} |
388 |
} |
389 |
} |
390 |
} |
391 |
} |
392 |
|
393 |
|
394 |
static void rtc_update_second(void *opaque) |
395 |
{ |
396 |
RTCState *s = opaque; |
397 |
int64_t delay; |
398 |
|
399 |
/* if the oscillator is not in normal operation, we do not update */
|
400 |
if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) { |
401 |
s->next_second_time += get_ticks_per_sec(); |
402 |
qemu_mod_timer(s->second_timer, s->next_second_time); |
403 |
} else {
|
404 |
rtc_next_second(&s->current_tm); |
405 |
|
406 |
if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
|
407 |
/* update in progress bit */
|
408 |
s->cmos_data[RTC_REG_A] |= REG_A_UIP; |
409 |
} |
410 |
/* should be 244 us = 8 / 32768 seconds, but currently the
|
411 |
timers do not have the necessary resolution. */
|
412 |
delay = (get_ticks_per_sec() * 1) / 100; |
413 |
if (delay < 1) |
414 |
delay = 1;
|
415 |
qemu_mod_timer(s->second_timer2, |
416 |
s->next_second_time + delay); |
417 |
} |
418 |
} |
419 |
|
420 |
static void rtc_update_second2(void *opaque) |
421 |
{ |
422 |
RTCState *s = opaque; |
423 |
|
424 |
if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
|
425 |
rtc_copy_date(s); |
426 |
} |
427 |
|
428 |
/* check alarm */
|
429 |
if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 || |
430 |
rtc_from_bcd(s, s->cmos_data[RTC_SECONDS_ALARM]) == s->current_tm.tm_sec) && |
431 |
((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 || |
432 |
rtc_from_bcd(s, s->cmos_data[RTC_MINUTES_ALARM]) == s->current_tm.tm_min) && |
433 |
((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 || |
434 |
rtc_from_bcd(s, s->cmos_data[RTC_HOURS_ALARM]) == s->current_tm.tm_hour)) { |
435 |
|
436 |
s->cmos_data[RTC_REG_C] |= REG_C_AF; |
437 |
if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
|
438 |
qemu_irq_raise(s->irq); |
439 |
s->cmos_data[RTC_REG_C] |= REG_C_IRQF; |
440 |
} |
441 |
} |
442 |
|
443 |
/* update ended interrupt */
|
444 |
s->cmos_data[RTC_REG_C] |= REG_C_UF; |
445 |
if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
|
446 |
s->cmos_data[RTC_REG_C] |= REG_C_IRQF; |
447 |
qemu_irq_raise(s->irq); |
448 |
} |
449 |
|
450 |
/* clear update in progress bit */
|
451 |
s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; |
452 |
|
453 |
s->next_second_time += get_ticks_per_sec(); |
454 |
qemu_mod_timer(s->second_timer, s->next_second_time); |
455 |
} |
456 |
|
457 |
static uint32_t cmos_ioport_read(void *opaque, uint32_t addr) |
458 |
{ |
459 |
RTCState *s = opaque; |
460 |
int ret;
|
461 |
if ((addr & 1) == 0) { |
462 |
return 0xff; |
463 |
} else {
|
464 |
switch(s->cmos_index) {
|
465 |
case RTC_SECONDS:
|
466 |
case RTC_MINUTES:
|
467 |
case RTC_HOURS:
|
468 |
case RTC_DAY_OF_WEEK:
|
469 |
case RTC_DAY_OF_MONTH:
|
470 |
case RTC_MONTH:
|
471 |
case RTC_YEAR:
|
472 |
ret = s->cmos_data[s->cmos_index]; |
473 |
break;
|
474 |
case RTC_REG_A:
|
475 |
ret = s->cmos_data[s->cmos_index]; |
476 |
break;
|
477 |
case RTC_REG_C:
|
478 |
ret = s->cmos_data[s->cmos_index]; |
479 |
qemu_irq_lower(s->irq); |
480 |
#ifdef TARGET_I386
|
481 |
if(s->irq_coalesced &&
|
482 |
s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COUNT) { |
483 |
s->irq_reinject_on_ack_count++; |
484 |
apic_reset_irq_delivered(); |
485 |
DPRINTF_C("cmos: injecting on ack\n");
|
486 |
qemu_irq_raise(s->irq); |
487 |
if (apic_get_irq_delivered()) {
|
488 |
s->irq_coalesced--; |
489 |
DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
|
490 |
s->irq_coalesced); |
491 |
} |
492 |
break;
|
493 |
} |
494 |
#endif
|
495 |
|
496 |
s->cmos_data[RTC_REG_C] = 0x00;
|
497 |
break;
|
498 |
default:
|
499 |
ret = s->cmos_data[s->cmos_index]; |
500 |
break;
|
501 |
} |
502 |
CMOS_DPRINTF("cmos: read index=0x%02x val=0x%02x\n",
|
503 |
s->cmos_index, ret); |
504 |
return ret;
|
505 |
} |
506 |
} |
507 |
|
508 |
void rtc_set_memory(ISADevice *dev, int addr, int val) |
509 |
{ |
510 |
RTCState *s = DO_UPCAST(RTCState, dev, dev); |
511 |
if (addr >= 0 && addr <= 127) |
512 |
s->cmos_data[addr] = val; |
513 |
} |
514 |
|
515 |
void rtc_set_date(ISADevice *dev, const struct tm *tm) |
516 |
{ |
517 |
RTCState *s = DO_UPCAST(RTCState, dev, dev); |
518 |
s->current_tm = *tm; |
519 |
rtc_copy_date(s); |
520 |
} |
521 |
|
522 |
/* PC cmos mappings */
|
523 |
#define REG_IBM_CENTURY_BYTE 0x32 |
524 |
#define REG_IBM_PS2_CENTURY_BYTE 0x37 |
525 |
|
526 |
static void rtc_set_date_from_host(ISADevice *dev) |
527 |
{ |
528 |
RTCState *s = DO_UPCAST(RTCState, dev, dev); |
529 |
struct tm tm;
|
530 |
int val;
|
531 |
|
532 |
/* set the CMOS date */
|
533 |
qemu_get_timedate(&tm, 0);
|
534 |
rtc_set_date(dev, &tm); |
535 |
|
536 |
val = rtc_to_bcd(s, (tm.tm_year / 100) + 19); |
537 |
rtc_set_memory(dev, REG_IBM_CENTURY_BYTE, val); |
538 |
rtc_set_memory(dev, REG_IBM_PS2_CENTURY_BYTE, val); |
539 |
} |
540 |
|
541 |
static int rtc_post_load(void *opaque, int version_id) |
542 |
{ |
543 |
#ifdef TARGET_I386
|
544 |
RTCState *s = opaque; |
545 |
|
546 |
if (version_id >= 2) { |
547 |
if (rtc_td_hack) {
|
548 |
rtc_coalesced_timer_update(s); |
549 |
} |
550 |
} |
551 |
#endif
|
552 |
return 0; |
553 |
} |
554 |
|
555 |
static const VMStateDescription vmstate_rtc = { |
556 |
.name = "mc146818rtc",
|
557 |
.version_id = 2,
|
558 |
.minimum_version_id = 1,
|
559 |
.minimum_version_id_old = 1,
|
560 |
.post_load = rtc_post_load, |
561 |
.fields = (VMStateField []) { |
562 |
VMSTATE_BUFFER(cmos_data, RTCState), |
563 |
VMSTATE_UINT8(cmos_index, RTCState), |
564 |
VMSTATE_INT32(current_tm.tm_sec, RTCState), |
565 |
VMSTATE_INT32(current_tm.tm_min, RTCState), |
566 |
VMSTATE_INT32(current_tm.tm_hour, RTCState), |
567 |
VMSTATE_INT32(current_tm.tm_wday, RTCState), |
568 |
VMSTATE_INT32(current_tm.tm_mday, RTCState), |
569 |
VMSTATE_INT32(current_tm.tm_mon, RTCState), |
570 |
VMSTATE_INT32(current_tm.tm_year, RTCState), |
571 |
VMSTATE_TIMER(periodic_timer, RTCState), |
572 |
VMSTATE_INT64(next_periodic_time, RTCState), |
573 |
VMSTATE_INT64(next_second_time, RTCState), |
574 |
VMSTATE_TIMER(second_timer, RTCState), |
575 |
VMSTATE_TIMER(second_timer2, RTCState), |
576 |
VMSTATE_UINT32_V(irq_coalesced, RTCState, 2),
|
577 |
VMSTATE_UINT32_V(period, RTCState, 2),
|
578 |
VMSTATE_END_OF_LIST() |
579 |
} |
580 |
}; |
581 |
|
582 |
static void rtc_notify_clock_reset(Notifier *notifier, void *data) |
583 |
{ |
584 |
RTCState *s = container_of(notifier, RTCState, clock_reset_notifier); |
585 |
int64_t now = *(int64_t *)data; |
586 |
|
587 |
rtc_set_date_from_host(&s->dev); |
588 |
s->next_second_time = now + (get_ticks_per_sec() * 99) / 100; |
589 |
qemu_mod_timer(s->second_timer2, s->next_second_time); |
590 |
rtc_timer_update(s, now); |
591 |
#ifdef TARGET_I386
|
592 |
if (rtc_td_hack) {
|
593 |
rtc_coalesced_timer_update(s); |
594 |
} |
595 |
#endif
|
596 |
} |
597 |
|
598 |
static void rtc_reset(void *opaque) |
599 |
{ |
600 |
RTCState *s = opaque; |
601 |
|
602 |
s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE); |
603 |
s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF); |
604 |
|
605 |
qemu_irq_lower(s->irq); |
606 |
|
607 |
#ifdef TARGET_I386
|
608 |
if (rtc_td_hack)
|
609 |
s->irq_coalesced = 0;
|
610 |
#endif
|
611 |
} |
612 |
|
613 |
static const MemoryRegionPortio cmos_portio[] = { |
614 |
{0, 2, 1, .read = cmos_ioport_read, .write = cmos_ioport_write }, |
615 |
PORTIO_END_OF_LIST(), |
616 |
}; |
617 |
|
618 |
static const MemoryRegionOps cmos_ops = { |
619 |
.old_portio = cmos_portio |
620 |
}; |
621 |
|
622 |
// FIXME add int32 visitor
|
623 |
static void visit_type_int32(Visitor *v, int *value, const char *name, Error **errp) |
624 |
{ |
625 |
int64_t val = *value; |
626 |
visit_type_int(v, &val, name, errp); |
627 |
} |
628 |
|
629 |
static void rtc_get_date(DeviceState *dev, Visitor *v, void *opaque, |
630 |
const char *name, Error **errp) |
631 |
{ |
632 |
ISADevice *isa = DO_UPCAST(ISADevice, qdev, dev); |
633 |
RTCState *s = DO_UPCAST(RTCState, dev, isa); |
634 |
|
635 |
visit_start_struct(v, NULL, "struct tm", name, 0, errp); |
636 |
visit_type_int32(v, &s->current_tm.tm_year, "tm_year", errp);
|
637 |
visit_type_int32(v, &s->current_tm.tm_mon, "tm_mon", errp);
|
638 |
visit_type_int32(v, &s->current_tm.tm_mday, "tm_mday", errp);
|
639 |
visit_type_int32(v, &s->current_tm.tm_hour, "tm_hour", errp);
|
640 |
visit_type_int32(v, &s->current_tm.tm_min, "tm_min", errp);
|
641 |
visit_type_int32(v, &s->current_tm.tm_sec, "tm_sec", errp);
|
642 |
visit_end_struct(v, errp); |
643 |
} |
644 |
|
645 |
static int rtc_initfn(ISADevice *dev) |
646 |
{ |
647 |
RTCState *s = DO_UPCAST(RTCState, dev, dev); |
648 |
int base = 0x70; |
649 |
|
650 |
s->cmos_data[RTC_REG_A] = 0x26;
|
651 |
s->cmos_data[RTC_REG_B] = 0x02;
|
652 |
s->cmos_data[RTC_REG_C] = 0x00;
|
653 |
s->cmos_data[RTC_REG_D] = 0x80;
|
654 |
|
655 |
rtc_set_date_from_host(dev); |
656 |
|
657 |
s->periodic_timer = qemu_new_timer_ns(rtc_clock, rtc_periodic_timer, s); |
658 |
#ifdef TARGET_I386
|
659 |
if (rtc_td_hack)
|
660 |
s->coalesced_timer = |
661 |
qemu_new_timer_ns(rtc_clock, rtc_coalesced_timer, s); |
662 |
#endif
|
663 |
s->second_timer = qemu_new_timer_ns(rtc_clock, rtc_update_second, s); |
664 |
s->second_timer2 = qemu_new_timer_ns(rtc_clock, rtc_update_second2, s); |
665 |
|
666 |
s->clock_reset_notifier.notify = rtc_notify_clock_reset; |
667 |
qemu_register_clock_reset_notifier(rtc_clock, &s->clock_reset_notifier); |
668 |
|
669 |
s->next_second_time = |
670 |
qemu_get_clock_ns(rtc_clock) + (get_ticks_per_sec() * 99) / 100; |
671 |
qemu_mod_timer(s->second_timer2, s->next_second_time); |
672 |
|
673 |
memory_region_init_io(&s->io, &cmos_ops, s, "rtc", 2); |
674 |
isa_register_ioport(dev, &s->io, base); |
675 |
|
676 |
qdev_set_legacy_instance_id(&dev->qdev, base, 2);
|
677 |
qemu_register_reset(rtc_reset, s); |
678 |
|
679 |
qdev_property_add(&s->dev.qdev, "date", "struct tm", |
680 |
rtc_get_date, NULL, NULL, s, NULL); |
681 |
|
682 |
return 0; |
683 |
} |
684 |
|
685 |
ISADevice *rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq)
|
686 |
{ |
687 |
ISADevice *dev; |
688 |
RTCState *s; |
689 |
|
690 |
dev = isa_create(bus, "mc146818rtc");
|
691 |
s = DO_UPCAST(RTCState, dev, dev); |
692 |
qdev_prop_set_int32(&dev->qdev, "base_year", base_year);
|
693 |
qdev_init_nofail(&dev->qdev); |
694 |
if (intercept_irq) {
|
695 |
s->irq = intercept_irq; |
696 |
} else {
|
697 |
isa_init_irq(dev, &s->irq, RTC_ISA_IRQ); |
698 |
} |
699 |
return dev;
|
700 |
} |
701 |
|
702 |
static ISADeviceInfo mc146818rtc_info = {
|
703 |
.qdev.name = "mc146818rtc",
|
704 |
.qdev.size = sizeof(RTCState),
|
705 |
.qdev.no_user = 1,
|
706 |
.qdev.vmsd = &vmstate_rtc, |
707 |
.init = rtc_initfn, |
708 |
.qdev.props = (Property[]) { |
709 |
DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980), |
710 |
DEFINE_PROP_END_OF_LIST(), |
711 |
} |
712 |
}; |
713 |
|
714 |
static void mc146818rtc_register(void) |
715 |
{ |
716 |
isa_qdev_register(&mc146818rtc_info); |
717 |
} |
718 |
device_init(mc146818rtc_register) |