Archipelago » qemu

/*

 * TI OMAP processors emulation.

 *

 * Copyright (C) 2006-2007 Andrzej Zaborowski  <balrog@zabor.org>

 *

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public License as

 * published by the Free Software Foundation; either version 2 of

 * the License, or (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,

 * MA 02111-1307 USA

 */

#include "vl.h"

#include "arm_pic.h"

/* Should signal the TCMI */

uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr)

{

    OMAP_8B_REG(addr);

    return 0;

}

void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,

                uint32_t value)

{

    OMAP_8B_REG(addr);

}

uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)

{

    OMAP_16B_REG(addr);

    return 0;

}

void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,

                uint32_t value)

{

    OMAP_16B_REG(addr);

}

uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)

{

    OMAP_32B_REG(addr);

    return 0;

}

void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,

                uint32_t value)

{

    OMAP_32B_REG(addr);

}

/* Interrupt Handlers */

struct omap_intr_handler_s {

    qemu_irq *pins;

    qemu_irq *parent_pic;

    target_phys_addr_t base;

    /* state */

    uint32_t irqs;

    uint32_t mask;

    uint32_t sens_edge;

    uint32_t fiq;

    int priority[32];

    uint32_t new_irq_agr;

    uint32_t new_fiq_agr;

    int sir_irq;

    int sir_fiq;

    int stats[32];

};

static void omap_inth_update(struct omap_intr_handler_s *s)

{

    uint32_t irq = s->irqs & ~s->mask & ~s->fiq;

    uint32_t fiq = s->irqs & ~s->mask & s->fiq;

    if (s->new_irq_agr || !irq) {

       qemu_set_irq(s->parent_pic[ARM_PIC_CPU_IRQ], irq);

       if (irq)

           s->new_irq_agr = 0;

    }

    if (s->new_fiq_agr || !irq) {

        qemu_set_irq(s->parent_pic[ARM_PIC_CPU_FIQ], fiq);

        if (fiq)

            s->new_fiq_agr = 0;

    }

}

static void omap_inth_sir_update(struct omap_intr_handler_s *s)

{

    int i, intr_irq, intr_fiq, p_irq, p_fiq, p, f;

    uint32_t level = s->irqs & ~s->mask;

    intr_irq = 0;

    intr_fiq = 0;

    p_irq = -1;

    p_fiq = -1;

    /* Find the interrupt line with the highest dynamic priority */

    for (f = ffs(level), i = f - 1, level >>= f - 1; f; i += f, level >>= f) {

        p = s->priority[i];

        if (s->fiq & (1 << i)) {

            if (p > p_fiq) {

                p_fiq = p;

                intr_fiq = i;

            }

        } else {

            if (p > p_irq) {

                p_irq = p;

                intr_irq = i;

            }

        }

        f = ffs(level >> 1);

    }

    s->sir_irq = intr_irq;

    s->sir_fiq = intr_fiq;

}

#define INT_FALLING_EDGE        0

#define INT_LOW_LEVEL                1

static void omap_set_intr(void *opaque, int irq, int req)

{

    struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;

    uint32_t rise;

    if (req) {

        rise = ~ih->irqs & (1 << irq);

        ih->irqs |= rise;

        ih->stats[irq] += !!rise;

    } else {

        rise = ih->sens_edge & ih->irqs & (1 << irq);

        ih->irqs &= ~rise;

    }

    if (rise & ~ih->mask) {

        omap_inth_sir_update(ih);

        omap_inth_update(ih);

    }

}

static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr)

{

    struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;

    int i, offset = addr - s->base;

    switch (offset) {

    case 0x00:        /* ITR */

        return s->irqs;

    case 0x04:        /* MIR */

        return s->mask;

    case 0x10:        /* SIR_IRQ_CODE */

        i = s->sir_irq;

        if (((s->sens_edge >> i) & 1) == INT_FALLING_EDGE && i) {

            s->irqs &= ~(1 << i);

            omap_inth_sir_update(s);

            omap_inth_update(s);

        }

        return i;

    case 0x14:        /* SIR_FIQ_CODE */

        i = s->sir_fiq;

        if (((s->sens_edge >> i) & 1) == INT_FALLING_EDGE && i) {

            s->irqs &= ~(1 << i);

            omap_inth_sir_update(s);

            omap_inth_update(s);

        }

        return i;

    case 0x18:        /* CONTROL_REG */

        return 0;

    case 0x1c:        /* ILR0 */

    case 0x20:        /* ILR1 */

    case 0x24:        /* ILR2 */

    case 0x28:        /* ILR3 */

    case 0x2c:        /* ILR4 */

    case 0x30:        /* ILR5 */

    case 0x34:        /* ILR6 */

    case 0x38:        /* ILR7 */

    case 0x3c:        /* ILR8 */

    case 0x40:        /* ILR9 */

    case 0x44:        /* ILR10 */

    case 0x48:        /* ILR11 */

    case 0x4c:        /* ILR12 */

    case 0x50:        /* ILR13 */

    case 0x54:        /* ILR14 */

    case 0x58:        /* ILR15 */

    case 0x5c:        /* ILR16 */

    case 0x60:        /* ILR17 */

    case 0x64:        /* ILR18 */

    case 0x68:        /* ILR19 */

    case 0x6c:        /* ILR20 */

    case 0x70:        /* ILR21 */

    case 0x74:        /* ILR22 */

    case 0x78:        /* ILR23 */

    case 0x7c:        /* ILR24 */

    case 0x80:        /* ILR25 */

    case 0x84:        /* ILR26 */

    case 0x88:        /* ILR27 */

    case 0x8c:        /* ILR28 */

    case 0x90:        /* ILR29 */

    case 0x94:        /* ILR30 */

    case 0x98:        /* ILR31 */

        i = (offset - 0x1c) >> 2;

        return (s->priority[i] << 2) |

                (((s->sens_edge >> i) & 1) << 1) |

                ((s->fiq >> i) & 1);

    case 0x9c:        /* ISR */

        return 0x00000000;

    default:

        OMAP_BAD_REG(addr);

        break;

    }

    return 0;

}

static void omap_inth_write(void *opaque, target_phys_addr_t addr,

                uint32_t value)

{

    struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;

    int i, offset = addr - s->base;

    switch (offset) {

    case 0x00:        /* ITR */

        s->irqs &= value;

        omap_inth_sir_update(s);

        omap_inth_update(s);

        return;

    case 0x04:        /* MIR */

        s->mask = value;

        omap_inth_sir_update(s);

        omap_inth_update(s);

        return;

    case 0x10:        /* SIR_IRQ_CODE */

    case 0x14:        /* SIR_FIQ_CODE */

        OMAP_RO_REG(addr);

        break;

    case 0x18:        /* CONTROL_REG */

        if (value & 2)

            s->new_fiq_agr = ~0;

        if (value & 1)

            s->new_irq_agr = ~0;

        omap_inth_update(s);

        return;

    case 0x1c:        /* ILR0 */

    case 0x20:        /* ILR1 */

    case 0x24:        /* ILR2 */

    case 0x28:        /* ILR3 */

    case 0x2c:        /* ILR4 */

    case 0x30:        /* ILR5 */

    case 0x34:        /* ILR6 */

    case 0x38:        /* ILR7 */

    case 0x3c:        /* ILR8 */

    case 0x40:        /* ILR9 */

    case 0x44:        /* ILR10 */

    case 0x48:        /* ILR11 */

    case 0x4c:        /* ILR12 */

    case 0x50:        /* ILR13 */

    case 0x54:        /* ILR14 */

    case 0x58:        /* ILR15 */

    case 0x5c:        /* ILR16 */

    case 0x60:        /* ILR17 */

    case 0x64:        /* ILR18 */

    case 0x68:        /* ILR19 */

    case 0x6c:        /* ILR20 */

    case 0x70:        /* ILR21 */

    case 0x74:        /* ILR22 */

    case 0x78:        /* ILR23 */

    case 0x7c:        /* ILR24 */

    case 0x80:        /* ILR25 */

    case 0x84:        /* ILR26 */

    case 0x88:        /* ILR27 */

    case 0x8c:        /* ILR28 */

    case 0x90:        /* ILR29 */

    case 0x94:        /* ILR30 */

    case 0x98:        /* ILR31 */

        i = (offset - 0x1c) >> 2;

        s->priority[i] = (value >> 2) & 0x1f;

        s->sens_edge &= ~(1 << i);

        s->sens_edge |= ((value >> 1) & 1) << i;

        s->fiq &= ~(1 << i);

        s->fiq |= (value & 1) << i;

        return;

    case 0x9c:        /* ISR */

        for (i = 0; i < 32; i ++)

            if (value & (1 << i)) {

                omap_set_intr(s, i, 1);

                return;

            }

        return;

    default:

        OMAP_BAD_REG(addr);

    }

}

static CPUReadMemoryFunc *omap_inth_readfn[] = {

    omap_badwidth_read32,

    omap_badwidth_read32,

    omap_inth_read,

};

static CPUWriteMemoryFunc *omap_inth_writefn[] = {

    omap_inth_write,

    omap_inth_write,

    omap_inth_write,

};

static void omap_inth_reset(struct omap_intr_handler_s *s)

{

    s->irqs = 0x00000000;

    s->mask = 0xffffffff;

    s->sens_edge = 0x00000000;

    s->fiq = 0x00000000;

    memset(s->priority, 0, sizeof(s->priority));

    s->new_irq_agr = ~0;

    s->new_fiq_agr = ~0;

    s->sir_irq = 0;

    s->sir_fiq = 0;

    omap_inth_update(s);

}

struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,

                unsigned long size, qemu_irq parent[2], omap_clk clk)

{

    int iomemtype;

    struct omap_intr_handler_s *s = (struct omap_intr_handler_s *)

            qemu_mallocz(sizeof(struct omap_intr_handler_s));

    s->parent_pic = parent;

    s->base = base;

    s->pins = qemu_allocate_irqs(omap_set_intr, s, 32);

    omap_inth_reset(s);

    iomemtype = cpu_register_io_memory(0, omap_inth_readfn,

                    omap_inth_writefn, s);

    cpu_register_physical_memory(s->base, size, iomemtype);

    return s;

}

/* OMAP1 DMA module */

typedef enum {

    constant = 0,

    post_incremented,

    single_index,

    double_index,

} omap_dma_addressing_t;

struct omap_dma_channel_s {

    int burst[2];

    int pack[2];

    enum omap_dma_port port[2];

    target_phys_addr_t addr[2];

    omap_dma_addressing_t mode[2];

    int data_type;

    int end_prog;

    int repeat;

    int auto_init;

    int priority;

    int fs;

    int sync;

    int running;

    int interrupts;

    int status;

    int signalled;

    int post_sync;

    int transfer;

    uint16_t elements;

    uint16_t frames;

    uint16_t frame_index;

    uint16_t element_index;

    uint16_t cpc;

    struct omap_dma_reg_set_s {

        target_phys_addr_t src, dest;

        int frame;

        int element;

        int frame_delta[2];

        int elem_delta[2];

        int frames;

        int elements;

    } active_set;

};

struct omap_dma_s {

    qemu_irq *ih;

    QEMUTimer *tm;

    struct omap_mpu_state_s *mpu;

    target_phys_addr_t base;

    omap_clk clk;

    int64_t delay;

    uint32_t drq;

    uint16_t gcr;

    int run_count;

    int chans;

    struct omap_dma_channel_s ch[16];

    struct omap_dma_lcd_channel_s lcd_ch;

};

static void omap_dma_interrupts_update(struct omap_dma_s *s)

{

    /* First three interrupts are shared between two channels each.  */

    qemu_set_irq(s->ih[OMAP_INT_DMA_CH0_6],

                    (s->ch[0].status | s->ch[6].status) & 0x3f);

    qemu_set_irq(s->ih[OMAP_INT_DMA_CH1_7],

                    (s->ch[1].status | s->ch[7].status) & 0x3f);

    qemu_set_irq(s->ih[OMAP_INT_DMA_CH2_8],

                    (s->ch[2].status | s->ch[8].status) & 0x3f);

    qemu_set_irq(s->ih[OMAP_INT_DMA_CH3],

                    (s->ch[3].status) & 0x3f);

    qemu_set_irq(s->ih[OMAP_INT_DMA_CH4],

                    (s->ch[4].status) & 0x3f);

    qemu_set_irq(s->ih[OMAP_INT_DMA_CH5],

                    (s->ch[5].status) & 0x3f);

}

static void omap_dma_channel_load(struct omap_dma_s *s, int ch)

{

    struct omap_dma_reg_set_s *a = &s->ch[ch].active_set;

    int i;

    /*

     * TODO: verify address ranges and alignment

     * TODO: port endianness

     */

    a->src = s->ch[ch].addr[0];

    a->dest = s->ch[ch].addr[1];

    a->frames = s->ch[ch].frames;

    a->elements = s->ch[ch].elements;

    a->frame = 0;

    a->element = 0;

    if (unlikely(!s->ch[ch].elements || !s->ch[ch].frames)) {

        printf("%s: bad DMA request\n", __FUNCTION__);

        return;

    }

    for (i = 0; i < 2; i ++)

        switch (s->ch[ch].mode[i]) {

        case constant:

            a->elem_delta[i] = 0;

            a->frame_delta[i] = 0;

            break;

        case post_incremented:

            a->elem_delta[i] = s->ch[ch].data_type;

            a->frame_delta[i] = 0;

            break;

        case single_index:

            a->elem_delta[i] = s->ch[ch].data_type +

                s->ch[ch].element_index - 1;

            if (s->ch[ch].element_index > 0x7fff)

                a->elem_delta[i] -= 0x10000;

            a->frame_delta[i] = 0;

            break;

        case double_index:

            a->elem_delta[i] = s->ch[ch].data_type +

                s->ch[ch].element_index - 1;

            if (s->ch[ch].element_index > 0x7fff)

                a->elem_delta[i] -= 0x10000;

            a->frame_delta[i] = s->ch[ch].frame_index -

                s->ch[ch].element_index;

            if (s->ch[ch].frame_index > 0x7fff)

                a->frame_delta[i] -= 0x10000;

            break;

        default:

            break;

        }

}

static inline void omap_dma_request_run(struct omap_dma_s *s,

                int channel, int request)

{

next_channel:

    if (request > 0)

        for (; channel < 9; channel ++)

            if (s->ch[channel].sync == request && s->ch[channel].running)

                break;

    if (channel >= 9)

        return;

    if (s->ch[channel].transfer) {

        if (request > 0) {

            s->ch[channel ++].post_sync = request;

            goto next_channel;

        }

        s->ch[channel].status |= 0x02;        /* Synchronisation drop */

        omap_dma_interrupts_update(s);

        return;

    }

    if (!s->ch[channel].signalled)

        s->run_count ++;

    s->ch[channel].signalled = 1;

    if (request > 0)

        s->ch[channel].status |= 0x40;        /* External request */

    if (s->delay && !qemu_timer_pending(s->tm))

        qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay);

    if (request > 0) {

        channel ++;

        goto next_channel;

    }

}

static inline void omap_dma_request_stop(struct omap_dma_s *s, int channel)

{

    if (s->ch[channel].signalled)

        s->run_count --;

    s->ch[channel].signalled = 0;

    if (!s->run_count)

        qemu_del_timer(s->tm);

}

static void omap_dma_channel_run(struct omap_dma_s *s)

{

    int ch;

    uint16_t status;

    uint8_t value[4];

    struct omap_dma_port_if_s *src_p, *dest_p;

    struct omap_dma_reg_set_s *a;

    for (ch = 0; ch < 9; ch ++) {

        a = &s->ch[ch].active_set;

        src_p = &s->mpu->port[s->ch[ch].port[0]];

        dest_p = &s->mpu->port[s->ch[ch].port[1]];

        if (s->ch[ch].signalled && (!src_p->addr_valid(s->mpu, a->src) ||

                    !dest_p->addr_valid(s->mpu, a->dest))) {

#if 0

            /* Bus time-out */

            if (s->ch[ch].interrupts & 0x01)

                s->ch[ch].status |= 0x01;

            omap_dma_request_stop(s, ch);

            continue;

#endif

            printf("%s: Bus time-out in DMA%i operation\n", __FUNCTION__, ch);

        }

        status = s->ch[ch].status;

        while (status == s->ch[ch].status && s->ch[ch].signalled) {

            /* Transfer a single element */

            s->ch[ch].transfer = 1;

            cpu_physical_memory_read(a->src, value, s->ch[ch].data_type);

            cpu_physical_memory_write(a->dest, value, s->ch[ch].data_type);

            s->ch[ch].transfer = 0;

            a->src += a->elem_delta[0];

            a->dest += a->elem_delta[1];

            a->element ++;

            /* Check interrupt conditions */

            if (a->element == a->elements) {

                a->element = 0;

                a->src += a->frame_delta[0];

                a->dest += a->frame_delta[1];

                a->frame ++;

                if (a->frame == a->frames) {

                    if (!s->ch[ch].repeat || !s->ch[ch].auto_init)

                        s->ch[ch].running = 0;

                    if (s->ch[ch].auto_init &&

                            (s->ch[ch].repeat ||

                             s->ch[ch].end_prog))

                        omap_dma_channel_load(s, ch);

                    if (s->ch[ch].interrupts & 0x20)

                        s->ch[ch].status |= 0x20;

                    if (!s->ch[ch].sync)

                        omap_dma_request_stop(s, ch);

                }

                if (s->ch[ch].interrupts & 0x08)

                    s->ch[ch].status |= 0x08;

                if (s->ch[ch].sync && s->ch[ch].fs &&

                                !(s->drq & (1 << s->ch[ch].sync))) {

                    s->ch[ch].status &= ~0x40;

                    omap_dma_request_stop(s, ch);

                }

            }

            if (a->element == 1 && a->frame == a->frames - 1)

                if (s->ch[ch].interrupts & 0x10)

                    s->ch[ch].status |= 0x10;

            if (a->element == (a->elements >> 1))

                if (s->ch[ch].interrupts & 0x04)

                    s->ch[ch].status |= 0x04;

            if (s->ch[ch].sync && !s->ch[ch].fs &&

                            !(s->drq & (1 << s->ch[ch].sync))) {

                s->ch[ch].status &= ~0x40;

                omap_dma_request_stop(s, ch);

            }

            /*

             * Process requests made while the element was

             * being transferred.

             */

            if (s->ch[ch].post_sync) {

                omap_dma_request_run(s, 0, s->ch[ch].post_sync);

                s->ch[ch].post_sync = 0;

            }

#if 0

            break;

#endif

        }

        s->ch[ch].cpc = a->dest & 0x0000ffff;

    }

    omap_dma_interrupts_update(s);

    if (s->run_count && s->delay)

        qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay);

}

static int omap_dma_ch_reg_read(struct omap_dma_s *s,

                int ch, int reg, uint16_t *value) {

    switch (reg) {

    case 0x00:        /* SYS_DMA_CSDP_CH0 */

        *value = (s->ch[ch].burst[1] << 14) |

                (s->ch[ch].pack[1] << 13) |

                (s->ch[ch].port[1] << 9) |

                (s->ch[ch].burst[0] << 7) |

                (s->ch[ch].pack[0] << 6) |

                (s->ch[ch].port[0] << 2) |

                (s->ch[ch].data_type >> 1);

        break;

    case 0x02:        /* SYS_DMA_CCR_CH0 */

        *value = (s->ch[ch].mode[1] << 14) |

                (s->ch[ch].mode[0] << 12) |

                (s->ch[ch].end_prog << 11) |

                (s->ch[ch].repeat << 9) |

                (s->ch[ch].auto_init << 8) |

                (s->ch[ch].running << 7) |

                (s->ch[ch].priority << 6) |

                (s->ch[ch].fs << 5) | s->ch[ch].sync;

        break;

    case 0x04:        /* SYS_DMA_CICR_CH0 */

        *value = s->ch[ch].interrupts;

        break;

    case 0x06:        /* SYS_DMA_CSR_CH0 */

        /* FIXME: shared CSR for channels sharing the interrupts */

        *value = s->ch[ch].status;

        s->ch[ch].status &= 0x40;

        omap_dma_interrupts_update(s);

        break;

    case 0x08:        /* SYS_DMA_CSSA_L_CH0 */

        *value = s->ch[ch].addr[0] & 0x0000ffff;

        break;

    case 0x0a:        /* SYS_DMA_CSSA_U_CH0 */

        *value = s->ch[ch].addr[0] >> 16;

        break;

    case 0x0c:        /* SYS_DMA_CDSA_L_CH0 */

        *value = s->ch[ch].addr[1] & 0x0000ffff;

        break;

    case 0x0e:        /* SYS_DMA_CDSA_U_CH0 */

        *value = s->ch[ch].addr[1] >> 16;

        break;

    case 0x10:        /* SYS_DMA_CEN_CH0 */

        *value = s->ch[ch].elements;

        break;

    case 0x12:        /* SYS_DMA_CFN_CH0 */

        *value = s->ch[ch].frames;

        break;

    case 0x14:        /* SYS_DMA_CFI_CH0 */

        *value = s->ch[ch].frame_index;

        break;

    case 0x16:        /* SYS_DMA_CEI_CH0 */

        *value = s->ch[ch].element_index;

        break;

    case 0x18:        /* SYS_DMA_CPC_CH0 */

        *value = s->ch[ch].cpc;

        break;

    default:

        return 1;

    }

    return 0;

}

static int omap_dma_ch_reg_write(struct omap_dma_s *s,

                int ch, int reg, uint16_t value) {

    switch (reg) {

    case 0x00:        /* SYS_DMA_CSDP_CH0 */

        s->ch[ch].burst[1] = (value & 0xc000) >> 14;

        s->ch[ch].pack[1] = (value & 0x2000) >> 13;

        s->ch[ch].port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9);

        s->ch[ch].burst[0] = (value & 0x0180) >> 7;

        s->ch[ch].pack[0] = (value & 0x0040) >> 6;

        s->ch[ch].port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2);

        s->ch[ch].data_type = (1 << (value & 3));

        if (s->ch[ch].port[0] >= omap_dma_port_last)

            printf("%s: invalid DMA port %i\n", __FUNCTION__,

                            s->ch[ch].port[0]);

        if (s->ch[ch].port[1] >= omap_dma_port_last)

            printf("%s: invalid DMA port %i\n", __FUNCTION__,

                            s->ch[ch].port[1]);

        if ((value & 3) == 3)

            printf("%s: bad data_type for DMA channel %i\n", __FUNCTION__, ch);

        break;

    case 0x02:        /* SYS_DMA_CCR_CH0 */

        s->ch[ch].mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14);

        s->ch[ch].mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12);

        s->ch[ch].end_prog = (value & 0x0800) >> 11;

        s->ch[ch].repeat = (value & 0x0200) >> 9;

        s->ch[ch].auto_init = (value & 0x0100) >> 8;

        s->ch[ch].priority = (value & 0x0040) >> 6;

        s->ch[ch].fs = (value & 0x0020) >> 5;

        s->ch[ch].sync = value & 0x001f;

        if (value & 0x0080) {

            if (s->ch[ch].running) {

                if (!s->ch[ch].signalled &&

                                s->ch[ch].auto_init && s->ch[ch].end_prog)

                    omap_dma_channel_load(s, ch);

            } else {

                s->ch[ch].running = 1;

                omap_dma_channel_load(s, ch);

            }

            if (!s->ch[ch].sync || (s->drq & (1 << s->ch[ch].sync)))

                omap_dma_request_run(s, ch, 0);

        } else {

            s->ch[ch].running = 0;

            omap_dma_request_stop(s, ch);

        }

        break;

    case 0x04:        /* SYS_DMA_CICR_CH0 */

        s->ch[ch].interrupts = value & 0x003f;

        break;

    case 0x06:        /* SYS_DMA_CSR_CH0 */

        return 1;

    case 0x08:        /* SYS_DMA_CSSA_L_CH0 */

        s->ch[ch].addr[0] &= 0xffff0000;

        s->ch[ch].addr[0] |= value;

        break;

    case 0x0a:        /* SYS_DMA_CSSA_U_CH0 */

        s->ch[ch].addr[0] &= 0x0000ffff;

        s->ch[ch].addr[0] |= value << 16;

        break;

    case 0x0c:        /* SYS_DMA_CDSA_L_CH0 */

        s->ch[ch].addr[1] &= 0xffff0000;

        s->ch[ch].addr[1] |= value;

        break;

    case 0x0e:        /* SYS_DMA_CDSA_U_CH0 */

        s->ch[ch].addr[1] &= 0x0000ffff;

        s->ch[ch].addr[1] |= value << 16;

        break;

    case 0x10:        /* SYS_DMA_CEN_CH0 */

        s->ch[ch].elements = value & 0xffff;

        break;

    case 0x12:        /* SYS_DMA_CFN_CH0 */

        s->ch[ch].frames = value & 0xffff;

        break;

    case 0x14:        /* SYS_DMA_CFI_CH0 */

        s->ch[ch].frame_index = value & 0xffff;

        break;

    case 0x16:        /* SYS_DMA_CEI_CH0 */

        s->ch[ch].element_index = value & 0xffff;

        break;

    case 0x18:        /* SYS_DMA_CPC_CH0 */

        return 1;

    default:

        OMAP_BAD_REG((unsigned long) reg);

    }

    return 0;

}

static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr)

{

    struct omap_dma_s *s = (struct omap_dma_s *) opaque;

    int i, reg, ch, offset = addr - s->base;

    uint16_t ret;

    switch (offset) {

    case 0x000 ... 0x2fe:

        reg = offset & 0x3f;

        ch = (offset >> 6) & 0x0f;

        if (omap_dma_ch_reg_read(s, ch, reg, &ret))

            break;

        return ret;

    case 0x300:        /* SYS_DMA_LCD_CTRL */

        i = s->lcd_ch.condition;

        s->lcd_ch.condition = 0;

        qemu_irq_lower(s->lcd_ch.irq);

        return ((s->lcd_ch.src == imif) << 6) | (i << 3) |

                (s->lcd_ch.interrupts << 1) | s->lcd_ch.dual;

    case 0x302:        /* SYS_DMA_LCD_TOP_F1_L */

        return s->lcd_ch.src_f1_top & 0xffff;

    case 0x304:        /* SYS_DMA_LCD_TOP_F1_U */

        return s->lcd_ch.src_f1_top >> 16;

    case 0x306:        /* SYS_DMA_LCD_BOT_F1_L */

        return s->lcd_ch.src_f1_bottom & 0xffff;

    case 0x308:        /* SYS_DMA_LCD_BOT_F1_U */

        return s->lcd_ch.src_f1_bottom >> 16;

    case 0x30a:        /* SYS_DMA_LCD_TOP_F2_L */

        return s->lcd_ch.src_f2_top & 0xffff;

    case 0x30c:        /* SYS_DMA_LCD_TOP_F2_U */

        return s->lcd_ch.src_f2_top >> 16;

    case 0x30e:        /* SYS_DMA_LCD_BOT_F2_L */

        return s->lcd_ch.src_f2_bottom & 0xffff;

    case 0x310:        /* SYS_DMA_LCD_BOT_F2_U */

        return s->lcd_ch.src_f2_bottom >> 16;

    case 0x400:        /* SYS_DMA_GCR */

        return s->gcr;