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/*
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 * Arm PrimeCell PL110 Color LCD Controller
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 *
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 * Copyright (c) 2005-2009 CodeSourcery.
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 * Written by Paul Brook
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 *
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 * This code is licensed under the GNU LGPL
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 */
9

    
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#include "sysbus.h"
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#include "console.h"
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#include "framebuffer.h"
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#define PL110_CR_EN   0x001
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#define PL110_CR_BGR  0x100
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#define PL110_CR_BEBO 0x200
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#define PL110_CR_BEPO 0x400
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#define PL110_CR_PWR  0x800
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enum pl110_bppmode
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{
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    BPP_1,
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    BPP_2,
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    BPP_4,
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    BPP_8,
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    BPP_16,
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    BPP_32,
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    BPP_16_565, /* PL111 only */
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    BPP_12      /* PL111 only */
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};
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/* The Versatile/PB uses a slightly modified PL110 controller.  */
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enum pl110_version
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{
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    PL110,
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    PL110_VERSATILE,
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    PL111
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};
40

    
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typedef struct {
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    SysBusDevice busdev;
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    MemoryRegion iomem;
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    DisplayState *ds;
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    int version;
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    uint32_t timing[4];
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    uint32_t cr;
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    uint32_t upbase;
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    uint32_t lpbase;
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    uint32_t int_status;
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    uint32_t int_mask;
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    int cols;
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    int rows;
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    enum pl110_bppmode bpp;
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    int invalidate;
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    uint32_t mux_ctrl;
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    uint32_t pallette[256];
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    uint32_t raw_pallette[128];
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    qemu_irq irq;
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} pl110_state;
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static const VMStateDescription vmstate_pl110 = {
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    .name = "pl110",
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    .version_id = 2,
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    .minimum_version_id = 1,
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    .fields = (VMStateField[]) {
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        VMSTATE_INT32(version, pl110_state),
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        VMSTATE_UINT32_ARRAY(timing, pl110_state, 4),
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        VMSTATE_UINT32(cr, pl110_state),
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        VMSTATE_UINT32(upbase, pl110_state),
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        VMSTATE_UINT32(lpbase, pl110_state),
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        VMSTATE_UINT32(int_status, pl110_state),
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        VMSTATE_UINT32(int_mask, pl110_state),
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        VMSTATE_INT32(cols, pl110_state),
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        VMSTATE_INT32(rows, pl110_state),
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        VMSTATE_UINT32(bpp, pl110_state),
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        VMSTATE_INT32(invalidate, pl110_state),
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        VMSTATE_UINT32_ARRAY(pallette, pl110_state, 256),
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        VMSTATE_UINT32_ARRAY(raw_pallette, pl110_state, 128),
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        VMSTATE_UINT32_V(mux_ctrl, pl110_state, 2),
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        VMSTATE_END_OF_LIST()
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    }
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};
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static const unsigned char pl110_id[] =
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{ 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
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/* The Arm documentation (DDI0224C) says the CLDC on the Versatile board
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   has a different ID.  However Linux only looks for the normal ID.  */
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#if 0
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static const unsigned char pl110_versatile_id[] =
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{ 0x93, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
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#else
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#define pl110_versatile_id pl110_id
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#endif
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static const unsigned char pl111_id[] = {
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    0x11, 0x11, 0x24, 0x00, 0x0d, 0xf0, 0x05, 0xb1
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};
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/* Indexed by pl110_version */
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static const unsigned char *idregs[] = {
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    pl110_id,
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    pl110_versatile_id,
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    pl111_id
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};
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#include "pixel_ops.h"
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#define BITS 8
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#include "pl110_template.h"
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#define BITS 15
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#include "pl110_template.h"
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#define BITS 16
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#include "pl110_template.h"
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#define BITS 24
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#include "pl110_template.h"
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#define BITS 32
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#include "pl110_template.h"
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static int pl110_enabled(pl110_state *s)
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{
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  return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR);
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}
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static void pl110_update_display(void *opaque)
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{
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    pl110_state *s = (pl110_state *)opaque;
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    drawfn* fntable;
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    drawfn fn;
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    int dest_width;
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    int src_width;
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    int bpp_offset;
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    int first;
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    int last;
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    if (!pl110_enabled(s))
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        return;
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    switch (ds_get_bits_per_pixel(s->ds)) {
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    case 0:
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        return;
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    case 8:
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        fntable = pl110_draw_fn_8;
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        dest_width = 1;
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        break;
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    case 15:
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        fntable = pl110_draw_fn_15;
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        dest_width = 2;
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        break;
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    case 16:
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        fntable = pl110_draw_fn_16;
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        dest_width = 2;
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        break;
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    case 24:
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        fntable = pl110_draw_fn_24;
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        dest_width = 3;
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        break;
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    case 32:
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        fntable = pl110_draw_fn_32;
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        dest_width = 4;
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        break;
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    default:
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        fprintf(stderr, "pl110: Bad color depth\n");
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        exit(1);
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    }
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    if (s->cr & PL110_CR_BGR)
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        bpp_offset = 0;
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    else
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        bpp_offset = 24;
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    if ((s->version != PL111) && (s->bpp == BPP_16)) {
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        /* The PL110's native 16 bit mode is 5551; however
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         * most boards with a PL110 implement an external
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         * mux which allows bits to be reshuffled to give
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         * 565 format. The mux is typically controlled by
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         * an external system register.
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         * This is controlled by a GPIO input pin
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         * so boards can wire it up to their register.
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         *
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         * The PL111 straightforwardly implements both
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         * 5551 and 565 under control of the bpp field
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         * in the LCDControl register.
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         */
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        switch (s->mux_ctrl) {
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        case 3: /* 565 BGR */
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            bpp_offset = (BPP_16_565 - BPP_16);
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            break;
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        case 1: /* 5551 */
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            break;
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        case 0: /* 888; also if we have loaded vmstate from an old version */
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        case 2: /* 565 RGB */
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        default:
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            /* treat as 565 but honour BGR bit */
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            bpp_offset += (BPP_16_565 - BPP_16);
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            break;
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        }
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    }
200

    
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    if (s->cr & PL110_CR_BEBO)
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        fn = fntable[s->bpp + 8 + bpp_offset];
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    else if (s->cr & PL110_CR_BEPO)
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        fn = fntable[s->bpp + 16 + bpp_offset];
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    else
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        fn = fntable[s->bpp + bpp_offset];
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    src_width = s->cols;
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    switch (s->bpp) {
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    case BPP_1:
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        src_width >>= 3;
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        break;
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    case BPP_2:
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        src_width >>= 2;
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        break;
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    case BPP_4:
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        src_width >>= 1;
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        break;
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    case BPP_8:
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        break;
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    case BPP_16:
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    case BPP_16_565:
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    case BPP_12:
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        src_width <<= 1;
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        break;
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    case BPP_32:
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        src_width <<= 2;
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        break;
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    }
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    dest_width *= s->cols;
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    first = 0;
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    framebuffer_update_display(s->ds,
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                               s->upbase, s->cols, s->rows,
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                               src_width, dest_width, 0,
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                               s->invalidate,
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                               fn, s->pallette,
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                               &first, &last);
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    if (first >= 0) {
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        dpy_update(s->ds, 0, first, s->cols, last - first + 1);
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    }
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    s->invalidate = 0;
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}
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static void pl110_invalidate_display(void * opaque)
245
{
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    pl110_state *s = (pl110_state *)opaque;
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    s->invalidate = 1;
248
    if (pl110_enabled(s)) {
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        qemu_console_resize(s->ds, s->cols, s->rows);
250
    }
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}
252

    
253
static void pl110_update_pallette(pl110_state *s, int n)
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{
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    int i;
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    uint32_t raw;
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    unsigned int r, g, b;
258

    
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    raw = s->raw_pallette[n];
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    n <<= 1;
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    for (i = 0; i < 2; i++) {
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        r = (raw & 0x1f) << 3;
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        raw >>= 5;
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        g = (raw & 0x1f) << 3;
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        raw >>= 5;
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        b = (raw & 0x1f) << 3;
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        /* The I bit is ignored.  */
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        raw >>= 6;
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        switch (ds_get_bits_per_pixel(s->ds)) {
270
        case 8:
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            s->pallette[n] = rgb_to_pixel8(r, g, b);
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            break;
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        case 15:
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            s->pallette[n] = rgb_to_pixel15(r, g, b);
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            break;
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        case 16:
277
            s->pallette[n] = rgb_to_pixel16(r, g, b);
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            break;
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        case 24:
280
        case 32:
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            s->pallette[n] = rgb_to_pixel32(r, g, b);
282
            break;
283
        }
284
        n++;
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    }
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}
287

    
288
static void pl110_resize(pl110_state *s, int width, int height)
289
{
290
    if (width != s->cols || height != s->rows) {
291
        if (pl110_enabled(s)) {
292
            qemu_console_resize(s->ds, width, height);
293
        }
294
    }
295
    s->cols = width;
296
    s->rows = height;
297
}
298

    
299
/* Update interrupts.  */
300
static void pl110_update(pl110_state *s)
301
{
302
  /* TODO: Implement interrupts.  */
303
}
304

    
305
static uint64_t pl110_read(void *opaque, target_phys_addr_t offset,
306
                           unsigned size)
307
{
308
    pl110_state *s = (pl110_state *)opaque;
309

    
310
    if (offset >= 0xfe0 && offset < 0x1000) {
311
        return idregs[s->version][(offset - 0xfe0) >> 2];
312
    }
313
    if (offset >= 0x200 && offset < 0x400) {
314
        return s->raw_pallette[(offset - 0x200) >> 2];
315
    }
316
    switch (offset >> 2) {
317
    case 0: /* LCDTiming0 */
318
        return s->timing[0];
319
    case 1: /* LCDTiming1 */
320
        return s->timing[1];
321
    case 2: /* LCDTiming2 */
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        return s->timing[2];
323
    case 3: /* LCDTiming3 */
324
        return s->timing[3];
325
    case 4: /* LCDUPBASE */
326
        return s->upbase;
327
    case 5: /* LCDLPBASE */
328
        return s->lpbase;
329
    case 6: /* LCDIMSC */
330
        if (s->version != PL110) {
331
            return s->cr;
332
        }
333
        return s->int_mask;
334
    case 7: /* LCDControl */
335
        if (s->version != PL110) {
336
            return s->int_mask;
337
        }
338
        return s->cr;
339
    case 8: /* LCDRIS */
340
        return s->int_status;
341
    case 9: /* LCDMIS */
342
        return s->int_status & s->int_mask;
343
    case 11: /* LCDUPCURR */
344
        /* TODO: Implement vertical refresh.  */
345
        return s->upbase;
346
    case 12: /* LCDLPCURR */
347
        return s->lpbase;
348
    default:
349
        hw_error("pl110_read: Bad offset %x\n", (int)offset);
350
        return 0;
351
    }
352
}
353

    
354
static void pl110_write(void *opaque, target_phys_addr_t offset,
355
                        uint64_t val, unsigned size)
356
{
357
    pl110_state *s = (pl110_state *)opaque;
358
    int n;
359

    
360
    /* For simplicity invalidate the display whenever a control register
361
       is written to.  */
362
    s->invalidate = 1;
363
    if (offset >= 0x200 && offset < 0x400) {
364
        /* Pallette.  */
365
        n = (offset - 0x200) >> 2;
366
        s->raw_pallette[(offset - 0x200) >> 2] = val;
367
        pl110_update_pallette(s, n);
368
        return;
369
    }
370
    switch (offset >> 2) {
371
    case 0: /* LCDTiming0 */
372
        s->timing[0] = val;
373
        n = ((val & 0xfc) + 4) * 4;
374
        pl110_resize(s, n, s->rows);
375
        break;
376
    case 1: /* LCDTiming1 */
377
        s->timing[1] = val;
378
        n = (val & 0x3ff) + 1;
379
        pl110_resize(s, s->cols, n);
380
        break;
381
    case 2: /* LCDTiming2 */
382
        s->timing[2] = val;
383
        break;
384
    case 3: /* LCDTiming3 */
385
        s->timing[3] = val;
386
        break;
387
    case 4: /* LCDUPBASE */
388
        s->upbase = val;
389
        break;
390
    case 5: /* LCDLPBASE */
391
        s->lpbase = val;
392
        break;
393
    case 6: /* LCDIMSC */
394
        if (s->version != PL110) {
395
            goto control;
396
        }
397
    imsc:
398
        s->int_mask = val;
399
        pl110_update(s);
400
        break;
401
    case 7: /* LCDControl */
402
        if (s->version != PL110) {
403
            goto imsc;
404
        }
405
    control:
406
        s->cr = val;
407
        s->bpp = (val >> 1) & 7;
408
        if (pl110_enabled(s)) {
409
            qemu_console_resize(s->ds, s->cols, s->rows);
410
        }
411
        break;
412
    case 10: /* LCDICR */
413
        s->int_status &= ~val;
414
        pl110_update(s);
415
        break;
416
    default:
417
        hw_error("pl110_write: Bad offset %x\n", (int)offset);
418
    }
419
}
420

    
421
static const MemoryRegionOps pl110_ops = {
422
    .read = pl110_read,
423
    .write = pl110_write,
424
    .endianness = DEVICE_NATIVE_ENDIAN,
425
};
426

    
427
static void pl110_mux_ctrl_set(void *opaque, int line, int level)
428
{
429
    pl110_state *s = (pl110_state *)opaque;
430
    s->mux_ctrl = level;
431
}
432

    
433
static int pl110_init(SysBusDevice *dev)
434
{
435
    pl110_state *s = FROM_SYSBUS(pl110_state, dev);
436

    
437
    memory_region_init_io(&s->iomem, &pl110_ops, s, "pl110", 0x1000);
438
    sysbus_init_mmio(dev, &s->iomem);
439
    sysbus_init_irq(dev, &s->irq);
440
    qdev_init_gpio_in(&s->busdev.qdev, pl110_mux_ctrl_set, 1);
441
    s->ds = graphic_console_init(pl110_update_display,
442
                                 pl110_invalidate_display,
443
                                 NULL, NULL, s);
444
    return 0;
445
}
446

    
447
static int pl110_versatile_init(SysBusDevice *dev)
448
{
449
    pl110_state *s = FROM_SYSBUS(pl110_state, dev);
450
    s->version = PL110_VERSATILE;
451
    return pl110_init(dev);
452
}
453

    
454
static int pl111_init(SysBusDevice *dev)
455
{
456
    pl110_state *s = FROM_SYSBUS(pl110_state, dev);
457
    s->version = PL111;
458
    return pl110_init(dev);
459
}
460

    
461
static SysBusDeviceInfo pl110_info = {
462
    .init = pl110_init,
463
    .qdev.name = "pl110",
464
    .qdev.size = sizeof(pl110_state),
465
    .qdev.vmsd = &vmstate_pl110,
466
    .qdev.no_user = 1,
467
};
468

    
469
static SysBusDeviceInfo pl110_versatile_info = {
470
    .init = pl110_versatile_init,
471
    .qdev.name = "pl110_versatile",
472
    .qdev.size = sizeof(pl110_state),
473
    .qdev.vmsd = &vmstate_pl110,
474
    .qdev.no_user = 1,
475
};
476

    
477
static SysBusDeviceInfo pl111_info = {
478
    .init = pl111_init,
479
    .qdev.name = "pl111",
480
    .qdev.size = sizeof(pl110_state),
481
    .qdev.vmsd = &vmstate_pl110,
482
    .qdev.no_user = 1,
483
};
484

    
485
static void pl110_register_devices(void)
486
{
487
    sysbus_register_withprop(&pl110_info);
488
    sysbus_register_withprop(&pl110_versatile_info);
489
    sysbus_register_withprop(&pl111_info);
490
}
491

    
492
device_init(pl110_register_devices)