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1 | 6af0bf9c | bellard | #if !defined (__MIPS_CPU_H__)
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2 | 6af0bf9c | bellard | #define __MIPS_CPU_H__
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3 | 6af0bf9c | bellard | |
4 | 4ad40f36 | bellard | #define TARGET_HAS_ICE 1 |
5 | 4ad40f36 | bellard | |
6 | 9042c0e2 | ths | #define ELF_MACHINE EM_MIPS
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7 | 9042c0e2 | ths | |
8 | c2764719 | pbrook | #define CPUState struct CPUMIPSState |
9 | c2764719 | pbrook | |
10 | c5d6edc3 | bellard | #include "config.h" |
11 | 6af0bf9c | bellard | #include "mips-defs.h" |
12 | 6af0bf9c | bellard | #include "cpu-defs.h" |
13 | 6af0bf9c | bellard | #include "softfloat.h" |
14 | 6af0bf9c | bellard | |
15 | fdbb4691 | bellard | // uint_fast8_t and uint_fast16_t not in <sys/int_types.h>
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16 | fdbb4691 | bellard | // XXX: move that elsewhere
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17 | dfe5fff3 | Juan Quintela | #if defined(CONFIG_SOLARIS) && CONFIG_SOLARIS_VERSION < 10 |
18 | fdbb4691 | bellard | typedef unsigned char uint_fast8_t; |
19 | fdbb4691 | bellard | typedef unsigned int uint_fast16_t; |
20 | fdbb4691 | bellard | #endif
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21 | fdbb4691 | bellard | |
22 | ead9360e | ths | struct CPUMIPSState;
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23 | 6af0bf9c | bellard | |
24 | 29929e34 | ths | typedef struct r4k_tlb_t r4k_tlb_t; |
25 | 29929e34 | ths | struct r4k_tlb_t {
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26 | 6af0bf9c | bellard | target_ulong VPN; |
27 | 9c2149c8 | ths | uint32_t PageMask; |
28 | 98c1b82b | pbrook | uint_fast8_t ASID; |
29 | 98c1b82b | pbrook | uint_fast16_t G:1;
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30 | 98c1b82b | pbrook | uint_fast16_t C0:3;
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31 | 98c1b82b | pbrook | uint_fast16_t C1:3;
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32 | 98c1b82b | pbrook | uint_fast16_t V0:1;
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33 | 98c1b82b | pbrook | uint_fast16_t V1:1;
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34 | 98c1b82b | pbrook | uint_fast16_t D0:1;
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35 | 98c1b82b | pbrook | uint_fast16_t D1:1;
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36 | 6af0bf9c | bellard | target_ulong PFN[2];
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37 | 6af0bf9c | bellard | }; |
38 | 6af0bf9c | bellard | |
39 | ead9360e | ths | typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; |
40 | ead9360e | ths | struct CPUMIPSTLBContext {
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41 | ead9360e | ths | uint32_t nb_tlb; |
42 | ead9360e | ths | uint32_t tlb_in_use; |
43 | ead9360e | ths | int (*map_address) (struct CPUMIPSState *env, target_ulong *physical, int *prot, target_ulong address, int rw, int access_type); |
44 | c01fccd2 | aurel32 | void (*helper_tlbwi) (void); |
45 | c01fccd2 | aurel32 | void (*helper_tlbwr) (void); |
46 | c01fccd2 | aurel32 | void (*helper_tlbp) (void); |
47 | c01fccd2 | aurel32 | void (*helper_tlbr) (void); |
48 | ead9360e | ths | union {
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49 | ead9360e | ths | struct {
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50 | ead9360e | ths | r4k_tlb_t tlb[MIPS_TLB_MAX]; |
51 | ead9360e | ths | } r4k; |
52 | ead9360e | ths | } mmu; |
53 | ead9360e | ths | }; |
54 | 51b2772f | ths | |
55 | ead9360e | ths | typedef union fpr_t fpr_t; |
56 | ead9360e | ths | union fpr_t {
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57 | ead9360e | ths | float64 fd; /* ieee double precision */
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58 | ead9360e | ths | float32 fs[2];/* ieee single precision */ |
59 | ead9360e | ths | uint64_t d; /* binary double fixed-point */
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60 | ead9360e | ths | uint32_t w[2]; /* binary single fixed-point */ |
61 | ead9360e | ths | }; |
62 | ead9360e | ths | /* define FP_ENDIAN_IDX to access the same location
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63 | ead9360e | ths | * in the fpr_t union regardless of the host endianess
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64 | ead9360e | ths | */
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65 | e2542fe2 | Juan Quintela | #if defined(HOST_WORDS_BIGENDIAN)
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66 | ead9360e | ths | # define FP_ENDIAN_IDX 1 |
67 | ead9360e | ths | #else
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68 | ead9360e | ths | # define FP_ENDIAN_IDX 0 |
69 | c570fd16 | ths | #endif
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70 | ead9360e | ths | |
71 | ead9360e | ths | typedef struct CPUMIPSFPUContext CPUMIPSFPUContext; |
72 | ead9360e | ths | struct CPUMIPSFPUContext {
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73 | 6af0bf9c | bellard | /* Floating point registers */
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74 | f7cfb2a1 | ths | fpr_t fpr[32];
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75 | 6ea83fed | bellard | float_status fp_status; |
76 | 5a5012ec | ths | /* fpu implementation/revision register (fir) */
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77 | 6af0bf9c | bellard | uint32_t fcr0; |
78 | 5a5012ec | ths | #define FCR0_F64 22 |
79 | 5a5012ec | ths | #define FCR0_L 21 |
80 | 5a5012ec | ths | #define FCR0_W 20 |
81 | 5a5012ec | ths | #define FCR0_3D 19 |
82 | 5a5012ec | ths | #define FCR0_PS 18 |
83 | 5a5012ec | ths | #define FCR0_D 17 |
84 | 5a5012ec | ths | #define FCR0_S 16 |
85 | 5a5012ec | ths | #define FCR0_PRID 8 |
86 | 5a5012ec | ths | #define FCR0_REV 0 |
87 | 6ea83fed | bellard | /* fcsr */
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88 | 6ea83fed | bellard | uint32_t fcr31; |
89 | f01be154 | ths | #define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0) |
90 | f01be154 | ths | #define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0) |
91 | f01be154 | ths | #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1)) |
92 | 5a5012ec | ths | #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) |
93 | 5a5012ec | ths | #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) |
94 | 5a5012ec | ths | #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) |
95 | 5a5012ec | ths | #define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0) |
96 | 5a5012ec | ths | #define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0) |
97 | 5a5012ec | ths | #define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0) |
98 | 5a5012ec | ths | #define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0) |
99 | 6ea83fed | bellard | #define FP_INEXACT 1 |
100 | 6ea83fed | bellard | #define FP_UNDERFLOW 2 |
101 | 6ea83fed | bellard | #define FP_OVERFLOW 4 |
102 | 6ea83fed | bellard | #define FP_DIV0 8 |
103 | 6ea83fed | bellard | #define FP_INVALID 16 |
104 | 6ea83fed | bellard | #define FP_UNIMPLEMENTED 32 |
105 | ead9360e | ths | }; |
106 | ead9360e | ths | |
107 | 623a930e | ths | #define NB_MMU_MODES 3 |
108 | 6ebbf390 | j_mayer | |
109 | ead9360e | ths | typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; |
110 | ead9360e | ths | struct CPUMIPSMVPContext {
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111 | ead9360e | ths | int32_t CP0_MVPControl; |
112 | ead9360e | ths | #define CP0MVPCo_CPA 3 |
113 | ead9360e | ths | #define CP0MVPCo_STLB 2 |
114 | ead9360e | ths | #define CP0MVPCo_VPC 1 |
115 | ead9360e | ths | #define CP0MVPCo_EVP 0 |
116 | ead9360e | ths | int32_t CP0_MVPConf0; |
117 | ead9360e | ths | #define CP0MVPC0_M 31 |
118 | ead9360e | ths | #define CP0MVPC0_TLBS 29 |
119 | ead9360e | ths | #define CP0MVPC0_GS 28 |
120 | ead9360e | ths | #define CP0MVPC0_PCP 27 |
121 | ead9360e | ths | #define CP0MVPC0_PTLBE 16 |
122 | ead9360e | ths | #define CP0MVPC0_TCA 15 |
123 | ead9360e | ths | #define CP0MVPC0_PVPE 10 |
124 | ead9360e | ths | #define CP0MVPC0_PTC 0 |
125 | ead9360e | ths | int32_t CP0_MVPConf1; |
126 | ead9360e | ths | #define CP0MVPC1_CIM 31 |
127 | ead9360e | ths | #define CP0MVPC1_CIF 30 |
128 | ead9360e | ths | #define CP0MVPC1_PCX 20 |
129 | ead9360e | ths | #define CP0MVPC1_PCP2 10 |
130 | ead9360e | ths | #define CP0MVPC1_PCP1 0 |
131 | ead9360e | ths | }; |
132 | ead9360e | ths | |
133 | ead9360e | ths | typedef struct mips_def_t mips_def_t; |
134 | ead9360e | ths | |
135 | ead9360e | ths | #define MIPS_SHADOW_SET_MAX 16 |
136 | ead9360e | ths | #define MIPS_TC_MAX 5 |
137 | f01be154 | ths | #define MIPS_FPU_MAX 1 |
138 | ead9360e | ths | #define MIPS_DSP_ACC 4 |
139 | ead9360e | ths | |
140 | b5dc7732 | ths | typedef struct TCState TCState; |
141 | b5dc7732 | ths | struct TCState {
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142 | b5dc7732 | ths | target_ulong gpr[32];
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143 | b5dc7732 | ths | target_ulong PC; |
144 | b5dc7732 | ths | target_ulong HI[MIPS_DSP_ACC]; |
145 | b5dc7732 | ths | target_ulong LO[MIPS_DSP_ACC]; |
146 | b5dc7732 | ths | target_ulong ACX[MIPS_DSP_ACC]; |
147 | b5dc7732 | ths | target_ulong DSPControl; |
148 | b5dc7732 | ths | int32_t CP0_TCStatus; |
149 | b5dc7732 | ths | #define CP0TCSt_TCU3 31 |
150 | b5dc7732 | ths | #define CP0TCSt_TCU2 30 |
151 | b5dc7732 | ths | #define CP0TCSt_TCU1 29 |
152 | b5dc7732 | ths | #define CP0TCSt_TCU0 28 |
153 | b5dc7732 | ths | #define CP0TCSt_TMX 27 |
154 | b5dc7732 | ths | #define CP0TCSt_RNST 23 |
155 | b5dc7732 | ths | #define CP0TCSt_TDS 21 |
156 | b5dc7732 | ths | #define CP0TCSt_DT 20 |
157 | b5dc7732 | ths | #define CP0TCSt_DA 15 |
158 | b5dc7732 | ths | #define CP0TCSt_A 13 |
159 | b5dc7732 | ths | #define CP0TCSt_TKSU 11 |
160 | b5dc7732 | ths | #define CP0TCSt_IXMT 10 |
161 | b5dc7732 | ths | #define CP0TCSt_TASID 0 |
162 | b5dc7732 | ths | int32_t CP0_TCBind; |
163 | b5dc7732 | ths | #define CP0TCBd_CurTC 21 |
164 | b5dc7732 | ths | #define CP0TCBd_TBE 17 |
165 | b5dc7732 | ths | #define CP0TCBd_CurVPE 0 |
166 | b5dc7732 | ths | target_ulong CP0_TCHalt; |
167 | b5dc7732 | ths | target_ulong CP0_TCContext; |
168 | b5dc7732 | ths | target_ulong CP0_TCSchedule; |
169 | b5dc7732 | ths | target_ulong CP0_TCScheFBack; |
170 | b5dc7732 | ths | int32_t CP0_Debug_tcstatus; |
171 | b5dc7732 | ths | }; |
172 | b5dc7732 | ths | |
173 | ead9360e | ths | typedef struct CPUMIPSState CPUMIPSState; |
174 | ead9360e | ths | struct CPUMIPSState {
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175 | b5dc7732 | ths | TCState active_tc; |
176 | f01be154 | ths | CPUMIPSFPUContext active_fpu; |
177 | b5dc7732 | ths | |
178 | ead9360e | ths | CPUMIPSMVPContext *mvp; |
179 | ead9360e | ths | CPUMIPSTLBContext *tlb; |
180 | ead9360e | ths | uint32_t current_tc; |
181 | f01be154 | ths | uint32_t current_fpu; |
182 | 36d23958 | ths | |
183 | e034e2c3 | ths | uint32_t SEGBITS; |
184 | 6d35524c | ths | uint32_t PABITS; |
185 | b6d96bed | ths | target_ulong SEGMask; |
186 | 6d35524c | ths | target_ulong PAMask; |
187 | 29929e34 | ths | |
188 | 9c2149c8 | ths | int32_t CP0_Index; |
189 | ead9360e | ths | /* CP0_MVP* are per MVP registers. */
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190 | 9c2149c8 | ths | int32_t CP0_Random; |
191 | ead9360e | ths | int32_t CP0_VPEControl; |
192 | ead9360e | ths | #define CP0VPECo_YSI 21 |
193 | ead9360e | ths | #define CP0VPECo_GSI 20 |
194 | ead9360e | ths | #define CP0VPECo_EXCPT 16 |
195 | ead9360e | ths | #define CP0VPECo_TE 15 |
196 | ead9360e | ths | #define CP0VPECo_TargTC 0 |
197 | ead9360e | ths | int32_t CP0_VPEConf0; |
198 | ead9360e | ths | #define CP0VPEC0_M 31 |
199 | ead9360e | ths | #define CP0VPEC0_XTC 21 |
200 | ead9360e | ths | #define CP0VPEC0_TCS 19 |
201 | ead9360e | ths | #define CP0VPEC0_SCS 18 |
202 | ead9360e | ths | #define CP0VPEC0_DSC 17 |
203 | ead9360e | ths | #define CP0VPEC0_ICS 16 |
204 | ead9360e | ths | #define CP0VPEC0_MVP 1 |
205 | ead9360e | ths | #define CP0VPEC0_VPA 0 |
206 | ead9360e | ths | int32_t CP0_VPEConf1; |
207 | ead9360e | ths | #define CP0VPEC1_NCX 20 |
208 | ead9360e | ths | #define CP0VPEC1_NCP2 10 |
209 | ead9360e | ths | #define CP0VPEC1_NCP1 0 |
210 | ead9360e | ths | target_ulong CP0_YQMask; |
211 | ead9360e | ths | target_ulong CP0_VPESchedule; |
212 | ead9360e | ths | target_ulong CP0_VPEScheFBack; |
213 | ead9360e | ths | int32_t CP0_VPEOpt; |
214 | ead9360e | ths | #define CP0VPEOpt_IWX7 15 |
215 | ead9360e | ths | #define CP0VPEOpt_IWX6 14 |
216 | ead9360e | ths | #define CP0VPEOpt_IWX5 13 |
217 | ead9360e | ths | #define CP0VPEOpt_IWX4 12 |
218 | ead9360e | ths | #define CP0VPEOpt_IWX3 11 |
219 | ead9360e | ths | #define CP0VPEOpt_IWX2 10 |
220 | ead9360e | ths | #define CP0VPEOpt_IWX1 9 |
221 | ead9360e | ths | #define CP0VPEOpt_IWX0 8 |
222 | ead9360e | ths | #define CP0VPEOpt_DWX7 7 |
223 | ead9360e | ths | #define CP0VPEOpt_DWX6 6 |
224 | ead9360e | ths | #define CP0VPEOpt_DWX5 5 |
225 | ead9360e | ths | #define CP0VPEOpt_DWX4 4 |
226 | ead9360e | ths | #define CP0VPEOpt_DWX3 3 |
227 | ead9360e | ths | #define CP0VPEOpt_DWX2 2 |
228 | ead9360e | ths | #define CP0VPEOpt_DWX1 1 |
229 | ead9360e | ths | #define CP0VPEOpt_DWX0 0 |
230 | 9c2149c8 | ths | target_ulong CP0_EntryLo0; |
231 | 9c2149c8 | ths | target_ulong CP0_EntryLo1; |
232 | 9c2149c8 | ths | target_ulong CP0_Context; |
233 | 9c2149c8 | ths | int32_t CP0_PageMask; |
234 | 9c2149c8 | ths | int32_t CP0_PageGrain; |
235 | 9c2149c8 | ths | int32_t CP0_Wired; |
236 | ead9360e | ths | int32_t CP0_SRSConf0_rw_bitmask; |
237 | ead9360e | ths | int32_t CP0_SRSConf0; |
238 | ead9360e | ths | #define CP0SRSC0_M 31 |
239 | ead9360e | ths | #define CP0SRSC0_SRS3 20 |
240 | ead9360e | ths | #define CP0SRSC0_SRS2 10 |
241 | ead9360e | ths | #define CP0SRSC0_SRS1 0 |
242 | ead9360e | ths | int32_t CP0_SRSConf1_rw_bitmask; |
243 | ead9360e | ths | int32_t CP0_SRSConf1; |
244 | ead9360e | ths | #define CP0SRSC1_M 31 |
245 | ead9360e | ths | #define CP0SRSC1_SRS6 20 |
246 | ead9360e | ths | #define CP0SRSC1_SRS5 10 |
247 | ead9360e | ths | #define CP0SRSC1_SRS4 0 |
248 | ead9360e | ths | int32_t CP0_SRSConf2_rw_bitmask; |
249 | ead9360e | ths | int32_t CP0_SRSConf2; |
250 | ead9360e | ths | #define CP0SRSC2_M 31 |
251 | ead9360e | ths | #define CP0SRSC2_SRS9 20 |
252 | ead9360e | ths | #define CP0SRSC2_SRS8 10 |
253 | ead9360e | ths | #define CP0SRSC2_SRS7 0 |
254 | ead9360e | ths | int32_t CP0_SRSConf3_rw_bitmask; |
255 | ead9360e | ths | int32_t CP0_SRSConf3; |
256 | ead9360e | ths | #define CP0SRSC3_M 31 |
257 | ead9360e | ths | #define CP0SRSC3_SRS12 20 |
258 | ead9360e | ths | #define CP0SRSC3_SRS11 10 |
259 | ead9360e | ths | #define CP0SRSC3_SRS10 0 |
260 | ead9360e | ths | int32_t CP0_SRSConf4_rw_bitmask; |
261 | ead9360e | ths | int32_t CP0_SRSConf4; |
262 | ead9360e | ths | #define CP0SRSC4_SRS15 20 |
263 | ead9360e | ths | #define CP0SRSC4_SRS14 10 |
264 | ead9360e | ths | #define CP0SRSC4_SRS13 0 |
265 | 9c2149c8 | ths | int32_t CP0_HWREna; |
266 | c570fd16 | ths | target_ulong CP0_BadVAddr; |
267 | 9c2149c8 | ths | int32_t CP0_Count; |
268 | 9c2149c8 | ths | target_ulong CP0_EntryHi; |
269 | 9c2149c8 | ths | int32_t CP0_Compare; |
270 | 9c2149c8 | ths | int32_t CP0_Status; |
271 | 6af0bf9c | bellard | #define CP0St_CU3 31 |
272 | 6af0bf9c | bellard | #define CP0St_CU2 30 |
273 | 6af0bf9c | bellard | #define CP0St_CU1 29 |
274 | 6af0bf9c | bellard | #define CP0St_CU0 28 |
275 | 6af0bf9c | bellard | #define CP0St_RP 27 |
276 | 6ea83fed | bellard | #define CP0St_FR 26 |
277 | 6af0bf9c | bellard | #define CP0St_RE 25 |
278 | 7a387fff | ths | #define CP0St_MX 24 |
279 | 7a387fff | ths | #define CP0St_PX 23 |
280 | 6af0bf9c | bellard | #define CP0St_BEV 22 |
281 | 6af0bf9c | bellard | #define CP0St_TS 21 |
282 | 6af0bf9c | bellard | #define CP0St_SR 20 |
283 | 6af0bf9c | bellard | #define CP0St_NMI 19 |
284 | 6af0bf9c | bellard | #define CP0St_IM 8 |
285 | 7a387fff | ths | #define CP0St_KX 7 |
286 | 7a387fff | ths | #define CP0St_SX 6 |
287 | 7a387fff | ths | #define CP0St_UX 5 |
288 | 623a930e | ths | #define CP0St_KSU 3 |
289 | 6af0bf9c | bellard | #define CP0St_ERL 2 |
290 | 6af0bf9c | bellard | #define CP0St_EXL 1 |
291 | 6af0bf9c | bellard | #define CP0St_IE 0 |
292 | 9c2149c8 | ths | int32_t CP0_IntCtl; |
293 | ead9360e | ths | #define CP0IntCtl_IPTI 29 |
294 | ead9360e | ths | #define CP0IntCtl_IPPC1 26 |
295 | ead9360e | ths | #define CP0IntCtl_VS 5 |
296 | 9c2149c8 | ths | int32_t CP0_SRSCtl; |
297 | ead9360e | ths | #define CP0SRSCtl_HSS 26 |
298 | ead9360e | ths | #define CP0SRSCtl_EICSS 18 |
299 | ead9360e | ths | #define CP0SRSCtl_ESS 12 |
300 | ead9360e | ths | #define CP0SRSCtl_PSS 6 |
301 | ead9360e | ths | #define CP0SRSCtl_CSS 0 |
302 | 9c2149c8 | ths | int32_t CP0_SRSMap; |
303 | ead9360e | ths | #define CP0SRSMap_SSV7 28 |
304 | ead9360e | ths | #define CP0SRSMap_SSV6 24 |
305 | ead9360e | ths | #define CP0SRSMap_SSV5 20 |
306 | ead9360e | ths | #define CP0SRSMap_SSV4 16 |
307 | ead9360e | ths | #define CP0SRSMap_SSV3 12 |
308 | ead9360e | ths | #define CP0SRSMap_SSV2 8 |
309 | ead9360e | ths | #define CP0SRSMap_SSV1 4 |
310 | ead9360e | ths | #define CP0SRSMap_SSV0 0 |
311 | 9c2149c8 | ths | int32_t CP0_Cause; |
312 | 7a387fff | ths | #define CP0Ca_BD 31 |
313 | 7a387fff | ths | #define CP0Ca_TI 30 |
314 | 7a387fff | ths | #define CP0Ca_CE 28 |
315 | 7a387fff | ths | #define CP0Ca_DC 27 |
316 | 7a387fff | ths | #define CP0Ca_PCI 26 |
317 | 6af0bf9c | bellard | #define CP0Ca_IV 23 |
318 | 7a387fff | ths | #define CP0Ca_WP 22 |
319 | 7a387fff | ths | #define CP0Ca_IP 8 |
320 | 4de9b249 | ths | #define CP0Ca_IP_mask 0x0000FF00 |
321 | 7a387fff | ths | #define CP0Ca_EC 2 |
322 | c570fd16 | ths | target_ulong CP0_EPC; |
323 | 9c2149c8 | ths | int32_t CP0_PRid; |
324 | b29a0341 | ths | int32_t CP0_EBase; |
325 | 9c2149c8 | ths | int32_t CP0_Config0; |
326 | 6af0bf9c | bellard | #define CP0C0_M 31 |
327 | 6af0bf9c | bellard | #define CP0C0_K23 28 |
328 | 6af0bf9c | bellard | #define CP0C0_KU 25 |
329 | 6af0bf9c | bellard | #define CP0C0_MDU 20 |
330 | 6af0bf9c | bellard | #define CP0C0_MM 17 |
331 | 6af0bf9c | bellard | #define CP0C0_BM 16 |
332 | 6af0bf9c | bellard | #define CP0C0_BE 15 |
333 | 6af0bf9c | bellard | #define CP0C0_AT 13 |
334 | 6af0bf9c | bellard | #define CP0C0_AR 10 |
335 | 6af0bf9c | bellard | #define CP0C0_MT 7 |
336 | 7a387fff | ths | #define CP0C0_VI 3 |
337 | 6af0bf9c | bellard | #define CP0C0_K0 0 |
338 | 9c2149c8 | ths | int32_t CP0_Config1; |
339 | 7a387fff | ths | #define CP0C1_M 31 |
340 | 6af0bf9c | bellard | #define CP0C1_MMU 25 |
341 | 6af0bf9c | bellard | #define CP0C1_IS 22 |
342 | 6af0bf9c | bellard | #define CP0C1_IL 19 |
343 | 6af0bf9c | bellard | #define CP0C1_IA 16 |
344 | 6af0bf9c | bellard | #define CP0C1_DS 13 |
345 | 6af0bf9c | bellard | #define CP0C1_DL 10 |
346 | 6af0bf9c | bellard | #define CP0C1_DA 7 |
347 | 7a387fff | ths | #define CP0C1_C2 6 |
348 | 7a387fff | ths | #define CP0C1_MD 5 |
349 | 6af0bf9c | bellard | #define CP0C1_PC 4 |
350 | 6af0bf9c | bellard | #define CP0C1_WR 3 |
351 | 6af0bf9c | bellard | #define CP0C1_CA 2 |
352 | 6af0bf9c | bellard | #define CP0C1_EP 1 |
353 | 6af0bf9c | bellard | #define CP0C1_FP 0 |
354 | 9c2149c8 | ths | int32_t CP0_Config2; |
355 | 7a387fff | ths | #define CP0C2_M 31 |
356 | 7a387fff | ths | #define CP0C2_TU 28 |
357 | 7a387fff | ths | #define CP0C2_TS 24 |
358 | 7a387fff | ths | #define CP0C2_TL 20 |
359 | 7a387fff | ths | #define CP0C2_TA 16 |
360 | 7a387fff | ths | #define CP0C2_SU 12 |
361 | 7a387fff | ths | #define CP0C2_SS 8 |
362 | 7a387fff | ths | #define CP0C2_SL 4 |
363 | 7a387fff | ths | #define CP0C2_SA 0 |
364 | 9c2149c8 | ths | int32_t CP0_Config3; |
365 | 7a387fff | ths | #define CP0C3_M 31 |
366 | 7a387fff | ths | #define CP0C3_DSPP 10 |
367 | 7a387fff | ths | #define CP0C3_LPA 7 |
368 | 7a387fff | ths | #define CP0C3_VEIC 6 |
369 | 7a387fff | ths | #define CP0C3_VInt 5 |
370 | 7a387fff | ths | #define CP0C3_SP 4 |
371 | 7a387fff | ths | #define CP0C3_MT 2 |
372 | 7a387fff | ths | #define CP0C3_SM 1 |
373 | 7a387fff | ths | #define CP0C3_TL 0 |
374 | e397ee33 | ths | int32_t CP0_Config6; |
375 | e397ee33 | ths | int32_t CP0_Config7; |
376 | ead9360e | ths | /* XXX: Maybe make LLAddr per-TC? */
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377 | c570fd16 | ths | target_ulong CP0_LLAddr; |
378 | 590bc601 | Paul Brook | target_ulong llval; |
379 | 590bc601 | Paul Brook | target_ulong llnewval; |
380 | 590bc601 | Paul Brook | target_ulong llreg; |
381 | fd88b6ab | ths | target_ulong CP0_WatchLo[8];
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382 | fd88b6ab | ths | int32_t CP0_WatchHi[8];
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383 | 9c2149c8 | ths | target_ulong CP0_XContext; |
384 | 9c2149c8 | ths | int32_t CP0_Framemask; |
385 | 9c2149c8 | ths | int32_t CP0_Debug; |
386 | ead9360e | ths | #define CP0DB_DBD 31 |
387 | 6af0bf9c | bellard | #define CP0DB_DM 30 |
388 | 6af0bf9c | bellard | #define CP0DB_LSNM 28 |
389 | 6af0bf9c | bellard | #define CP0DB_Doze 27 |
390 | 6af0bf9c | bellard | #define CP0DB_Halt 26 |
391 | 6af0bf9c | bellard | #define CP0DB_CNT 25 |
392 | 6af0bf9c | bellard | #define CP0DB_IBEP 24 |
393 | 6af0bf9c | bellard | #define CP0DB_DBEP 21 |
394 | 6af0bf9c | bellard | #define CP0DB_IEXI 20 |
395 | 6af0bf9c | bellard | #define CP0DB_VER 15 |
396 | 6af0bf9c | bellard | #define CP0DB_DEC 10 |
397 | 6af0bf9c | bellard | #define CP0DB_SSt 8 |
398 | 6af0bf9c | bellard | #define CP0DB_DINT 5 |
399 | 6af0bf9c | bellard | #define CP0DB_DIB 4 |
400 | 6af0bf9c | bellard | #define CP0DB_DDBS 3 |
401 | 6af0bf9c | bellard | #define CP0DB_DDBL 2 |
402 | 6af0bf9c | bellard | #define CP0DB_DBp 1 |
403 | 6af0bf9c | bellard | #define CP0DB_DSS 0 |
404 | c570fd16 | ths | target_ulong CP0_DEPC; |
405 | 9c2149c8 | ths | int32_t CP0_Performance0; |
406 | 9c2149c8 | ths | int32_t CP0_TagLo; |
407 | 9c2149c8 | ths | int32_t CP0_DataLo; |
408 | 9c2149c8 | ths | int32_t CP0_TagHi; |
409 | 9c2149c8 | ths | int32_t CP0_DataHi; |
410 | c570fd16 | ths | target_ulong CP0_ErrorEPC; |
411 | 9c2149c8 | ths | int32_t CP0_DESAVE; |
412 | b5dc7732 | ths | /* We waste some space so we can handle shadow registers like TCs. */
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413 | b5dc7732 | ths | TCState tcs[MIPS_SHADOW_SET_MAX]; |
414 | f01be154 | ths | CPUMIPSFPUContext fpus[MIPS_FPU_MAX]; |
415 | 6af0bf9c | bellard | /* Qemu */
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416 | 6af0bf9c | bellard | int error_code;
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417 | 6af0bf9c | bellard | uint32_t hflags; /* CPU State */
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418 | 6af0bf9c | bellard | /* TMASK defines different execution modes */
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419 | 2623c1ec | aurel32 | #define MIPS_HFLAG_TMASK 0x03FF |
420 | 78749ba8 | ths | #define MIPS_HFLAG_MODE 0x0007 /* execution modes */ |
421 | 623a930e | ths | /* The KSU flags must be the lowest bits in hflags. The flag order
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422 | 623a930e | ths | must be the same as defined for CP0 Status. This allows to use
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423 | 623a930e | ths | the bits as the value of mmu_idx. */
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424 | 623a930e | ths | #define MIPS_HFLAG_KSU 0x0003 /* kernel/supervisor/user mode mask */ |
425 | 623a930e | ths | #define MIPS_HFLAG_UM 0x0002 /* user mode flag */ |
426 | 623a930e | ths | #define MIPS_HFLAG_SM 0x0001 /* supervisor mode flag */ |
427 | 623a930e | ths | #define MIPS_HFLAG_KM 0x0000 /* kernel mode flag */ |
428 | 623a930e | ths | #define MIPS_HFLAG_DM 0x0004 /* Debug mode */ |
429 | 5e755519 | ths | #define MIPS_HFLAG_64 0x0008 /* 64-bit instructions enabled */ |
430 | 387a8fe5 | ths | #define MIPS_HFLAG_CP0 0x0010 /* CP0 enabled */ |
431 | 387a8fe5 | ths | #define MIPS_HFLAG_FPU 0x0020 /* FPU enabled */ |
432 | 387a8fe5 | ths | #define MIPS_HFLAG_F64 0x0040 /* 64-bit FPU enabled */ |
433 | b8aa4598 | ths | /* True if the MIPS IV COP1X instructions can be used. This also
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434 | b8aa4598 | ths | controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
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435 | b8aa4598 | ths | and RSQRT.D. */
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436 | b8aa4598 | ths | #define MIPS_HFLAG_COP1X 0x0080 /* COP1X instructions enabled */ |
437 | b8aa4598 | ths | #define MIPS_HFLAG_RE 0x0100 /* Reversed endianness */ |
438 | 2623c1ec | aurel32 | #define MIPS_HFLAG_UX 0x0200 /* 64-bit user mode */ |
439 | 4ad40f36 | bellard | /* If translation is interrupted between the branch instruction and
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440 | 4ad40f36 | bellard | * the delay slot, record what type of branch it is so that we can
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441 | 4ad40f36 | bellard | * resume translation properly. It might be possible to reduce
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442 | 4ad40f36 | bellard | * this from three bits to two. */
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443 | 2623c1ec | aurel32 | #define MIPS_HFLAG_BMASK 0x1C00 |
444 | 2623c1ec | aurel32 | #define MIPS_HFLAG_B 0x0400 /* Unconditional branch */ |
445 | 2623c1ec | aurel32 | #define MIPS_HFLAG_BC 0x0800 /* Conditional branch */ |
446 | 2623c1ec | aurel32 | #define MIPS_HFLAG_BL 0x0C00 /* Likely branch */ |
447 | 2623c1ec | aurel32 | #define MIPS_HFLAG_BR 0x1000 /* branch to register (can't link TB) */ |
448 | 6af0bf9c | bellard | target_ulong btarget; /* Jump / branch target */
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449 | 1ba74fb8 | aurel32 | target_ulong bcond; /* Branch condition (if needed) */
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450 | a316d335 | bellard | |
451 | 7a387fff | ths | int SYNCI_Step; /* Address step size for SYNCI */ |
452 | 7a387fff | ths | int CCRes; /* Cycle count resolution/divisor */ |
453 | ead9360e | ths | uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
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454 | ead9360e | ths | uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
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455 | e189e748 | ths | int insn_flags; /* Supported instruction set */ |
456 | 7a387fff | ths | |
457 | 0eaef5aa | ths | target_ulong tls_value; /* For usermode emulation */
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458 | 6f5b89a0 | ths | |
459 | a316d335 | bellard | CPU_COMMON |
460 | 6ae81775 | ths | |
461 | aaed909a | bellard | const mips_def_t *cpu_model;
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462 | 33ac7f16 | ths | void *irq[8]; |
463 | 6ae81775 | ths | struct QEMUTimer *timer; /* Internal timer */ |
464 | 6af0bf9c | bellard | }; |
465 | 6af0bf9c | bellard | |
466 | 29929e34 | ths | int no_mmu_map_address (CPUMIPSState *env, target_ulong *physical, int *prot, |
467 | 29929e34 | ths | target_ulong address, int rw, int access_type); |
468 | 29929e34 | ths | int fixed_mmu_map_address (CPUMIPSState *env, target_ulong *physical, int *prot, |
469 | 29929e34 | ths | target_ulong address, int rw, int access_type); |
470 | 29929e34 | ths | int r4k_map_address (CPUMIPSState *env, target_ulong *physical, int *prot, |
471 | 29929e34 | ths | target_ulong address, int rw, int access_type); |
472 | c01fccd2 | aurel32 | void r4k_helper_tlbwi (void); |
473 | c01fccd2 | aurel32 | void r4k_helper_tlbwr (void); |
474 | c01fccd2 | aurel32 | void r4k_helper_tlbp (void); |
475 | c01fccd2 | aurel32 | void r4k_helper_tlbr (void); |
476 | 33d68b5f | ths | void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
477 | 33d68b5f | ths | |
478 | 647de6ca | ths | void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
479 | e18231a3 | blueswir1 | int unused, int size); |
480 | 647de6ca | ths | |
481 | 9467d44c | ths | #define cpu_init cpu_mips_init
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482 | 9467d44c | ths | #define cpu_exec cpu_mips_exec
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483 | 9467d44c | ths | #define cpu_gen_code cpu_mips_gen_code
|
484 | 9467d44c | ths | #define cpu_signal_handler cpu_mips_signal_handler
|
485 | c732abe2 | j_mayer | #define cpu_list mips_cpu_list
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486 | 9467d44c | ths | |
487 | b3c7724c | pbrook | #define CPU_SAVE_VERSION 3 |
488 | b3c7724c | pbrook | |
489 | 623a930e | ths | /* MMU modes definitions. We carefully match the indices with our
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490 | 623a930e | ths | hflags layout. */
|
491 | 6ebbf390 | j_mayer | #define MMU_MODE0_SUFFIX _kernel
|
492 | 623a930e | ths | #define MMU_MODE1_SUFFIX _super
|
493 | 623a930e | ths | #define MMU_MODE2_SUFFIX _user
|
494 | 623a930e | ths | #define MMU_USER_IDX 2 |
495 | 6ebbf390 | j_mayer | static inline int cpu_mmu_index (CPUState *env) |
496 | 6ebbf390 | j_mayer | { |
497 | 623a930e | ths | return env->hflags & MIPS_HFLAG_KSU;
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498 | 6ebbf390 | j_mayer | } |
499 | 6ebbf390 | j_mayer | |
500 | 6e68e076 | pbrook | static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) |
501 | 6e68e076 | pbrook | { |
502 | f8ed7070 | pbrook | if (newsp)
|
503 | b5dc7732 | ths | env->active_tc.gpr[29] = newsp;
|
504 | b5dc7732 | ths | env->active_tc.gpr[7] = 0; |
505 | b5dc7732 | ths | env->active_tc.gpr[2] = 0; |
506 | 6e68e076 | pbrook | } |
507 | 6e68e076 | pbrook | |
508 | 6af0bf9c | bellard | #include "cpu-all.h" |
509 | 622ed360 | aliguori | #include "exec-all.h" |
510 | 6af0bf9c | bellard | |
511 | 6af0bf9c | bellard | /* Memory access type :
|
512 | 6af0bf9c | bellard | * may be needed for precise access rights control and precise exceptions.
|
513 | 6af0bf9c | bellard | */
|
514 | 6af0bf9c | bellard | enum {
|
515 | 6af0bf9c | bellard | /* 1 bit to define user level / supervisor access */
|
516 | 6af0bf9c | bellard | ACCESS_USER = 0x00,
|
517 | 6af0bf9c | bellard | ACCESS_SUPER = 0x01,
|
518 | 6af0bf9c | bellard | /* 1 bit to indicate direction */
|
519 | 6af0bf9c | bellard | ACCESS_STORE = 0x02,
|
520 | 6af0bf9c | bellard | /* Type of instruction that generated the access */
|
521 | 6af0bf9c | bellard | ACCESS_CODE = 0x10, /* Code fetch access */ |
522 | 6af0bf9c | bellard | ACCESS_INT = 0x20, /* Integer load/store access */ |
523 | 6af0bf9c | bellard | ACCESS_FLOAT = 0x30, /* floating point load/store access */ |
524 | 6af0bf9c | bellard | }; |
525 | 6af0bf9c | bellard | |
526 | 6af0bf9c | bellard | /* Exceptions */
|
527 | 6af0bf9c | bellard | enum {
|
528 | 6af0bf9c | bellard | EXCP_NONE = -1,
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529 | 6af0bf9c | bellard | EXCP_RESET = 0,
|
530 | 6af0bf9c | bellard | EXCP_SRESET, |
531 | 6af0bf9c | bellard | EXCP_DSS, |
532 | 6af0bf9c | bellard | EXCP_DINT, |
533 | 14e51cc7 | ths | EXCP_DDBL, |
534 | 14e51cc7 | ths | EXCP_DDBS, |
535 | 6af0bf9c | bellard | EXCP_NMI, |
536 | 6af0bf9c | bellard | EXCP_MCHECK, |
537 | 14e51cc7 | ths | EXCP_EXT_INTERRUPT, /* 8 */
|
538 | 6af0bf9c | bellard | EXCP_DFWATCH, |
539 | 14e51cc7 | ths | EXCP_DIB, |
540 | 6af0bf9c | bellard | EXCP_IWATCH, |
541 | 6af0bf9c | bellard | EXCP_AdEL, |
542 | 6af0bf9c | bellard | EXCP_AdES, |
543 | 6af0bf9c | bellard | EXCP_TLBF, |
544 | 6af0bf9c | bellard | EXCP_IBE, |
545 | 14e51cc7 | ths | EXCP_DBp, /* 16 */
|
546 | 6af0bf9c | bellard | EXCP_SYSCALL, |
547 | 14e51cc7 | ths | EXCP_BREAK, |
548 | 4ad40f36 | bellard | EXCP_CpU, |
549 | 6af0bf9c | bellard | EXCP_RI, |
550 | 6af0bf9c | bellard | EXCP_OVERFLOW, |
551 | 6af0bf9c | bellard | EXCP_TRAP, |
552 | 5a5012ec | ths | EXCP_FPE, |
553 | 14e51cc7 | ths | EXCP_DWATCH, /* 24 */
|
554 | 6af0bf9c | bellard | EXCP_LTLBL, |
555 | 6af0bf9c | bellard | EXCP_TLBL, |
556 | 6af0bf9c | bellard | EXCP_TLBS, |
557 | 6af0bf9c | bellard | EXCP_DBE, |
558 | ead9360e | ths | EXCP_THREAD, |
559 | 14e51cc7 | ths | EXCP_MDMX, |
560 | 14e51cc7 | ths | EXCP_C2E, |
561 | 14e51cc7 | ths | EXCP_CACHE, /* 32 */
|
562 | 14e51cc7 | ths | |
563 | 14e51cc7 | ths | EXCP_LAST = EXCP_CACHE, |
564 | 6af0bf9c | bellard | }; |
565 | 590bc601 | Paul Brook | /* Dummy exception for conditional stores. */
|
566 | 590bc601 | Paul Brook | #define EXCP_SC 0x100 |
567 | 6af0bf9c | bellard | |
568 | 6af0bf9c | bellard | int cpu_mips_exec(CPUMIPSState *s);
|
569 | aaed909a | bellard | CPUMIPSState *cpu_mips_init(const char *cpu_model); |
570 | f9480ffc | ths | //~ uint32_t cpu_mips_get_clock (void);
|
571 | 388bb21a | ths | int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); |
572 | 6af0bf9c | bellard | |
573 | f9480ffc | ths | /* mips_timer.c */
|
574 | f9480ffc | ths | uint32_t cpu_mips_get_random (CPUState *env); |
575 | f9480ffc | ths | uint32_t cpu_mips_get_count (CPUState *env); |
576 | f9480ffc | ths | void cpu_mips_store_count (CPUState *env, uint32_t value);
|
577 | f9480ffc | ths | void cpu_mips_store_compare (CPUState *env, uint32_t value);
|
578 | f9480ffc | ths | void cpu_mips_start_count(CPUState *env);
|
579 | f9480ffc | ths | void cpu_mips_stop_count(CPUState *env);
|
580 | f9480ffc | ths | |
581 | f9480ffc | ths | /* mips_int.c */
|
582 | f9480ffc | ths | void cpu_mips_update_irq (CPUState *env);
|
583 | f9480ffc | ths | |
584 | f9480ffc | ths | /* helper.c */
|
585 | f9480ffc | ths | int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
586 | f9480ffc | ths | int mmu_idx, int is_softmmu); |
587 | 0b5c1ce8 | Nathan Froyd | #define cpu_handle_mmu_fault cpu_mips_handle_mmu_fault
|
588 | f9480ffc | ths | void do_interrupt (CPUState *env);
|
589 | f9480ffc | ths | void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra); |
590 | f9480ffc | ths | |
591 | 622ed360 | aliguori | static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) |
592 | 622ed360 | aliguori | { |
593 | 622ed360 | aliguori | env->active_tc.PC = tb->pc; |
594 | 622ed360 | aliguori | env->hflags &= ~MIPS_HFLAG_BMASK; |
595 | 622ed360 | aliguori | env->hflags |= tb->flags & MIPS_HFLAG_BMASK; |
596 | 622ed360 | aliguori | } |
597 | 2e70f6ef | pbrook | |
598 | 6b917547 | aliguori | static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
599 | 6b917547 | aliguori | target_ulong *cs_base, int *flags)
|
600 | 6b917547 | aliguori | { |
601 | 6b917547 | aliguori | *pc = env->active_tc.PC; |
602 | 6b917547 | aliguori | *cs_base = 0;
|
603 | 6b917547 | aliguori | *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK); |
604 | 6b917547 | aliguori | } |
605 | 6b917547 | aliguori | |
606 | ff867ddc | Paul Brook | static inline void cpu_set_tls(CPUState *env, target_ulong newtls) |
607 | ff867ddc | Paul Brook | { |
608 | ff867ddc | Paul Brook | env->tls_value = newtls; |
609 | ff867ddc | Paul Brook | } |
610 | ff867ddc | Paul Brook | |
611 | 6af0bf9c | bellard | #endif /* !defined (__MIPS_CPU_H__) */ |