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/*
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* QEMU SPARC iommu emulation
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h" |
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/* debug iommu */
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//#define DEBUG_IOMMU
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#ifdef DEBUG_IOMMU
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#define DPRINTF(fmt, args...) \
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do { printf("IOMMU: " fmt , ##args); } while (0) |
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#else
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#define DPRINTF(fmt, args...)
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#endif
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#define IOMMU_NREGS (3*4096/4) |
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#define IOMMU_CTRL (0x0000 >> 2) |
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#define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */ |
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#define IOMMU_CTRL_VERS 0x0f000000 /* Version */ |
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#define IOMMU_VERSION 0x04000000 |
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#define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */ |
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#define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */ |
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#define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */ |
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#define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */ |
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#define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */ |
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#define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */ |
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#define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */ |
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#define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */ |
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#define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */ |
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#define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */ |
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#define IOMMU_CTRL_MASK 0x0000001d |
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#define IOMMU_BASE (0x0004 >> 2) |
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#define IOMMU_BASE_MASK 0x07fffc00 |
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#define IOMMU_TLBFLUSH (0x0014 >> 2) |
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#define IOMMU_TLBFLUSH_MASK 0xffffffff |
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#define IOMMU_PGFLUSH (0x0018 >> 2) |
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#define IOMMU_PGFLUSH_MASK 0xffffffff |
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#define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configration per-slot */ |
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#define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */ |
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#define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */ |
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#define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configration per-slot */ |
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#define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when bypass enabled */ |
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#define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */ |
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#define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */ |
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#define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses |
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produced by this device as pure
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physical. */
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#define IOMMU_SBCFG_MASK 0x00010003 |
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#define IOMMU_ARBEN (0x2000 >> 2) /* SBUS arbitration enable */ |
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#define IOMMU_ARBEN_MASK 0x001f0000 |
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#define IOMMU_MID 0x00000008 |
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/* The format of an iopte in the page tables */
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#define IOPTE_PAGE 0x07ffff00 /* Physical page number (PA[30:12]) */ |
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#define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or Viking/MXCC) */ |
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#define IOPTE_WRITE 0x00000004 /* Writeable */ |
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#define IOPTE_VALID 0x00000002 /* IOPTE is valid */ |
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#define IOPTE_WAZ 0x00000001 /* Write as zeros */ |
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#define PAGE_SHIFT 12 |
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#define PAGE_SIZE (1 << PAGE_SHIFT) |
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#define PAGE_MASK (PAGE_SIZE - 1) |
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typedef struct IOMMUState { |
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uint32_t addr; |
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uint32_t regs[IOMMU_NREGS]; |
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uint32_t iostart; |
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} IOMMUState; |
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static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr) |
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{ |
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IOMMUState *s = opaque; |
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uint32_t saddr; |
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saddr = (addr - s->addr) >> 2;
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switch (saddr) {
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default:
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DPRINTF("read reg[%d] = %x\n", saddr, s->regs[saddr]);
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return s->regs[saddr];
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break;
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} |
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return 0; |
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} |
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static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
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{ |
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IOMMUState *s = opaque; |
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uint32_t saddr; |
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saddr = (addr - s->addr) >> 2;
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DPRINTF("write reg[%d] = %x\n", saddr, val);
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switch (saddr) {
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case IOMMU_CTRL:
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switch (val & IOMMU_CTRL_RNGE) {
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case IOMMU_RNGE_16MB:
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s->iostart = 0xff000000;
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break;
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case IOMMU_RNGE_32MB:
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s->iostart = 0xfe000000;
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break;
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case IOMMU_RNGE_64MB:
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s->iostart = 0xfc000000;
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break;
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case IOMMU_RNGE_128MB:
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s->iostart = 0xf8000000;
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break;
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case IOMMU_RNGE_256MB:
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s->iostart = 0xf0000000;
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break;
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case IOMMU_RNGE_512MB:
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s->iostart = 0xe0000000;
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break;
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case IOMMU_RNGE_1GB:
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s->iostart = 0xc0000000;
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break;
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default:
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case IOMMU_RNGE_2GB:
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s->iostart = 0x80000000;
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break;
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} |
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DPRINTF("iostart = %x\n", s->iostart);
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s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | IOMMU_VERSION); |
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break;
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case IOMMU_BASE:
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s->regs[saddr] = val & IOMMU_BASE_MASK; |
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break;
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case IOMMU_TLBFLUSH:
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DPRINTF("tlb flush %x\n", val);
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s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK; |
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break;
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case IOMMU_PGFLUSH:
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DPRINTF("page flush %x\n", val);
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s->regs[saddr] = val & IOMMU_PGFLUSH_MASK; |
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break;
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case IOMMU_SBCFG0:
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case IOMMU_SBCFG1:
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case IOMMU_SBCFG2:
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case IOMMU_SBCFG3:
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s->regs[saddr] = val & IOMMU_SBCFG_MASK; |
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break;
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case IOMMU_ARBEN:
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// XXX implement SBus probing: fault when reading unmapped
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// addresses, fault cause and address stored to MMU/IOMMU
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s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID; |
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break;
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default:
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s->regs[saddr] = val; |
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break;
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} |
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} |
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static CPUReadMemoryFunc *iommu_mem_read[3] = { |
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iommu_mem_readw, |
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iommu_mem_readw, |
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iommu_mem_readw, |
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}; |
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static CPUWriteMemoryFunc *iommu_mem_write[3] = { |
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iommu_mem_writew, |
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iommu_mem_writew, |
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iommu_mem_writew, |
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}; |
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uint32_t iommu_translate_local(void *opaque, uint32_t addr)
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{ |
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IOMMUState *s = opaque; |
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uint32_t iopte, pa, tmppte; |
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iopte = s->regs[1] << 4; |
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addr &= ~s->iostart; |
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iopte += (addr >> (PAGE_SHIFT - 2)) & ~3; |
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pa = ldl_phys(iopte); |
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tmppte = pa; |
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pa = ((pa & IOPTE_PAGE) << 4) + (addr & PAGE_MASK);
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DPRINTF("xlate dva %x => pa %x (iopte[%x] = %x)\n", addr, pa, iopte, tmppte);
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return pa;
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} |
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static void iommu_save(QEMUFile *f, void *opaque) |
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{ |
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IOMMUState *s = opaque; |
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int i;
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qemu_put_be32s(f, &s->addr); |
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for (i = 0; i < IOMMU_NREGS; i++) |
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qemu_put_be32s(f, &s->regs[i]); |
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qemu_put_be32s(f, &s->iostart); |
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} |
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static int iommu_load(QEMUFile *f, void *opaque, int version_id) |
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{ |
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IOMMUState *s = opaque; |
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int i;
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if (version_id != 1) |
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return -EINVAL;
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qemu_get_be32s(f, &s->addr); |
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for (i = 0; i < IOMMU_NREGS; i++) |
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qemu_put_be32s(f, &s->regs[i]); |
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qemu_get_be32s(f, &s->iostart); |
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return 0; |
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} |
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static void iommu_reset(void *opaque) |
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{ |
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IOMMUState *s = opaque; |
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memset(s->regs, 0, IOMMU_NREGS * 4); |
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s->iostart = 0;
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s->regs[0] = IOMMU_VERSION;
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} |
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void *iommu_init(uint32_t addr)
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{ |
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IOMMUState *s; |
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int iommu_io_memory;
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s = qemu_mallocz(sizeof(IOMMUState));
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if (!s)
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return NULL; |
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s->addr = addr; |
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iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read, iommu_mem_write, s);
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cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);
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register_savevm("iommu", addr, 1, iommu_save, iommu_load, s); |
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qemu_register_reset(iommu_reset, s); |
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return s;
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} |
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