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/*
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* OneNAND flash memories emulation.
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*
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* Copyright (C) 2008 Nokia Corporation
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* Written by Andrzej Zaborowski <andrew@openedhand.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu-common.h" |
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#include "hw.h" |
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#include "flash.h" |
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#include "irq.h" |
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#include "blockdev.h" |
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#include "memory.h" |
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#include "exec-memory.h" |
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/* 11 for 2kB-page OneNAND ("2nd generation") and 10 for 1kB-page chips */
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#define PAGE_SHIFT 11 |
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/* Fixed */
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#define BLOCK_SHIFT (PAGE_SHIFT + 6) |
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typedef struct { |
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struct {
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uint16_t man; |
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uint16_t dev; |
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uint16_t ver; |
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} id; |
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int shift;
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target_phys_addr_t base; |
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qemu_irq intr; |
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qemu_irq rdy; |
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BlockDriverState *bdrv; |
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BlockDriverState *bdrv_cur; |
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uint8_t *image; |
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uint8_t *otp; |
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uint8_t *current; |
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MemoryRegion ram; |
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MemoryRegion mapped_ram; |
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uint8_t *boot[2];
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uint8_t *data[2][2]; |
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MemoryRegion iomem; |
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MemoryRegion container; |
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int cycle;
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int otpmode;
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uint16_t addr[8];
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uint16_t unladdr[8];
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int bufaddr;
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int count;
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uint16_t command; |
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uint16_t config[2];
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uint16_t status; |
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uint16_t intstatus; |
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uint16_t wpstatus; |
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ECCState ecc; |
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int density_mask;
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int secs;
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int secs_cur;
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int blocks;
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uint8_t *blockwp; |
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} OneNANDState; |
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enum {
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ONEN_BUF_BLOCK = 0,
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ONEN_BUF_BLOCK2 = 1,
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ONEN_BUF_DEST_BLOCK = 2,
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ONEN_BUF_DEST_PAGE = 3,
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ONEN_BUF_PAGE = 7,
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}; |
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enum {
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ONEN_ERR_CMD = 1 << 10, |
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ONEN_ERR_ERASE = 1 << 11, |
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ONEN_ERR_PROG = 1 << 12, |
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ONEN_ERR_LOAD = 1 << 13, |
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}; |
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enum {
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ONEN_INT_RESET = 1 << 4, |
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ONEN_INT_ERASE = 1 << 5, |
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ONEN_INT_PROG = 1 << 6, |
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ONEN_INT_LOAD = 1 << 7, |
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ONEN_INT = 1 << 15, |
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}; |
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enum {
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ONEN_LOCK_LOCKTIGHTEN = 1 << 0, |
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ONEN_LOCK_LOCKED = 1 << 1, |
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ONEN_LOCK_UNLOCKED = 1 << 2, |
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}; |
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static void onenand_mem_setup(OneNANDState *s) |
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{ |
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/* XXX: We should use IO_MEM_ROMD but we broke it earlier...
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* Both 0x0000 ... 0x01ff and 0x8000 ... 0x800f can be used to
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* write boot commands. Also take note of the BWPS bit. */
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memory_region_init(&s->container, "onenand", 0x10000 << s->shift); |
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memory_region_add_subregion(&s->container, 0, &s->iomem);
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memory_region_init_alias(&s->mapped_ram, "onenand-mapped-ram",
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&s->ram, 0x0200 << s->shift,
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0xbe00 << s->shift);
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memory_region_add_subregion_overlap(&s->container, |
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0x0200 << s->shift,
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&s->mapped_ram, |
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1);
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} |
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void onenand_base_update(void *opaque, target_phys_addr_t new) |
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{ |
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OneNANDState *s = (OneNANDState *) opaque; |
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s->base = new; |
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memory_region_add_subregion(get_system_memory(), s->base, &s->container); |
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} |
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void onenand_base_unmap(void *opaque) |
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{ |
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OneNANDState *s = (OneNANDState *) opaque; |
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memory_region_del_subregion(get_system_memory(), &s->container); |
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} |
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static void onenand_intr_update(OneNANDState *s) |
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{ |
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qemu_set_irq(s->intr, ((s->intstatus >> 15) ^ (~s->config[0] >> 6)) & 1); |
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} |
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/* Hot reset (Reset OneNAND command) or warm reset (RP pin low) */
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static void onenand_reset(OneNANDState *s, int cold) |
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{ |
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memset(&s->addr, 0, sizeof(s->addr)); |
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s->command = 0;
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s->count = 1;
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s->bufaddr = 0;
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s->config[0] = 0x40c0; |
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s->config[1] = 0x0000; |
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onenand_intr_update(s); |
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qemu_irq_raise(s->rdy); |
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s->status = 0x0000;
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s->intstatus = cold ? 0x8080 : 0x8010; |
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s->unladdr[0] = 0; |
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s->unladdr[1] = 0; |
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s->wpstatus = 0x0002;
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s->cycle = 0;
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s->otpmode = 0;
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s->bdrv_cur = s->bdrv; |
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s->current = s->image; |
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s->secs_cur = s->secs; |
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if (cold) {
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/* Lock the whole flash */
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memset(s->blockwp, ONEN_LOCK_LOCKED, s->blocks); |
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if (s->bdrv && bdrv_read(s->bdrv, 0, s->boot[0], 8) < 0) |
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hw_error("%s: Loading the BootRAM failed.\n", __FUNCTION__);
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} |
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} |
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static inline int onenand_load_main(OneNANDState *s, int sec, int secn, |
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void *dest)
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{ |
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if (s->bdrv_cur)
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return bdrv_read(s->bdrv_cur, sec, dest, secn) < 0; |
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else if (sec + secn > s->secs_cur) |
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return 1; |
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memcpy(dest, s->current + (sec << 9), secn << 9); |
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return 0; |
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} |
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static inline int onenand_prog_main(OneNANDState *s, int sec, int secn, |
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void *src)
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{ |
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int result = 0; |
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if (secn > 0) { |
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uint32_t size = (uint32_t) secn * 512;
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const uint8_t *sp = (const uint8_t *) src; |
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uint8_t *dp = 0;
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if (s->bdrv_cur) {
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dp = g_malloc(size); |
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if (!dp || bdrv_read(s->bdrv_cur, sec, dp, secn) < 0) { |
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result = 1;
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} |
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} else {
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if (sec + secn > s->secs_cur) {
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result = 1;
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} else {
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dp = (uint8_t *) s->current + (sec << 9);
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} |
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} |
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if (!result) {
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uint32_t i; |
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for (i = 0; i < size; i++) { |
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dp[i] &= sp[i]; |
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} |
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if (s->bdrv_cur) {
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result = bdrv_write(s->bdrv_cur, sec, dp, secn) < 0;
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} |
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} |
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if (dp && s->bdrv_cur) {
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g_free(dp); |
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} |
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} |
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return result;
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} |
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static inline int onenand_load_spare(OneNANDState *s, int sec, int secn, |
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void *dest)
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{ |
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uint8_t buf[512];
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if (s->bdrv_cur) {
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if (bdrv_read(s->bdrv_cur, s->secs_cur + (sec >> 5), buf, 1) < 0) |
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return 1; |
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memcpy(dest, buf + ((sec & 31) << 4), secn << 4); |
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} else if (sec + secn > s->secs_cur) |
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return 1; |
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else
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memcpy(dest, s->current + (s->secs_cur << 9) + (sec << 4), secn << 4); |
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return 0; |
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} |
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static inline int onenand_prog_spare(OneNANDState *s, int sec, int secn, |
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void *src)
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{ |
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int result = 0; |
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if (secn > 0) { |
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const uint8_t *sp = (const uint8_t *) src; |
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uint8_t *dp = 0, *dpp = 0; |
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if (s->bdrv_cur) {
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dp = g_malloc(512);
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if (!dp || bdrv_read(s->bdrv_cur,
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s->secs_cur + (sec >> 5),
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dp, 1) < 0) { |
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result = 1;
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} else {
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dpp = dp + ((sec & 31) << 4); |
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} |
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} else {
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if (sec + secn > s->secs_cur) {
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result = 1;
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} else {
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dpp = s->current + (s->secs_cur << 9) + (sec << 4); |
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} |
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} |
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if (!result) {
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uint32_t i; |
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for (i = 0; i < (secn << 4); i++) { |
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dpp[i] &= sp[i]; |
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} |
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if (s->bdrv_cur) {
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result = bdrv_write(s->bdrv_cur, s->secs_cur + (sec >> 5),
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dp, 1) < 0; |
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} |
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} |
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if (dp) {
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g_free(dp); |
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} |
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} |
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return result;
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} |
282 |
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static inline int onenand_erase(OneNANDState *s, int sec, int num) |
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{ |
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uint8_t *blankbuf, *tmpbuf; |
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blankbuf = g_malloc(512);
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if (!blankbuf) {
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return 1; |
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} |
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tmpbuf = g_malloc(512);
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if (!tmpbuf) {
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g_free(blankbuf); |
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return 1; |
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} |
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memset(blankbuf, 0xff, 512); |
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for (; num > 0; num--, sec++) { |
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if (s->bdrv_cur) {
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int erasesec = s->secs_cur + (sec >> 5); |
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if (bdrv_write(s->bdrv_cur, sec, blankbuf, 1)) { |
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goto fail;
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} |
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if (bdrv_read(s->bdrv_cur, erasesec, tmpbuf, 1) < 0) { |
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goto fail;
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} |
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memcpy(tmpbuf + ((sec & 31) << 4), blankbuf, 1 << 4); |
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if (bdrv_write(s->bdrv_cur, erasesec, tmpbuf, 1) < 0) { |
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goto fail;
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} |
309 |
} else {
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if (sec + 1 > s->secs_cur) { |
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goto fail;
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} |
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memcpy(s->current + (sec << 9), blankbuf, 512); |
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memcpy(s->current + (s->secs_cur << 9) + (sec << 4), |
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blankbuf, 1 << 4); |
316 |
} |
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} |
318 |
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g_free(tmpbuf); |
320 |
g_free(blankbuf); |
321 |
return 0; |
322 |
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fail:
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g_free(tmpbuf); |
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g_free(blankbuf); |
326 |
return 1; |
327 |
} |
328 |
|
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static void onenand_command(OneNANDState *s, int cmd) |
330 |
{ |
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int b;
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int sec;
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void *buf;
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#define SETADDR(block, page) \
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sec = (s->addr[page] & 3) + \
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((((s->addr[page] >> 2) & 0x3f) + \ |
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(((s->addr[block] & 0xfff) | \
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(s->addr[block] >> 15 ? \
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s->density_mask : 0)) << 6)) << (PAGE_SHIFT - 9)); |
340 |
#define SETBUF_M() \
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buf = (s->bufaddr & 8) ? \
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s->data[(s->bufaddr >> 2) & 1][0] : s->boot[0]; \ |
343 |
buf += (s->bufaddr & 3) << 9; |
344 |
#define SETBUF_S() \
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buf = (s->bufaddr & 8) ? \
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s->data[(s->bufaddr >> 2) & 1][1] : s->boot[1]; \ |
347 |
buf += (s->bufaddr & 3) << 4; |
348 |
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switch (cmd) {
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case 0x00: /* Load single/multiple sector data unit into buffer */ |
351 |
SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
352 |
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SETBUF_M() |
354 |
if (onenand_load_main(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_LOAD; |
356 |
|
357 |
#if 0
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358 |
SETBUF_S()
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359 |
if (onenand_load_spare(s, sec, s->count, buf))
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360 |
s->status |= ONEN_ERR_CMD | ONEN_ERR_LOAD;
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361 |
#endif
|
362 |
|
363 |
/* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
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364 |
* or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
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365 |
* then we need two split the read/write into two chunks.
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366 |
*/
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367 |
s->intstatus |= ONEN_INT | ONEN_INT_LOAD; |
368 |
break;
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369 |
case 0x13: /* Load single/multiple spare sector into buffer */ |
370 |
SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
371 |
|
372 |
SETBUF_S() |
373 |
if (onenand_load_spare(s, sec, s->count, buf))
|
374 |
s->status |= ONEN_ERR_CMD | ONEN_ERR_LOAD; |
375 |
|
376 |
/* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
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377 |
* or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
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378 |
* then we need two split the read/write into two chunks.
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379 |
*/
|
380 |
s->intstatus |= ONEN_INT | ONEN_INT_LOAD; |
381 |
break;
|
382 |
case 0x80: /* Program single/multiple sector data unit from buffer */ |
383 |
SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
384 |
|
385 |
SETBUF_M() |
386 |
if (onenand_prog_main(s, sec, s->count, buf))
|
387 |
s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG; |
388 |
|
389 |
#if 0
|
390 |
SETBUF_S()
|
391 |
if (onenand_prog_spare(s, sec, s->count, buf))
|
392 |
s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG;
|
393 |
#endif
|
394 |
|
395 |
/* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
|
396 |
* or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
|
397 |
* then we need two split the read/write into two chunks.
|
398 |
*/
|
399 |
s->intstatus |= ONEN_INT | ONEN_INT_PROG; |
400 |
break;
|
401 |
case 0x1a: /* Program single/multiple spare area sector from buffer */ |
402 |
SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
403 |
|
404 |
SETBUF_S() |
405 |
if (onenand_prog_spare(s, sec, s->count, buf))
|
406 |
s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG; |
407 |
|
408 |
/* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
|
409 |
* or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
|
410 |
* then we need two split the read/write into two chunks.
|
411 |
*/
|
412 |
s->intstatus |= ONEN_INT | ONEN_INT_PROG; |
413 |
break;
|
414 |
case 0x1b: /* Copy-back program */ |
415 |
SETBUF_S() |
416 |
|
417 |
SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
418 |
if (onenand_load_main(s, sec, s->count, buf))
|
419 |
s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG; |
420 |
|
421 |
SETADDR(ONEN_BUF_DEST_BLOCK, ONEN_BUF_DEST_PAGE) |
422 |
if (onenand_prog_main(s, sec, s->count, buf))
|
423 |
s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG; |
424 |
|
425 |
/* TODO: spare areas */
|
426 |
|
427 |
s->intstatus |= ONEN_INT | ONEN_INT_PROG; |
428 |
break;
|
429 |
|
430 |
case 0x23: /* Unlock NAND array block(s) */ |
431 |
s->intstatus |= ONEN_INT; |
432 |
|
433 |
/* XXX the previous (?) area should be locked automatically */
|
434 |
for (b = s->unladdr[0]; b <= s->unladdr[1]; b ++) { |
435 |
if (b >= s->blocks) {
|
436 |
s->status |= ONEN_ERR_CMD; |
437 |
break;
|
438 |
} |
439 |
if (s->blockwp[b] == ONEN_LOCK_LOCKTIGHTEN)
|
440 |
break;
|
441 |
|
442 |
s->wpstatus = s->blockwp[b] = ONEN_LOCK_UNLOCKED; |
443 |
} |
444 |
break;
|
445 |
case 0x27: /* Unlock All NAND array blocks */ |
446 |
s->intstatus |= ONEN_INT; |
447 |
|
448 |
for (b = 0; b < s->blocks; b ++) { |
449 |
if (b >= s->blocks) {
|
450 |
s->status |= ONEN_ERR_CMD; |
451 |
break;
|
452 |
} |
453 |
if (s->blockwp[b] == ONEN_LOCK_LOCKTIGHTEN)
|
454 |
break;
|
455 |
|
456 |
s->wpstatus = s->blockwp[b] = ONEN_LOCK_UNLOCKED; |
457 |
} |
458 |
break;
|
459 |
|
460 |
case 0x2a: /* Lock NAND array block(s) */ |
461 |
s->intstatus |= ONEN_INT; |
462 |
|
463 |
for (b = s->unladdr[0]; b <= s->unladdr[1]; b ++) { |
464 |
if (b >= s->blocks) {
|
465 |
s->status |= ONEN_ERR_CMD; |
466 |
break;
|
467 |
} |
468 |
if (s->blockwp[b] == ONEN_LOCK_LOCKTIGHTEN)
|
469 |
break;
|
470 |
|
471 |
s->wpstatus = s->blockwp[b] = ONEN_LOCK_LOCKED; |
472 |
} |
473 |
break;
|
474 |
case 0x2c: /* Lock-tight NAND array block(s) */ |
475 |
s->intstatus |= ONEN_INT; |
476 |
|
477 |
for (b = s->unladdr[0]; b <= s->unladdr[1]; b ++) { |
478 |
if (b >= s->blocks) {
|
479 |
s->status |= ONEN_ERR_CMD; |
480 |
break;
|
481 |
} |
482 |
if (s->blockwp[b] == ONEN_LOCK_UNLOCKED)
|
483 |
continue;
|
484 |
|
485 |
s->wpstatus = s->blockwp[b] = ONEN_LOCK_LOCKTIGHTEN; |
486 |
} |
487 |
break;
|
488 |
|
489 |
case 0x71: /* Erase-Verify-Read */ |
490 |
s->intstatus |= ONEN_INT; |
491 |
break;
|
492 |
case 0x95: /* Multi-block erase */ |
493 |
qemu_irq_pulse(s->intr); |
494 |
/* Fall through. */
|
495 |
case 0x94: /* Block erase */ |
496 |
sec = ((s->addr[ONEN_BUF_BLOCK] & 0xfff) |
|
497 |
(s->addr[ONEN_BUF_BLOCK] >> 15 ? s->density_mask : 0)) |
498 |
<< (BLOCK_SHIFT - 9);
|
499 |
if (onenand_erase(s, sec, 1 << (BLOCK_SHIFT - 9))) |
500 |
s->status |= ONEN_ERR_CMD | ONEN_ERR_ERASE; |
501 |
|
502 |
s->intstatus |= ONEN_INT | ONEN_INT_ERASE; |
503 |
break;
|
504 |
case 0xb0: /* Erase suspend */ |
505 |
break;
|
506 |
case 0x30: /* Erase resume */ |
507 |
s->intstatus |= ONEN_INT | ONEN_INT_ERASE; |
508 |
break;
|
509 |
|
510 |
case 0xf0: /* Reset NAND Flash core */ |
511 |
onenand_reset(s, 0);
|
512 |
break;
|
513 |
case 0xf3: /* Reset OneNAND */ |
514 |
onenand_reset(s, 0);
|
515 |
break;
|
516 |
|
517 |
case 0x65: /* OTP Access */ |
518 |
s->intstatus |= ONEN_INT; |
519 |
s->bdrv_cur = NULL;
|
520 |
s->current = s->otp; |
521 |
s->secs_cur = 1 << (BLOCK_SHIFT - 9); |
522 |
s->addr[ONEN_BUF_BLOCK] = 0;
|
523 |
s->otpmode = 1;
|
524 |
break;
|
525 |
|
526 |
default:
|
527 |
s->status |= ONEN_ERR_CMD; |
528 |
s->intstatus |= ONEN_INT; |
529 |
fprintf(stderr, "%s: unknown OneNAND command %x\n",
|
530 |
__FUNCTION__, cmd); |
531 |
} |
532 |
|
533 |
onenand_intr_update(s); |
534 |
} |
535 |
|
536 |
static uint64_t onenand_read(void *opaque, target_phys_addr_t addr, |
537 |
unsigned size)
|
538 |
{ |
539 |
OneNANDState *s = (OneNANDState *) opaque; |
540 |
int offset = addr >> s->shift;
|
541 |
|
542 |
switch (offset) {
|
543 |
case 0x0000 ... 0xc000: |
544 |
return lduw_le_p(s->boot[0] + addr); |
545 |
|
546 |
case 0xf000: /* Manufacturer ID */ |
547 |
return s->id.man;
|
548 |
case 0xf001: /* Device ID */ |
549 |
return s->id.dev;
|
550 |
case 0xf002: /* Version ID */ |
551 |
return s->id.ver;
|
552 |
/* TODO: get the following values from a real chip! */
|
553 |
case 0xf003: /* Data Buffer size */ |
554 |
return 1 << PAGE_SHIFT; |
555 |
case 0xf004: /* Boot Buffer size */ |
556 |
return 0x200; |
557 |
case 0xf005: /* Amount of buffers */ |
558 |
return 1 | (2 << 8); |
559 |
case 0xf006: /* Technology */ |
560 |
return 0; |
561 |
|
562 |
case 0xf100 ... 0xf107: /* Start addresses */ |
563 |
return s->addr[offset - 0xf100]; |
564 |
|
565 |
case 0xf200: /* Start buffer */ |
566 |
return (s->bufaddr << 8) | ((s->count - 1) & (1 << (PAGE_SHIFT - 10))); |
567 |
|
568 |
case 0xf220: /* Command */ |
569 |
return s->command;
|
570 |
case 0xf221: /* System Configuration 1 */ |
571 |
return s->config[0] & 0xffe0; |
572 |
case 0xf222: /* System Configuration 2 */ |
573 |
return s->config[1]; |
574 |
|
575 |
case 0xf240: /* Controller Status */ |
576 |
return s->status;
|
577 |
case 0xf241: /* Interrupt */ |
578 |
return s->intstatus;
|
579 |
case 0xf24c: /* Unlock Start Block Address */ |
580 |
return s->unladdr[0]; |
581 |
case 0xf24d: /* Unlock End Block Address */ |
582 |
return s->unladdr[1]; |
583 |
case 0xf24e: /* Write Protection Status */ |
584 |
return s->wpstatus;
|
585 |
|
586 |
case 0xff00: /* ECC Status */ |
587 |
return 0x00; |
588 |
case 0xff01: /* ECC Result of main area data */ |
589 |
case 0xff02: /* ECC Result of spare area data */ |
590 |
case 0xff03: /* ECC Result of main area data */ |
591 |
case 0xff04: /* ECC Result of spare area data */ |
592 |
hw_error("%s: imeplement ECC\n", __FUNCTION__);
|
593 |
return 0x0000; |
594 |
} |
595 |
|
596 |
fprintf(stderr, "%s: unknown OneNAND register %x\n",
|
597 |
__FUNCTION__, offset); |
598 |
return 0; |
599 |
} |
600 |
|
601 |
static void onenand_write(void *opaque, target_phys_addr_t addr, |
602 |
uint64_t value, unsigned size)
|
603 |
{ |
604 |
OneNANDState *s = (OneNANDState *) opaque; |
605 |
int offset = addr >> s->shift;
|
606 |
int sec;
|
607 |
|
608 |
switch (offset) {
|
609 |
case 0x0000 ... 0x01ff: |
610 |
case 0x8000 ... 0x800f: |
611 |
if (s->cycle) {
|
612 |
s->cycle = 0;
|
613 |
|
614 |
if (value == 0x0000) { |
615 |
SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
616 |
onenand_load_main(s, sec, |
617 |
1 << (PAGE_SHIFT - 9), s->data[0][0]); |
618 |
s->addr[ONEN_BUF_PAGE] += 4;
|
619 |
s->addr[ONEN_BUF_PAGE] &= 0xff;
|
620 |
} |
621 |
break;
|
622 |
} |
623 |
|
624 |
switch (value) {
|
625 |
case 0x00f0: /* Reset OneNAND */ |
626 |
onenand_reset(s, 0);
|
627 |
break;
|
628 |
|
629 |
case 0x00e0: /* Load Data into Buffer */ |
630 |
s->cycle = 1;
|
631 |
break;
|
632 |
|
633 |
case 0x0090: /* Read Identification Data */ |
634 |
memset(s->boot[0], 0, 3 << s->shift); |
635 |
s->boot[0][0 << s->shift] = s->id.man & 0xff; |
636 |
s->boot[0][1 << s->shift] = s->id.dev & 0xff; |
637 |
s->boot[0][2 << s->shift] = s->wpstatus & 0xff; |
638 |
break;
|
639 |
|
640 |
default:
|
641 |
fprintf(stderr, "%s: unknown OneNAND boot command %"PRIx64"\n", |
642 |
__FUNCTION__, value); |
643 |
} |
644 |
break;
|
645 |
|
646 |
case 0xf100 ... 0xf107: /* Start addresses */ |
647 |
s->addr[offset - 0xf100] = value;
|
648 |
break;
|
649 |
|
650 |
case 0xf200: /* Start buffer */ |
651 |
s->bufaddr = (value >> 8) & 0xf; |
652 |
if (PAGE_SHIFT == 11) |
653 |
s->count = (value & 3) ?: 4; |
654 |
else if (PAGE_SHIFT == 10) |
655 |
s->count = (value & 1) ?: 2; |
656 |
break;
|
657 |
|
658 |
case 0xf220: /* Command */ |
659 |
if (s->intstatus & (1 << 15)) |
660 |
break;
|
661 |
s->command = value; |
662 |
onenand_command(s, s->command); |
663 |
break;
|
664 |
case 0xf221: /* System Configuration 1 */ |
665 |
s->config[0] = value;
|
666 |
onenand_intr_update(s); |
667 |
qemu_set_irq(s->rdy, (s->config[0] >> 7) & 1); |
668 |
break;
|
669 |
case 0xf222: /* System Configuration 2 */ |
670 |
s->config[1] = value;
|
671 |
break;
|
672 |
|
673 |
case 0xf241: /* Interrupt */ |
674 |
s->intstatus &= value; |
675 |
if ((1 << 15) & ~s->intstatus) |
676 |
s->status &= ~(ONEN_ERR_CMD | ONEN_ERR_ERASE | |
677 |
ONEN_ERR_PROG | ONEN_ERR_LOAD); |
678 |
onenand_intr_update(s); |
679 |
break;
|
680 |
case 0xf24c: /* Unlock Start Block Address */ |
681 |
s->unladdr[0] = value & (s->blocks - 1); |
682 |
/* For some reason we have to set the end address to by default
|
683 |
* be same as start because the software forgets to write anything
|
684 |
* in there. */
|
685 |
s->unladdr[1] = value & (s->blocks - 1); |
686 |
break;
|
687 |
case 0xf24d: /* Unlock End Block Address */ |
688 |
s->unladdr[1] = value & (s->blocks - 1); |
689 |
break;
|
690 |
|
691 |
default:
|
692 |
fprintf(stderr, "%s: unknown OneNAND register %x\n",
|
693 |
__FUNCTION__, offset); |
694 |
} |
695 |
} |
696 |
|
697 |
static const MemoryRegionOps onenand_ops = { |
698 |
.read = onenand_read, |
699 |
.write = onenand_write, |
700 |
.endianness = DEVICE_NATIVE_ENDIAN, |
701 |
}; |
702 |
|
703 |
void *onenand_init(BlockDriverState *bdrv,
|
704 |
uint16_t man_id, uint16_t dev_id, uint16_t ver_id, |
705 |
int regshift, qemu_irq irq)
|
706 |
{ |
707 |
OneNANDState *s = (OneNANDState *) g_malloc0(sizeof(*s));
|
708 |
uint32_t size = 1 << (24 + ((dev_id >> 4) & 7)); |
709 |
void *ram;
|
710 |
|
711 |
s->shift = regshift; |
712 |
s->intr = irq; |
713 |
s->rdy = NULL;
|
714 |
s->id.man = man_id; |
715 |
s->id.dev = dev_id; |
716 |
s->id.ver = ver_id; |
717 |
s->blocks = size >> BLOCK_SHIFT; |
718 |
s->secs = size >> 9;
|
719 |
s->blockwp = g_malloc(s->blocks); |
720 |
s->density_mask = (dev_id & 0x08) ? (1 << (6 + ((dev_id >> 4) & 7))) : 0; |
721 |
memory_region_init_io(&s->iomem, &onenand_ops, s, "onenand",
|
722 |
0x10000 << s->shift);
|
723 |
s->bdrv = bdrv; |
724 |
if (!s->bdrv) {
|
725 |
s->image = memset(g_malloc(size + (size >> 5)),
|
726 |
0xff, size + (size >> 5)); |
727 |
} |
728 |
s->otp = memset(g_malloc((64 + 2) << PAGE_SHIFT), |
729 |
0xff, (64 + 2) << PAGE_SHIFT); |
730 |
memory_region_init_ram(&s->ram, NULL, "onenand.ram", 0xc000 << s->shift); |
731 |
ram = memory_region_get_ram_ptr(&s->ram); |
732 |
s->boot[0] = ram + (0x0000 << s->shift); |
733 |
s->boot[1] = ram + (0x8000 << s->shift); |
734 |
s->data[0][0] = ram + ((0x0200 + (0 << (PAGE_SHIFT - 1))) << s->shift); |
735 |
s->data[0][1] = ram + ((0x8010 + (0 << (PAGE_SHIFT - 6))) << s->shift); |
736 |
s->data[1][0] = ram + ((0x0200 + (1 << (PAGE_SHIFT - 1))) << s->shift); |
737 |
s->data[1][1] = ram + ((0x8010 + (1 << (PAGE_SHIFT - 6))) << s->shift); |
738 |
onenand_mem_setup(s); |
739 |
|
740 |
onenand_reset(s, 1);
|
741 |
|
742 |
return s;
|
743 |
} |
744 |
|
745 |
void *onenand_raw_otp(void *opaque) |
746 |
{ |
747 |
OneNANDState *s = (OneNANDState *) opaque; |
748 |
|
749 |
return s->otp;
|
750 |
} |