root / target-arm / cpu.c @ 68e0a40a
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/*
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* QEMU ARM CPU
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*
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see
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* <http://www.gnu.org/licenses/gpl-2.0.html>
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*/
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#include "cpu.h" |
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#include "qemu-common.h" |
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#include "hw/qdev-properties.h" |
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#include "qapi/qmp/qerror.h" |
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#if !defined(CONFIG_USER_ONLY)
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#include "hw/loader.h" |
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#endif
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#include "hw/arm/arm.h" |
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#include "sysemu/sysemu.h" |
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#include "sysemu/kvm.h" |
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static void arm_cpu_set_pc(CPUState *cs, vaddr value) |
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{
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ARMCPU *cpu = ARM_CPU(cs); |
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cpu->env.regs[15] = value;
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} |
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static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) |
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{
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/* Reset a single ARMCPRegInfo register */
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ARMCPRegInfo *ri = value; |
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ARMCPU *cpu = opaque; |
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if (ri->type & ARM_CP_SPECIAL) {
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return;
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} |
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if (ri->resetfn) {
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ri->resetfn(&cpu->env, ri); |
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return;
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} |
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/* A zero offset is never possible as it would be regs[0]
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* so we use it to indicate that reset is being handled elsewhere.
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* This is basically only used for fields in non-core coprocessors
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* (like the pxa2xx ones).
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*/
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if (!ri->fieldoffset) {
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return;
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} |
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if (ri->type & ARM_CP_64BIT) {
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CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; |
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} else {
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CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; |
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} |
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} |
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/* CPUClass::reset() */
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static void arm_cpu_reset(CPUState *s) |
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{
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ARMCPU *cpu = ARM_CPU(s); |
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ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); |
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CPUARMState *env = &cpu->env; |
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acc->parent_reset(s); |
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memset(env, 0, offsetof(CPUARMState, breakpoints));
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g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); |
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env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; |
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env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; |
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env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; |
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if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
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env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; |
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} |
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if (arm_feature(env, ARM_FEATURE_AARCH64)) {
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/* 64 bit CPUs always start in 64 bit mode */
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env->aarch64 = 1;
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} |
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#if defined(CONFIG_USER_ONLY)
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env->uncached_cpsr = ARM_CPU_MODE_USR; |
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/* For user mode we must enable access to coprocessors */
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env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; |
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if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
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env->cp15.c15_cpar = 3;
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} else if (arm_feature(env, ARM_FEATURE_XSCALE)) { |
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env->cp15.c15_cpar = 1;
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} |
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#else
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/* SVC mode with interrupts disabled. */
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env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I; |
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/* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
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clear at reset. Initial SP and PC are loaded from ROM. */
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if (IS_M(env)) {
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uint32_t pc; |
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uint8_t *rom; |
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env->uncached_cpsr &= ~CPSR_I; |
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rom = rom_ptr(0);
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if (rom) {
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/* We should really use ldl_phys here, in case the guest
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modified flash and reset itself. However images
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loaded via -kernel have not been copied yet, so load the
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values directly from there. */
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env->regs[13] = ldl_p(rom) & 0xFFFFFFFC; |
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pc = ldl_p(rom + 4);
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env->thumb = pc & 1;
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env->regs[15] = pc & ~1; |
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} |
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} |
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env->vfp.xregs[ARM_VFP_FPEXC] = 0;
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#endif
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set_flush_to_zero(1, &env->vfp.standard_fp_status);
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set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
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set_default_nan_mode(1, &env->vfp.standard_fp_status);
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set_float_detect_tininess(float_tininess_before_rounding, |
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&env->vfp.fp_status); |
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set_float_detect_tininess(float_tininess_before_rounding, |
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&env->vfp.standard_fp_status); |
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tlb_flush(env, 1);
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/* Reset is a state change for some CPUARMState fields which we
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* bake assumptions about into translated code, so we need to
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* tb_flush().
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*/
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tb_flush(env); |
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} |
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#ifndef CONFIG_USER_ONLY
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static void arm_cpu_set_irq(void *opaque, int irq, int level) |
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{
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ARMCPU *cpu = opaque; |
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CPUState *cs = CPU(cpu); |
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switch (irq) {
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case ARM_CPU_IRQ:
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if (level) {
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cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
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} else {
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); |
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} |
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break;
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case ARM_CPU_FIQ:
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if (level) {
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cpu_interrupt(cs, CPU_INTERRUPT_FIQ); |
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} else {
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cpu_reset_interrupt(cs, CPU_INTERRUPT_FIQ); |
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} |
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break;
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default:
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hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq);
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} |
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} |
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static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) |
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{
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#ifdef CONFIG_KVM
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ARMCPU *cpu = opaque; |
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CPUState *cs = CPU(cpu); |
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int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
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switch (irq) {
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case ARM_CPU_IRQ:
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kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; |
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break;
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case ARM_CPU_FIQ:
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kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; |
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break;
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default:
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hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq);
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} |
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kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; |
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kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); |
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#endif
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} |
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#endif
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static inline void set_feature(CPUARMState *env, int feature) |
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{
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env->features |= 1ULL << feature;
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} |
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static void arm_cpu_initfn(Object *obj) |
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{
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CPUState *cs = CPU(obj); |
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ARMCPU *cpu = ARM_CPU(obj); |
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static bool inited; |
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cs->env_ptr = &cpu->env; |
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cpu_exec_init(&cpu->env); |
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cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, |
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g_free, g_free); |
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#ifndef CONFIG_USER_ONLY
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/* Our inbound IRQ and FIQ lines */
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if (kvm_enabled()) {
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qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 2);
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} else {
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qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 2);
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} |
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cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, |
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arm_gt_ptimer_cb, cpu); |
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cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, |
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arm_gt_vtimer_cb, cpu); |
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qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, |
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ARRAY_SIZE(cpu->gt_timer_outputs)); |
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#endif
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/* DTB consumers generally don't in fact care what the 'compatible'
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* string is, so always provide some string and trust that a hypothetical
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* picky DTB consumer will also provide a helpful error message.
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*/
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cpu->dtb_compatible = "qemu,unknown";
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cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; |
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if (tcg_enabled() && !inited) {
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inited = true;
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arm_translate_init(); |
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} |
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} |
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static Property arm_cpu_reset_cbar_property =
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DEFINE_PROP_UINT32("reset-cbar", ARMCPU, reset_cbar, 0); |
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static Property arm_cpu_reset_hivecs_property =
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DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); |
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static void arm_cpu_post_init(Object *obj) |
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{
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ARMCPU *cpu = ARM_CPU(obj); |
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Error *err = NULL;
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if (arm_feature(&cpu->env, ARM_FEATURE_CBAR)) {
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qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, |
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&err); |
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assert_no_error(err); |
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} |
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if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
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qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, |
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&err); |
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assert_no_error(err); |
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} |
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} |
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static void arm_cpu_finalizefn(Object *obj) |
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{
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ARMCPU *cpu = ARM_CPU(obj); |
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g_hash_table_destroy(cpu->cp_regs); |
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} |
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static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
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{
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CPUState *cs = CPU(dev); |
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ARMCPU *cpu = ARM_CPU(dev); |
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ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); |
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CPUARMState *env = &cpu->env; |
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/* Some features automatically imply others: */
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if (arm_feature(env, ARM_FEATURE_V8)) {
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set_feature(env, ARM_FEATURE_V7); |
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set_feature(env, ARM_FEATURE_ARM_DIV); |
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set_feature(env, ARM_FEATURE_LPAE); |
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set_feature(env, ARM_FEATURE_V8_AES); |
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} |
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if (arm_feature(env, ARM_FEATURE_V7)) {
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set_feature(env, ARM_FEATURE_VAPA); |
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set_feature(env, ARM_FEATURE_THUMB2); |
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set_feature(env, ARM_FEATURE_MPIDR); |
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if (!arm_feature(env, ARM_FEATURE_M)) {
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set_feature(env, ARM_FEATURE_V6K); |
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} else {
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set_feature(env, ARM_FEATURE_V6); |
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} |
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} |
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if (arm_feature(env, ARM_FEATURE_V6K)) {
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set_feature(env, ARM_FEATURE_V6); |
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set_feature(env, ARM_FEATURE_MVFR); |
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} |
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if (arm_feature(env, ARM_FEATURE_V6)) {
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set_feature(env, ARM_FEATURE_V5); |
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if (!arm_feature(env, ARM_FEATURE_M)) {
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set_feature(env, ARM_FEATURE_AUXCR); |
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} |
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} |
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if (arm_feature(env, ARM_FEATURE_V5)) {
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set_feature(env, ARM_FEATURE_V4T); |
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} |
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if (arm_feature(env, ARM_FEATURE_M)) {
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set_feature(env, ARM_FEATURE_THUMB_DIV); |
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} |
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if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
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set_feature(env, ARM_FEATURE_THUMB_DIV); |
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} |
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if (arm_feature(env, ARM_FEATURE_VFP4)) {
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set_feature(env, ARM_FEATURE_VFP3); |
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} |
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if (arm_feature(env, ARM_FEATURE_VFP3)) {
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set_feature(env, ARM_FEATURE_VFP); |
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} |
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if (arm_feature(env, ARM_FEATURE_LPAE)) {
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set_feature(env, ARM_FEATURE_V7MP); |
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set_feature(env, ARM_FEATURE_PXN); |
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} |
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|
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if (cpu->reset_hivecs) {
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cpu->reset_sctlr |= (1 << 13); |
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} |
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register_cp_regs_for_features(cpu); |
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arm_cpu_register_gdb_regs_for_features(cpu); |
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|
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init_cpreg_list(cpu); |
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cpu_reset(cs); |
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qemu_init_vcpu(cs); |
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acc->parent_realize(dev, errp); |
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} |
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|
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static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) |
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{
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ObjectClass *oc; |
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char *typename;
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|
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if (!cpu_model) {
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return NULL; |
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} |
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typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model);
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oc = object_class_by_name(typename); |
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g_free(typename); |
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if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
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object_class_is_abstract(oc)) {
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return NULL; |
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} |
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return oc;
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} |
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|
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/* CPU models. These are not needed for the AArch64 linux-user build. */
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#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
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|
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static void arm926_initfn(Object *obj) |
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{
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ARMCPU *cpu = ARM_CPU(obj); |
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|
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cpu->dtb_compatible = "arm,arm926";
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set_feature(&cpu->env, ARM_FEATURE_V5); |
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set_feature(&cpu->env, ARM_FEATURE_VFP); |
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set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
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set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); |
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cpu->midr = 0x41069265;
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cpu->reset_fpsid = 0x41011090;
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cpu->ctr = 0x1dd20d2;
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cpu->reset_sctlr = 0x00090078;
|
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} |
| 370 |
|
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static void arm946_initfn(Object *obj) |
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{
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ARMCPU *cpu = ARM_CPU(obj); |
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|
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cpu->dtb_compatible = "arm,arm946";
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set_feature(&cpu->env, ARM_FEATURE_V5); |
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set_feature(&cpu->env, ARM_FEATURE_MPU); |
| 378 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
| 379 |
cpu->midr = 0x41059461;
|
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cpu->ctr = 0x0f004006;
|
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cpu->reset_sctlr = 0x00000078;
|
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} |
| 383 |
|
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static void arm1026_initfn(Object *obj) |
| 385 |
{
|
| 386 |
ARMCPU *cpu = ARM_CPU(obj); |
| 387 |
|
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cpu->dtb_compatible = "arm,arm1026";
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set_feature(&cpu->env, ARM_FEATURE_V5); |
| 390 |
set_feature(&cpu->env, ARM_FEATURE_VFP); |
| 391 |
set_feature(&cpu->env, ARM_FEATURE_AUXCR); |
| 392 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
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set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); |
| 394 |
cpu->midr = 0x4106a262;
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cpu->reset_fpsid = 0x410110a0;
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cpu->ctr = 0x1dd20d2;
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cpu->reset_sctlr = 0x00090078;
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cpu->reset_auxcr = 1;
|
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{
|
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/* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
|
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ARMCPRegInfo ifar = {
|
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.name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, |
| 403 |
.access = PL1_RW, |
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.fieldoffset = offsetof(CPUARMState, cp15.c6_insn), |
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.resetvalue = 0
|
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}; |
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define_one_arm_cp_reg(cpu, &ifar); |
| 408 |
} |
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} |
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|
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static void arm1136_r2_initfn(Object *obj) |
| 412 |
{
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ARMCPU *cpu = ARM_CPU(obj); |
| 414 |
/* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
|
| 415 |
* older core than plain "arm1136". In particular this does not
|
| 416 |
* have the v6K features.
|
| 417 |
* These ID register values are correct for 1136 but may be wrong
|
| 418 |
* for 1136_r2 (in particular r0p2 does not actually implement most
|
| 419 |
* of the ID registers).
|
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*/
|
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|
| 422 |
cpu->dtb_compatible = "arm,arm1136";
|
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set_feature(&cpu->env, ARM_FEATURE_V6); |
| 424 |
set_feature(&cpu->env, ARM_FEATURE_VFP); |
| 425 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
| 426 |
set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); |
| 427 |
set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); |
| 428 |
cpu->midr = 0x4107b362;
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cpu->reset_fpsid = 0x410120b4;
|
| 430 |
cpu->mvfr0 = 0x11111111;
|
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cpu->mvfr1 = 0x00000000;
|
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cpu->ctr = 0x1dd20d2;
|
| 433 |
cpu->reset_sctlr = 0x00050078;
|
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cpu->id_pfr0 = 0x111;
|
| 435 |
cpu->id_pfr1 = 0x1;
|
| 436 |
cpu->id_dfr0 = 0x2;
|
| 437 |
cpu->id_afr0 = 0x3;
|
| 438 |
cpu->id_mmfr0 = 0x01130003;
|
| 439 |
cpu->id_mmfr1 = 0x10030302;
|
| 440 |
cpu->id_mmfr2 = 0x01222110;
|
| 441 |
cpu->id_isar0 = 0x00140011;
|
| 442 |
cpu->id_isar1 = 0x12002111;
|
| 443 |
cpu->id_isar2 = 0x11231111;
|
| 444 |
cpu->id_isar3 = 0x01102131;
|
| 445 |
cpu->id_isar4 = 0x141;
|
| 446 |
cpu->reset_auxcr = 7;
|
| 447 |
} |
| 448 |
|
| 449 |
static void arm1136_initfn(Object *obj) |
| 450 |
{
|
| 451 |
ARMCPU *cpu = ARM_CPU(obj); |
| 452 |
|
| 453 |
cpu->dtb_compatible = "arm,arm1136";
|
| 454 |
set_feature(&cpu->env, ARM_FEATURE_V6K); |
| 455 |
set_feature(&cpu->env, ARM_FEATURE_V6); |
| 456 |
set_feature(&cpu->env, ARM_FEATURE_VFP); |
| 457 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
| 458 |
set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); |
| 459 |
set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); |
| 460 |
cpu->midr = 0x4117b363;
|
| 461 |
cpu->reset_fpsid = 0x410120b4;
|
| 462 |
cpu->mvfr0 = 0x11111111;
|
| 463 |
cpu->mvfr1 = 0x00000000;
|
| 464 |
cpu->ctr = 0x1dd20d2;
|
| 465 |
cpu->reset_sctlr = 0x00050078;
|
| 466 |
cpu->id_pfr0 = 0x111;
|
| 467 |
cpu->id_pfr1 = 0x1;
|
| 468 |
cpu->id_dfr0 = 0x2;
|
| 469 |
cpu->id_afr0 = 0x3;
|
| 470 |
cpu->id_mmfr0 = 0x01130003;
|
| 471 |
cpu->id_mmfr1 = 0x10030302;
|
| 472 |
cpu->id_mmfr2 = 0x01222110;
|
| 473 |
cpu->id_isar0 = 0x00140011;
|
| 474 |
cpu->id_isar1 = 0x12002111;
|
| 475 |
cpu->id_isar2 = 0x11231111;
|
| 476 |
cpu->id_isar3 = 0x01102131;
|
| 477 |
cpu->id_isar4 = 0x141;
|
| 478 |
cpu->reset_auxcr = 7;
|
| 479 |
} |
| 480 |
|
| 481 |
static void arm1176_initfn(Object *obj) |
| 482 |
{
|
| 483 |
ARMCPU *cpu = ARM_CPU(obj); |
| 484 |
|
| 485 |
cpu->dtb_compatible = "arm,arm1176";
|
| 486 |
set_feature(&cpu->env, ARM_FEATURE_V6K); |
| 487 |
set_feature(&cpu->env, ARM_FEATURE_VFP); |
| 488 |
set_feature(&cpu->env, ARM_FEATURE_VAPA); |
| 489 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
| 490 |
set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); |
| 491 |
set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); |
| 492 |
cpu->midr = 0x410fb767;
|
| 493 |
cpu->reset_fpsid = 0x410120b5;
|
| 494 |
cpu->mvfr0 = 0x11111111;
|
| 495 |
cpu->mvfr1 = 0x00000000;
|
| 496 |
cpu->ctr = 0x1dd20d2;
|
| 497 |
cpu->reset_sctlr = 0x00050078;
|
| 498 |
cpu->id_pfr0 = 0x111;
|
| 499 |
cpu->id_pfr1 = 0x11;
|
| 500 |
cpu->id_dfr0 = 0x33;
|
| 501 |
cpu->id_afr0 = 0;
|
| 502 |
cpu->id_mmfr0 = 0x01130003;
|
| 503 |
cpu->id_mmfr1 = 0x10030302;
|
| 504 |
cpu->id_mmfr2 = 0x01222100;
|
| 505 |
cpu->id_isar0 = 0x0140011;
|
| 506 |
cpu->id_isar1 = 0x12002111;
|
| 507 |
cpu->id_isar2 = 0x11231121;
|
| 508 |
cpu->id_isar3 = 0x01102131;
|
| 509 |
cpu->id_isar4 = 0x01141;
|
| 510 |
cpu->reset_auxcr = 7;
|
| 511 |
} |
| 512 |
|
| 513 |
static void arm11mpcore_initfn(Object *obj) |
| 514 |
{
|
| 515 |
ARMCPU *cpu = ARM_CPU(obj); |
| 516 |
|
| 517 |
cpu->dtb_compatible = "arm,arm11mpcore";
|
| 518 |
set_feature(&cpu->env, ARM_FEATURE_V6K); |
| 519 |
set_feature(&cpu->env, ARM_FEATURE_VFP); |
| 520 |
set_feature(&cpu->env, ARM_FEATURE_VAPA); |
| 521 |
set_feature(&cpu->env, ARM_FEATURE_MPIDR); |
| 522 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
| 523 |
cpu->midr = 0x410fb022;
|
| 524 |
cpu->reset_fpsid = 0x410120b4;
|
| 525 |
cpu->mvfr0 = 0x11111111;
|
| 526 |
cpu->mvfr1 = 0x00000000;
|
| 527 |
cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ |
| 528 |
cpu->id_pfr0 = 0x111;
|
| 529 |
cpu->id_pfr1 = 0x1;
|
| 530 |
cpu->id_dfr0 = 0;
|
| 531 |
cpu->id_afr0 = 0x2;
|
| 532 |
cpu->id_mmfr0 = 0x01100103;
|
| 533 |
cpu->id_mmfr1 = 0x10020302;
|
| 534 |
cpu->id_mmfr2 = 0x01222000;
|
| 535 |
cpu->id_isar0 = 0x00100011;
|
| 536 |
cpu->id_isar1 = 0x12002111;
|
| 537 |
cpu->id_isar2 = 0x11221011;
|
| 538 |
cpu->id_isar3 = 0x01102131;
|
| 539 |
cpu->id_isar4 = 0x141;
|
| 540 |
cpu->reset_auxcr = 1;
|
| 541 |
} |
| 542 |
|
| 543 |
static void cortex_m3_initfn(Object *obj) |
| 544 |
{
|
| 545 |
ARMCPU *cpu = ARM_CPU(obj); |
| 546 |
set_feature(&cpu->env, ARM_FEATURE_V7); |
| 547 |
set_feature(&cpu->env, ARM_FEATURE_M); |
| 548 |
cpu->midr = 0x410fc231;
|
| 549 |
} |
| 550 |
|
| 551 |
static void arm_v7m_class_init(ObjectClass *oc, void *data) |
| 552 |
{
|
| 553 |
#ifndef CONFIG_USER_ONLY
|
| 554 |
CPUClass *cc = CPU_CLASS(oc); |
| 555 |
|
| 556 |
cc->do_interrupt = arm_v7m_cpu_do_interrupt; |
| 557 |
#endif
|
| 558 |
} |
| 559 |
|
| 560 |
static const ARMCPRegInfo cortexa8_cp_reginfo[] = { |
| 561 |
{ .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
|
| 562 |
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
| 563 |
{ .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
|
| 564 |
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
| 565 |
REGINFO_SENTINEL |
| 566 |
}; |
| 567 |
|
| 568 |
static void cortex_a8_initfn(Object *obj) |
| 569 |
{
|
| 570 |
ARMCPU *cpu = ARM_CPU(obj); |
| 571 |
|
| 572 |
cpu->dtb_compatible = "arm,cortex-a8";
|
| 573 |
set_feature(&cpu->env, ARM_FEATURE_V7); |
| 574 |
set_feature(&cpu->env, ARM_FEATURE_VFP3); |
| 575 |
set_feature(&cpu->env, ARM_FEATURE_NEON); |
| 576 |
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); |
| 577 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
| 578 |
cpu->midr = 0x410fc080;
|
| 579 |
cpu->reset_fpsid = 0x410330c0;
|
| 580 |
cpu->mvfr0 = 0x11110222;
|
| 581 |
cpu->mvfr1 = 0x00011100;
|
| 582 |
cpu->ctr = 0x82048004;
|
| 583 |
cpu->reset_sctlr = 0x00c50078;
|
| 584 |
cpu->id_pfr0 = 0x1031;
|
| 585 |
cpu->id_pfr1 = 0x11;
|
| 586 |
cpu->id_dfr0 = 0x400;
|
| 587 |
cpu->id_afr0 = 0;
|
| 588 |
cpu->id_mmfr0 = 0x31100003;
|
| 589 |
cpu->id_mmfr1 = 0x20000000;
|
| 590 |
cpu->id_mmfr2 = 0x01202000;
|
| 591 |
cpu->id_mmfr3 = 0x11;
|
| 592 |
cpu->id_isar0 = 0x00101111;
|
| 593 |
cpu->id_isar1 = 0x12112111;
|
| 594 |
cpu->id_isar2 = 0x21232031;
|
| 595 |
cpu->id_isar3 = 0x11112131;
|
| 596 |
cpu->id_isar4 = 0x00111142;
|
| 597 |
cpu->clidr = (1 << 27) | (2 << 24) | 3; |
| 598 |
cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ |
| 599 |
cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ |
| 600 |
cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ |
| 601 |
cpu->reset_auxcr = 2;
|
| 602 |
define_arm_cp_regs(cpu, cortexa8_cp_reginfo); |
| 603 |
} |
| 604 |
|
| 605 |
static const ARMCPRegInfo cortexa9_cp_reginfo[] = { |
| 606 |
/* power_control should be set to maximum latency. Again,
|
| 607 |
* default to 0 and set by private hook
|
| 608 |
*/
|
| 609 |
{ .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
|
| 610 |
.access = PL1_RW, .resetvalue = 0,
|
| 611 |
.fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, |
| 612 |
{ .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
|
| 613 |
.access = PL1_RW, .resetvalue = 0,
|
| 614 |
.fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, |
| 615 |
{ .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
|
| 616 |
.access = PL1_RW, .resetvalue = 0,
|
| 617 |
.fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, |
| 618 |
{ .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
|
| 619 |
.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
|
| 620 |
/* TLB lockdown control */
|
| 621 |
{ .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
|
| 622 |
.access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
|
| 623 |
{ .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
|
| 624 |
.access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
|
| 625 |
{ .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
|
| 626 |
.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
|
| 627 |
{ .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
|
| 628 |
.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
|
| 629 |
{ .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
|
| 630 |
.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
|
| 631 |
REGINFO_SENTINEL |
| 632 |
}; |
| 633 |
|
| 634 |
static void cortex_a9_initfn(Object *obj) |
| 635 |
{
|
| 636 |
ARMCPU *cpu = ARM_CPU(obj); |
| 637 |
|
| 638 |
cpu->dtb_compatible = "arm,cortex-a9";
|
| 639 |
set_feature(&cpu->env, ARM_FEATURE_V7); |
| 640 |
set_feature(&cpu->env, ARM_FEATURE_VFP3); |
| 641 |
set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); |
| 642 |
set_feature(&cpu->env, ARM_FEATURE_NEON); |
| 643 |
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); |
| 644 |
/* Note that A9 supports the MP extensions even for
|
| 645 |
* A9UP and single-core A9MP (which are both different
|
| 646 |
* and valid configurations; we don't model A9UP).
|
| 647 |
*/
|
| 648 |
set_feature(&cpu->env, ARM_FEATURE_V7MP); |
| 649 |
set_feature(&cpu->env, ARM_FEATURE_CBAR); |
| 650 |
cpu->midr = 0x410fc090;
|
| 651 |
cpu->reset_fpsid = 0x41033090;
|
| 652 |
cpu->mvfr0 = 0x11110222;
|
| 653 |
cpu->mvfr1 = 0x01111111;
|
| 654 |
cpu->ctr = 0x80038003;
|
| 655 |
cpu->reset_sctlr = 0x00c50078;
|
| 656 |
cpu->id_pfr0 = 0x1031;
|
| 657 |
cpu->id_pfr1 = 0x11;
|
| 658 |
cpu->id_dfr0 = 0x000;
|
| 659 |
cpu->id_afr0 = 0;
|
| 660 |
cpu->id_mmfr0 = 0x00100103;
|
| 661 |
cpu->id_mmfr1 = 0x20000000;
|
| 662 |
cpu->id_mmfr2 = 0x01230000;
|
| 663 |
cpu->id_mmfr3 = 0x00002111;
|
| 664 |
cpu->id_isar0 = 0x00101111;
|
| 665 |
cpu->id_isar1 = 0x13112111;
|
| 666 |
cpu->id_isar2 = 0x21232041;
|
| 667 |
cpu->id_isar3 = 0x11112131;
|
| 668 |
cpu->id_isar4 = 0x00111142;
|
| 669 |
cpu->clidr = (1 << 27) | (1 << 24) | 3; |
| 670 |
cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */ |
| 671 |
cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */ |
| 672 |
define_arm_cp_regs(cpu, cortexa9_cp_reginfo); |
| 673 |
} |
| 674 |
|
| 675 |
#ifndef CONFIG_USER_ONLY
|
| 676 |
static int a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri, |
| 677 |
uint64_t *value) |
| 678 |
{
|
| 679 |
/* Linux wants the number of processors from here.
|
| 680 |
* Might as well set the interrupt-controller bit too.
|
| 681 |
*/
|
| 682 |
*value = ((smp_cpus - 1) << 24) | (1 << 23); |
| 683 |
return 0; |
| 684 |
} |
| 685 |
#endif
|
| 686 |
|
| 687 |
static const ARMCPRegInfo cortexa15_cp_reginfo[] = { |
| 688 |
#ifndef CONFIG_USER_ONLY
|
| 689 |
{ .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
|
| 690 |
.access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
|
| 691 |
.writefn = arm_cp_write_ignore, }, |
| 692 |
#endif
|
| 693 |
{ .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
|
| 694 |
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
| 695 |
REGINFO_SENTINEL |
| 696 |
}; |
| 697 |
|
| 698 |
static void cortex_a15_initfn(Object *obj) |
| 699 |
{
|
| 700 |
ARMCPU *cpu = ARM_CPU(obj); |
| 701 |
|
| 702 |
cpu->dtb_compatible = "arm,cortex-a15";
|
| 703 |
set_feature(&cpu->env, ARM_FEATURE_V7); |
| 704 |
set_feature(&cpu->env, ARM_FEATURE_VFP4); |
| 705 |
set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); |
| 706 |
set_feature(&cpu->env, ARM_FEATURE_NEON); |
| 707 |
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); |
| 708 |
set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); |
| 709 |
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); |
| 710 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
| 711 |
set_feature(&cpu->env, ARM_FEATURE_CBAR); |
| 712 |
set_feature(&cpu->env, ARM_FEATURE_LPAE); |
| 713 |
cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; |
| 714 |
cpu->midr = 0x412fc0f1;
|
| 715 |
cpu->reset_fpsid = 0x410430f0;
|
| 716 |
cpu->mvfr0 = 0x10110222;
|
| 717 |
cpu->mvfr1 = 0x11111111;
|
| 718 |
cpu->ctr = 0x8444c004;
|
| 719 |
cpu->reset_sctlr = 0x00c50078;
|
| 720 |
cpu->id_pfr0 = 0x00001131;
|
| 721 |
cpu->id_pfr1 = 0x00011011;
|
| 722 |
cpu->id_dfr0 = 0x02010555;
|
| 723 |
cpu->id_afr0 = 0x00000000;
|
| 724 |
cpu->id_mmfr0 = 0x10201105;
|
| 725 |
cpu->id_mmfr1 = 0x20000000;
|
| 726 |
cpu->id_mmfr2 = 0x01240000;
|
| 727 |
cpu->id_mmfr3 = 0x02102211;
|
| 728 |
cpu->id_isar0 = 0x02101110;
|
| 729 |
cpu->id_isar1 = 0x13112111;
|
| 730 |
cpu->id_isar2 = 0x21232041;
|
| 731 |
cpu->id_isar3 = 0x11112131;
|
| 732 |
cpu->id_isar4 = 0x10011142;
|
| 733 |
cpu->clidr = 0x0a200023;
|
| 734 |
cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ |
| 735 |
cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ |
| 736 |
cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ |
| 737 |
define_arm_cp_regs(cpu, cortexa15_cp_reginfo); |
| 738 |
} |
| 739 |
|
| 740 |
static void ti925t_initfn(Object *obj) |
| 741 |
{
|
| 742 |
ARMCPU *cpu = ARM_CPU(obj); |
| 743 |
set_feature(&cpu->env, ARM_FEATURE_V4T); |
| 744 |
set_feature(&cpu->env, ARM_FEATURE_OMAPCP); |
| 745 |
cpu->midr = ARM_CPUID_TI925T; |
| 746 |
cpu->ctr = 0x5109149;
|
| 747 |
cpu->reset_sctlr = 0x00000070;
|
| 748 |
} |
| 749 |
|
| 750 |
static void sa1100_initfn(Object *obj) |
| 751 |
{
|
| 752 |
ARMCPU *cpu = ARM_CPU(obj); |
| 753 |
|
| 754 |
cpu->dtb_compatible = "intel,sa1100";
|
| 755 |
set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
| 756 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
| 757 |
cpu->midr = 0x4401A11B;
|
| 758 |
cpu->reset_sctlr = 0x00000070;
|
| 759 |
} |
| 760 |
|
| 761 |
static void sa1110_initfn(Object *obj) |
| 762 |
{
|
| 763 |
ARMCPU *cpu = ARM_CPU(obj); |
| 764 |
set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
| 765 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
| 766 |
cpu->midr = 0x6901B119;
|
| 767 |
cpu->reset_sctlr = 0x00000070;
|
| 768 |
} |
| 769 |
|
| 770 |
static void pxa250_initfn(Object *obj) |
| 771 |
{
|
| 772 |
ARMCPU *cpu = ARM_CPU(obj); |
| 773 |
|
| 774 |
cpu->dtb_compatible = "marvell,xscale";
|
| 775 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
| 776 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
| 777 |
cpu->midr = 0x69052100;
|
| 778 |
cpu->ctr = 0xd172172;
|
| 779 |
cpu->reset_sctlr = 0x00000078;
|
| 780 |
} |
| 781 |
|
| 782 |
static void pxa255_initfn(Object *obj) |
| 783 |
{
|
| 784 |
ARMCPU *cpu = ARM_CPU(obj); |
| 785 |
|
| 786 |
cpu->dtb_compatible = "marvell,xscale";
|
| 787 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
| 788 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
| 789 |
cpu->midr = 0x69052d00;
|
| 790 |
cpu->ctr = 0xd172172;
|
| 791 |
cpu->reset_sctlr = 0x00000078;
|
| 792 |
} |
| 793 |
|
| 794 |
static void pxa260_initfn(Object *obj) |
| 795 |
{
|
| 796 |
ARMCPU *cpu = ARM_CPU(obj); |
| 797 |
|
| 798 |
cpu->dtb_compatible = "marvell,xscale";
|
| 799 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
| 800 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
| 801 |
cpu->midr = 0x69052903;
|
| 802 |
cpu->ctr = 0xd172172;
|
| 803 |
cpu->reset_sctlr = 0x00000078;
|
| 804 |
} |
| 805 |
|
| 806 |
static void pxa261_initfn(Object *obj) |
| 807 |
{
|
| 808 |
ARMCPU *cpu = ARM_CPU(obj); |
| 809 |
|
| 810 |
cpu->dtb_compatible = "marvell,xscale";
|
| 811 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
| 812 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
| 813 |
cpu->midr = 0x69052d05;
|
| 814 |
cpu->ctr = 0xd172172;
|
| 815 |
cpu->reset_sctlr = 0x00000078;
|
| 816 |
} |
| 817 |
|
| 818 |
static void pxa262_initfn(Object *obj) |
| 819 |
{
|
| 820 |
ARMCPU *cpu = ARM_CPU(obj); |
| 821 |
|
| 822 |
cpu->dtb_compatible = "marvell,xscale";
|
| 823 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
| 824 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
| 825 |
cpu->midr = 0x69052d06;
|
| 826 |
cpu->ctr = 0xd172172;
|
| 827 |
cpu->reset_sctlr = 0x00000078;
|
| 828 |
} |
| 829 |
|
| 830 |
static void pxa270a0_initfn(Object *obj) |
| 831 |
{
|
| 832 |
ARMCPU *cpu = ARM_CPU(obj); |
| 833 |
|
| 834 |
cpu->dtb_compatible = "marvell,xscale";
|
| 835 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
| 836 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
| 837 |
set_feature(&cpu->env, ARM_FEATURE_IWMMXT); |
| 838 |
cpu->midr = 0x69054110;
|
| 839 |
cpu->ctr = 0xd172172;
|
| 840 |
cpu->reset_sctlr = 0x00000078;
|
| 841 |
} |
| 842 |
|
| 843 |
static void pxa270a1_initfn(Object *obj) |
| 844 |
{
|
| 845 |
ARMCPU *cpu = ARM_CPU(obj); |
| 846 |
|
| 847 |
cpu->dtb_compatible = "marvell,xscale";
|
| 848 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
| 849 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
| 850 |
set_feature(&cpu->env, ARM_FEATURE_IWMMXT); |
| 851 |
cpu->midr = 0x69054111;
|
| 852 |
cpu->ctr = 0xd172172;
|
| 853 |
cpu->reset_sctlr = 0x00000078;
|
| 854 |
} |
| 855 |
|
| 856 |
static void pxa270b0_initfn(Object *obj) |
| 857 |
{
|
| 858 |
ARMCPU *cpu = ARM_CPU(obj); |
| 859 |
|
| 860 |
cpu->dtb_compatible = "marvell,xscale";
|
| 861 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
| 862 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
| 863 |
set_feature(&cpu->env, ARM_FEATURE_IWMMXT); |
| 864 |
cpu->midr = 0x69054112;
|
| 865 |
cpu->ctr = 0xd172172;
|
| 866 |
cpu->reset_sctlr = 0x00000078;
|
| 867 |
} |
| 868 |
|
| 869 |
static void pxa270b1_initfn(Object *obj) |
| 870 |
{
|
| 871 |
ARMCPU *cpu = ARM_CPU(obj); |
| 872 |
|
| 873 |
cpu->dtb_compatible = "marvell,xscale";
|
| 874 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
| 875 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
| 876 |
set_feature(&cpu->env, ARM_FEATURE_IWMMXT); |
| 877 |
cpu->midr = 0x69054113;
|
| 878 |
cpu->ctr = 0xd172172;
|
| 879 |
cpu->reset_sctlr = 0x00000078;
|
| 880 |
} |
| 881 |
|
| 882 |
static void pxa270c0_initfn(Object *obj) |
| 883 |
{
|
| 884 |
ARMCPU *cpu = ARM_CPU(obj); |
| 885 |
|
| 886 |
cpu->dtb_compatible = "marvell,xscale";
|
| 887 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
| 888 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
| 889 |
set_feature(&cpu->env, ARM_FEATURE_IWMMXT); |
| 890 |
cpu->midr = 0x69054114;
|
| 891 |
cpu->ctr = 0xd172172;
|
| 892 |
cpu->reset_sctlr = 0x00000078;
|
| 893 |
} |
| 894 |
|
| 895 |
static void pxa270c5_initfn(Object *obj) |
| 896 |
{
|
| 897 |
ARMCPU *cpu = ARM_CPU(obj); |
| 898 |
|
| 899 |
cpu->dtb_compatible = "marvell,xscale";
|
| 900 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
| 901 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
| 902 |
set_feature(&cpu->env, ARM_FEATURE_IWMMXT); |
| 903 |
cpu->midr = 0x69054117;
|
| 904 |
cpu->ctr = 0xd172172;
|
| 905 |
cpu->reset_sctlr = 0x00000078;
|
| 906 |
} |
| 907 |
|
| 908 |
#ifdef CONFIG_USER_ONLY
|
| 909 |
static void arm_any_initfn(Object *obj) |
| 910 |
{
|
| 911 |
ARMCPU *cpu = ARM_CPU(obj); |
| 912 |
set_feature(&cpu->env, ARM_FEATURE_V8); |
| 913 |
set_feature(&cpu->env, ARM_FEATURE_VFP4); |
| 914 |
set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); |
| 915 |
set_feature(&cpu->env, ARM_FEATURE_NEON); |
| 916 |
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); |
| 917 |
set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); |
| 918 |
set_feature(&cpu->env, ARM_FEATURE_V7MP); |
| 919 |
#ifdef TARGET_AARCH64
|
| 920 |
set_feature(&cpu->env, ARM_FEATURE_AARCH64); |
| 921 |
#endif
|
| 922 |
cpu->midr = 0xffffffff;
|
| 923 |
} |
| 924 |
#endif
|
| 925 |
|
| 926 |
#endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ |
| 927 |
|
| 928 |
typedef struct ARMCPUInfo { |
| 929 |
const char *name; |
| 930 |
void (*initfn)(Object *obj);
|
| 931 |
void (*class_init)(ObjectClass *oc, void *data); |
| 932 |
} ARMCPUInfo; |
| 933 |
|
| 934 |
static const ARMCPUInfo arm_cpus[] = { |
| 935 |
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
|
| 936 |
{ .name = "arm926", .initfn = arm926_initfn },
|
| 937 |
{ .name = "arm946", .initfn = arm946_initfn },
|
| 938 |
{ .name = "arm1026", .initfn = arm1026_initfn },
|
| 939 |
/* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
|
| 940 |
* older core than plain "arm1136". In particular this does not
|
| 941 |
* have the v6K features.
|
| 942 |
*/
|
| 943 |
{ .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
|
| 944 |
{ .name = "arm1136", .initfn = arm1136_initfn },
|
| 945 |
{ .name = "arm1176", .initfn = arm1176_initfn },
|
| 946 |
{ .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
|
| 947 |
{ .name = "cortex-m3", .initfn = cortex_m3_initfn,
|
| 948 |
.class_init = arm_v7m_class_init }, |
| 949 |
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
|
| 950 |
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
|
| 951 |
{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
|
| 952 |
{ .name = "ti925t", .initfn = ti925t_initfn },
|
| 953 |
{ .name = "sa1100", .initfn = sa1100_initfn },
|
| 954 |
{ .name = "sa1110", .initfn = sa1110_initfn },
|
| 955 |
{ .name = "pxa250", .initfn = pxa250_initfn },
|
| 956 |
{ .name = "pxa255", .initfn = pxa255_initfn },
|
| 957 |
{ .name = "pxa260", .initfn = pxa260_initfn },
|
| 958 |
{ .name = "pxa261", .initfn = pxa261_initfn },
|
| 959 |
{ .name = "pxa262", .initfn = pxa262_initfn },
|
| 960 |
/* "pxa270" is an alias for "pxa270-a0" */
|
| 961 |
{ .name = "pxa270", .initfn = pxa270a0_initfn },
|
| 962 |
{ .name = "pxa270-a0", .initfn = pxa270a0_initfn },
|
| 963 |
{ .name = "pxa270-a1", .initfn = pxa270a1_initfn },
|
| 964 |
{ .name = "pxa270-b0", .initfn = pxa270b0_initfn },
|
| 965 |
{ .name = "pxa270-b1", .initfn = pxa270b1_initfn },
|
| 966 |
{ .name = "pxa270-c0", .initfn = pxa270c0_initfn },
|
| 967 |
{ .name = "pxa270-c5", .initfn = pxa270c5_initfn },
|
| 968 |
#ifdef CONFIG_USER_ONLY
|
| 969 |
{ .name = "any", .initfn = arm_any_initfn },
|
| 970 |
#endif
|
| 971 |
#endif
|
| 972 |
}; |
| 973 |
|
| 974 |
static Property arm_cpu_properties[] = {
|
| 975 |
DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), |
| 976 |
DEFINE_PROP_END_OF_LIST() |
| 977 |
}; |
| 978 |
|
| 979 |
static void arm_cpu_class_init(ObjectClass *oc, void *data) |
| 980 |
{
|
| 981 |
ARMCPUClass *acc = ARM_CPU_CLASS(oc); |
| 982 |
CPUClass *cc = CPU_CLASS(acc); |
| 983 |
DeviceClass *dc = DEVICE_CLASS(oc); |
| 984 |
|
| 985 |
acc->parent_realize = dc->realize; |
| 986 |
dc->realize = arm_cpu_realizefn; |
| 987 |
dc->props = arm_cpu_properties; |
| 988 |
|
| 989 |
acc->parent_reset = cc->reset; |
| 990 |
cc->reset = arm_cpu_reset; |
| 991 |
|
| 992 |
cc->class_by_name = arm_cpu_class_by_name; |
| 993 |
cc->do_interrupt = arm_cpu_do_interrupt; |
| 994 |
cc->dump_state = arm_cpu_dump_state; |
| 995 |
cc->set_pc = arm_cpu_set_pc; |
| 996 |
cc->gdb_read_register = arm_cpu_gdb_read_register; |
| 997 |
cc->gdb_write_register = arm_cpu_gdb_write_register; |
| 998 |
#ifndef CONFIG_USER_ONLY
|
| 999 |
cc->get_phys_page_debug = arm_cpu_get_phys_page_debug; |
| 1000 |
cc->vmsd = &vmstate_arm_cpu; |
| 1001 |
#endif
|
| 1002 |
cc->gdb_num_core_regs = 26;
|
| 1003 |
cc->gdb_core_xml_file = "arm-core.xml";
|
| 1004 |
} |
| 1005 |
|
| 1006 |
static void cpu_register(const ARMCPUInfo *info) |
| 1007 |
{
|
| 1008 |
TypeInfo type_info = {
|
| 1009 |
.parent = TYPE_ARM_CPU, |
| 1010 |
.instance_size = sizeof(ARMCPU),
|
| 1011 |
.instance_init = info->initfn, |
| 1012 |
.class_size = sizeof(ARMCPUClass),
|
| 1013 |
.class_init = info->class_init, |
| 1014 |
}; |
| 1015 |
|
| 1016 |
type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
|
| 1017 |
type_register(&type_info); |
| 1018 |
g_free((void *)type_info.name);
|
| 1019 |
} |
| 1020 |
|
| 1021 |
static const TypeInfo arm_cpu_type_info = { |
| 1022 |
.name = TYPE_ARM_CPU, |
| 1023 |
.parent = TYPE_CPU, |
| 1024 |
.instance_size = sizeof(ARMCPU),
|
| 1025 |
.instance_init = arm_cpu_initfn, |
| 1026 |
.instance_post_init = arm_cpu_post_init, |
| 1027 |
.instance_finalize = arm_cpu_finalizefn, |
| 1028 |
.abstract = true,
|
| 1029 |
.class_size = sizeof(ARMCPUClass),
|
| 1030 |
.class_init = arm_cpu_class_init, |
| 1031 |
}; |
| 1032 |
|
| 1033 |
static void arm_cpu_register_types(void) |
| 1034 |
{
|
| 1035 |
int i;
|
| 1036 |
|
| 1037 |
type_register_static(&arm_cpu_type_info); |
| 1038 |
for (i = 0; i < ARRAY_SIZE(arm_cpus); i++) { |
| 1039 |
cpu_register(&arm_cpus[i]); |
| 1040 |
} |
| 1041 |
} |
| 1042 |
|
| 1043 |
type_init(arm_cpu_register_types) |