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1 | 5a9fdfec | bellard | /*
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2 | 5a9fdfec | bellard | * defines common to all virtual CPUs
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3 | 5fafdf24 | ths | *
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4 | 5a9fdfec | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 5a9fdfec | bellard | *
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6 | 5a9fdfec | bellard | * This library is free software; you can redistribute it and/or
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7 | 5a9fdfec | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 5a9fdfec | bellard | * License as published by the Free Software Foundation; either
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9 | 5a9fdfec | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 5a9fdfec | bellard | *
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11 | 5a9fdfec | bellard | * This library is distributed in the hope that it will be useful,
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12 | 5a9fdfec | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 5a9fdfec | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 5a9fdfec | bellard | * Lesser General Public License for more details.
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15 | 5a9fdfec | bellard | *
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16 | 5a9fdfec | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | 5a9fdfec | bellard | */
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19 | 5a9fdfec | bellard | #ifndef CPU_ALL_H
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20 | 5a9fdfec | bellard | #define CPU_ALL_H
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21 | 5a9fdfec | bellard | |
22 | 7d99a001 | blueswir1 | #include "qemu-common.h" |
23 | 1ad2134f | Paul Brook | #include "cpu-common.h" |
24 | 0ac4bd56 | bellard | |
25 | 5fafdf24 | ths | /* some important defines:
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26 | 5fafdf24 | ths | *
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27 | 0ac4bd56 | bellard | * WORDS_ALIGNED : if defined, the host cpu can only make word aligned
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28 | 0ac4bd56 | bellard | * memory accesses.
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29 | 5fafdf24 | ths | *
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30 | e2542fe2 | Juan Quintela | * HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and
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31 | 0ac4bd56 | bellard | * otherwise little endian.
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32 | 5fafdf24 | ths | *
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33 | 0ac4bd56 | bellard | * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
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34 | 5fafdf24 | ths | *
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35 | 0ac4bd56 | bellard | * TARGET_WORDS_BIGENDIAN : same for target cpu
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36 | 0ac4bd56 | bellard | */
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37 | 0ac4bd56 | bellard | |
38 | 939ef593 | aurel32 | #include "softfloat.h" |
39 | f193c797 | bellard | |
40 | e2542fe2 | Juan Quintela | #if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
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41 | f193c797 | bellard | #define BSWAP_NEEDED
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42 | f193c797 | bellard | #endif
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43 | f193c797 | bellard | |
44 | f193c797 | bellard | #ifdef BSWAP_NEEDED
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45 | f193c797 | bellard | |
46 | f193c797 | bellard | static inline uint16_t tswap16(uint16_t s) |
47 | f193c797 | bellard | { |
48 | f193c797 | bellard | return bswap16(s);
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49 | f193c797 | bellard | } |
50 | f193c797 | bellard | |
51 | f193c797 | bellard | static inline uint32_t tswap32(uint32_t s) |
52 | f193c797 | bellard | { |
53 | f193c797 | bellard | return bswap32(s);
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54 | f193c797 | bellard | } |
55 | f193c797 | bellard | |
56 | f193c797 | bellard | static inline uint64_t tswap64(uint64_t s) |
57 | f193c797 | bellard | { |
58 | f193c797 | bellard | return bswap64(s);
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59 | f193c797 | bellard | } |
60 | f193c797 | bellard | |
61 | f193c797 | bellard | static inline void tswap16s(uint16_t *s) |
62 | f193c797 | bellard | { |
63 | f193c797 | bellard | *s = bswap16(*s); |
64 | f193c797 | bellard | } |
65 | f193c797 | bellard | |
66 | f193c797 | bellard | static inline void tswap32s(uint32_t *s) |
67 | f193c797 | bellard | { |
68 | f193c797 | bellard | *s = bswap32(*s); |
69 | f193c797 | bellard | } |
70 | f193c797 | bellard | |
71 | f193c797 | bellard | static inline void tswap64s(uint64_t *s) |
72 | f193c797 | bellard | { |
73 | f193c797 | bellard | *s = bswap64(*s); |
74 | f193c797 | bellard | } |
75 | f193c797 | bellard | |
76 | f193c797 | bellard | #else
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77 | f193c797 | bellard | |
78 | f193c797 | bellard | static inline uint16_t tswap16(uint16_t s) |
79 | f193c797 | bellard | { |
80 | f193c797 | bellard | return s;
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81 | f193c797 | bellard | } |
82 | f193c797 | bellard | |
83 | f193c797 | bellard | static inline uint32_t tswap32(uint32_t s) |
84 | f193c797 | bellard | { |
85 | f193c797 | bellard | return s;
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86 | f193c797 | bellard | } |
87 | f193c797 | bellard | |
88 | f193c797 | bellard | static inline uint64_t tswap64(uint64_t s) |
89 | f193c797 | bellard | { |
90 | f193c797 | bellard | return s;
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91 | f193c797 | bellard | } |
92 | f193c797 | bellard | |
93 | f193c797 | bellard | static inline void tswap16s(uint16_t *s) |
94 | f193c797 | bellard | { |
95 | f193c797 | bellard | } |
96 | f193c797 | bellard | |
97 | f193c797 | bellard | static inline void tswap32s(uint32_t *s) |
98 | f193c797 | bellard | { |
99 | f193c797 | bellard | } |
100 | f193c797 | bellard | |
101 | f193c797 | bellard | static inline void tswap64s(uint64_t *s) |
102 | f193c797 | bellard | { |
103 | f193c797 | bellard | } |
104 | f193c797 | bellard | |
105 | f193c797 | bellard | #endif
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106 | f193c797 | bellard | |
107 | f193c797 | bellard | #if TARGET_LONG_SIZE == 4 |
108 | f193c797 | bellard | #define tswapl(s) tswap32(s)
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109 | f193c797 | bellard | #define tswapls(s) tswap32s((uint32_t *)(s))
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110 | 0a962c02 | bellard | #define bswaptls(s) bswap32s(s)
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111 | f193c797 | bellard | #else
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112 | f193c797 | bellard | #define tswapl(s) tswap64(s)
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113 | f193c797 | bellard | #define tswapls(s) tswap64s((uint64_t *)(s))
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114 | 0a962c02 | bellard | #define bswaptls(s) bswap64s(s)
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115 | f193c797 | bellard | #endif
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116 | f193c797 | bellard | |
117 | 0ca9d380 | aurel32 | typedef union { |
118 | 0ca9d380 | aurel32 | float32 f; |
119 | 0ca9d380 | aurel32 | uint32_t l; |
120 | 0ca9d380 | aurel32 | } CPU_FloatU; |
121 | 0ca9d380 | aurel32 | |
122 | 832ed0fa | bellard | /* NOTE: arm FPA is horrible as double 32 bit words are stored in big
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123 | 832ed0fa | bellard | endian ! */
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124 | 0ac4bd56 | bellard | typedef union { |
125 | 53cd6637 | bellard | float64 d; |
126 | e2542fe2 | Juan Quintela | #if defined(HOST_WORDS_BIGENDIAN) \
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127 | 9d60cac0 | bellard | || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT)) |
128 | 0ac4bd56 | bellard | struct {
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129 | 0ac4bd56 | bellard | uint32_t upper; |
130 | 832ed0fa | bellard | uint32_t lower; |
131 | 0ac4bd56 | bellard | } l; |
132 | 0ac4bd56 | bellard | #else
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133 | 0ac4bd56 | bellard | struct {
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134 | 0ac4bd56 | bellard | uint32_t lower; |
135 | 832ed0fa | bellard | uint32_t upper; |
136 | 0ac4bd56 | bellard | } l; |
137 | 0ac4bd56 | bellard | #endif
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138 | 0ac4bd56 | bellard | uint64_t ll; |
139 | 0ac4bd56 | bellard | } CPU_DoubleU; |
140 | 0ac4bd56 | bellard | |
141 | 1f587329 | blueswir1 | #ifdef TARGET_SPARC
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142 | 1f587329 | blueswir1 | typedef union { |
143 | 1f587329 | blueswir1 | float128 q; |
144 | e2542fe2 | Juan Quintela | #if defined(HOST_WORDS_BIGENDIAN) \
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145 | 1f587329 | blueswir1 | || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT)) |
146 | 1f587329 | blueswir1 | struct {
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147 | 1f587329 | blueswir1 | uint32_t upmost; |
148 | 1f587329 | blueswir1 | uint32_t upper; |
149 | 1f587329 | blueswir1 | uint32_t lower; |
150 | 1f587329 | blueswir1 | uint32_t lowest; |
151 | 1f587329 | blueswir1 | } l; |
152 | 1f587329 | blueswir1 | struct {
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153 | 1f587329 | blueswir1 | uint64_t upper; |
154 | 1f587329 | blueswir1 | uint64_t lower; |
155 | 1f587329 | blueswir1 | } ll; |
156 | 1f587329 | blueswir1 | #else
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157 | 1f587329 | blueswir1 | struct {
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158 | 1f587329 | blueswir1 | uint32_t lowest; |
159 | 1f587329 | blueswir1 | uint32_t lower; |
160 | 1f587329 | blueswir1 | uint32_t upper; |
161 | 1f587329 | blueswir1 | uint32_t upmost; |
162 | 1f587329 | blueswir1 | } l; |
163 | 1f587329 | blueswir1 | struct {
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164 | 1f587329 | blueswir1 | uint64_t lower; |
165 | 1f587329 | blueswir1 | uint64_t upper; |
166 | 1f587329 | blueswir1 | } ll; |
167 | 1f587329 | blueswir1 | #endif
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168 | 1f587329 | blueswir1 | } CPU_QuadU; |
169 | 1f587329 | blueswir1 | #endif
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170 | 1f587329 | blueswir1 | |
171 | 61382a50 | bellard | /* CPU memory access without any memory or io remapping */
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172 | 61382a50 | bellard | |
173 | 83d73968 | bellard | /*
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174 | 83d73968 | bellard | * the generic syntax for the memory accesses is:
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175 | 83d73968 | bellard | *
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176 | 83d73968 | bellard | * load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
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177 | 83d73968 | bellard | *
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178 | 83d73968 | bellard | * store: st{type}{size}{endian}_{access_type}(ptr, val)
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179 | 83d73968 | bellard | *
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180 | 83d73968 | bellard | * type is:
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181 | 83d73968 | bellard | * (empty): integer access
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182 | 83d73968 | bellard | * f : float access
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183 | 5fafdf24 | ths | *
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184 | 83d73968 | bellard | * sign is:
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185 | 83d73968 | bellard | * (empty): for floats or 32 bit size
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186 | 83d73968 | bellard | * u : unsigned
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187 | 83d73968 | bellard | * s : signed
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188 | 83d73968 | bellard | *
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189 | 83d73968 | bellard | * size is:
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190 | 83d73968 | bellard | * b: 8 bits
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191 | 83d73968 | bellard | * w: 16 bits
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192 | 83d73968 | bellard | * l: 32 bits
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193 | 83d73968 | bellard | * q: 64 bits
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194 | 5fafdf24 | ths | *
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195 | 83d73968 | bellard | * endian is:
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196 | 83d73968 | bellard | * (empty): target cpu endianness or 8 bit access
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197 | 83d73968 | bellard | * r : reversed target cpu endianness (not implemented yet)
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198 | 83d73968 | bellard | * be : big endian (not implemented yet)
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199 | 83d73968 | bellard | * le : little endian (not implemented yet)
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200 | 83d73968 | bellard | *
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201 | 83d73968 | bellard | * access_type is:
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202 | 83d73968 | bellard | * raw : host memory access
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203 | 83d73968 | bellard | * user : user mode access using soft MMU
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204 | 83d73968 | bellard | * kernel : kernel mode access using soft MMU
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205 | 83d73968 | bellard | */
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206 | 8bba3ea1 | balrog | static inline int ldub_p(const void *ptr) |
207 | 5a9fdfec | bellard | { |
208 | 5a9fdfec | bellard | return *(uint8_t *)ptr;
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209 | 5a9fdfec | bellard | } |
210 | 5a9fdfec | bellard | |
211 | 8bba3ea1 | balrog | static inline int ldsb_p(const void *ptr) |
212 | 5a9fdfec | bellard | { |
213 | 5a9fdfec | bellard | return *(int8_t *)ptr;
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214 | 5a9fdfec | bellard | } |
215 | 5a9fdfec | bellard | |
216 | c27004ec | bellard | static inline void stb_p(void *ptr, int v) |
217 | 5a9fdfec | bellard | { |
218 | 5a9fdfec | bellard | *(uint8_t *)ptr = v; |
219 | 5a9fdfec | bellard | } |
220 | 5a9fdfec | bellard | |
221 | 5a9fdfec | bellard | /* NOTE: on arm, putting 2 in /proc/sys/debug/alignment so that the
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222 | 5a9fdfec | bellard | kernel handles unaligned load/stores may give better results, but
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223 | 5a9fdfec | bellard | it is a system wide setting : bad */
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224 | e2542fe2 | Juan Quintela | #if defined(HOST_WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
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225 | 5a9fdfec | bellard | |
226 | 5a9fdfec | bellard | /* conservative code for little endian unaligned accesses */
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227 | 8bba3ea1 | balrog | static inline int lduw_le_p(const void *ptr) |
228 | 5a9fdfec | bellard | { |
229 | e58ffeb3 | malc | #ifdef _ARCH_PPC
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230 | 5a9fdfec | bellard | int val;
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231 | 5a9fdfec | bellard | __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr)); |
232 | 5a9fdfec | bellard | return val;
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233 | 5a9fdfec | bellard | #else
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234 | e01fe6d5 | malc | const uint8_t *p = ptr;
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235 | 5a9fdfec | bellard | return p[0] | (p[1] << 8); |
236 | 5a9fdfec | bellard | #endif
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237 | 5a9fdfec | bellard | } |
238 | 5a9fdfec | bellard | |
239 | 8bba3ea1 | balrog | static inline int ldsw_le_p(const void *ptr) |
240 | 5a9fdfec | bellard | { |
241 | e58ffeb3 | malc | #ifdef _ARCH_PPC
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242 | 5a9fdfec | bellard | int val;
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243 | 5a9fdfec | bellard | __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr)); |
244 | 5a9fdfec | bellard | return (int16_t)val;
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245 | 5a9fdfec | bellard | #else
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246 | e01fe6d5 | malc | const uint8_t *p = ptr;
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247 | 5a9fdfec | bellard | return (int16_t)(p[0] | (p[1] << 8)); |
248 | 5a9fdfec | bellard | #endif
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249 | 5a9fdfec | bellard | } |
250 | 5a9fdfec | bellard | |
251 | 8bba3ea1 | balrog | static inline int ldl_le_p(const void *ptr) |
252 | 5a9fdfec | bellard | { |
253 | e58ffeb3 | malc | #ifdef _ARCH_PPC
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254 | 5a9fdfec | bellard | int val;
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255 | 5a9fdfec | bellard | __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (ptr)); |
256 | 5a9fdfec | bellard | return val;
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257 | 5a9fdfec | bellard | #else
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258 | e01fe6d5 | malc | const uint8_t *p = ptr;
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259 | 5a9fdfec | bellard | return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24); |
260 | 5a9fdfec | bellard | #endif
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261 | 5a9fdfec | bellard | } |
262 | 5a9fdfec | bellard | |
263 | 8bba3ea1 | balrog | static inline uint64_t ldq_le_p(const void *ptr) |
264 | 5a9fdfec | bellard | { |
265 | e01fe6d5 | malc | const uint8_t *p = ptr;
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266 | 5a9fdfec | bellard | uint32_t v1, v2; |
267 | f0aca822 | bellard | v1 = ldl_le_p(p); |
268 | f0aca822 | bellard | v2 = ldl_le_p(p + 4);
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269 | 5a9fdfec | bellard | return v1 | ((uint64_t)v2 << 32); |
270 | 5a9fdfec | bellard | } |
271 | 5a9fdfec | bellard | |
272 | 2df3b95d | bellard | static inline void stw_le_p(void *ptr, int v) |
273 | 5a9fdfec | bellard | { |
274 | e58ffeb3 | malc | #ifdef _ARCH_PPC
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275 | 5a9fdfec | bellard | __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr) : "r" (v), "r" (ptr)); |
276 | 5a9fdfec | bellard | #else
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277 | 5a9fdfec | bellard | uint8_t *p = ptr; |
278 | 5a9fdfec | bellard | p[0] = v;
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279 | 5a9fdfec | bellard | p[1] = v >> 8; |
280 | 5a9fdfec | bellard | #endif
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281 | 5a9fdfec | bellard | } |
282 | 5a9fdfec | bellard | |
283 | 2df3b95d | bellard | static inline void stl_le_p(void *ptr, int v) |
284 | 5a9fdfec | bellard | { |
285 | e58ffeb3 | malc | #ifdef _ARCH_PPC
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286 | 5a9fdfec | bellard | __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr) : "r" (v), "r" (ptr)); |
287 | 5a9fdfec | bellard | #else
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288 | 5a9fdfec | bellard | uint8_t *p = ptr; |
289 | 5a9fdfec | bellard | p[0] = v;
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290 | 5a9fdfec | bellard | p[1] = v >> 8; |
291 | 5a9fdfec | bellard | p[2] = v >> 16; |
292 | 5a9fdfec | bellard | p[3] = v >> 24; |
293 | 5a9fdfec | bellard | #endif
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294 | 5a9fdfec | bellard | } |
295 | 5a9fdfec | bellard | |
296 | 2df3b95d | bellard | static inline void stq_le_p(void *ptr, uint64_t v) |
297 | 5a9fdfec | bellard | { |
298 | 5a9fdfec | bellard | uint8_t *p = ptr; |
299 | f0aca822 | bellard | stl_le_p(p, (uint32_t)v); |
300 | f0aca822 | bellard | stl_le_p(p + 4, v >> 32); |
301 | 5a9fdfec | bellard | } |
302 | 5a9fdfec | bellard | |
303 | 5a9fdfec | bellard | /* float access */
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304 | 5a9fdfec | bellard | |
305 | 8bba3ea1 | balrog | static inline float32 ldfl_le_p(const void *ptr) |
306 | 5a9fdfec | bellard | { |
307 | 5a9fdfec | bellard | union {
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308 | 53cd6637 | bellard | float32 f; |
309 | 5a9fdfec | bellard | uint32_t i; |
310 | 5a9fdfec | bellard | } u; |
311 | 2df3b95d | bellard | u.i = ldl_le_p(ptr); |
312 | 5a9fdfec | bellard | return u.f;
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313 | 5a9fdfec | bellard | } |
314 | 5a9fdfec | bellard | |
315 | 2df3b95d | bellard | static inline void stfl_le_p(void *ptr, float32 v) |
316 | 5a9fdfec | bellard | { |
317 | 5a9fdfec | bellard | union {
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318 | 53cd6637 | bellard | float32 f; |
319 | 5a9fdfec | bellard | uint32_t i; |
320 | 5a9fdfec | bellard | } u; |
321 | 5a9fdfec | bellard | u.f = v; |
322 | 2df3b95d | bellard | stl_le_p(ptr, u.i); |
323 | 5a9fdfec | bellard | } |
324 | 5a9fdfec | bellard | |
325 | 8bba3ea1 | balrog | static inline float64 ldfq_le_p(const void *ptr) |
326 | 5a9fdfec | bellard | { |
327 | 0ac4bd56 | bellard | CPU_DoubleU u; |
328 | 2df3b95d | bellard | u.l.lower = ldl_le_p(ptr); |
329 | 2df3b95d | bellard | u.l.upper = ldl_le_p(ptr + 4);
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330 | 5a9fdfec | bellard | return u.d;
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331 | 5a9fdfec | bellard | } |
332 | 5a9fdfec | bellard | |
333 | 2df3b95d | bellard | static inline void stfq_le_p(void *ptr, float64 v) |
334 | 5a9fdfec | bellard | { |
335 | 0ac4bd56 | bellard | CPU_DoubleU u; |
336 | 5a9fdfec | bellard | u.d = v; |
337 | 2df3b95d | bellard | stl_le_p(ptr, u.l.lower); |
338 | 2df3b95d | bellard | stl_le_p(ptr + 4, u.l.upper);
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339 | 5a9fdfec | bellard | } |
340 | 5a9fdfec | bellard | |
341 | 2df3b95d | bellard | #else
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342 | 2df3b95d | bellard | |
343 | 8bba3ea1 | balrog | static inline int lduw_le_p(const void *ptr) |
344 | 2df3b95d | bellard | { |
345 | 2df3b95d | bellard | return *(uint16_t *)ptr;
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346 | 2df3b95d | bellard | } |
347 | 2df3b95d | bellard | |
348 | 8bba3ea1 | balrog | static inline int ldsw_le_p(const void *ptr) |
349 | 2df3b95d | bellard | { |
350 | 2df3b95d | bellard | return *(int16_t *)ptr;
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351 | 2df3b95d | bellard | } |
352 | 93ac68bc | bellard | |
353 | 8bba3ea1 | balrog | static inline int ldl_le_p(const void *ptr) |
354 | 2df3b95d | bellard | { |
355 | 2df3b95d | bellard | return *(uint32_t *)ptr;
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356 | 2df3b95d | bellard | } |
357 | 2df3b95d | bellard | |
358 | 8bba3ea1 | balrog | static inline uint64_t ldq_le_p(const void *ptr) |
359 | 2df3b95d | bellard | { |
360 | 2df3b95d | bellard | return *(uint64_t *)ptr;
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361 | 2df3b95d | bellard | } |
362 | 2df3b95d | bellard | |
363 | 2df3b95d | bellard | static inline void stw_le_p(void *ptr, int v) |
364 | 2df3b95d | bellard | { |
365 | 2df3b95d | bellard | *(uint16_t *)ptr = v; |
366 | 2df3b95d | bellard | } |
367 | 2df3b95d | bellard | |
368 | 2df3b95d | bellard | static inline void stl_le_p(void *ptr, int v) |
369 | 2df3b95d | bellard | { |
370 | 2df3b95d | bellard | *(uint32_t *)ptr = v; |
371 | 2df3b95d | bellard | } |
372 | 2df3b95d | bellard | |
373 | 2df3b95d | bellard | static inline void stq_le_p(void *ptr, uint64_t v) |
374 | 2df3b95d | bellard | { |
375 | 2df3b95d | bellard | *(uint64_t *)ptr = v; |
376 | 2df3b95d | bellard | } |
377 | 2df3b95d | bellard | |
378 | 2df3b95d | bellard | /* float access */
|
379 | 2df3b95d | bellard | |
380 | 8bba3ea1 | balrog | static inline float32 ldfl_le_p(const void *ptr) |
381 | 2df3b95d | bellard | { |
382 | 2df3b95d | bellard | return *(float32 *)ptr;
|
383 | 2df3b95d | bellard | } |
384 | 2df3b95d | bellard | |
385 | 8bba3ea1 | balrog | static inline float64 ldfq_le_p(const void *ptr) |
386 | 2df3b95d | bellard | { |
387 | 2df3b95d | bellard | return *(float64 *)ptr;
|
388 | 2df3b95d | bellard | } |
389 | 2df3b95d | bellard | |
390 | 2df3b95d | bellard | static inline void stfl_le_p(void *ptr, float32 v) |
391 | 2df3b95d | bellard | { |
392 | 2df3b95d | bellard | *(float32 *)ptr = v; |
393 | 2df3b95d | bellard | } |
394 | 2df3b95d | bellard | |
395 | 2df3b95d | bellard | static inline void stfq_le_p(void *ptr, float64 v) |
396 | 2df3b95d | bellard | { |
397 | 2df3b95d | bellard | *(float64 *)ptr = v; |
398 | 2df3b95d | bellard | } |
399 | 2df3b95d | bellard | #endif
|
400 | 2df3b95d | bellard | |
401 | e2542fe2 | Juan Quintela | #if !defined(HOST_WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
|
402 | 2df3b95d | bellard | |
403 | 8bba3ea1 | balrog | static inline int lduw_be_p(const void *ptr) |
404 | 93ac68bc | bellard | { |
405 | 83d73968 | bellard | #if defined(__i386__)
|
406 | 83d73968 | bellard | int val;
|
407 | 83d73968 | bellard | asm volatile ("movzwl %1, %0\n" |
408 | 83d73968 | bellard | "xchgb %b0, %h0\n"
|
409 | 83d73968 | bellard | : "=q" (val)
|
410 | 83d73968 | bellard | : "m" (*(uint16_t *)ptr));
|
411 | 83d73968 | bellard | return val;
|
412 | 83d73968 | bellard | #else
|
413 | e01fe6d5 | malc | const uint8_t *b = ptr;
|
414 | 83d73968 | bellard | return ((b[0] << 8) | b[1]); |
415 | 83d73968 | bellard | #endif
|
416 | 93ac68bc | bellard | } |
417 | 93ac68bc | bellard | |
418 | 8bba3ea1 | balrog | static inline int ldsw_be_p(const void *ptr) |
419 | 93ac68bc | bellard | { |
420 | 83d73968 | bellard | #if defined(__i386__)
|
421 | 83d73968 | bellard | int val;
|
422 | 83d73968 | bellard | asm volatile ("movzwl %1, %0\n" |
423 | 83d73968 | bellard | "xchgb %b0, %h0\n"
|
424 | 83d73968 | bellard | : "=q" (val)
|
425 | 83d73968 | bellard | : "m" (*(uint16_t *)ptr));
|
426 | 83d73968 | bellard | return (int16_t)val;
|
427 | 83d73968 | bellard | #else
|
428 | e01fe6d5 | malc | const uint8_t *b = ptr;
|
429 | 83d73968 | bellard | return (int16_t)((b[0] << 8) | b[1]); |
430 | 83d73968 | bellard | #endif
|
431 | 93ac68bc | bellard | } |
432 | 93ac68bc | bellard | |
433 | 8bba3ea1 | balrog | static inline int ldl_be_p(const void *ptr) |
434 | 93ac68bc | bellard | { |
435 | 4f2ac237 | bellard | #if defined(__i386__) || defined(__x86_64__)
|
436 | 83d73968 | bellard | int val;
|
437 | 83d73968 | bellard | asm volatile ("movl %1, %0\n" |
438 | 83d73968 | bellard | "bswap %0\n"
|
439 | 83d73968 | bellard | : "=r" (val)
|
440 | 83d73968 | bellard | : "m" (*(uint32_t *)ptr));
|
441 | 83d73968 | bellard | return val;
|
442 | 83d73968 | bellard | #else
|
443 | e01fe6d5 | malc | const uint8_t *b = ptr;
|
444 | 83d73968 | bellard | return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3]; |
445 | 83d73968 | bellard | #endif
|
446 | 93ac68bc | bellard | } |
447 | 93ac68bc | bellard | |
448 | 8bba3ea1 | balrog | static inline uint64_t ldq_be_p(const void *ptr) |
449 | 93ac68bc | bellard | { |
450 | 93ac68bc | bellard | uint32_t a,b; |
451 | 2df3b95d | bellard | a = ldl_be_p(ptr); |
452 | 4d7a0880 | blueswir1 | b = ldl_be_p((uint8_t *)ptr + 4);
|
453 | 93ac68bc | bellard | return (((uint64_t)a<<32)|b); |
454 | 93ac68bc | bellard | } |
455 | 93ac68bc | bellard | |
456 | 2df3b95d | bellard | static inline void stw_be_p(void *ptr, int v) |
457 | 93ac68bc | bellard | { |
458 | 83d73968 | bellard | #if defined(__i386__)
|
459 | 83d73968 | bellard | asm volatile ("xchgb %b0, %h0\n" |
460 | 83d73968 | bellard | "movw %w0, %1\n"
|
461 | 83d73968 | bellard | : "=q" (v)
|
462 | 83d73968 | bellard | : "m" (*(uint16_t *)ptr), "0" (v)); |
463 | 83d73968 | bellard | #else
|
464 | 93ac68bc | bellard | uint8_t *d = (uint8_t *) ptr; |
465 | 93ac68bc | bellard | d[0] = v >> 8; |
466 | 93ac68bc | bellard | d[1] = v;
|
467 | 83d73968 | bellard | #endif
|
468 | 93ac68bc | bellard | } |
469 | 93ac68bc | bellard | |
470 | 2df3b95d | bellard | static inline void stl_be_p(void *ptr, int v) |
471 | 93ac68bc | bellard | { |
472 | 4f2ac237 | bellard | #if defined(__i386__) || defined(__x86_64__)
|
473 | 83d73968 | bellard | asm volatile ("bswap %0\n" |
474 | 83d73968 | bellard | "movl %0, %1\n"
|
475 | 83d73968 | bellard | : "=r" (v)
|
476 | 83d73968 | bellard | : "m" (*(uint32_t *)ptr), "0" (v)); |
477 | 83d73968 | bellard | #else
|
478 | 93ac68bc | bellard | uint8_t *d = (uint8_t *) ptr; |
479 | 93ac68bc | bellard | d[0] = v >> 24; |
480 | 93ac68bc | bellard | d[1] = v >> 16; |
481 | 93ac68bc | bellard | d[2] = v >> 8; |
482 | 93ac68bc | bellard | d[3] = v;
|
483 | 83d73968 | bellard | #endif
|
484 | 93ac68bc | bellard | } |
485 | 93ac68bc | bellard | |
486 | 2df3b95d | bellard | static inline void stq_be_p(void *ptr, uint64_t v) |
487 | 93ac68bc | bellard | { |
488 | 2df3b95d | bellard | stl_be_p(ptr, v >> 32);
|
489 | 4d7a0880 | blueswir1 | stl_be_p((uint8_t *)ptr + 4, v);
|
490 | 0ac4bd56 | bellard | } |
491 | 0ac4bd56 | bellard | |
492 | 0ac4bd56 | bellard | /* float access */
|
493 | 0ac4bd56 | bellard | |
494 | 8bba3ea1 | balrog | static inline float32 ldfl_be_p(const void *ptr) |
495 | 0ac4bd56 | bellard | { |
496 | 0ac4bd56 | bellard | union {
|
497 | 53cd6637 | bellard | float32 f; |
498 | 0ac4bd56 | bellard | uint32_t i; |
499 | 0ac4bd56 | bellard | } u; |
500 | 2df3b95d | bellard | u.i = ldl_be_p(ptr); |
501 | 0ac4bd56 | bellard | return u.f;
|
502 | 0ac4bd56 | bellard | } |
503 | 0ac4bd56 | bellard | |
504 | 2df3b95d | bellard | static inline void stfl_be_p(void *ptr, float32 v) |
505 | 0ac4bd56 | bellard | { |
506 | 0ac4bd56 | bellard | union {
|
507 | 53cd6637 | bellard | float32 f; |
508 | 0ac4bd56 | bellard | uint32_t i; |
509 | 0ac4bd56 | bellard | } u; |
510 | 0ac4bd56 | bellard | u.f = v; |
511 | 2df3b95d | bellard | stl_be_p(ptr, u.i); |
512 | 0ac4bd56 | bellard | } |
513 | 0ac4bd56 | bellard | |
514 | 8bba3ea1 | balrog | static inline float64 ldfq_be_p(const void *ptr) |
515 | 0ac4bd56 | bellard | { |
516 | 0ac4bd56 | bellard | CPU_DoubleU u; |
517 | 2df3b95d | bellard | u.l.upper = ldl_be_p(ptr); |
518 | 4d7a0880 | blueswir1 | u.l.lower = ldl_be_p((uint8_t *)ptr + 4);
|
519 | 0ac4bd56 | bellard | return u.d;
|
520 | 0ac4bd56 | bellard | } |
521 | 0ac4bd56 | bellard | |
522 | 2df3b95d | bellard | static inline void stfq_be_p(void *ptr, float64 v) |
523 | 0ac4bd56 | bellard | { |
524 | 0ac4bd56 | bellard | CPU_DoubleU u; |
525 | 0ac4bd56 | bellard | u.d = v; |
526 | 2df3b95d | bellard | stl_be_p(ptr, u.l.upper); |
527 | 4d7a0880 | blueswir1 | stl_be_p((uint8_t *)ptr + 4, u.l.lower);
|
528 | 93ac68bc | bellard | } |
529 | 93ac68bc | bellard | |
530 | 5a9fdfec | bellard | #else
|
531 | 5a9fdfec | bellard | |
532 | 8bba3ea1 | balrog | static inline int lduw_be_p(const void *ptr) |
533 | 5a9fdfec | bellard | { |
534 | 5a9fdfec | bellard | return *(uint16_t *)ptr;
|
535 | 5a9fdfec | bellard | } |
536 | 5a9fdfec | bellard | |
537 | 8bba3ea1 | balrog | static inline int ldsw_be_p(const void *ptr) |
538 | 5a9fdfec | bellard | { |
539 | 5a9fdfec | bellard | return *(int16_t *)ptr;
|
540 | 5a9fdfec | bellard | } |
541 | 5a9fdfec | bellard | |
542 | 8bba3ea1 | balrog | static inline int ldl_be_p(const void *ptr) |
543 | 5a9fdfec | bellard | { |
544 | 5a9fdfec | bellard | return *(uint32_t *)ptr;
|
545 | 5a9fdfec | bellard | } |
546 | 5a9fdfec | bellard | |
547 | 8bba3ea1 | balrog | static inline uint64_t ldq_be_p(const void *ptr) |
548 | 5a9fdfec | bellard | { |
549 | 5a9fdfec | bellard | return *(uint64_t *)ptr;
|
550 | 5a9fdfec | bellard | } |
551 | 5a9fdfec | bellard | |
552 | 2df3b95d | bellard | static inline void stw_be_p(void *ptr, int v) |
553 | 5a9fdfec | bellard | { |
554 | 5a9fdfec | bellard | *(uint16_t *)ptr = v; |
555 | 5a9fdfec | bellard | } |
556 | 5a9fdfec | bellard | |
557 | 2df3b95d | bellard | static inline void stl_be_p(void *ptr, int v) |
558 | 5a9fdfec | bellard | { |
559 | 5a9fdfec | bellard | *(uint32_t *)ptr = v; |
560 | 5a9fdfec | bellard | } |
561 | 5a9fdfec | bellard | |
562 | 2df3b95d | bellard | static inline void stq_be_p(void *ptr, uint64_t v) |
563 | 5a9fdfec | bellard | { |
564 | 5a9fdfec | bellard | *(uint64_t *)ptr = v; |
565 | 5a9fdfec | bellard | } |
566 | 5a9fdfec | bellard | |
567 | 5a9fdfec | bellard | /* float access */
|
568 | 5a9fdfec | bellard | |
569 | 8bba3ea1 | balrog | static inline float32 ldfl_be_p(const void *ptr) |
570 | 5a9fdfec | bellard | { |
571 | 53cd6637 | bellard | return *(float32 *)ptr;
|
572 | 5a9fdfec | bellard | } |
573 | 5a9fdfec | bellard | |
574 | 8bba3ea1 | balrog | static inline float64 ldfq_be_p(const void *ptr) |
575 | 5a9fdfec | bellard | { |
576 | 53cd6637 | bellard | return *(float64 *)ptr;
|
577 | 5a9fdfec | bellard | } |
578 | 5a9fdfec | bellard | |
579 | 2df3b95d | bellard | static inline void stfl_be_p(void *ptr, float32 v) |
580 | 5a9fdfec | bellard | { |
581 | 53cd6637 | bellard | *(float32 *)ptr = v; |
582 | 5a9fdfec | bellard | } |
583 | 5a9fdfec | bellard | |
584 | 2df3b95d | bellard | static inline void stfq_be_p(void *ptr, float64 v) |
585 | 5a9fdfec | bellard | { |
586 | 53cd6637 | bellard | *(float64 *)ptr = v; |
587 | 5a9fdfec | bellard | } |
588 | 2df3b95d | bellard | |
589 | 2df3b95d | bellard | #endif
|
590 | 2df3b95d | bellard | |
591 | 2df3b95d | bellard | /* target CPU memory access functions */
|
592 | 2df3b95d | bellard | #if defined(TARGET_WORDS_BIGENDIAN)
|
593 | 2df3b95d | bellard | #define lduw_p(p) lduw_be_p(p)
|
594 | 2df3b95d | bellard | #define ldsw_p(p) ldsw_be_p(p)
|
595 | 2df3b95d | bellard | #define ldl_p(p) ldl_be_p(p)
|
596 | 2df3b95d | bellard | #define ldq_p(p) ldq_be_p(p)
|
597 | 2df3b95d | bellard | #define ldfl_p(p) ldfl_be_p(p)
|
598 | 2df3b95d | bellard | #define ldfq_p(p) ldfq_be_p(p)
|
599 | 2df3b95d | bellard | #define stw_p(p, v) stw_be_p(p, v)
|
600 | 2df3b95d | bellard | #define stl_p(p, v) stl_be_p(p, v)
|
601 | 2df3b95d | bellard | #define stq_p(p, v) stq_be_p(p, v)
|
602 | 2df3b95d | bellard | #define stfl_p(p, v) stfl_be_p(p, v)
|
603 | 2df3b95d | bellard | #define stfq_p(p, v) stfq_be_p(p, v)
|
604 | 2df3b95d | bellard | #else
|
605 | 2df3b95d | bellard | #define lduw_p(p) lduw_le_p(p)
|
606 | 2df3b95d | bellard | #define ldsw_p(p) ldsw_le_p(p)
|
607 | 2df3b95d | bellard | #define ldl_p(p) ldl_le_p(p)
|
608 | 2df3b95d | bellard | #define ldq_p(p) ldq_le_p(p)
|
609 | 2df3b95d | bellard | #define ldfl_p(p) ldfl_le_p(p)
|
610 | 2df3b95d | bellard | #define ldfq_p(p) ldfq_le_p(p)
|
611 | 2df3b95d | bellard | #define stw_p(p, v) stw_le_p(p, v)
|
612 | 2df3b95d | bellard | #define stl_p(p, v) stl_le_p(p, v)
|
613 | 2df3b95d | bellard | #define stq_p(p, v) stq_le_p(p, v)
|
614 | 2df3b95d | bellard | #define stfl_p(p, v) stfl_le_p(p, v)
|
615 | 2df3b95d | bellard | #define stfq_p(p, v) stfq_le_p(p, v)
|
616 | 5a9fdfec | bellard | #endif
|
617 | 5a9fdfec | bellard | |
618 | 61382a50 | bellard | /* MMU memory access macros */
|
619 | 61382a50 | bellard | |
620 | 53a5960a | pbrook | #if defined(CONFIG_USER_ONLY)
|
621 | 0e62fd79 | aurel32 | #include <assert.h> |
622 | 0e62fd79 | aurel32 | #include "qemu-types.h" |
623 | 0e62fd79 | aurel32 | |
624 | 53a5960a | pbrook | /* On some host systems the guest address space is reserved on the host.
|
625 | 53a5960a | pbrook | * This allows the guest address space to be offset to a convenient location.
|
626 | 53a5960a | pbrook | */
|
627 | 379f6698 | Paul Brook | #if defined(CONFIG_USE_GUEST_BASE)
|
628 | 379f6698 | Paul Brook | extern unsigned long guest_base; |
629 | 379f6698 | Paul Brook | extern int have_guest_base; |
630 | 379f6698 | Paul Brook | #define GUEST_BASE guest_base
|
631 | 379f6698 | Paul Brook | #else
|
632 | 379f6698 | Paul Brook | #define GUEST_BASE 0ul |
633 | 379f6698 | Paul Brook | #endif
|
634 | 53a5960a | pbrook | |
635 | 53a5960a | pbrook | /* All direct uses of g2h and h2g need to go away for usermode softmmu. */
|
636 | 53a5960a | pbrook | #define g2h(x) ((void *)((unsigned long)(x) + GUEST_BASE)) |
637 | 0e62fd79 | aurel32 | #define h2g(x) ({ \
|
638 | 0e62fd79 | aurel32 | unsigned long __ret = (unsigned long)(x) - GUEST_BASE; \ |
639 | 0e62fd79 | aurel32 | /* Check if given address fits target address space */ \
|
640 | 0e62fd79 | aurel32 | assert(__ret == (abi_ulong)__ret); \ |
641 | 0e62fd79 | aurel32 | (abi_ulong)__ret; \ |
642 | 0e62fd79 | aurel32 | }) |
643 | 14cc46b1 | aurel32 | #define h2g_valid(x) ({ \
|
644 | 14cc46b1 | aurel32 | unsigned long __guest = (unsigned long)(x) - GUEST_BASE; \ |
645 | 14cc46b1 | aurel32 | (__guest == (abi_ulong)__guest); \ |
646 | 14cc46b1 | aurel32 | }) |
647 | 53a5960a | pbrook | |
648 | 53a5960a | pbrook | #define saddr(x) g2h(x)
|
649 | 53a5960a | pbrook | #define laddr(x) g2h(x)
|
650 | 53a5960a | pbrook | |
651 | 53a5960a | pbrook | #else /* !CONFIG_USER_ONLY */ |
652 | c27004ec | bellard | /* NOTE: we use double casts if pointers and target_ulong have
|
653 | c27004ec | bellard | different sizes */
|
654 | 53a5960a | pbrook | #define saddr(x) (uint8_t *)(long)(x) |
655 | 53a5960a | pbrook | #define laddr(x) (uint8_t *)(long)(x) |
656 | 53a5960a | pbrook | #endif
|
657 | 53a5960a | pbrook | |
658 | 53a5960a | pbrook | #define ldub_raw(p) ldub_p(laddr((p)))
|
659 | 53a5960a | pbrook | #define ldsb_raw(p) ldsb_p(laddr((p)))
|
660 | 53a5960a | pbrook | #define lduw_raw(p) lduw_p(laddr((p)))
|
661 | 53a5960a | pbrook | #define ldsw_raw(p) ldsw_p(laddr((p)))
|
662 | 53a5960a | pbrook | #define ldl_raw(p) ldl_p(laddr((p)))
|
663 | 53a5960a | pbrook | #define ldq_raw(p) ldq_p(laddr((p)))
|
664 | 53a5960a | pbrook | #define ldfl_raw(p) ldfl_p(laddr((p)))
|
665 | 53a5960a | pbrook | #define ldfq_raw(p) ldfq_p(laddr((p)))
|
666 | 53a5960a | pbrook | #define stb_raw(p, v) stb_p(saddr((p)), v)
|
667 | 53a5960a | pbrook | #define stw_raw(p, v) stw_p(saddr((p)), v)
|
668 | 53a5960a | pbrook | #define stl_raw(p, v) stl_p(saddr((p)), v)
|
669 | 53a5960a | pbrook | #define stq_raw(p, v) stq_p(saddr((p)), v)
|
670 | 53a5960a | pbrook | #define stfl_raw(p, v) stfl_p(saddr((p)), v)
|
671 | 53a5960a | pbrook | #define stfq_raw(p, v) stfq_p(saddr((p)), v)
|
672 | c27004ec | bellard | |
673 | c27004ec | bellard | |
674 | 5fafdf24 | ths | #if defined(CONFIG_USER_ONLY)
|
675 | 61382a50 | bellard | |
676 | 61382a50 | bellard | /* if user mode, no other memory access functions */
|
677 | 61382a50 | bellard | #define ldub(p) ldub_raw(p)
|
678 | 61382a50 | bellard | #define ldsb(p) ldsb_raw(p)
|
679 | 61382a50 | bellard | #define lduw(p) lduw_raw(p)
|
680 | 61382a50 | bellard | #define ldsw(p) ldsw_raw(p)
|
681 | 61382a50 | bellard | #define ldl(p) ldl_raw(p)
|
682 | 61382a50 | bellard | #define ldq(p) ldq_raw(p)
|
683 | 61382a50 | bellard | #define ldfl(p) ldfl_raw(p)
|
684 | 61382a50 | bellard | #define ldfq(p) ldfq_raw(p)
|
685 | 61382a50 | bellard | #define stb(p, v) stb_raw(p, v)
|
686 | 61382a50 | bellard | #define stw(p, v) stw_raw(p, v)
|
687 | 61382a50 | bellard | #define stl(p, v) stl_raw(p, v)
|
688 | 61382a50 | bellard | #define stq(p, v) stq_raw(p, v)
|
689 | 61382a50 | bellard | #define stfl(p, v) stfl_raw(p, v)
|
690 | 61382a50 | bellard | #define stfq(p, v) stfq_raw(p, v)
|
691 | 61382a50 | bellard | |
692 | 61382a50 | bellard | #define ldub_code(p) ldub_raw(p)
|
693 | 61382a50 | bellard | #define ldsb_code(p) ldsb_raw(p)
|
694 | 61382a50 | bellard | #define lduw_code(p) lduw_raw(p)
|
695 | 61382a50 | bellard | #define ldsw_code(p) ldsw_raw(p)
|
696 | 61382a50 | bellard | #define ldl_code(p) ldl_raw(p)
|
697 | bc98a7ef | j_mayer | #define ldq_code(p) ldq_raw(p)
|
698 | 61382a50 | bellard | |
699 | 61382a50 | bellard | #define ldub_kernel(p) ldub_raw(p)
|
700 | 61382a50 | bellard | #define ldsb_kernel(p) ldsb_raw(p)
|
701 | 61382a50 | bellard | #define lduw_kernel(p) lduw_raw(p)
|
702 | 61382a50 | bellard | #define ldsw_kernel(p) ldsw_raw(p)
|
703 | 61382a50 | bellard | #define ldl_kernel(p) ldl_raw(p)
|
704 | bc98a7ef | j_mayer | #define ldq_kernel(p) ldq_raw(p)
|
705 | 0ac4bd56 | bellard | #define ldfl_kernel(p) ldfl_raw(p)
|
706 | 0ac4bd56 | bellard | #define ldfq_kernel(p) ldfq_raw(p)
|
707 | 61382a50 | bellard | #define stb_kernel(p, v) stb_raw(p, v)
|
708 | 61382a50 | bellard | #define stw_kernel(p, v) stw_raw(p, v)
|
709 | 61382a50 | bellard | #define stl_kernel(p, v) stl_raw(p, v)
|
710 | 61382a50 | bellard | #define stq_kernel(p, v) stq_raw(p, v)
|
711 | 0ac4bd56 | bellard | #define stfl_kernel(p, v) stfl_raw(p, v)
|
712 | 0ac4bd56 | bellard | #define stfq_kernel(p, vt) stfq_raw(p, v)
|
713 | 61382a50 | bellard | |
714 | 61382a50 | bellard | #endif /* defined(CONFIG_USER_ONLY) */ |
715 | 61382a50 | bellard | |
716 | 5a9fdfec | bellard | /* page related stuff */
|
717 | 5a9fdfec | bellard | |
718 | 03875444 | aurel32 | #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) |
719 | 5a9fdfec | bellard | #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1) |
720 | 5a9fdfec | bellard | #define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK) |
721 | 5a9fdfec | bellard | |
722 | 53a5960a | pbrook | /* ??? These should be the larger of unsigned long and target_ulong. */
|
723 | 83fb7adf | bellard | extern unsigned long qemu_real_host_page_size; |
724 | 83fb7adf | bellard | extern unsigned long qemu_host_page_bits; |
725 | 83fb7adf | bellard | extern unsigned long qemu_host_page_size; |
726 | 83fb7adf | bellard | extern unsigned long qemu_host_page_mask; |
727 | 5a9fdfec | bellard | |
728 | 83fb7adf | bellard | #define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask) |
729 | 5a9fdfec | bellard | |
730 | 5a9fdfec | bellard | /* same as PROT_xxx */
|
731 | 5a9fdfec | bellard | #define PAGE_READ 0x0001 |
732 | 5a9fdfec | bellard | #define PAGE_WRITE 0x0002 |
733 | 5a9fdfec | bellard | #define PAGE_EXEC 0x0004 |
734 | 5a9fdfec | bellard | #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
|
735 | 5a9fdfec | bellard | #define PAGE_VALID 0x0008 |
736 | 5a9fdfec | bellard | /* original state of the write flag (used when tracking self-modifying
|
737 | 5a9fdfec | bellard | code */
|
738 | 5fafdf24 | ths | #define PAGE_WRITE_ORG 0x0010 |
739 | 50a9569b | balrog | #define PAGE_RESERVED 0x0020 |
740 | 5a9fdfec | bellard | |
741 | 5a9fdfec | bellard | void page_dump(FILE *f);
|
742 | edf8e2af | Mika Westerberg | int walk_memory_regions(void *, |
743 | edf8e2af | Mika Westerberg | int (*fn)(void *, unsigned long, unsigned long, unsigned long)); |
744 | 53a5960a | pbrook | int page_get_flags(target_ulong address);
|
745 | 53a5960a | pbrook | void page_set_flags(target_ulong start, target_ulong end, int flags); |
746 | 3d97b40b | ths | int page_check_range(target_ulong start, target_ulong len, int flags); |
747 | 5a9fdfec | bellard | |
748 | 26a5f13b | bellard | void cpu_exec_init_all(unsigned long tb_size); |
749 | c5be9f08 | ths | CPUState *cpu_copy(CPUState *env); |
750 | 950f1472 | Glauber Costa | CPUState *qemu_get_cpu(int cpu);
|
751 | c5be9f08 | ths | |
752 | 5fafdf24 | ths | void cpu_dump_state(CPUState *env, FILE *f,
|
753 | 7fe48483 | bellard | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
754 | 7fe48483 | bellard | int flags);
|
755 | 76a66253 | j_mayer | void cpu_dump_statistics (CPUState *env, FILE *f,
|
756 | 76a66253 | j_mayer | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
757 | 76a66253 | j_mayer | int flags);
|
758 | 7fe48483 | bellard | |
759 | a5e50b26 | malc | void QEMU_NORETURN cpu_abort(CPUState *env, const char *fmt, ...) |
760 | 7d99a001 | blueswir1 | __attribute__ ((__format__ (__printf__, 2, 3))); |
761 | f0aca822 | bellard | extern CPUState *first_cpu;
|
762 | e2f22898 | bellard | extern CPUState *cpu_single_env;
|
763 | 2e70f6ef | pbrook | extern int64_t qemu_icount;
|
764 | 2e70f6ef | pbrook | extern int use_icount; |
765 | 5a9fdfec | bellard | |
766 | 9acbed06 | bellard | #define CPU_INTERRUPT_HARD 0x02 /* hardware interrupt pending */ |
767 | 9acbed06 | bellard | #define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */ |
768 | ef792f9d | bellard | #define CPU_INTERRUPT_TIMER 0x08 /* internal timer exception pending */ |
769 | 98699967 | bellard | #define CPU_INTERRUPT_FIQ 0x10 /* Fast interrupt pending. */ |
770 | ba3c64fb | bellard | #define CPU_INTERRUPT_HALT 0x20 /* CPU halt wanted */ |
771 | 3b21e03e | bellard | #define CPU_INTERRUPT_SMI 0x40 /* (x86 only) SMI interrupt pending */ |
772 | 6658ffb8 | pbrook | #define CPU_INTERRUPT_DEBUG 0x80 /* Debug event occured. */ |
773 | 0573fbfc | ths | #define CPU_INTERRUPT_VIRQ 0x100 /* virtual interrupt pending. */ |
774 | 474ea849 | aurel32 | #define CPU_INTERRUPT_NMI 0x200 /* NMI pending. */ |
775 | b09ea7d5 | Gleb Natapov | #define CPU_INTERRUPT_INIT 0x400 /* INIT pending. */ |
776 | b09ea7d5 | Gleb Natapov | #define CPU_INTERRUPT_SIPI 0x800 /* SIPI pending. */ |
777 | 79c4f6b0 | Huang Ying | #define CPU_INTERRUPT_MCE 0x1000 /* (x86 only) MCE pending. */ |
778 | 98699967 | bellard | |
779 | 4690764b | bellard | void cpu_interrupt(CPUState *s, int mask); |
780 | b54ad049 | bellard | void cpu_reset_interrupt(CPUState *env, int mask); |
781 | 68a79315 | bellard | |
782 | 3098dba0 | aurel32 | void cpu_exit(CPUState *s);
|
783 | 3098dba0 | aurel32 | |
784 | 6a4955a8 | aliguori | int qemu_cpu_has_work(CPUState *env);
|
785 | 6a4955a8 | aliguori | |
786 | a1d1bb31 | aliguori | /* Breakpoint/watchpoint flags */
|
787 | a1d1bb31 | aliguori | #define BP_MEM_READ 0x01 |
788 | a1d1bb31 | aliguori | #define BP_MEM_WRITE 0x02 |
789 | a1d1bb31 | aliguori | #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE)
|
790 | 06d55cc1 | aliguori | #define BP_STOP_BEFORE_ACCESS 0x04 |
791 | 6e140f28 | aliguori | #define BP_WATCHPOINT_HIT 0x08 |
792 | a1d1bb31 | aliguori | #define BP_GDB 0x10 |
793 | 2dc9f411 | aliguori | #define BP_CPU 0x20 |
794 | a1d1bb31 | aliguori | |
795 | a1d1bb31 | aliguori | int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags, |
796 | a1d1bb31 | aliguori | CPUBreakpoint **breakpoint); |
797 | a1d1bb31 | aliguori | int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags); |
798 | a1d1bb31 | aliguori | void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint);
|
799 | a1d1bb31 | aliguori | void cpu_breakpoint_remove_all(CPUState *env, int mask); |
800 | a1d1bb31 | aliguori | int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len,
|
801 | a1d1bb31 | aliguori | int flags, CPUWatchpoint **watchpoint);
|
802 | a1d1bb31 | aliguori | int cpu_watchpoint_remove(CPUState *env, target_ulong addr,
|
803 | a1d1bb31 | aliguori | target_ulong len, int flags);
|
804 | a1d1bb31 | aliguori | void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint);
|
805 | a1d1bb31 | aliguori | void cpu_watchpoint_remove_all(CPUState *env, int mask); |
806 | 60897d36 | edgar_igl | |
807 | 60897d36 | edgar_igl | #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */ |
808 | 60897d36 | edgar_igl | #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */ |
809 | 60897d36 | edgar_igl | #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ |
810 | 60897d36 | edgar_igl | |
811 | c33a346e | bellard | void cpu_single_step(CPUState *env, int enabled); |
812 | d95dc32d | bellard | void cpu_reset(CPUState *s);
|
813 | 4c3a88a2 | bellard | |
814 | 13eb76e0 | bellard | /* Return the physical page corresponding to a virtual one. Use it
|
815 | 13eb76e0 | bellard | only for debugging because no protection checks are done. Return -1
|
816 | 13eb76e0 | bellard | if no page found. */
|
817 | 9b3c35e0 | j_mayer | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr); |
818 | 13eb76e0 | bellard | |
819 | 5fafdf24 | ths | #define CPU_LOG_TB_OUT_ASM (1 << 0) |
820 | 9fddaa0c | bellard | #define CPU_LOG_TB_IN_ASM (1 << 1) |
821 | f193c797 | bellard | #define CPU_LOG_TB_OP (1 << 2) |
822 | f193c797 | bellard | #define CPU_LOG_TB_OP_OPT (1 << 3) |
823 | f193c797 | bellard | #define CPU_LOG_INT (1 << 4) |
824 | f193c797 | bellard | #define CPU_LOG_EXEC (1 << 5) |
825 | f193c797 | bellard | #define CPU_LOG_PCALL (1 << 6) |
826 | fd872598 | bellard | #define CPU_LOG_IOPORT (1 << 7) |
827 | 9fddaa0c | bellard | #define CPU_LOG_TB_CPU (1 << 8) |
828 | eca1bdf4 | aliguori | #define CPU_LOG_RESET (1 << 9) |
829 | f193c797 | bellard | |
830 | f193c797 | bellard | /* define log items */
|
831 | f193c797 | bellard | typedef struct CPULogItem { |
832 | f193c797 | bellard | int mask;
|
833 | f193c797 | bellard | const char *name; |
834 | f193c797 | bellard | const char *help; |
835 | f193c797 | bellard | } CPULogItem; |
836 | f193c797 | bellard | |
837 | c7cd6a37 | blueswir1 | extern const CPULogItem cpu_log_items[]; |
838 | f193c797 | bellard | |
839 | 34865134 | bellard | void cpu_set_log(int log_flags); |
840 | 34865134 | bellard | void cpu_set_log_filename(const char *filename); |
841 | f193c797 | bellard | int cpu_str_to_log_mask(const char *str); |
842 | 34865134 | bellard | |
843 | 09683d35 | bellard | /* IO ports API */
|
844 | 32993977 | Isaku Yamahata | #include "ioport.h" |
845 | 09683d35 | bellard | |
846 | 33417e70 | bellard | /* memory API */
|
847 | 33417e70 | bellard | |
848 | edf75d59 | bellard | extern int phys_ram_fd; |
849 | 1ccde1cb | bellard | extern uint8_t *phys_ram_dirty;
|
850 | 00f82b8a | aurel32 | extern ram_addr_t ram_size;
|
851 | 94a6b54f | pbrook | extern ram_addr_t last_ram_offset;
|
852 | edf75d59 | bellard | |
853 | edf75d59 | bellard | /* physical memory access */
|
854 | 0f459d16 | pbrook | |
855 | 0f459d16 | pbrook | /* MMIO pages are identified by a combination of an IO device index and
|
856 | 0f459d16 | pbrook | 3 flags. The ROMD code stores the page ram offset in iotlb entry,
|
857 | 0f459d16 | pbrook | so only a limited number of ids are avaiable. */
|
858 | 0f459d16 | pbrook | |
859 | 98699967 | bellard | #define IO_MEM_NB_ENTRIES (1 << (TARGET_PAGE_BITS - IO_MEM_SHIFT)) |
860 | edf75d59 | bellard | |
861 | 0f459d16 | pbrook | /* Flags stored in the low bits of the TLB virtual address. These are
|
862 | 0f459d16 | pbrook | defined so that fast path ram access is all zeros. */
|
863 | 0f459d16 | pbrook | /* Zero if TLB entry is valid. */
|
864 | 0f459d16 | pbrook | #define TLB_INVALID_MASK (1 << 3) |
865 | 0f459d16 | pbrook | /* Set if TLB entry references a clean RAM page. The iotlb entry will
|
866 | 0f459d16 | pbrook | contain the page physical address. */
|
867 | 0f459d16 | pbrook | #define TLB_NOTDIRTY (1 << 4) |
868 | 0f459d16 | pbrook | /* Set if TLB entry is an IO callback. */
|
869 | 0f459d16 | pbrook | #define TLB_MMIO (1 << 5) |
870 | 0f459d16 | pbrook | |
871 | 5fafdf24 | ths | int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
|
872 | 8b1f24b0 | bellard | uint8_t *buf, int len, int is_write); |
873 | 13eb76e0 | bellard | |
874 | 74576198 | aliguori | #define VGA_DIRTY_FLAG 0x01 |
875 | 74576198 | aliguori | #define CODE_DIRTY_FLAG 0x02 |
876 | 74576198 | aliguori | #define MIGRATION_DIRTY_FLAG 0x08 |
877 | 0a962c02 | bellard | |
878 | 1ccde1cb | bellard | /* read dirty bit (return 0 or 1) */
|
879 | 04c504cc | bellard | static inline int cpu_physical_memory_is_dirty(ram_addr_t addr) |
880 | 1ccde1cb | bellard | { |
881 | 0a962c02 | bellard | return phys_ram_dirty[addr >> TARGET_PAGE_BITS] == 0xff; |
882 | 0a962c02 | bellard | } |
883 | 0a962c02 | bellard | |
884 | 5fafdf24 | ths | static inline int cpu_physical_memory_get_dirty(ram_addr_t addr, |
885 | 0a962c02 | bellard | int dirty_flags)
|
886 | 0a962c02 | bellard | { |
887 | 0a962c02 | bellard | return phys_ram_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags;
|
888 | 1ccde1cb | bellard | } |
889 | 1ccde1cb | bellard | |
890 | 04c504cc | bellard | static inline void cpu_physical_memory_set_dirty(ram_addr_t addr) |
891 | 1ccde1cb | bellard | { |
892 | 0a962c02 | bellard | phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 0xff;
|
893 | 1ccde1cb | bellard | } |
894 | 1ccde1cb | bellard | |
895 | 04c504cc | bellard | void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
|
896 | 0a962c02 | bellard | int dirty_flags);
|
897 | 04c504cc | bellard | void cpu_tlb_update_dirty(CPUState *env);
|
898 | 1ccde1cb | bellard | |
899 | 74576198 | aliguori | int cpu_physical_memory_set_dirty_tracking(int enable); |
900 | 74576198 | aliguori | |
901 | 74576198 | aliguori | int cpu_physical_memory_get_dirty_tracking(void); |
902 | 74576198 | aliguori | |
903 | 151f7749 | Jan Kiszka | int cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr,
|
904 | 151f7749 | Jan Kiszka | target_phys_addr_t end_addr); |
905 | 2bec46dc | aliguori | |
906 | e3db7226 | bellard | void dump_exec_info(FILE *f,
|
907 | e3db7226 | bellard | int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
908 | e3db7226 | bellard | |
909 | f65ed4c1 | aliguori | /* Coalesced MMIO regions are areas where write operations can be reordered.
|
910 | f65ed4c1 | aliguori | * This usually implies that write operations are side-effect free. This allows
|
911 | f65ed4c1 | aliguori | * batching which can make a major impact on performance when using
|
912 | f65ed4c1 | aliguori | * virtualization.
|
913 | f65ed4c1 | aliguori | */
|
914 | f65ed4c1 | aliguori | void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
|
915 | f65ed4c1 | aliguori | |
916 | f65ed4c1 | aliguori | void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
|
917 | f65ed4c1 | aliguori | |
918 | effedbc9 | bellard | /*******************************************/
|
919 | effedbc9 | bellard | /* host CPU ticks (if available) */
|
920 | effedbc9 | bellard | |
921 | e58ffeb3 | malc | #if defined(_ARCH_PPC)
|
922 | effedbc9 | bellard | |
923 | effedbc9 | bellard | static inline int64_t cpu_get_real_ticks(void) |
924 | effedbc9 | bellard | { |
925 | 5e10fc90 | malc | int64_t retval; |
926 | 5e10fc90 | malc | #ifdef _ARCH_PPC64
|
927 | 5e10fc90 | malc | /* This reads timebase in one 64bit go and includes Cell workaround from:
|
928 | 5e10fc90 | malc | http://ozlabs.org/pipermail/linuxppc-dev/2006-October/027052.html
|
929 | 5e10fc90 | malc | */
|
930 | 5e10fc90 | malc | __asm__ __volatile__ ( |
931 | 5e10fc90 | malc | "mftb %0\n\t"
|
932 | 5e10fc90 | malc | "cmpwi %0,0\n\t"
|
933 | 5e10fc90 | malc | "beq- $-8"
|
934 | 5e10fc90 | malc | : "=r" (retval));
|
935 | 5e10fc90 | malc | #else
|
936 | 5e10fc90 | malc | /* http://ozlabs.org/pipermail/linuxppc-dev/1999-October/003889.html */
|
937 | 5e10fc90 | malc | unsigned long junk; |
938 | 5e10fc90 | malc | __asm__ __volatile__ ( |
939 | 5e10fc90 | malc | "mftbu %1\n\t"
|
940 | 5e10fc90 | malc | "mftb %L0\n\t"
|
941 | 5e10fc90 | malc | "mftbu %0\n\t"
|
942 | 5e10fc90 | malc | "cmpw %0,%1\n\t"
|
943 | 5e10fc90 | malc | "bne $-16"
|
944 | 5e10fc90 | malc | : "=r" (retval), "=r" (junk)); |
945 | 5e10fc90 | malc | #endif
|
946 | 5e10fc90 | malc | return retval;
|
947 | effedbc9 | bellard | } |
948 | effedbc9 | bellard | |
949 | effedbc9 | bellard | #elif defined(__i386__)
|
950 | effedbc9 | bellard | |
951 | effedbc9 | bellard | static inline int64_t cpu_get_real_ticks(void) |
952 | 5f1ce948 | bellard | { |
953 | 5f1ce948 | bellard | int64_t val; |
954 | 5f1ce948 | bellard | asm volatile ("rdtsc" : "=A" (val)); |
955 | 5f1ce948 | bellard | return val;
|
956 | 5f1ce948 | bellard | } |
957 | 5f1ce948 | bellard | |
958 | effedbc9 | bellard | #elif defined(__x86_64__)
|
959 | effedbc9 | bellard | |
960 | effedbc9 | bellard | static inline int64_t cpu_get_real_ticks(void) |
961 | effedbc9 | bellard | { |
962 | effedbc9 | bellard | uint32_t low,high; |
963 | effedbc9 | bellard | int64_t val; |
964 | effedbc9 | bellard | asm volatile("rdtsc" : "=a" (low), "=d" (high)); |
965 | effedbc9 | bellard | val = high; |
966 | effedbc9 | bellard | val <<= 32;
|
967 | effedbc9 | bellard | val |= low; |
968 | effedbc9 | bellard | return val;
|
969 | effedbc9 | bellard | } |
970 | effedbc9 | bellard | |
971 | f54b3f92 | aurel32 | #elif defined(__hppa__)
|
972 | f54b3f92 | aurel32 | |
973 | f54b3f92 | aurel32 | static inline int64_t cpu_get_real_ticks(void) |
974 | f54b3f92 | aurel32 | { |
975 | f54b3f92 | aurel32 | int val;
|
976 | f54b3f92 | aurel32 | asm volatile ("mfctl %%cr16, %0" : "=r"(val)); |
977 | f54b3f92 | aurel32 | return val;
|
978 | f54b3f92 | aurel32 | } |
979 | f54b3f92 | aurel32 | |
980 | effedbc9 | bellard | #elif defined(__ia64)
|
981 | effedbc9 | bellard | |
982 | effedbc9 | bellard | static inline int64_t cpu_get_real_ticks(void) |
983 | effedbc9 | bellard | { |
984 | effedbc9 | bellard | int64_t val; |
985 | effedbc9 | bellard | asm volatile ("mov %0 = ar.itc" : "=r"(val) :: "memory"); |
986 | effedbc9 | bellard | return val;
|
987 | effedbc9 | bellard | } |
988 | effedbc9 | bellard | |
989 | effedbc9 | bellard | #elif defined(__s390__)
|
990 | effedbc9 | bellard | |
991 | effedbc9 | bellard | static inline int64_t cpu_get_real_ticks(void) |
992 | effedbc9 | bellard | { |
993 | effedbc9 | bellard | int64_t val; |
994 | effedbc9 | bellard | asm volatile("stck 0(%1)" : "=m" (val) : "a" (&val) : "cc"); |
995 | effedbc9 | bellard | return val;
|
996 | effedbc9 | bellard | } |
997 | effedbc9 | bellard | |
998 | 3142255c | blueswir1 | #elif defined(__sparc_v8plus__) || defined(__sparc_v8plusa__) || defined(__sparc_v9__)
|
999 | effedbc9 | bellard | |
1000 | effedbc9 | bellard | static inline int64_t cpu_get_real_ticks (void) |
1001 | effedbc9 | bellard | { |
1002 | effedbc9 | bellard | #if defined(_LP64)
|
1003 | effedbc9 | bellard | uint64_t rval; |
1004 | effedbc9 | bellard | asm volatile("rd %%tick,%0" : "=r"(rval)); |
1005 | effedbc9 | bellard | return rval;
|
1006 | effedbc9 | bellard | #else
|
1007 | effedbc9 | bellard | union {
|
1008 | effedbc9 | bellard | uint64_t i64; |
1009 | effedbc9 | bellard | struct {
|
1010 | effedbc9 | bellard | uint32_t high; |
1011 | effedbc9 | bellard | uint32_t low; |
1012 | effedbc9 | bellard | } i32; |
1013 | effedbc9 | bellard | } rval; |
1014 | effedbc9 | bellard | asm volatile("rd %%tick,%1; srlx %1,32,%0" |
1015 | effedbc9 | bellard | : "=r"(rval.i32.high), "=r"(rval.i32.low)); |
1016 | effedbc9 | bellard | return rval.i64;
|
1017 | effedbc9 | bellard | #endif
|
1018 | effedbc9 | bellard | } |
1019 | c4b89d18 | ths | |
1020 | c4b89d18 | ths | #elif defined(__mips__)
|
1021 | c4b89d18 | ths | |
1022 | c4b89d18 | ths | static inline int64_t cpu_get_real_ticks(void) |
1023 | c4b89d18 | ths | { |
1024 | aeec26d3 | Stefan Weil | #if defined(__mips_isa_rev) && __mips_isa_rev >= 2 |
1025 | c4b89d18 | ths | uint32_t count; |
1026 | c4b89d18 | ths | static uint32_t cyc_per_count = 0; |
1027 | c4b89d18 | ths | |
1028 | c4b89d18 | ths | if (!cyc_per_count)
|
1029 | c4b89d18 | ths | __asm__ __volatile__("rdhwr %0, $3" : "=r" (cyc_per_count)); |
1030 | c4b89d18 | ths | |
1031 | c4b89d18 | ths | __asm__ __volatile__("rdhwr %1, $2" : "=r" (count)); |
1032 | c4b89d18 | ths | return (int64_t)(count * cyc_per_count);
|
1033 | c4b89d18 | ths | #else
|
1034 | c4b89d18 | ths | /* FIXME */
|
1035 | c4b89d18 | ths | static int64_t ticks = 0; |
1036 | c4b89d18 | ths | return ticks++;
|
1037 | c4b89d18 | ths | #endif
|
1038 | c4b89d18 | ths | } |
1039 | c4b89d18 | ths | |
1040 | 46152182 | pbrook | #else
|
1041 | 46152182 | pbrook | /* The host CPU doesn't have an easily accessible cycle counter.
|
1042 | 85028e4d | ths | Just return a monotonically increasing value. This will be
|
1043 | 85028e4d | ths | totally wrong, but hopefully better than nothing. */
|
1044 | 46152182 | pbrook | static inline int64_t cpu_get_real_ticks (void) |
1045 | 46152182 | pbrook | { |
1046 | 46152182 | pbrook | static int64_t ticks = 0; |
1047 | 46152182 | pbrook | return ticks++;
|
1048 | 46152182 | pbrook | } |
1049 | effedbc9 | bellard | #endif
|
1050 | effedbc9 | bellard | |
1051 | effedbc9 | bellard | /* profiling */
|
1052 | effedbc9 | bellard | #ifdef CONFIG_PROFILER
|
1053 | effedbc9 | bellard | static inline int64_t profile_getclock(void) |
1054 | effedbc9 | bellard | { |
1055 | effedbc9 | bellard | return cpu_get_real_ticks();
|
1056 | effedbc9 | bellard | } |
1057 | effedbc9 | bellard | |
1058 | 5f1ce948 | bellard | extern int64_t qemu_time, qemu_time_start;
|
1059 | 5f1ce948 | bellard | extern int64_t tlb_flush_time;
|
1060 | 5f1ce948 | bellard | extern int64_t dev_time;
|
1061 | 5f1ce948 | bellard | #endif
|
1062 | 5f1ce948 | bellard | |
1063 | 79c4f6b0 | Huang Ying | void cpu_inject_x86_mce(CPUState *cenv, int bank, uint64_t status, |
1064 | 79c4f6b0 | Huang Ying | uint64_t mcg_status, uint64_t addr, uint64_t misc); |
1065 | 79c4f6b0 | Huang Ying | |
1066 | 5a9fdfec | bellard | #endif /* CPU_ALL_H */ |