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1 | 94cff60a | ths | /*
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2 | 94cff60a | ths | * CRIS mmu emulation.
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3 | 94cff60a | ths | *
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4 | 94cff60a | ths | * Copyright (c) 2007 AXIS Communications AB
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5 | 94cff60a | ths | * Written by Edgar E. Iglesias.
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6 | 94cff60a | ths | *
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7 | 94cff60a | ths | * This library is free software; you can redistribute it and/or
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8 | 94cff60a | ths | * modify it under the terms of the GNU Lesser General Public
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9 | 94cff60a | ths | * License as published by the Free Software Foundation; either
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10 | 94cff60a | ths | * version 2 of the License, or (at your option) any later version.
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11 | 94cff60a | ths | *
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12 | 94cff60a | ths | * This library is distributed in the hope that it will be useful,
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13 | 94cff60a | ths | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 94cff60a | ths | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 94cff60a | ths | * Lesser General Public License for more details.
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16 | 94cff60a | ths | *
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17 | 94cff60a | ths | * You should have received a copy of the GNU Lesser General Public
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18 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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19 | 94cff60a | ths | */
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20 | 94cff60a | ths | |
21 | 94cff60a | ths | #ifndef CONFIG_USER_ONLY
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22 | 94cff60a | ths | |
23 | 94cff60a | ths | #include <stdio.h> |
24 | 94cff60a | ths | #include <string.h> |
25 | 94cff60a | ths | #include <stdlib.h> |
26 | 94cff60a | ths | |
27 | 94cff60a | ths | #include "config.h" |
28 | 94cff60a | ths | #include "cpu.h" |
29 | 94cff60a | ths | #include "mmu.h" |
30 | 94cff60a | ths | #include "exec-all.h" |
31 | 94cff60a | ths | |
32 | d297f464 | edgar_igl | #ifdef DEBUG
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33 | d297f464 | edgar_igl | #define D(x) x
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34 | 93fcfe39 | aliguori | #define D_LOG(...) qemu_log(__VA__ARGS__)
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35 | d297f464 | edgar_igl | #else
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36 | 786c02f1 | edgar_igl | #define D(x)
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37 | d12d51d5 | aliguori | #define D_LOG(...) do { } while (0) |
38 | d297f464 | edgar_igl | #endif
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39 | 94cff60a | ths | |
40 | 44cd42ee | edgar_igl | void cris_mmu_init(CPUState *env)
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41 | 44cd42ee | edgar_igl | { |
42 | 44cd42ee | edgar_igl | env->mmu_rand_lfsr = 0xcccc;
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43 | 44cd42ee | edgar_igl | } |
44 | 44cd42ee | edgar_igl | |
45 | 44cd42ee | edgar_igl | #define SR_POLYNOM 0x8805 |
46 | 44cd42ee | edgar_igl | static inline unsigned int compute_polynom(unsigned int sr) |
47 | 44cd42ee | edgar_igl | { |
48 | 44cd42ee | edgar_igl | unsigned int i; |
49 | 44cd42ee | edgar_igl | unsigned int f; |
50 | 44cd42ee | edgar_igl | |
51 | 44cd42ee | edgar_igl | f = 0;
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52 | 44cd42ee | edgar_igl | for (i = 0; i < 16; i++) |
53 | 44cd42ee | edgar_igl | f += ((SR_POLYNOM >> i) & 1) & ((sr >> i) & 1); |
54 | 44cd42ee | edgar_igl | |
55 | 44cd42ee | edgar_igl | return f;
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56 | 44cd42ee | edgar_igl | } |
57 | 44cd42ee | edgar_igl | |
58 | ef29a70d | edgar_igl | static inline int cris_mmu_enabled(uint32_t rw_gc_cfg) |
59 | 94cff60a | ths | { |
60 | 94cff60a | ths | return (rw_gc_cfg & 12) != 0; |
61 | 94cff60a | ths | } |
62 | 94cff60a | ths | |
63 | ef29a70d | edgar_igl | static inline int cris_mmu_segmented_addr(int seg, uint32_t rw_mm_cfg) |
64 | 94cff60a | ths | { |
65 | 94cff60a | ths | return (1 << seg) & rw_mm_cfg; |
66 | 94cff60a | ths | } |
67 | 94cff60a | ths | |
68 | 94cff60a | ths | static uint32_t cris_mmu_translate_seg(CPUState *env, int seg) |
69 | 94cff60a | ths | { |
70 | 94cff60a | ths | uint32_t base; |
71 | 94cff60a | ths | int i;
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72 | 94cff60a | ths | |
73 | 94cff60a | ths | if (seg < 8) |
74 | 94cff60a | ths | base = env->sregs[SFR_RW_MM_KBASE_LO]; |
75 | 94cff60a | ths | else
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76 | 94cff60a | ths | base = env->sregs[SFR_RW_MM_KBASE_HI]; |
77 | 94cff60a | ths | |
78 | 94cff60a | ths | i = seg & 7;
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79 | 94cff60a | ths | base >>= i * 4;
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80 | 94cff60a | ths | base &= 15;
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81 | 94cff60a | ths | |
82 | 94cff60a | ths | base <<= 28;
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83 | 94cff60a | ths | return base;
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84 | 94cff60a | ths | } |
85 | 94cff60a | ths | /* Used by the tlb decoder. */
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86 | 94cff60a | ths | #define EXTRACT_FIELD(src, start, end) \
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87 | 786c02f1 | edgar_igl | (((src) >> start) & ((1 << (end - start + 1)) - 1)) |
88 | 786c02f1 | edgar_igl | |
89 | 786c02f1 | edgar_igl | static inline void set_field(uint32_t *dst, unsigned int val, |
90 | 786c02f1 | edgar_igl | unsigned int offset, unsigned int width) |
91 | 786c02f1 | edgar_igl | { |
92 | 786c02f1 | edgar_igl | uint32_t mask; |
93 | 786c02f1 | edgar_igl | |
94 | 786c02f1 | edgar_igl | mask = (1 << width) - 1; |
95 | 786c02f1 | edgar_igl | mask <<= offset; |
96 | 786c02f1 | edgar_igl | val <<= offset; |
97 | 786c02f1 | edgar_igl | |
98 | 786c02f1 | edgar_igl | val &= mask; |
99 | 786c02f1 | edgar_igl | *dst &= ~(mask); |
100 | 786c02f1 | edgar_igl | *dst |= val; |
101 | 786c02f1 | edgar_igl | } |
102 | 94cff60a | ths | |
103 | d297f464 | edgar_igl | #ifdef DEBUG
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104 | b41f7df0 | edgar_igl | static void dump_tlb(CPUState *env, int mmu) |
105 | b41f7df0 | edgar_igl | { |
106 | b41f7df0 | edgar_igl | int set;
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107 | b41f7df0 | edgar_igl | int idx;
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108 | b41f7df0 | edgar_igl | uint32_t hi, lo, tlb_vpn, tlb_pfn; |
109 | b41f7df0 | edgar_igl | |
110 | b41f7df0 | edgar_igl | for (set = 0; set < 4; set++) { |
111 | b41f7df0 | edgar_igl | for (idx = 0; idx < 16; idx++) { |
112 | b41f7df0 | edgar_igl | lo = env->tlbsets[mmu][set][idx].lo; |
113 | b41f7df0 | edgar_igl | hi = env->tlbsets[mmu][set][idx].hi; |
114 | b41f7df0 | edgar_igl | tlb_vpn = EXTRACT_FIELD(hi, 13, 31); |
115 | b41f7df0 | edgar_igl | tlb_pfn = EXTRACT_FIELD(lo, 13, 31); |
116 | b41f7df0 | edgar_igl | |
117 | b41f7df0 | edgar_igl | printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
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118 | b41f7df0 | edgar_igl | set, idx, hi, lo, tlb_vpn, tlb_pfn); |
119 | b41f7df0 | edgar_igl | } |
120 | b41f7df0 | edgar_igl | } |
121 | b41f7df0 | edgar_igl | } |
122 | d297f464 | edgar_igl | #endif
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123 | b41f7df0 | edgar_igl | |
124 | b41f7df0 | edgar_igl | /* rw 0 = read, 1 = write, 2 = exec. */
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125 | 2fa73ec8 | Edgar E. Iglesias | static int cris_mmu_translate_page(struct cris_mmu_result *res, |
126 | 94cff60a | ths | CPUState *env, uint32_t vaddr, |
127 | 94cff60a | ths | int rw, int usermode) |
128 | 94cff60a | ths | { |
129 | 94cff60a | ths | unsigned int vpage; |
130 | 94cff60a | ths | unsigned int idx; |
131 | b23761f9 | edgar_igl | uint32_t pid, lo, hi; |
132 | 786c02f1 | edgar_igl | uint32_t tlb_vpn, tlb_pfn = 0;
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133 | 786c02f1 | edgar_igl | int tlb_pid, tlb_g, tlb_v, tlb_k, tlb_w, tlb_x;
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134 | 786c02f1 | edgar_igl | int cfg_v, cfg_k, cfg_w, cfg_x;
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135 | b41f7df0 | edgar_igl | int set, match = 0; |
136 | 786c02f1 | edgar_igl | uint32_t r_cause; |
137 | 786c02f1 | edgar_igl | uint32_t r_cfg; |
138 | 786c02f1 | edgar_igl | int rwcause;
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139 | b41f7df0 | edgar_igl | int mmu = 1; /* Data mmu is default. */ |
140 | b41f7df0 | edgar_igl | int vect_base;
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141 | 786c02f1 | edgar_igl | |
142 | 786c02f1 | edgar_igl | r_cause = env->sregs[SFR_R_MM_CAUSE]; |
143 | 786c02f1 | edgar_igl | r_cfg = env->sregs[SFR_RW_MM_CFG]; |
144 | 28de16da | edgar_igl | pid = env->pregs[PR_PID] & 0xff;
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145 | b41f7df0 | edgar_igl | |
146 | b41f7df0 | edgar_igl | switch (rw) {
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147 | b41f7df0 | edgar_igl | case 2: rwcause = CRIS_MMU_ERR_EXEC; mmu = 0; break; |
148 | b41f7df0 | edgar_igl | case 1: rwcause = CRIS_MMU_ERR_WRITE; break; |
149 | b41f7df0 | edgar_igl | default:
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150 | b41f7df0 | edgar_igl | case 0: rwcause = CRIS_MMU_ERR_READ; break; |
151 | b41f7df0 | edgar_igl | } |
152 | b41f7df0 | edgar_igl | |
153 | b41f7df0 | edgar_igl | /* I exception vectors 4 - 7, D 8 - 11. */
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154 | b41f7df0 | edgar_igl | vect_base = (mmu + 1) * 4; |
155 | 94cff60a | ths | |
156 | 94cff60a | ths | vpage = vaddr >> 13;
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157 | 94cff60a | ths | |
158 | 94cff60a | ths | /* We know the index which to check on each set.
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159 | 94cff60a | ths | Scan both I and D. */
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160 | 786c02f1 | edgar_igl | #if 0
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161 | b41f7df0 | edgar_igl | for (set = 0; set < 4; set++) {
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162 | b41f7df0 | edgar_igl | for (idx = 0; idx < 16; idx++) {
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163 | b41f7df0 | edgar_igl | lo = env->tlbsets[mmu][set][idx].lo;
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164 | b41f7df0 | edgar_igl | hi = env->tlbsets[mmu][set][idx].hi;
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165 | 786c02f1 | edgar_igl | tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
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166 | 786c02f1 | edgar_igl | tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
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167 | 786c02f1 | edgar_igl | |
168 | 786c02f1 | edgar_igl | printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
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169 | b41f7df0 | edgar_igl | set, idx, hi, lo, tlb_vpn, tlb_pfn);
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170 | 786c02f1 | edgar_igl | }
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171 | 786c02f1 | edgar_igl | }
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172 | 786c02f1 | edgar_igl | #endif
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173 | b41f7df0 | edgar_igl | |
174 | b41f7df0 | edgar_igl | idx = vpage & 15;
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175 | b41f7df0 | edgar_igl | for (set = 0; set < 4; set++) |
176 | 94cff60a | ths | { |
177 | b41f7df0 | edgar_igl | lo = env->tlbsets[mmu][set][idx].lo; |
178 | b41f7df0 | edgar_igl | hi = env->tlbsets[mmu][set][idx].hi; |
179 | 94cff60a | ths | |
180 | b23761f9 | edgar_igl | tlb_vpn = hi >> 13;
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181 | 44cd42ee | edgar_igl | tlb_pid = EXTRACT_FIELD(hi, 0, 7); |
182 | 44cd42ee | edgar_igl | tlb_g = EXTRACT_FIELD(lo, 4, 4); |
183 | 94cff60a | ths | |
184 | d12d51d5 | aliguori | D_LOG("TLB[%d][%d][%d] v=%x vpage=%x lo=%x hi=%x\n",
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185 | d12d51d5 | aliguori | mmu, set, idx, tlb_vpn, vpage, lo, hi); |
186 | b23761f9 | edgar_igl | if ((tlb_g || (tlb_pid == pid))
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187 | 44cd42ee | edgar_igl | && tlb_vpn == vpage) { |
188 | 94cff60a | ths | match = 1;
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189 | 94cff60a | ths | break;
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190 | 94cff60a | ths | } |
191 | 94cff60a | ths | } |
192 | 94cff60a | ths | |
193 | b41f7df0 | edgar_igl | res->bf_vec = vect_base; |
194 | 94cff60a | ths | if (match) {
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195 | 786c02f1 | edgar_igl | cfg_w = EXTRACT_FIELD(r_cfg, 19, 19); |
196 | 786c02f1 | edgar_igl | cfg_k = EXTRACT_FIELD(r_cfg, 18, 18); |
197 | 786c02f1 | edgar_igl | cfg_x = EXTRACT_FIELD(r_cfg, 17, 17); |
198 | 786c02f1 | edgar_igl | cfg_v = EXTRACT_FIELD(r_cfg, 16, 16); |
199 | 786c02f1 | edgar_igl | |
200 | 786c02f1 | edgar_igl | tlb_pfn = EXTRACT_FIELD(lo, 13, 31); |
201 | 786c02f1 | edgar_igl | tlb_v = EXTRACT_FIELD(lo, 3, 3); |
202 | 786c02f1 | edgar_igl | tlb_k = EXTRACT_FIELD(lo, 2, 2); |
203 | 786c02f1 | edgar_igl | tlb_w = EXTRACT_FIELD(lo, 1, 1); |
204 | 786c02f1 | edgar_igl | tlb_x = EXTRACT_FIELD(lo, 0, 0); |
205 | 786c02f1 | edgar_igl | |
206 | 786c02f1 | edgar_igl | /*
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207 | 786c02f1 | edgar_igl | set_exception_vector(0x04, i_mmu_refill);
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208 | 786c02f1 | edgar_igl | set_exception_vector(0x05, i_mmu_invalid);
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209 | 786c02f1 | edgar_igl | set_exception_vector(0x06, i_mmu_access);
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210 | 786c02f1 | edgar_igl | set_exception_vector(0x07, i_mmu_execute);
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211 | 786c02f1 | edgar_igl | set_exception_vector(0x08, d_mmu_refill);
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212 | 786c02f1 | edgar_igl | set_exception_vector(0x09, d_mmu_invalid);
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213 | 786c02f1 | edgar_igl | set_exception_vector(0x0a, d_mmu_access);
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214 | 786c02f1 | edgar_igl | set_exception_vector(0x0b, d_mmu_write);
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215 | 786c02f1 | edgar_igl | */
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216 | 44cd42ee | edgar_igl | if (cfg_k && tlb_k && usermode) {
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217 | ef29a70d | edgar_igl | D(printf ("tlb: kernel protected %x lo=%x pc=%x\n",
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218 | ef29a70d | edgar_igl | vaddr, lo, env->pc)); |
219 | ef29a70d | edgar_igl | match = 0;
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220 | ef29a70d | edgar_igl | res->bf_vec = vect_base + 2;
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221 | b41f7df0 | edgar_igl | } else if (rw == 1 && cfg_w && !tlb_w) { |
222 | ef29a70d | edgar_igl | D(printf ("tlb: write protected %x lo=%x pc=%x\n",
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223 | ef29a70d | edgar_igl | vaddr, lo, env->pc)); |
224 | ef29a70d | edgar_igl | match = 0;
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225 | ef29a70d | edgar_igl | /* write accesses never go through the I mmu. */
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226 | ef29a70d | edgar_igl | res->bf_vec = vect_base + 3;
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227 | ef29a70d | edgar_igl | } else if (rw == 2 && cfg_x && !tlb_x) { |
228 | ef29a70d | edgar_igl | D(printf ("tlb: exec protected %x lo=%x pc=%x\n",
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229 | ef29a70d | edgar_igl | vaddr, lo, env->pc)); |
230 | 786c02f1 | edgar_igl | match = 0;
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231 | b41f7df0 | edgar_igl | res->bf_vec = vect_base + 3;
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232 | b41f7df0 | edgar_igl | } else if (cfg_v && !tlb_v) { |
233 | b41f7df0 | edgar_igl | D(printf ("tlb: invalid %x\n", vaddr));
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234 | 786c02f1 | edgar_igl | match = 0;
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235 | b41f7df0 | edgar_igl | res->bf_vec = vect_base + 1;
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236 | 786c02f1 | edgar_igl | } |
237 | 786c02f1 | edgar_igl | |
238 | b41f7df0 | edgar_igl | res->prot = 0;
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239 | b41f7df0 | edgar_igl | if (match) {
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240 | b41f7df0 | edgar_igl | res->prot |= PAGE_READ; |
241 | b41f7df0 | edgar_igl | if (tlb_w)
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242 | b41f7df0 | edgar_igl | res->prot |= PAGE_WRITE; |
243 | b41f7df0 | edgar_igl | if (tlb_x)
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244 | b41f7df0 | edgar_igl | res->prot |= PAGE_EXEC; |
245 | b41f7df0 | edgar_igl | } |
246 | b41f7df0 | edgar_igl | else
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247 | b41f7df0 | edgar_igl | D(dump_tlb(env, mmu)); |
248 | 44cd42ee | edgar_igl | } else {
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249 | 44cd42ee | edgar_igl | /* If refill, provide a randomized set. */
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250 | 44cd42ee | edgar_igl | set = env->mmu_rand_lfsr & 3;
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251 | 786c02f1 | edgar_igl | } |
252 | 786c02f1 | edgar_igl | |
253 | 786c02f1 | edgar_igl | if (!match) {
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254 | 44cd42ee | edgar_igl | unsigned int f; |
255 | 44cd42ee | edgar_igl | |
256 | 44cd42ee | edgar_igl | /* Update lfsr at every fault. */
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257 | 44cd42ee | edgar_igl | f = compute_polynom(env->mmu_rand_lfsr); |
258 | 44cd42ee | edgar_igl | env->mmu_rand_lfsr >>= 1;
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259 | 44cd42ee | edgar_igl | env->mmu_rand_lfsr |= (f << 15);
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260 | 44cd42ee | edgar_igl | env->mmu_rand_lfsr &= 0xffff;
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261 | 44cd42ee | edgar_igl | |
262 | 44cd42ee | edgar_igl | /* Compute index. */
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263 | b41f7df0 | edgar_igl | idx = vpage & 15;
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264 | b41f7df0 | edgar_igl | |
265 | b41f7df0 | edgar_igl | /* Update RW_MM_TLB_SEL. */
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266 | b41f7df0 | edgar_igl | env->sregs[SFR_RW_MM_TLB_SEL] = 0;
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267 | b41f7df0 | edgar_igl | set_field(&env->sregs[SFR_RW_MM_TLB_SEL], idx, 0, 4); |
268 | 44cd42ee | edgar_igl | set_field(&env->sregs[SFR_RW_MM_TLB_SEL], set, 4, 2); |
269 | b41f7df0 | edgar_igl | |
270 | b41f7df0 | edgar_igl | /* Update RW_MM_CAUSE. */
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271 | b41f7df0 | edgar_igl | set_field(&r_cause, rwcause, 8, 2); |
272 | 786c02f1 | edgar_igl | set_field(&r_cause, vpage, 13, 19); |
273 | 28de16da | edgar_igl | set_field(&r_cause, pid, 0, 8); |
274 | 786c02f1 | edgar_igl | env->sregs[SFR_R_MM_CAUSE] = r_cause; |
275 | b41f7df0 | edgar_igl | D(printf("refill vaddr=%x pc=%x\n", vaddr, env->pc));
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276 | 94cff60a | ths | } |
277 | b41f7df0 | edgar_igl | |
278 | b41f7df0 | edgar_igl | D(printf ("%s rw=%d mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x"
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279 | b41f7df0 | edgar_igl | " %x cause=%x sel=%x sp=%x %x %x\n",
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280 | b41f7df0 | edgar_igl | __func__, rw, match, env->pc, |
281 | 786c02f1 | edgar_igl | vaddr, vpage, |
282 | 786c02f1 | edgar_igl | tlb_vpn, tlb_pfn, tlb_pid, |
283 | 28de16da | edgar_igl | pid, |
284 | 786c02f1 | edgar_igl | r_cause, |
285 | 786c02f1 | edgar_igl | env->sregs[SFR_RW_MM_TLB_SEL], |
286 | b41f7df0 | edgar_igl | env->regs[R_SP], env->pregs[PR_USP], env->ksp)); |
287 | 786c02f1 | edgar_igl | |
288 | bf91ada5 | edgar_igl | res->phy = tlb_pfn << TARGET_PAGE_BITS; |
289 | 94cff60a | ths | return !match;
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290 | 94cff60a | ths | } |
291 | 94cff60a | ths | |
292 | cf1d97f0 | edgar_igl | void cris_mmu_flush_pid(CPUState *env, uint32_t pid)
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293 | 786c02f1 | edgar_igl | { |
294 | cf1d97f0 | edgar_igl | target_ulong vaddr; |
295 | cf1d97f0 | edgar_igl | unsigned int idx; |
296 | cf1d97f0 | edgar_igl | uint32_t lo, hi; |
297 | cf1d97f0 | edgar_igl | uint32_t tlb_vpn; |
298 | 80e1b265 | edgar_igl | int tlb_pid, tlb_g, tlb_v;
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299 | cf1d97f0 | edgar_igl | unsigned int set; |
300 | cf1d97f0 | edgar_igl | unsigned int mmu; |
301 | cf1d97f0 | edgar_igl | |
302 | cf1d97f0 | edgar_igl | pid &= 0xff;
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303 | cf1d97f0 | edgar_igl | for (mmu = 0; mmu < 2; mmu++) { |
304 | cf1d97f0 | edgar_igl | for (set = 0; set < 4; set++) |
305 | cf1d97f0 | edgar_igl | { |
306 | cf1d97f0 | edgar_igl | for (idx = 0; idx < 16; idx++) { |
307 | cf1d97f0 | edgar_igl | lo = env->tlbsets[mmu][set][idx].lo; |
308 | cf1d97f0 | edgar_igl | hi = env->tlbsets[mmu][set][idx].hi; |
309 | cf1d97f0 | edgar_igl | |
310 | cf1d97f0 | edgar_igl | tlb_vpn = EXTRACT_FIELD(hi, 13, 31); |
311 | cf1d97f0 | edgar_igl | tlb_pid = EXTRACT_FIELD(hi, 0, 7); |
312 | cf1d97f0 | edgar_igl | tlb_g = EXTRACT_FIELD(lo, 4, 4); |
313 | cf1d97f0 | edgar_igl | tlb_v = EXTRACT_FIELD(lo, 3, 3); |
314 | cf1d97f0 | edgar_igl | |
315 | 80e1b265 | edgar_igl | if (tlb_v && !tlb_g && (tlb_pid == pid)) {
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316 | cf1d97f0 | edgar_igl | vaddr = tlb_vpn << TARGET_PAGE_BITS; |
317 | d12d51d5 | aliguori | D_LOG("flush pid=%x vaddr=%x\n",
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318 | d12d51d5 | aliguori | pid, vaddr); |
319 | cf1d97f0 | edgar_igl | tlb_flush_page(env, vaddr); |
320 | cf1d97f0 | edgar_igl | } |
321 | cf1d97f0 | edgar_igl | } |
322 | cf1d97f0 | edgar_igl | } |
323 | cf1d97f0 | edgar_igl | } |
324 | 786c02f1 | edgar_igl | } |
325 | 786c02f1 | edgar_igl | |
326 | 2fa73ec8 | Edgar E. Iglesias | int cris_mmu_translate(struct cris_mmu_result *res, |
327 | 94cff60a | ths | CPUState *env, uint32_t vaddr, |
328 | 6ebbf390 | j_mayer | int rw, int mmu_idx) |
329 | 94cff60a | ths | { |
330 | 94cff60a | ths | uint32_t phy = vaddr; |
331 | 94cff60a | ths | int seg;
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332 | 94cff60a | ths | int miss = 0; |
333 | 786c02f1 | edgar_igl | int is_user = mmu_idx == MMU_USER_IDX;
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334 | b41f7df0 | edgar_igl | uint32_t old_srs; |
335 | b41f7df0 | edgar_igl | |
336 | b41f7df0 | edgar_igl | old_srs= env->pregs[PR_SRS]; |
337 | b41f7df0 | edgar_igl | |
338 | b41f7df0 | edgar_igl | /* rw == 2 means exec, map the access to the insn mmu. */
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339 | b41f7df0 | edgar_igl | env->pregs[PR_SRS] = rw == 2 ? 1 : 2; |
340 | 94cff60a | ths | |
341 | 94cff60a | ths | if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) {
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342 | 94cff60a | ths | res->phy = vaddr; |
343 | b23761f9 | edgar_igl | res->prot = PAGE_BITS; |
344 | b41f7df0 | edgar_igl | goto done;
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345 | 94cff60a | ths | } |
346 | 94cff60a | ths | |
347 | 94cff60a | ths | seg = vaddr >> 28;
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348 | 94cff60a | ths | if (cris_mmu_segmented_addr(seg, env->sregs[SFR_RW_MM_CFG]))
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349 | 94cff60a | ths | { |
350 | 94cff60a | ths | uint32_t base; |
351 | 94cff60a | ths | |
352 | 94cff60a | ths | miss = 0;
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353 | 94cff60a | ths | base = cris_mmu_translate_seg(env, seg); |
354 | 94cff60a | ths | phy = base | (0x0fffffff & vaddr);
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355 | 94cff60a | ths | res->phy = phy; |
356 | b23761f9 | edgar_igl | res->prot = PAGE_BITS; |
357 | 94cff60a | ths | } |
358 | 94cff60a | ths | else
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359 | 94cff60a | ths | miss = cris_mmu_translate_page(res, env, vaddr, rw, is_user); |
360 | b41f7df0 | edgar_igl | done:
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361 | b41f7df0 | edgar_igl | env->pregs[PR_SRS] = old_srs; |
362 | 94cff60a | ths | return miss;
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363 | 94cff60a | ths | } |
364 | 94cff60a | ths | #endif |