root / hw / cs4231.c @ 69bf405b
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1 | b8174937 | bellard | /*
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2 | b8174937 | bellard | * QEMU Crystal CS4231 audio chip emulation
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3 | b8174937 | bellard | *
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4 | b8174937 | bellard | * Copyright (c) 2006 Fabrice Bellard
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5 | b8174937 | bellard | *
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6 | b8174937 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | b8174937 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | b8174937 | bellard | * in the Software without restriction, including without limitation the rights
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9 | b8174937 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | b8174937 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | b8174937 | bellard | * furnished to do so, subject to the following conditions:
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12 | b8174937 | bellard | *
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13 | b8174937 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | b8174937 | bellard | * all copies or substantial portions of the Software.
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15 | b8174937 | bellard | *
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16 | b8174937 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | b8174937 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | b8174937 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | b8174937 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | b8174937 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | b8174937 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | b8174937 | bellard | * THE SOFTWARE.
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23 | b8174937 | bellard | */
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24 | fa28ec52 | Blue Swirl | |
25 | fa28ec52 | Blue Swirl | #include "sysbus.h" |
26 | 97bf4851 | Blue Swirl | #include "trace.h" |
27 | b8174937 | bellard | |
28 | b8174937 | bellard | /*
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29 | b8174937 | bellard | * In addition to Crystal CS4231 there is a DMA controller on Sparc.
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30 | b8174937 | bellard | */
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31 | e64d7d59 | blueswir1 | #define CS_SIZE 0x40 |
32 | b8174937 | bellard | #define CS_REGS 16 |
33 | b8174937 | bellard | #define CS_DREGS 32 |
34 | b8174937 | bellard | #define CS_MAXDREG (CS_DREGS - 1) |
35 | b8174937 | bellard | |
36 | b8174937 | bellard | typedef struct CSState { |
37 | fa28ec52 | Blue Swirl | SysBusDevice busdev; |
38 | fa28ec52 | Blue Swirl | qemu_irq irq; |
39 | b8174937 | bellard | uint32_t regs[CS_REGS]; |
40 | b8174937 | bellard | uint8_t dregs[CS_DREGS]; |
41 | b8174937 | bellard | } CSState; |
42 | b8174937 | bellard | |
43 | b8174937 | bellard | #define CS_RAP(s) ((s)->regs[0] & CS_MAXDREG) |
44 | b8174937 | bellard | #define CS_VER 0xa0 |
45 | b8174937 | bellard | #define CS_CDC_VER 0x8a |
46 | b8174937 | bellard | |
47 | 82d4c6e6 | Blue Swirl | static void cs_reset(DeviceState *d) |
48 | b8174937 | bellard | { |
49 | 82d4c6e6 | Blue Swirl | CSState *s = container_of(d, CSState, busdev.qdev); |
50 | b8174937 | bellard | |
51 | b8174937 | bellard | memset(s->regs, 0, CS_REGS * 4); |
52 | b8174937 | bellard | memset(s->dregs, 0, CS_DREGS);
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53 | b8174937 | bellard | s->dregs[12] = CS_CDC_VER;
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54 | b8174937 | bellard | s->dregs[25] = CS_VER;
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55 | b8174937 | bellard | } |
56 | b8174937 | bellard | |
57 | c227f099 | Anthony Liguori | static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr) |
58 | b8174937 | bellard | { |
59 | b8174937 | bellard | CSState *s = opaque; |
60 | b8174937 | bellard | uint32_t saddr, ret; |
61 | b8174937 | bellard | |
62 | e64d7d59 | blueswir1 | saddr = addr >> 2;
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63 | b8174937 | bellard | switch (saddr) {
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64 | b8174937 | bellard | case 1: |
65 | b8174937 | bellard | switch (CS_RAP(s)) {
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66 | b8174937 | bellard | case 3: // Write only |
67 | b8174937 | bellard | ret = 0;
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68 | b8174937 | bellard | break;
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69 | b8174937 | bellard | default:
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70 | b8174937 | bellard | ret = s->dregs[CS_RAP(s)]; |
71 | b8174937 | bellard | break;
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72 | b8174937 | bellard | } |
73 | 97bf4851 | Blue Swirl | trace_cs4231_mem_readl_dreg(CS_RAP(s), ret); |
74 | f930d07e | blueswir1 | break;
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75 | b8174937 | bellard | default:
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76 | b8174937 | bellard | ret = s->regs[saddr]; |
77 | 97bf4851 | Blue Swirl | trace_cs4231_mem_readl_reg(saddr, ret); |
78 | f930d07e | blueswir1 | break;
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79 | b8174937 | bellard | } |
80 | b8174937 | bellard | return ret;
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81 | b8174937 | bellard | } |
82 | b8174937 | bellard | |
83 | c227f099 | Anthony Liguori | static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
84 | b8174937 | bellard | { |
85 | b8174937 | bellard | CSState *s = opaque; |
86 | b8174937 | bellard | uint32_t saddr; |
87 | b8174937 | bellard | |
88 | e64d7d59 | blueswir1 | saddr = addr >> 2;
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89 | 97bf4851 | Blue Swirl | trace_cs4231_mem_writel_reg(saddr, s->regs[saddr], val); |
90 | b8174937 | bellard | switch (saddr) {
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91 | b8174937 | bellard | case 1: |
92 | 97bf4851 | Blue Swirl | trace_cs4231_mem_writel_dreg(CS_RAP(s), s->dregs[CS_RAP(s)], val); |
93 | b8174937 | bellard | switch(CS_RAP(s)) {
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94 | b8174937 | bellard | case 11: |
95 | b8174937 | bellard | case 25: // Read only |
96 | b8174937 | bellard | break;
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97 | b8174937 | bellard | case 12: |
98 | b8174937 | bellard | val &= 0x40;
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99 | b8174937 | bellard | val |= CS_CDC_VER; // Codec version
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100 | b8174937 | bellard | s->dregs[CS_RAP(s)] = val; |
101 | b8174937 | bellard | break;
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102 | b8174937 | bellard | default:
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103 | b8174937 | bellard | s->dregs[CS_RAP(s)] = val; |
104 | b8174937 | bellard | break;
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105 | b8174937 | bellard | } |
106 | b8174937 | bellard | break;
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107 | b8174937 | bellard | case 2: // Read only |
108 | b8174937 | bellard | break;
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109 | b8174937 | bellard | case 4: |
110 | 82d4c6e6 | Blue Swirl | if (val & 1) { |
111 | 82d4c6e6 | Blue Swirl | cs_reset(&s->busdev.qdev); |
112 | 82d4c6e6 | Blue Swirl | } |
113 | b8174937 | bellard | val &= 0x7f;
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114 | b8174937 | bellard | s->regs[saddr] = val; |
115 | b8174937 | bellard | break;
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116 | b8174937 | bellard | default:
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117 | b8174937 | bellard | s->regs[saddr] = val; |
118 | f930d07e | blueswir1 | break;
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119 | b8174937 | bellard | } |
120 | b8174937 | bellard | } |
121 | b8174937 | bellard | |
122 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const cs_mem_read[3] = { |
123 | b8174937 | bellard | cs_mem_readl, |
124 | b8174937 | bellard | cs_mem_readl, |
125 | b8174937 | bellard | cs_mem_readl, |
126 | b8174937 | bellard | }; |
127 | b8174937 | bellard | |
128 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const cs_mem_write[3] = { |
129 | b8174937 | bellard | cs_mem_writel, |
130 | b8174937 | bellard | cs_mem_writel, |
131 | b8174937 | bellard | cs_mem_writel, |
132 | b8174937 | bellard | }; |
133 | b8174937 | bellard | |
134 | 82d4c6e6 | Blue Swirl | static const VMStateDescription vmstate_cs4231 = { |
135 | 82d4c6e6 | Blue Swirl | .name ="cs4231",
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136 | 82d4c6e6 | Blue Swirl | .version_id = 1,
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137 | 82d4c6e6 | Blue Swirl | .minimum_version_id = 1,
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138 | 82d4c6e6 | Blue Swirl | .minimum_version_id_old = 1,
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139 | 82d4c6e6 | Blue Swirl | .fields = (VMStateField []) { |
140 | 82d4c6e6 | Blue Swirl | VMSTATE_UINT32_ARRAY(regs, CSState, CS_REGS), |
141 | 82d4c6e6 | Blue Swirl | VMSTATE_UINT8_ARRAY(dregs, CSState, CS_DREGS), |
142 | 82d4c6e6 | Blue Swirl | VMSTATE_END_OF_LIST() |
143 | 82d4c6e6 | Blue Swirl | } |
144 | 82d4c6e6 | Blue Swirl | }; |
145 | b8174937 | bellard | |
146 | 81a322d4 | Gerd Hoffmann | static int cs4231_init1(SysBusDevice *dev) |
147 | b8174937 | bellard | { |
148 | fa28ec52 | Blue Swirl | int io;
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149 | fa28ec52 | Blue Swirl | CSState *s = FROM_SYSBUS(CSState, dev); |
150 | b8174937 | bellard | |
151 | 2507c12a | Alexander Graf | io = cpu_register_io_memory(cs_mem_read, cs_mem_write, s, |
152 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
153 | fa28ec52 | Blue Swirl | sysbus_init_mmio(dev, CS_SIZE, io); |
154 | fa28ec52 | Blue Swirl | sysbus_init_irq(dev, &s->irq); |
155 | b8174937 | bellard | |
156 | 81a322d4 | Gerd Hoffmann | return 0; |
157 | b8174937 | bellard | } |
158 | fa28ec52 | Blue Swirl | |
159 | fa28ec52 | Blue Swirl | static SysBusDeviceInfo cs4231_info = {
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160 | fa28ec52 | Blue Swirl | .init = cs4231_init1, |
161 | fa28ec52 | Blue Swirl | .qdev.name = "SUNW,CS4231",
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162 | fa28ec52 | Blue Swirl | .qdev.size = sizeof(CSState),
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163 | 82d4c6e6 | Blue Swirl | .qdev.vmsd = &vmstate_cs4231, |
164 | 82d4c6e6 | Blue Swirl | .qdev.reset = cs_reset, |
165 | ee6847d1 | Gerd Hoffmann | .qdev.props = (Property[]) { |
166 | fa28ec52 | Blue Swirl | {.name = NULL}
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167 | fa28ec52 | Blue Swirl | } |
168 | fa28ec52 | Blue Swirl | }; |
169 | fa28ec52 | Blue Swirl | |
170 | fa28ec52 | Blue Swirl | static void cs4231_register_devices(void) |
171 | fa28ec52 | Blue Swirl | { |
172 | fa28ec52 | Blue Swirl | sysbus_register_withprop(&cs4231_info); |
173 | fa28ec52 | Blue Swirl | } |
174 | fa28ec52 | Blue Swirl | |
175 | fa28ec52 | Blue Swirl | device_init(cs4231_register_devices) |