Revision 6a80e088
| b/cpu-exec.c | ||
|---|---|---|
| 488 | 488 |
next_tb = 0; |
| 489 | 489 |
} |
| 490 | 490 |
#elif defined(TARGET_ALPHA) |
| 491 |
if (interrupt_request & CPU_INTERRUPT_HARD) {
|
|
| 492 |
do_interrupt(env); |
|
| 493 |
next_tb = 0; |
|
| 491 |
{
|
|
| 492 |
int idx = -1; |
|
| 493 |
/* ??? This hard-codes the OSF/1 interrupt levels. */ |
|
| 494 |
switch (env->pal_mode ? 7 : env->ps & PS_INT_MASK) {
|
|
| 495 |
case 0 ... 3: |
|
| 496 |
if (interrupt_request & CPU_INTERRUPT_HARD) {
|
|
| 497 |
idx = EXCP_DEV_INTERRUPT; |
|
| 498 |
} |
|
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/* FALLTHRU */ |
|
| 500 |
case 4: |
|
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if (interrupt_request & CPU_INTERRUPT_TIMER) {
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idx = EXCP_CLK_INTERRUPT; |
|
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} |
|
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/* FALLTHRU */ |
|
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case 5: |
|
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if (interrupt_request & CPU_INTERRUPT_SMP) {
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|
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idx = EXCP_SMP_INTERRUPT; |
|
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} |
|
| 509 |
/* FALLTHRU */ |
|
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case 6: |
|
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if (interrupt_request & CPU_INTERRUPT_MCHK) {
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idx = EXCP_MCHK; |
|
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} |
|
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} |
|
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if (idx >= 0) {
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env->exception_index = idx; |
|
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env->error_code = 0; |
|
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do_interrupt(env); |
|
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next_tb = 0; |
|
| 520 |
} |
|
| 494 | 521 |
} |
| 495 | 522 |
#elif defined(TARGET_CRIS) |
| 496 | 523 |
if (interrupt_request & CPU_INTERRUPT_HARD |
| b/target-alpha/cpu.h | ||
|---|---|---|
| 315 | 315 |
EXCP_STQ_C, |
| 316 | 316 |
}; |
| 317 | 317 |
|
| 318 |
/* Alpha-specific interrupt pending bits. */ |
|
| 319 |
#define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_EXT_0 |
|
| 320 |
#define CPU_INTERRUPT_SMP CPU_INTERRUPT_TGT_EXT_1 |
|
| 321 |
#define CPU_INTERRUPT_MCHK CPU_INTERRUPT_TGT_EXT_2 |
|
| 322 |
|
|
| 318 | 323 |
/* Hardware interrupt (entInt) constants. */ |
| 319 | 324 |
enum {
|
| 320 | 325 |
INT_K_IP, |
| b/target-alpha/exec.h | ||
|---|---|---|
| 39 | 39 |
|
| 40 | 40 |
static inline int cpu_has_work(CPUState *env) |
| 41 | 41 |
{
|
| 42 |
return (env->interrupt_request & CPU_INTERRUPT_HARD); |
|
| 42 |
/* Here we are checking to see if the CPU should wake up from HALT. |
|
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We will have gotten into this state only for WTINT from PALmode. */ |
|
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/* ??? I'm not sure how the IPL state works with WTINT to keep a CPU |
|
| 45 |
asleep even if (some) interrupts have been asserted. For now, |
|
| 46 |
assume that if a CPU really wants to stay asleep, it will mask |
|
| 47 |
interrupts at the chipset level, which will prevent these bits |
|
| 48 |
from being set in the first place. */ |
|
| 49 |
return env->interrupt_request & (CPU_INTERRUPT_HARD |
|
| 50 |
| CPU_INTERRUPT_TIMER |
|
| 51 |
| CPU_INTERRUPT_SMP |
|
| 52 |
| CPU_INTERRUPT_MCHK); |
|
| 43 | 53 |
} |
| 44 | 54 |
|
| 45 | 55 |
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) |
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