Revision 6ad02592
| b/target-alpha/cpu.h | ||
|---|---|---|
| 269 | 269 |
uint64_t ps; |
| 270 | 270 |
uint64_t unique; |
| 271 | 271 |
int saved_mode; /* Used for HW_LD / HW_ST */ |
| 272 |
int intr_flag; /* For RC and RS */ |
|
| 272 | 273 |
|
| 273 | 274 |
#if TARGET_LONG_BITS > HOST_LONG_BITS |
| 274 | 275 |
/* temporary fixed-point registers |
| b/target-alpha/helper.h | ||
|---|---|---|
| 4 | 4 |
|
| 5 | 5 |
DEF_HELPER(void, helper_tb_flush, (void)) |
| 6 | 6 |
|
| 7 |
DEF_HELPER(void, helper_excp, (int, int)) |
|
| 7 | 8 |
DEF_HELPER(uint64_t, helper_amask, (uint64_t)) |
| 9 |
DEF_HELPER(uint64_t, helper_load_pcc, (void)) |
|
| 10 |
DEF_HELPER(uint64_t, helper_load_implver, (void)) |
|
| 11 |
DEF_HELPER(uint64_t, helper_rc, (void)) |
|
| 12 |
DEF_HELPER(uint64_t, helper_rs, (void)) |
|
| 8 | 13 |
|
| 9 | 14 |
DEF_HELPER(uint64_t, helper_ctpop, (uint64_t)) |
| 10 | 15 |
DEF_HELPER(uint64_t, helper_ctlz, (uint64_t)) |
| b/target-alpha/op.c | ||
|---|---|---|
| 149 | 149 |
#endif |
| 150 | 150 |
|
| 151 | 151 |
/* Misc */ |
| 152 |
void OPPROTO op_excp (void) |
|
| 153 |
{
|
|
| 154 |
helper_excp(PARAM(1), PARAM(2)); |
|
| 155 |
RETURN(); |
|
| 156 |
} |
|
| 157 |
|
|
| 158 |
void OPPROTO op_load_pcc (void) |
|
| 159 |
{
|
|
| 160 |
helper_load_pcc(); |
|
| 161 |
RETURN(); |
|
| 162 |
} |
|
| 163 |
|
|
| 164 |
void OPPROTO op_load_implver (void) |
|
| 165 |
{
|
|
| 166 |
helper_load_implver(); |
|
| 167 |
RETURN(); |
|
| 168 |
} |
|
| 169 |
|
|
| 170 | 152 |
void OPPROTO op_load_fpcr (void) |
| 171 | 153 |
{
|
| 172 | 154 |
helper_load_fpcr(); |
| ... | ... | |
| 179 | 161 |
RETURN(); |
| 180 | 162 |
} |
| 181 | 163 |
|
| 182 |
void OPPROTO op_load_irf (void) |
|
| 183 |
{
|
|
| 184 |
helper_load_irf(); |
|
| 185 |
RETURN(); |
|
| 186 |
} |
|
| 187 |
|
|
| 188 |
void OPPROTO op_set_irf (void) |
|
| 189 |
{
|
|
| 190 |
helper_set_irf(); |
|
| 191 |
RETURN(); |
|
| 192 |
} |
|
| 193 |
|
|
| 194 |
void OPPROTO op_clear_irf (void) |
|
| 195 |
{
|
|
| 196 |
helper_clear_irf(); |
|
| 197 |
RETURN(); |
|
| 198 |
} |
|
| 199 |
|
|
| 200 | 164 |
/* Arithmetic */ |
| 201 | 165 |
void OPPROTO op_addqv (void) |
| 202 | 166 |
{
|
| b/target-alpha/op_helper.c | ||
|---|---|---|
| 58 | 58 |
|
| 59 | 59 |
/*****************************************************************************/ |
| 60 | 60 |
/* Exceptions processing helpers */ |
| 61 |
void helper_excp (uint32_t excp, uint32_t error)
|
|
| 61 |
void helper_excp (int excp, int error)
|
|
| 62 | 62 |
{
|
| 63 | 63 |
env->exception_index = excp; |
| 64 | 64 |
env->error_code = error; |
| ... | ... | |
| 80 | 80 |
return arg; |
| 81 | 81 |
} |
| 82 | 82 |
|
| 83 |
void helper_load_pcc (void)
|
|
| 83 |
uint64_t helper_load_pcc (void)
|
|
| 84 | 84 |
{
|
| 85 | 85 |
/* XXX: TODO */ |
| 86 |
T0 = 0;
|
|
| 86 |
return 0;
|
|
| 87 | 87 |
} |
| 88 | 88 |
|
| 89 |
void helper_load_implver (void)
|
|
| 89 |
uint64_t helper_load_implver (void)
|
|
| 90 | 90 |
{
|
| 91 |
T0 = env->implver;
|
|
| 91 |
return env->implver;
|
|
| 92 | 92 |
} |
| 93 | 93 |
|
| 94 | 94 |
void helper_load_fpcr (void) |
| ... | ... | |
| 137 | 137 |
} |
| 138 | 138 |
} |
| 139 | 139 |
|
| 140 |
void helper_load_irf (void) |
|
| 141 |
{
|
|
| 142 |
/* XXX: TODO */ |
|
| 143 |
T0 = 0; |
|
| 144 |
} |
|
| 140 |
spinlock_t intr_cpu_lock = SPIN_LOCK_UNLOCKED; |
|
| 145 | 141 |
|
| 146 |
void helper_set_irf (void)
|
|
| 142 |
uint64_t helper_rs(void)
|
|
| 147 | 143 |
{
|
| 148 |
/* XXX: TODO */ |
|
| 144 |
uint64_t tmp; |
|
| 145 |
|
|
| 146 |
spin_lock(&intr_cpu_lock); |
|
| 147 |
tmp = env->intr_flag; |
|
| 148 |
env->intr_flag = 1; |
|
| 149 |
spin_unlock(&intr_cpu_lock); |
|
| 150 |
|
|
| 151 |
return tmp; |
|
| 149 | 152 |
} |
| 150 | 153 |
|
| 151 |
void helper_clear_irf (void)
|
|
| 154 |
uint64_t helper_rc(void)
|
|
| 152 | 155 |
{
|
| 153 |
/* XXX: TODO */ |
|
| 156 |
uint64_t tmp; |
|
| 157 |
|
|
| 158 |
spin_lock(&intr_cpu_lock); |
|
| 159 |
tmp = env->intr_flag; |
|
| 160 |
env->intr_flag = 0; |
|
| 161 |
spin_unlock(&intr_cpu_lock); |
|
| 162 |
|
|
| 163 |
return tmp; |
|
| 154 | 164 |
} |
| 155 | 165 |
|
| 156 | 166 |
void helper_addqv (void) |
| b/target-alpha/op_helper.h | ||
|---|---|---|
| 19 | 19 |
*/ |
| 20 | 20 |
|
| 21 | 21 |
void helper_call_pal (uint32_t palcode); |
| 22 |
void helper_excp (uint32_t excp, uint32_t error); |
|
| 23 |
void helper_load_pcc (void); |
|
| 24 |
void helper_load_implver (void); |
|
| 25 | 22 |
void helper_load_fpcr (void); |
| 26 | 23 |
void helper_store_fpcr (void); |
| 27 |
void helper_load_irf (void); |
|
| 28 |
void helper_set_irf (void); |
|
| 29 |
void helper_clear_irf (void); |
|
| 30 | 24 |
void helper_addqv (void); |
| 31 | 25 |
void helper_addlv (void); |
| 32 | 26 |
void helper_subqv (void); |
| b/target-alpha/translate.c | ||
|---|---|---|
| 250 | 250 |
static always_inline void gen_excp (DisasContext *ctx, |
| 251 | 251 |
int exception, int error_code) |
| 252 | 252 |
{
|
| 253 |
TCGv tmp1, tmp2; |
|
| 254 |
|
|
| 253 | 255 |
tcg_gen_movi_i64(cpu_pc, ctx->pc); |
| 254 |
gen_op_excp(exception, error_code); |
|
| 256 |
tmp1 = tcg_const_i32(exception); |
|
| 257 |
tmp2 = tcg_const_i32(error_code); |
|
| 258 |
tcg_gen_helper_0_2(helper_excp, tmp1, tmp2); |
|
| 259 |
tcg_temp_free(tmp2); |
|
| 260 |
tcg_temp_free(tmp1); |
|
| 255 | 261 |
} |
| 256 | 262 |
|
| 257 | 263 |
static always_inline void gen_invalid (DisasContext *ctx) |
| ... | ... | |
| 1176 | 1182 |
break; |
| 1177 | 1183 |
case 0x6C: |
| 1178 | 1184 |
/* IMPLVER */ |
| 1179 |
gen_op_load_implver(); |
|
| 1180 | 1185 |
if (rc != 31) |
| 1181 |
tcg_gen_mov_i64(cpu_ir[rc], cpu_T[0]);
|
|
| 1186 |
tcg_gen_helper_1_0(helper_load_implver, cpu_ir[rc]);
|
|
| 1182 | 1187 |
break; |
| 1183 | 1188 |
default: |
| 1184 | 1189 |
goto invalid_opc; |
| ... | ... | |
| 1699 | 1704 |
break; |
| 1700 | 1705 |
case 0xC000: |
| 1701 | 1706 |
/* RPCC */ |
| 1702 |
gen_op_load_pcc(); |
|
| 1703 | 1707 |
if (ra != 31) |
| 1704 |
tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]);
|
|
| 1708 |
tcg_gen_helper_1_0(helper_load_pcc, cpu_ir[ra]);
|
|
| 1705 | 1709 |
break; |
| 1706 | 1710 |
case 0xE000: |
| 1707 | 1711 |
/* RC */ |
| 1708 |
gen_op_load_irf(); |
|
| 1709 | 1712 |
if (ra != 31) |
| 1710 |
tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]); |
|
| 1711 |
gen_op_clear_irf(); |
|
| 1713 |
tcg_gen_helper_1_0(helper_rc, cpu_ir[ra]); |
|
| 1712 | 1714 |
break; |
| 1713 | 1715 |
case 0xE800: |
| 1714 | 1716 |
/* ECB */ |
| ... | ... | |
| 1721 | 1723 |
break; |
| 1722 | 1724 |
case 0xF000: |
| 1723 | 1725 |
/* RS */ |
| 1724 |
gen_op_load_irf(); |
|
| 1725 | 1726 |
if (ra != 31) |
| 1726 |
tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]); |
|
| 1727 |
gen_op_set_irf(); |
|
| 1727 |
tcg_gen_helper_1_0(helper_rs, cpu_ir[ra]); |
|
| 1728 | 1728 |
break; |
| 1729 | 1729 |
case 0xF800: |
| 1730 | 1730 |
/* WH64 */ |
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