root / target-mips / exec.h @ 6ad0a1ed
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1 | 6af0bf9c | bellard | #if !defined(__QEMU_MIPS_EXEC_H__)
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2 | 6af0bf9c | bellard | #define __QEMU_MIPS_EXEC_H__
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3 | 6af0bf9c | bellard | |
4 | 01dbbdf1 | bellard | //#define DEBUG_OP
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5 | 6af0bf9c | bellard | |
6 | c570fd16 | ths | #include "config.h" |
7 | 6af0bf9c | bellard | #include "mips-defs.h" |
8 | 6af0bf9c | bellard | #include "dyngen-exec.h" |
9 | 01179c38 | ths | #include "cpu-defs.h" |
10 | 6af0bf9c | bellard | |
11 | 6af0bf9c | bellard | register struct CPUMIPSState *env asm(AREG0); |
12 | 6af0bf9c | bellard | |
13 | 6af0bf9c | bellard | #include "cpu.h" |
14 | 6af0bf9c | bellard | #include "exec-all.h" |
15 | 6af0bf9c | bellard | |
16 | 6af0bf9c | bellard | #if !defined(CONFIG_USER_ONLY)
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17 | a9049a07 | bellard | #include "softmmu_exec.h" |
18 | 6af0bf9c | bellard | #endif /* !defined(CONFIG_USER_ONLY) */ |
19 | 6af0bf9c | bellard | |
20 | 6a4955a8 | aliguori | static inline int cpu_has_work(CPUState *env) |
21 | 6a4955a8 | aliguori | { |
22 | 4cdc1cd1 | Aurelien Jarno | int has_work = 0; |
23 | 4cdc1cd1 | Aurelien Jarno | |
24 | 4cdc1cd1 | Aurelien Jarno | /* It is implementation dependent if non-enabled interrupts
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25 | 4cdc1cd1 | Aurelien Jarno | wake-up the CPU, however most of the implementations only
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26 | 4cdc1cd1 | Aurelien Jarno | check for interrupts that can be taken. */
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27 | 4cdc1cd1 | Aurelien Jarno | if ((env->interrupt_request & CPU_INTERRUPT_HARD) &&
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28 | 4cdc1cd1 | Aurelien Jarno | cpu_mips_hw_interrupts_pending(env)) { |
29 | 4cdc1cd1 | Aurelien Jarno | has_work = 1;
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30 | 4cdc1cd1 | Aurelien Jarno | } |
31 | 6a4955a8 | aliguori | |
32 | 4cdc1cd1 | Aurelien Jarno | if (env->interrupt_request & CPU_INTERRUPT_TIMER) {
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33 | 4cdc1cd1 | Aurelien Jarno | has_work = 1;
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34 | 4cdc1cd1 | Aurelien Jarno | } |
35 | 4cdc1cd1 | Aurelien Jarno | |
36 | 4cdc1cd1 | Aurelien Jarno | return has_work;
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37 | 4cdc1cd1 | Aurelien Jarno | } |
38 | 6a4955a8 | aliguori | |
39 | c904ef0e | ths | static inline int cpu_halted(CPUState *env) |
40 | 08fa4bab | ths | { |
41 | bfed01fc | ths | if (!env->halted)
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42 | bfed01fc | ths | return 0; |
43 | 6a4955a8 | aliguori | if (cpu_has_work(env)) {
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44 | bfed01fc | ths | env->halted = 0;
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45 | bfed01fc | ths | return 0; |
46 | bfed01fc | ths | } |
47 | bfed01fc | ths | return EXCP_HALTED;
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48 | bfed01fc | ths | } |
49 | bfed01fc | ths | |
50 | c904ef0e | ths | static inline void compute_hflags(CPUState *env) |
51 | 08fa4bab | ths | { |
52 | b8aa4598 | ths | env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | |
53 | 2623c1ec | aurel32 | MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU | |
54 | 2623c1ec | aurel32 | MIPS_HFLAG_UX); |
55 | 08fa4bab | ths | if (!(env->CP0_Status & (1 << CP0St_EXL)) && |
56 | 08fa4bab | ths | !(env->CP0_Status & (1 << CP0St_ERL)) &&
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57 | 671880e6 | ths | !(env->hflags & MIPS_HFLAG_DM)) { |
58 | 623a930e | ths | env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU; |
59 | 671880e6 | ths | } |
60 | d26bc211 | ths | #if defined(TARGET_MIPS64)
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61 | 623a930e | ths | if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
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62 | 08fa4bab | ths | (env->CP0_Status & (1 << CP0St_PX)) ||
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63 | 08fa4bab | ths | (env->CP0_Status & (1 << CP0St_UX)))
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64 | 08fa4bab | ths | env->hflags |= MIPS_HFLAG_64; |
65 | 2623c1ec | aurel32 | if (env->CP0_Status & (1 << CP0St_UX)) |
66 | 2623c1ec | aurel32 | env->hflags |= MIPS_HFLAG_UX; |
67 | 08fa4bab | ths | #endif
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68 | 671880e6 | ths | if ((env->CP0_Status & (1 << CP0St_CU0)) || |
69 | 623a930e | ths | !(env->hflags & MIPS_HFLAG_KSU)) |
70 | 08fa4bab | ths | env->hflags |= MIPS_HFLAG_CP0; |
71 | 08fa4bab | ths | if (env->CP0_Status & (1 << CP0St_CU1)) |
72 | 08fa4bab | ths | env->hflags |= MIPS_HFLAG_FPU; |
73 | 08fa4bab | ths | if (env->CP0_Status & (1 << CP0St_FR)) |
74 | 08fa4bab | ths | env->hflags |= MIPS_HFLAG_F64; |
75 | b8aa4598 | ths | if (env->insn_flags & ISA_MIPS32R2) {
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76 | f01be154 | ths | if (env->active_fpu.fcr0 & (1 << FCR0_F64)) |
77 | b8aa4598 | ths | env->hflags |= MIPS_HFLAG_COP1X; |
78 | b8aa4598 | ths | } else if (env->insn_flags & ISA_MIPS32) { |
79 | b8aa4598 | ths | if (env->hflags & MIPS_HFLAG_64)
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80 | b8aa4598 | ths | env->hflags |= MIPS_HFLAG_COP1X; |
81 | b8aa4598 | ths | } else if (env->insn_flags & ISA_MIPS4) { |
82 | b8aa4598 | ths | /* All supported MIPS IV CPUs use the XX (CU3) to enable
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83 | b8aa4598 | ths | and disable the MIPS IV extensions to the MIPS III ISA.
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84 | b8aa4598 | ths | Some other MIPS IV CPUs ignore the bit, so the check here
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85 | b8aa4598 | ths | would be too restrictive for them. */
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86 | b8aa4598 | ths | if (env->CP0_Status & (1 << CP0St_CU3)) |
87 | b8aa4598 | ths | env->hflags |= MIPS_HFLAG_COP1X; |
88 | b8aa4598 | ths | } |
89 | 08fa4bab | ths | } |
90 | 08fa4bab | ths | |
91 | 10eb0cc0 | Paolo Bonzini | static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) |
92 | 10eb0cc0 | Paolo Bonzini | { |
93 | 10eb0cc0 | Paolo Bonzini | env->active_tc.PC = tb->pc; |
94 | 10eb0cc0 | Paolo Bonzini | env->hflags &= ~MIPS_HFLAG_BMASK; |
95 | 10eb0cc0 | Paolo Bonzini | env->hflags |= tb->flags & MIPS_HFLAG_BMASK; |
96 | 10eb0cc0 | Paolo Bonzini | } |
97 | 10eb0cc0 | Paolo Bonzini | |
98 | 6af0bf9c | bellard | #endif /* !defined(__QEMU_MIPS_EXEC_H__) */ |