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1 | 6f7e9aec | bellard | /*
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2 | 67e999be | bellard | * QEMU ESP/NCR53C9x emulation
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3 | 5fafdf24 | ths | *
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4 | 4e9aec74 | pbrook | * Copyright (c) 2005-2006 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 6f7e9aec | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 6f7e9aec | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 6f7e9aec | bellard | * in the Software without restriction, including without limitation the rights
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9 | 6f7e9aec | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 6f7e9aec | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 6f7e9aec | bellard | * furnished to do so, subject to the following conditions:
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12 | 6f7e9aec | bellard | *
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13 | 6f7e9aec | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 6f7e9aec | bellard | * all copies or substantial portions of the Software.
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15 | 6f7e9aec | bellard | *
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16 | 6f7e9aec | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 6f7e9aec | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 6f7e9aec | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 6f7e9aec | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 6f7e9aec | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 6f7e9aec | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 6f7e9aec | bellard | * THE SOFTWARE.
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23 | 6f7e9aec | bellard | */
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24 | 5d20fa6b | blueswir1 | |
25 | cfb9de9c | Paul Brook | #include "sysbus.h" |
26 | 87ecb68b | pbrook | #include "scsi-disk.h" |
27 | 8b17de88 | blueswir1 | #include "scsi.h" |
28 | 6f7e9aec | bellard | |
29 | 6f7e9aec | bellard | /* debug ESP card */
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30 | 2f275b8f | bellard | //#define DEBUG_ESP
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31 | 6f7e9aec | bellard | |
32 | 67e999be | bellard | /*
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33 | 5ad6bb97 | blueswir1 | * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
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34 | 5ad6bb97 | blueswir1 | * also produced as NCR89C100. See
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35 | 67e999be | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
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36 | 67e999be | bellard | * and
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37 | 67e999be | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
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38 | 67e999be | bellard | */
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39 | 67e999be | bellard | |
40 | 6f7e9aec | bellard | #ifdef DEBUG_ESP
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41 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) \
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42 | 001faf32 | Blue Swirl | do { printf("ESP: " fmt , ## __VA_ARGS__); } while (0) |
43 | 6f7e9aec | bellard | #else
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44 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) do {} while (0) |
45 | 6f7e9aec | bellard | #endif
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46 | 6f7e9aec | bellard | |
47 | 001faf32 | Blue Swirl | #define ESP_ERROR(fmt, ...) \
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48 | 001faf32 | Blue Swirl | do { printf("ESP ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0) |
49 | 8dea1dd4 | blueswir1 | |
50 | 5aca8c3b | blueswir1 | #define ESP_REGS 16 |
51 | 8dea1dd4 | blueswir1 | #define TI_BUFSZ 16 |
52 | 67e999be | bellard | |
53 | 4e9aec74 | pbrook | typedef struct ESPState ESPState; |
54 | 6f7e9aec | bellard | |
55 | 4e9aec74 | pbrook | struct ESPState {
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56 | cfb9de9c | Paul Brook | SysBusDevice busdev; |
57 | 5d20fa6b | blueswir1 | uint32_t it_shift; |
58 | 70c0de96 | blueswir1 | qemu_irq irq; |
59 | 5aca8c3b | blueswir1 | uint8_t rregs[ESP_REGS]; |
60 | 5aca8c3b | blueswir1 | uint8_t wregs[ESP_REGS]; |
61 | 67e999be | bellard | int32_t ti_size; |
62 | 4f6200f0 | bellard | uint32_t ti_rptr, ti_wptr; |
63 | 4f6200f0 | bellard | uint8_t ti_buf[TI_BUFSZ]; |
64 | 22548760 | blueswir1 | uint32_t sense; |
65 | 22548760 | blueswir1 | uint32_t dma; |
66 | e4bcb14c | ths | SCSIDevice *scsi_dev[ESP_MAX_DEVS]; |
67 | 2e5d83bb | pbrook | SCSIDevice *current_dev; |
68 | 9f149aa9 | pbrook | uint8_t cmdbuf[TI_BUFSZ]; |
69 | 22548760 | blueswir1 | uint32_t cmdlen; |
70 | 22548760 | blueswir1 | uint32_t do_cmd; |
71 | 4d611c9a | pbrook | |
72 | 6787f5fa | pbrook | /* The amount of data left in the current DMA transfer. */
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73 | 4d611c9a | pbrook | uint32_t dma_left; |
74 | 6787f5fa | pbrook | /* The size of the current DMA transfer. Zero if no transfer is in
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75 | 6787f5fa | pbrook | progress. */
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76 | 6787f5fa | pbrook | uint32_t dma_counter; |
77 | a917d384 | pbrook | uint8_t *async_buf; |
78 | 4d611c9a | pbrook | uint32_t async_len; |
79 | 8b17de88 | blueswir1 | |
80 | 8b17de88 | blueswir1 | espdma_memory_read_write dma_memory_read; |
81 | 8b17de88 | blueswir1 | espdma_memory_read_write dma_memory_write; |
82 | 67e999be | bellard | void *dma_opaque;
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83 | 4e9aec74 | pbrook | }; |
84 | 6f7e9aec | bellard | |
85 | 5ad6bb97 | blueswir1 | #define ESP_TCLO 0x0 |
86 | 5ad6bb97 | blueswir1 | #define ESP_TCMID 0x1 |
87 | 5ad6bb97 | blueswir1 | #define ESP_FIFO 0x2 |
88 | 5ad6bb97 | blueswir1 | #define ESP_CMD 0x3 |
89 | 5ad6bb97 | blueswir1 | #define ESP_RSTAT 0x4 |
90 | 5ad6bb97 | blueswir1 | #define ESP_WBUSID 0x4 |
91 | 5ad6bb97 | blueswir1 | #define ESP_RINTR 0x5 |
92 | 5ad6bb97 | blueswir1 | #define ESP_WSEL 0x5 |
93 | 5ad6bb97 | blueswir1 | #define ESP_RSEQ 0x6 |
94 | 5ad6bb97 | blueswir1 | #define ESP_WSYNTP 0x6 |
95 | 5ad6bb97 | blueswir1 | #define ESP_RFLAGS 0x7 |
96 | 5ad6bb97 | blueswir1 | #define ESP_WSYNO 0x7 |
97 | 5ad6bb97 | blueswir1 | #define ESP_CFG1 0x8 |
98 | 5ad6bb97 | blueswir1 | #define ESP_RRES1 0x9 |
99 | 5ad6bb97 | blueswir1 | #define ESP_WCCF 0x9 |
100 | 5ad6bb97 | blueswir1 | #define ESP_RRES2 0xa |
101 | 5ad6bb97 | blueswir1 | #define ESP_WTEST 0xa |
102 | 5ad6bb97 | blueswir1 | #define ESP_CFG2 0xb |
103 | 5ad6bb97 | blueswir1 | #define ESP_CFG3 0xc |
104 | 5ad6bb97 | blueswir1 | #define ESP_RES3 0xd |
105 | 5ad6bb97 | blueswir1 | #define ESP_TCHI 0xe |
106 | 5ad6bb97 | blueswir1 | #define ESP_RES4 0xf |
107 | 5ad6bb97 | blueswir1 | |
108 | 5ad6bb97 | blueswir1 | #define CMD_DMA 0x80 |
109 | 5ad6bb97 | blueswir1 | #define CMD_CMD 0x7f |
110 | 5ad6bb97 | blueswir1 | |
111 | 5ad6bb97 | blueswir1 | #define CMD_NOP 0x00 |
112 | 5ad6bb97 | blueswir1 | #define CMD_FLUSH 0x01 |
113 | 5ad6bb97 | blueswir1 | #define CMD_RESET 0x02 |
114 | 5ad6bb97 | blueswir1 | #define CMD_BUSRESET 0x03 |
115 | 5ad6bb97 | blueswir1 | #define CMD_TI 0x10 |
116 | 5ad6bb97 | blueswir1 | #define CMD_ICCS 0x11 |
117 | 5ad6bb97 | blueswir1 | #define CMD_MSGACC 0x12 |
118 | 0fd0eb21 | Blue Swirl | #define CMD_PAD 0x18 |
119 | 5ad6bb97 | blueswir1 | #define CMD_SATN 0x1a |
120 | 5e1e0a3b | Blue Swirl | #define CMD_SEL 0x41 |
121 | 5ad6bb97 | blueswir1 | #define CMD_SELATN 0x42 |
122 | 5ad6bb97 | blueswir1 | #define CMD_SELATNS 0x43 |
123 | 5ad6bb97 | blueswir1 | #define CMD_ENSEL 0x44 |
124 | 5ad6bb97 | blueswir1 | |
125 | 2f275b8f | bellard | #define STAT_DO 0x00 |
126 | 2f275b8f | bellard | #define STAT_DI 0x01 |
127 | 2f275b8f | bellard | #define STAT_CD 0x02 |
128 | 2f275b8f | bellard | #define STAT_ST 0x03 |
129 | 8dea1dd4 | blueswir1 | #define STAT_MO 0x06 |
130 | 8dea1dd4 | blueswir1 | #define STAT_MI 0x07 |
131 | 5ad6bb97 | blueswir1 | #define STAT_PIO_MASK 0x06 |
132 | 2f275b8f | bellard | |
133 | 2f275b8f | bellard | #define STAT_TC 0x10 |
134 | 4d611c9a | pbrook | #define STAT_PE 0x20 |
135 | 4d611c9a | pbrook | #define STAT_GE 0x40 |
136 | c73f96fd | blueswir1 | #define STAT_INT 0x80 |
137 | 2f275b8f | bellard | |
138 | 8dea1dd4 | blueswir1 | #define BUSID_DID 0x07 |
139 | 8dea1dd4 | blueswir1 | |
140 | 2f275b8f | bellard | #define INTR_FC 0x08 |
141 | 2f275b8f | bellard | #define INTR_BS 0x10 |
142 | 2f275b8f | bellard | #define INTR_DC 0x20 |
143 | 9e61bde5 | bellard | #define INTR_RST 0x80 |
144 | 2f275b8f | bellard | |
145 | 2f275b8f | bellard | #define SEQ_0 0x0 |
146 | 2f275b8f | bellard | #define SEQ_CD 0x4 |
147 | 2f275b8f | bellard | |
148 | 5ad6bb97 | blueswir1 | #define CFG1_RESREPT 0x40 |
149 | 5ad6bb97 | blueswir1 | |
150 | 5ad6bb97 | blueswir1 | #define TCHI_FAS100A 0x4 |
151 | 5ad6bb97 | blueswir1 | |
152 | c73f96fd | blueswir1 | static void esp_raise_irq(ESPState *s) |
153 | c73f96fd | blueswir1 | { |
154 | c73f96fd | blueswir1 | if (!(s->rregs[ESP_RSTAT] & STAT_INT)) {
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155 | c73f96fd | blueswir1 | s->rregs[ESP_RSTAT] |= STAT_INT; |
156 | c73f96fd | blueswir1 | qemu_irq_raise(s->irq); |
157 | c73f96fd | blueswir1 | } |
158 | c73f96fd | blueswir1 | } |
159 | c73f96fd | blueswir1 | |
160 | c73f96fd | blueswir1 | static void esp_lower_irq(ESPState *s) |
161 | c73f96fd | blueswir1 | { |
162 | c73f96fd | blueswir1 | if (s->rregs[ESP_RSTAT] & STAT_INT) {
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163 | c73f96fd | blueswir1 | s->rregs[ESP_RSTAT] &= ~STAT_INT; |
164 | c73f96fd | blueswir1 | qemu_irq_lower(s->irq); |
165 | c73f96fd | blueswir1 | } |
166 | c73f96fd | blueswir1 | } |
167 | c73f96fd | blueswir1 | |
168 | 22548760 | blueswir1 | static uint32_t get_cmd(ESPState *s, uint8_t *buf)
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169 | 2f275b8f | bellard | { |
170 | a917d384 | pbrook | uint32_t dmalen; |
171 | 2f275b8f | bellard | int target;
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172 | 2f275b8f | bellard | |
173 | 8dea1dd4 | blueswir1 | target = s->wregs[ESP_WBUSID] & BUSID_DID; |
174 | 4f6200f0 | bellard | if (s->dma) {
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175 | fc4d65da | blueswir1 | dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
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176 | 8b17de88 | blueswir1 | s->dma_memory_read(s->dma_opaque, buf, dmalen); |
177 | 4f6200f0 | bellard | } else {
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178 | fc4d65da | blueswir1 | dmalen = s->ti_size; |
179 | fc4d65da | blueswir1 | memcpy(buf, s->ti_buf, dmalen); |
180 | f930d07e | blueswir1 | buf[0] = 0; |
181 | 4f6200f0 | bellard | } |
182 | fc4d65da | blueswir1 | DPRINTF("get_cmd: len %d target %d\n", dmalen, target);
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183 | 2e5d83bb | pbrook | |
184 | 2f275b8f | bellard | s->ti_size = 0;
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185 | 4f6200f0 | bellard | s->ti_rptr = 0;
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186 | 4f6200f0 | bellard | s->ti_wptr = 0;
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187 | 2f275b8f | bellard | |
188 | a917d384 | pbrook | if (s->current_dev) {
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189 | a917d384 | pbrook | /* Started a new command before the old one finished. Cancel it. */
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190 | 8ccc2ace | ths | s->current_dev->cancel_io(s->current_dev, 0);
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191 | a917d384 | pbrook | s->async_len = 0;
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192 | a917d384 | pbrook | } |
193 | a917d384 | pbrook | |
194 | e4bcb14c | ths | if (target >= ESP_MAX_DEVS || !s->scsi_dev[target]) {
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195 | 2e5d83bb | pbrook | // No such drive
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196 | c73f96fd | blueswir1 | s->rregs[ESP_RSTAT] = 0;
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197 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RINTR] = INTR_DC; |
198 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSEQ] = SEQ_0; |
199 | c73f96fd | blueswir1 | esp_raise_irq(s); |
200 | f930d07e | blueswir1 | return 0; |
201 | 2f275b8f | bellard | } |
202 | 2e5d83bb | pbrook | s->current_dev = s->scsi_dev[target]; |
203 | 9f149aa9 | pbrook | return dmalen;
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204 | 9f149aa9 | pbrook | } |
205 | 9f149aa9 | pbrook | |
206 | 9f149aa9 | pbrook | static void do_cmd(ESPState *s, uint8_t *buf) |
207 | 9f149aa9 | pbrook | { |
208 | 9f149aa9 | pbrook | int32_t datalen; |
209 | 9f149aa9 | pbrook | int lun;
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210 | 9f149aa9 | pbrook | |
211 | 9f149aa9 | pbrook | DPRINTF("do_cmd: busid 0x%x\n", buf[0]); |
212 | 9f149aa9 | pbrook | lun = buf[0] & 7; |
213 | 8ccc2ace | ths | datalen = s->current_dev->send_command(s->current_dev, 0, &buf[1], lun); |
214 | 67e999be | bellard | s->ti_size = datalen; |
215 | 67e999be | bellard | if (datalen != 0) { |
216 | c73f96fd | blueswir1 | s->rregs[ESP_RSTAT] = STAT_TC; |
217 | a917d384 | pbrook | s->dma_left = 0;
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218 | 6787f5fa | pbrook | s->dma_counter = 0;
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219 | 2e5d83bb | pbrook | if (datalen > 0) { |
220 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSTAT] |= STAT_DI; |
221 | 8ccc2ace | ths | s->current_dev->read_data(s->current_dev, 0);
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222 | 2e5d83bb | pbrook | } else {
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223 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSTAT] |= STAT_DO; |
224 | 8ccc2ace | ths | s->current_dev->write_data(s->current_dev, 0);
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225 | b9788fc4 | bellard | } |
226 | 2f275b8f | bellard | } |
227 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
228 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSEQ] = SEQ_CD; |
229 | c73f96fd | blueswir1 | esp_raise_irq(s); |
230 | 2f275b8f | bellard | } |
231 | 2f275b8f | bellard | |
232 | 9f149aa9 | pbrook | static void handle_satn(ESPState *s) |
233 | 9f149aa9 | pbrook | { |
234 | 9f149aa9 | pbrook | uint8_t buf[32];
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235 | 9f149aa9 | pbrook | int len;
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236 | 9f149aa9 | pbrook | |
237 | 9f149aa9 | pbrook | len = get_cmd(s, buf); |
238 | 9f149aa9 | pbrook | if (len)
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239 | 9f149aa9 | pbrook | do_cmd(s, buf); |
240 | 9f149aa9 | pbrook | } |
241 | 9f149aa9 | pbrook | |
242 | 9f149aa9 | pbrook | static void handle_satn_stop(ESPState *s) |
243 | 9f149aa9 | pbrook | { |
244 | 9f149aa9 | pbrook | s->cmdlen = get_cmd(s, s->cmdbuf); |
245 | 9f149aa9 | pbrook | if (s->cmdlen) {
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246 | 9f149aa9 | pbrook | DPRINTF("Set ATN & Stop: cmdlen %d\n", s->cmdlen);
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247 | 9f149aa9 | pbrook | s->do_cmd = 1;
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248 | c73f96fd | blueswir1 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; |
249 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
250 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSEQ] = SEQ_CD; |
251 | c73f96fd | blueswir1 | esp_raise_irq(s); |
252 | 9f149aa9 | pbrook | } |
253 | 9f149aa9 | pbrook | } |
254 | 9f149aa9 | pbrook | |
255 | 0fc5c15a | pbrook | static void write_response(ESPState *s) |
256 | 2f275b8f | bellard | { |
257 | 0fc5c15a | pbrook | DPRINTF("Transfer status (sense=%d)\n", s->sense);
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258 | 0fc5c15a | pbrook | s->ti_buf[0] = s->sense;
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259 | 0fc5c15a | pbrook | s->ti_buf[1] = 0; |
260 | 4f6200f0 | bellard | if (s->dma) {
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261 | 8b17de88 | blueswir1 | s->dma_memory_write(s->dma_opaque, s->ti_buf, 2);
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262 | c73f96fd | blueswir1 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; |
263 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
264 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSEQ] = SEQ_CD; |
265 | 4f6200f0 | bellard | } else {
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266 | f930d07e | blueswir1 | s->ti_size = 2;
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267 | f930d07e | blueswir1 | s->ti_rptr = 0;
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268 | f930d07e | blueswir1 | s->ti_wptr = 0;
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269 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RFLAGS] = 2;
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270 | 4f6200f0 | bellard | } |
271 | c73f96fd | blueswir1 | esp_raise_irq(s); |
272 | 2f275b8f | bellard | } |
273 | 4f6200f0 | bellard | |
274 | a917d384 | pbrook | static void esp_dma_done(ESPState *s) |
275 | a917d384 | pbrook | { |
276 | c73f96fd | blueswir1 | s->rregs[ESP_RSTAT] |= STAT_TC; |
277 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RINTR] = INTR_BS; |
278 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSEQ] = 0;
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279 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RFLAGS] = 0;
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280 | 5ad6bb97 | blueswir1 | s->rregs[ESP_TCLO] = 0;
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281 | 5ad6bb97 | blueswir1 | s->rregs[ESP_TCMID] = 0;
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282 | c73f96fd | blueswir1 | esp_raise_irq(s); |
283 | a917d384 | pbrook | } |
284 | a917d384 | pbrook | |
285 | 4d611c9a | pbrook | static void esp_do_dma(ESPState *s) |
286 | 4d611c9a | pbrook | { |
287 | 67e999be | bellard | uint32_t len; |
288 | 4d611c9a | pbrook | int to_device;
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289 | a917d384 | pbrook | |
290 | 67e999be | bellard | to_device = (s->ti_size < 0);
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291 | a917d384 | pbrook | len = s->dma_left; |
292 | 4d611c9a | pbrook | if (s->do_cmd) {
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293 | 4d611c9a | pbrook | DPRINTF("command len %d + %d\n", s->cmdlen, len);
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294 | 8b17de88 | blueswir1 | s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len); |
295 | 4d611c9a | pbrook | s->ti_size = 0;
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296 | 4d611c9a | pbrook | s->cmdlen = 0;
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297 | 4d611c9a | pbrook | s->do_cmd = 0;
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298 | 4d611c9a | pbrook | do_cmd(s, s->cmdbuf); |
299 | 4d611c9a | pbrook | return;
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300 | a917d384 | pbrook | } |
301 | a917d384 | pbrook | if (s->async_len == 0) { |
302 | a917d384 | pbrook | /* Defer until data is available. */
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303 | a917d384 | pbrook | return;
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304 | a917d384 | pbrook | } |
305 | a917d384 | pbrook | if (len > s->async_len) {
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306 | a917d384 | pbrook | len = s->async_len; |
307 | a917d384 | pbrook | } |
308 | a917d384 | pbrook | if (to_device) {
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309 | 8b17de88 | blueswir1 | s->dma_memory_read(s->dma_opaque, s->async_buf, len); |
310 | 4d611c9a | pbrook | } else {
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311 | 8b17de88 | blueswir1 | s->dma_memory_write(s->dma_opaque, s->async_buf, len); |
312 | a917d384 | pbrook | } |
313 | a917d384 | pbrook | s->dma_left -= len; |
314 | a917d384 | pbrook | s->async_buf += len; |
315 | a917d384 | pbrook | s->async_len -= len; |
316 | 6787f5fa | pbrook | if (to_device)
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317 | 6787f5fa | pbrook | s->ti_size += len; |
318 | 6787f5fa | pbrook | else
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319 | 6787f5fa | pbrook | s->ti_size -= len; |
320 | a917d384 | pbrook | if (s->async_len == 0) { |
321 | 4d611c9a | pbrook | if (to_device) {
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322 | 67e999be | bellard | // ti_size is negative
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323 | 8ccc2ace | ths | s->current_dev->write_data(s->current_dev, 0);
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324 | 4d611c9a | pbrook | } else {
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325 | 8ccc2ace | ths | s->current_dev->read_data(s->current_dev, 0);
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326 | 6787f5fa | pbrook | /* If there is still data to be read from the device then
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327 | 8dea1dd4 | blueswir1 | complete the DMA operation immediately. Otherwise defer
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328 | 6787f5fa | pbrook | until the scsi layer has completed. */
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329 | 6787f5fa | pbrook | if (s->dma_left == 0 && s->ti_size > 0) { |
330 | 6787f5fa | pbrook | esp_dma_done(s); |
331 | 6787f5fa | pbrook | } |
332 | 4d611c9a | pbrook | } |
333 | 6787f5fa | pbrook | } else {
|
334 | 6787f5fa | pbrook | /* Partially filled a scsi buffer. Complete immediately. */
|
335 | a917d384 | pbrook | esp_dma_done(s); |
336 | a917d384 | pbrook | } |
337 | 4d611c9a | pbrook | } |
338 | 4d611c9a | pbrook | |
339 | a917d384 | pbrook | static void esp_command_complete(void *opaque, int reason, uint32_t tag, |
340 | a917d384 | pbrook | uint32_t arg) |
341 | 2e5d83bb | pbrook | { |
342 | 2e5d83bb | pbrook | ESPState *s = (ESPState *)opaque; |
343 | 2e5d83bb | pbrook | |
344 | 4d611c9a | pbrook | if (reason == SCSI_REASON_DONE) {
|
345 | 4d611c9a | pbrook | DPRINTF("SCSI Command complete\n");
|
346 | 4d611c9a | pbrook | if (s->ti_size != 0) |
347 | 4d611c9a | pbrook | DPRINTF("SCSI command completed unexpectedly\n");
|
348 | 4d611c9a | pbrook | s->ti_size = 0;
|
349 | a917d384 | pbrook | s->dma_left = 0;
|
350 | a917d384 | pbrook | s->async_len = 0;
|
351 | a917d384 | pbrook | if (arg)
|
352 | 4d611c9a | pbrook | DPRINTF("Command failed\n");
|
353 | a917d384 | pbrook | s->sense = arg; |
354 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSTAT] = STAT_ST; |
355 | a917d384 | pbrook | esp_dma_done(s); |
356 | a917d384 | pbrook | s->current_dev = NULL;
|
357 | 4d611c9a | pbrook | } else {
|
358 | 4d611c9a | pbrook | DPRINTF("transfer %d/%d\n", s->dma_left, s->ti_size);
|
359 | a917d384 | pbrook | s->async_len = arg; |
360 | 8ccc2ace | ths | s->async_buf = s->current_dev->get_buf(s->current_dev, 0);
|
361 | 6787f5fa | pbrook | if (s->dma_left) {
|
362 | a917d384 | pbrook | esp_do_dma(s); |
363 | 6787f5fa | pbrook | } else if (s->dma_counter != 0 && s->ti_size <= 0) { |
364 | 6787f5fa | pbrook | /* If this was the last part of a DMA transfer then the
|
365 | 6787f5fa | pbrook | completion interrupt is deferred to here. */
|
366 | 6787f5fa | pbrook | esp_dma_done(s); |
367 | 6787f5fa | pbrook | } |
368 | 4d611c9a | pbrook | } |
369 | 2e5d83bb | pbrook | } |
370 | 2e5d83bb | pbrook | |
371 | 2f275b8f | bellard | static void handle_ti(ESPState *s) |
372 | 2f275b8f | bellard | { |
373 | 4d611c9a | pbrook | uint32_t dmalen, minlen; |
374 | 2f275b8f | bellard | |
375 | 5ad6bb97 | blueswir1 | dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
|
376 | db59203d | pbrook | if (dmalen==0) { |
377 | db59203d | pbrook | dmalen=0x10000;
|
378 | db59203d | pbrook | } |
379 | 6787f5fa | pbrook | s->dma_counter = dmalen; |
380 | db59203d | pbrook | |
381 | 9f149aa9 | pbrook | if (s->do_cmd)
|
382 | 9f149aa9 | pbrook | minlen = (dmalen < 32) ? dmalen : 32; |
383 | 67e999be | bellard | else if (s->ti_size < 0) |
384 | 67e999be | bellard | minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size; |
385 | 9f149aa9 | pbrook | else
|
386 | 9f149aa9 | pbrook | minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size; |
387 | db59203d | pbrook | DPRINTF("Transfer Information len %d\n", minlen);
|
388 | 4f6200f0 | bellard | if (s->dma) {
|
389 | 4d611c9a | pbrook | s->dma_left = minlen; |
390 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSTAT] &= ~STAT_TC; |
391 | 4d611c9a | pbrook | esp_do_dma(s); |
392 | 9f149aa9 | pbrook | } else if (s->do_cmd) { |
393 | 9f149aa9 | pbrook | DPRINTF("command len %d\n", s->cmdlen);
|
394 | 9f149aa9 | pbrook | s->ti_size = 0;
|
395 | 9f149aa9 | pbrook | s->cmdlen = 0;
|
396 | 9f149aa9 | pbrook | s->do_cmd = 0;
|
397 | 9f149aa9 | pbrook | do_cmd(s, s->cmdbuf); |
398 | 9f149aa9 | pbrook | return;
|
399 | 9f149aa9 | pbrook | } |
400 | 2f275b8f | bellard | } |
401 | 2f275b8f | bellard | |
402 | 5aca8c3b | blueswir1 | static void esp_reset(void *opaque) |
403 | 6f7e9aec | bellard | { |
404 | 6f7e9aec | bellard | ESPState *s = opaque; |
405 | 67e999be | bellard | |
406 | 5aca8c3b | blueswir1 | memset(s->rregs, 0, ESP_REGS);
|
407 | 5aca8c3b | blueswir1 | memset(s->wregs, 0, ESP_REGS);
|
408 | 5ad6bb97 | blueswir1 | s->rregs[ESP_TCHI] = TCHI_FAS100A; // Indicate fas100a
|
409 | 4e9aec74 | pbrook | s->ti_size = 0;
|
410 | 4e9aec74 | pbrook | s->ti_rptr = 0;
|
411 | 4e9aec74 | pbrook | s->ti_wptr = 0;
|
412 | 4e9aec74 | pbrook | s->dma = 0;
|
413 | 9f149aa9 | pbrook | s->do_cmd = 0;
|
414 | 8dea1dd4 | blueswir1 | |
415 | 8dea1dd4 | blueswir1 | s->rregs[ESP_CFG1] = 7;
|
416 | 6f7e9aec | bellard | } |
417 | 6f7e9aec | bellard | |
418 | 2d069bab | blueswir1 | static void parent_esp_reset(void *opaque, int irq, int level) |
419 | 2d069bab | blueswir1 | { |
420 | 2d069bab | blueswir1 | if (level)
|
421 | 2d069bab | blueswir1 | esp_reset(opaque); |
422 | 2d069bab | blueswir1 | } |
423 | 2d069bab | blueswir1 | |
424 | 6f7e9aec | bellard | static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr) |
425 | 6f7e9aec | bellard | { |
426 | 6f7e9aec | bellard | ESPState *s = opaque; |
427 | 2814df28 | Blue Swirl | uint32_t saddr, old_val; |
428 | 6f7e9aec | bellard | |
429 | e64d7d59 | blueswir1 | saddr = addr >> s->it_shift; |
430 | 9e61bde5 | bellard | DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);
|
431 | 6f7e9aec | bellard | switch (saddr) {
|
432 | 5ad6bb97 | blueswir1 | case ESP_FIFO:
|
433 | f930d07e | blueswir1 | if (s->ti_size > 0) { |
434 | f930d07e | blueswir1 | s->ti_size--; |
435 | 5ad6bb97 | blueswir1 | if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { |
436 | 8dea1dd4 | blueswir1 | /* Data out. */
|
437 | 8dea1dd4 | blueswir1 | ESP_ERROR("PIO data read not implemented\n");
|
438 | 5ad6bb97 | blueswir1 | s->rregs[ESP_FIFO] = 0;
|
439 | 2e5d83bb | pbrook | } else {
|
440 | 5ad6bb97 | blueswir1 | s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++]; |
441 | 2e5d83bb | pbrook | } |
442 | c73f96fd | blueswir1 | esp_raise_irq(s); |
443 | f930d07e | blueswir1 | } |
444 | f930d07e | blueswir1 | if (s->ti_size == 0) { |
445 | 4f6200f0 | bellard | s->ti_rptr = 0;
|
446 | 4f6200f0 | bellard | s->ti_wptr = 0;
|
447 | 4f6200f0 | bellard | } |
448 | f930d07e | blueswir1 | break;
|
449 | 5ad6bb97 | blueswir1 | case ESP_RINTR:
|
450 | 2814df28 | Blue Swirl | /* Clear sequence step, interrupt register and all status bits
|
451 | 2814df28 | Blue Swirl | except TC */
|
452 | 2814df28 | Blue Swirl | old_val = s->rregs[ESP_RINTR]; |
453 | 2814df28 | Blue Swirl | s->rregs[ESP_RINTR] = 0;
|
454 | 2814df28 | Blue Swirl | s->rregs[ESP_RSTAT] &= ~STAT_TC; |
455 | 2814df28 | Blue Swirl | s->rregs[ESP_RSEQ] = SEQ_CD; |
456 | c73f96fd | blueswir1 | esp_lower_irq(s); |
457 | 2814df28 | Blue Swirl | |
458 | 2814df28 | Blue Swirl | return old_val;
|
459 | 6f7e9aec | bellard | default:
|
460 | f930d07e | blueswir1 | break;
|
461 | 6f7e9aec | bellard | } |
462 | 2f275b8f | bellard | return s->rregs[saddr];
|
463 | 6f7e9aec | bellard | } |
464 | 6f7e9aec | bellard | |
465 | 6f7e9aec | bellard | static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
466 | 6f7e9aec | bellard | { |
467 | 6f7e9aec | bellard | ESPState *s = opaque; |
468 | 6f7e9aec | bellard | uint32_t saddr; |
469 | 6f7e9aec | bellard | |
470 | e64d7d59 | blueswir1 | saddr = addr >> s->it_shift; |
471 | 5ad6bb97 | blueswir1 | DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr],
|
472 | 5ad6bb97 | blueswir1 | val); |
473 | 6f7e9aec | bellard | switch (saddr) {
|
474 | 5ad6bb97 | blueswir1 | case ESP_TCLO:
|
475 | 5ad6bb97 | blueswir1 | case ESP_TCMID:
|
476 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSTAT] &= ~STAT_TC; |
477 | 4f6200f0 | bellard | break;
|
478 | 5ad6bb97 | blueswir1 | case ESP_FIFO:
|
479 | 9f149aa9 | pbrook | if (s->do_cmd) {
|
480 | 9f149aa9 | pbrook | s->cmdbuf[s->cmdlen++] = val & 0xff;
|
481 | 8dea1dd4 | blueswir1 | } else if (s->ti_size == TI_BUFSZ - 1) { |
482 | 8dea1dd4 | blueswir1 | ESP_ERROR("fifo overrun\n");
|
483 | 2e5d83bb | pbrook | } else {
|
484 | 2e5d83bb | pbrook | s->ti_size++; |
485 | 2e5d83bb | pbrook | s->ti_buf[s->ti_wptr++] = val & 0xff;
|
486 | 2e5d83bb | pbrook | } |
487 | f930d07e | blueswir1 | break;
|
488 | 5ad6bb97 | blueswir1 | case ESP_CMD:
|
489 | 4f6200f0 | bellard | s->rregs[saddr] = val; |
490 | 5ad6bb97 | blueswir1 | if (val & CMD_DMA) {
|
491 | f930d07e | blueswir1 | s->dma = 1;
|
492 | 6787f5fa | pbrook | /* Reload DMA counter. */
|
493 | 5ad6bb97 | blueswir1 | s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO]; |
494 | 5ad6bb97 | blueswir1 | s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID]; |
495 | f930d07e | blueswir1 | } else {
|
496 | f930d07e | blueswir1 | s->dma = 0;
|
497 | f930d07e | blueswir1 | } |
498 | 5ad6bb97 | blueswir1 | switch(val & CMD_CMD) {
|
499 | 5ad6bb97 | blueswir1 | case CMD_NOP:
|
500 | f930d07e | blueswir1 | DPRINTF("NOP (%2.2x)\n", val);
|
501 | f930d07e | blueswir1 | break;
|
502 | 5ad6bb97 | blueswir1 | case CMD_FLUSH:
|
503 | f930d07e | blueswir1 | DPRINTF("Flush FIFO (%2.2x)\n", val);
|
504 | 9e61bde5 | bellard | //s->ti_size = 0;
|
505 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RINTR] = INTR_FC; |
506 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSEQ] = 0;
|
507 | a214c598 | blueswir1 | s->rregs[ESP_RFLAGS] = 0;
|
508 | f930d07e | blueswir1 | break;
|
509 | 5ad6bb97 | blueswir1 | case CMD_RESET:
|
510 | f930d07e | blueswir1 | DPRINTF("Chip reset (%2.2x)\n", val);
|
511 | f930d07e | blueswir1 | esp_reset(s); |
512 | f930d07e | blueswir1 | break;
|
513 | 5ad6bb97 | blueswir1 | case CMD_BUSRESET:
|
514 | f930d07e | blueswir1 | DPRINTF("Bus reset (%2.2x)\n", val);
|
515 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RINTR] = INTR_RST; |
516 | 5ad6bb97 | blueswir1 | if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {
|
517 | c73f96fd | blueswir1 | esp_raise_irq(s); |
518 | 9e61bde5 | bellard | } |
519 | f930d07e | blueswir1 | break;
|
520 | 5ad6bb97 | blueswir1 | case CMD_TI:
|
521 | f930d07e | blueswir1 | handle_ti(s); |
522 | f930d07e | blueswir1 | break;
|
523 | 5ad6bb97 | blueswir1 | case CMD_ICCS:
|
524 | f930d07e | blueswir1 | DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val);
|
525 | f930d07e | blueswir1 | write_response(s); |
526 | 4bf5801d | blueswir1 | s->rregs[ESP_RINTR] = INTR_FC; |
527 | 4bf5801d | blueswir1 | s->rregs[ESP_RSTAT] |= STAT_MI; |
528 | f930d07e | blueswir1 | break;
|
529 | 5ad6bb97 | blueswir1 | case CMD_MSGACC:
|
530 | f930d07e | blueswir1 | DPRINTF("Message Accepted (%2.2x)\n", val);
|
531 | f930d07e | blueswir1 | write_response(s); |
532 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RINTR] = INTR_DC; |
533 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSEQ] = 0;
|
534 | f930d07e | blueswir1 | break;
|
535 | 0fd0eb21 | Blue Swirl | case CMD_PAD:
|
536 | 0fd0eb21 | Blue Swirl | DPRINTF("Transfer padding (%2.2x)\n", val);
|
537 | 0fd0eb21 | Blue Swirl | s->rregs[ESP_RSTAT] = STAT_TC; |
538 | 0fd0eb21 | Blue Swirl | s->rregs[ESP_RINTR] = INTR_FC; |
539 | 0fd0eb21 | Blue Swirl | s->rregs[ESP_RSEQ] = 0;
|
540 | 0fd0eb21 | Blue Swirl | break;
|
541 | 5ad6bb97 | blueswir1 | case CMD_SATN:
|
542 | f930d07e | blueswir1 | DPRINTF("Set ATN (%2.2x)\n", val);
|
543 | f930d07e | blueswir1 | break;
|
544 | 5e1e0a3b | Blue Swirl | case CMD_SEL:
|
545 | 5e1e0a3b | Blue Swirl | DPRINTF("Select without ATN (%2.2x)\n", val);
|
546 | 5e1e0a3b | Blue Swirl | handle_satn(s); |
547 | 5e1e0a3b | Blue Swirl | break;
|
548 | 5ad6bb97 | blueswir1 | case CMD_SELATN:
|
549 | 5e1e0a3b | Blue Swirl | DPRINTF("Select with ATN (%2.2x)\n", val);
|
550 | f930d07e | blueswir1 | handle_satn(s); |
551 | f930d07e | blueswir1 | break;
|
552 | 5ad6bb97 | blueswir1 | case CMD_SELATNS:
|
553 | 5e1e0a3b | Blue Swirl | DPRINTF("Select with ATN & stop (%2.2x)\n", val);
|
554 | f930d07e | blueswir1 | handle_satn_stop(s); |
555 | f930d07e | blueswir1 | break;
|
556 | 5ad6bb97 | blueswir1 | case CMD_ENSEL:
|
557 | 74ec6048 | blueswir1 | DPRINTF("Enable selection (%2.2x)\n", val);
|
558 | e3926838 | blueswir1 | s->rregs[ESP_RINTR] = 0;
|
559 | 74ec6048 | blueswir1 | break;
|
560 | f930d07e | blueswir1 | default:
|
561 | 8dea1dd4 | blueswir1 | ESP_ERROR("Unhandled ESP command (%2.2x)\n", val);
|
562 | f930d07e | blueswir1 | break;
|
563 | f930d07e | blueswir1 | } |
564 | f930d07e | blueswir1 | break;
|
565 | 5ad6bb97 | blueswir1 | case ESP_WBUSID ... ESP_WSYNO:
|
566 | f930d07e | blueswir1 | break;
|
567 | 5ad6bb97 | blueswir1 | case ESP_CFG1:
|
568 | 4f6200f0 | bellard | s->rregs[saddr] = val; |
569 | 4f6200f0 | bellard | break;
|
570 | 5ad6bb97 | blueswir1 | case ESP_WCCF ... ESP_WTEST:
|
571 | 4f6200f0 | bellard | break;
|
572 | b44c08fa | blueswir1 | case ESP_CFG2 ... ESP_RES4:
|
573 | 4f6200f0 | bellard | s->rregs[saddr] = val; |
574 | 4f6200f0 | bellard | break;
|
575 | 6f7e9aec | bellard | default:
|
576 | 8dea1dd4 | blueswir1 | ESP_ERROR("invalid write of 0x%02x at [0x%x]\n", val, saddr);
|
577 | 8dea1dd4 | blueswir1 | return;
|
578 | 6f7e9aec | bellard | } |
579 | 2f275b8f | bellard | s->wregs[saddr] = val; |
580 | 6f7e9aec | bellard | } |
581 | 6f7e9aec | bellard | |
582 | 6f7e9aec | bellard | static CPUReadMemoryFunc *esp_mem_read[3] = { |
583 | 6f7e9aec | bellard | esp_mem_readb, |
584 | 7c560456 | blueswir1 | NULL,
|
585 | 7c560456 | blueswir1 | NULL,
|
586 | 6f7e9aec | bellard | }; |
587 | 6f7e9aec | bellard | |
588 | 6f7e9aec | bellard | static CPUWriteMemoryFunc *esp_mem_write[3] = { |
589 | 6f7e9aec | bellard | esp_mem_writeb, |
590 | 7c560456 | blueswir1 | NULL,
|
591 | daa41b00 | blueswir1 | esp_mem_writeb, |
592 | 6f7e9aec | bellard | }; |
593 | 6f7e9aec | bellard | |
594 | 6f7e9aec | bellard | static void esp_save(QEMUFile *f, void *opaque) |
595 | 6f7e9aec | bellard | { |
596 | 6f7e9aec | bellard | ESPState *s = opaque; |
597 | 2f275b8f | bellard | |
598 | 5aca8c3b | blueswir1 | qemu_put_buffer(f, s->rregs, ESP_REGS); |
599 | 5aca8c3b | blueswir1 | qemu_put_buffer(f, s->wregs, ESP_REGS); |
600 | b6c4f71f | blueswir1 | qemu_put_sbe32s(f, &s->ti_size); |
601 | 4f6200f0 | bellard | qemu_put_be32s(f, &s->ti_rptr); |
602 | 4f6200f0 | bellard | qemu_put_be32s(f, &s->ti_wptr); |
603 | 4f6200f0 | bellard | qemu_put_buffer(f, s->ti_buf, TI_BUFSZ); |
604 | 5425a216 | blueswir1 | qemu_put_be32s(f, &s->sense); |
605 | 4f6200f0 | bellard | qemu_put_be32s(f, &s->dma); |
606 | 5425a216 | blueswir1 | qemu_put_buffer(f, s->cmdbuf, TI_BUFSZ); |
607 | 5425a216 | blueswir1 | qemu_put_be32s(f, &s->cmdlen); |
608 | 5425a216 | blueswir1 | qemu_put_be32s(f, &s->do_cmd); |
609 | 5425a216 | blueswir1 | qemu_put_be32s(f, &s->dma_left); |
610 | 5425a216 | blueswir1 | // There should be no transfers in progress, so dma_counter is not saved
|
611 | 6f7e9aec | bellard | } |
612 | 6f7e9aec | bellard | |
613 | 6f7e9aec | bellard | static int esp_load(QEMUFile *f, void *opaque, int version_id) |
614 | 6f7e9aec | bellard | { |
615 | 6f7e9aec | bellard | ESPState *s = opaque; |
616 | 3b46e624 | ths | |
617 | 5425a216 | blueswir1 | if (version_id != 3) |
618 | 5425a216 | blueswir1 | return -EINVAL; // Cannot emulate 2 |
619 | 6f7e9aec | bellard | |
620 | 5aca8c3b | blueswir1 | qemu_get_buffer(f, s->rregs, ESP_REGS); |
621 | 5aca8c3b | blueswir1 | qemu_get_buffer(f, s->wregs, ESP_REGS); |
622 | b6c4f71f | blueswir1 | qemu_get_sbe32s(f, &s->ti_size); |
623 | 4f6200f0 | bellard | qemu_get_be32s(f, &s->ti_rptr); |
624 | 4f6200f0 | bellard | qemu_get_be32s(f, &s->ti_wptr); |
625 | 4f6200f0 | bellard | qemu_get_buffer(f, s->ti_buf, TI_BUFSZ); |
626 | 5425a216 | blueswir1 | qemu_get_be32s(f, &s->sense); |
627 | 4f6200f0 | bellard | qemu_get_be32s(f, &s->dma); |
628 | 5425a216 | blueswir1 | qemu_get_buffer(f, s->cmdbuf, TI_BUFSZ); |
629 | 5425a216 | blueswir1 | qemu_get_be32s(f, &s->cmdlen); |
630 | 5425a216 | blueswir1 | qemu_get_be32s(f, &s->do_cmd); |
631 | 5425a216 | blueswir1 | qemu_get_be32s(f, &s->dma_left); |
632 | 2f275b8f | bellard | |
633 | 6f7e9aec | bellard | return 0; |
634 | 6f7e9aec | bellard | } |
635 | 6f7e9aec | bellard | |
636 | cfb9de9c | Paul Brook | static void esp_scsi_attach(DeviceState *host, BlockDriverState *bd, int id) |
637 | fa1fb14c | ths | { |
638 | cfb9de9c | Paul Brook | ESPState *s = FROM_SYSBUS(ESPState, sysbus_from_qdev(host)); |
639 | fa1fb14c | ths | |
640 | fa1fb14c | ths | if (id < 0) { |
641 | fa1fb14c | ths | for (id = 0; id < ESP_MAX_DEVS; id++) { |
642 | 8dea1dd4 | blueswir1 | if (id == (s->rregs[ESP_CFG1] & 0x7)) |
643 | 8dea1dd4 | blueswir1 | continue;
|
644 | fa1fb14c | ths | if (s->scsi_dev[id] == NULL) |
645 | fa1fb14c | ths | break;
|
646 | fa1fb14c | ths | } |
647 | fa1fb14c | ths | } |
648 | fa1fb14c | ths | if (id >= ESP_MAX_DEVS) {
|
649 | fa1fb14c | ths | DPRINTF("Bad Device ID %d\n", id);
|
650 | fa1fb14c | ths | return;
|
651 | fa1fb14c | ths | } |
652 | fa1fb14c | ths | if (s->scsi_dev[id]) {
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653 | fa1fb14c | ths | DPRINTF("Destroying device %d\n", id);
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654 | 8ccc2ace | ths | s->scsi_dev[id]->destroy(s->scsi_dev[id]); |
655 | fa1fb14c | ths | } |
656 | fa1fb14c | ths | DPRINTF("Attaching block device %d\n", id);
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657 | fa1fb14c | ths | /* Command queueing is not implemented. */
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658 | 985a03b0 | ths | s->scsi_dev[id] = scsi_generic_init(bd, 0, esp_command_complete, s);
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659 | 985a03b0 | ths | if (s->scsi_dev[id] == NULL) |
660 | 985a03b0 | ths | s->scsi_dev[id] = scsi_disk_init(bd, 0, esp_command_complete, s);
|
661 | fa1fb14c | ths | } |
662 | fa1fb14c | ths | |
663 | cfb9de9c | Paul Brook | void esp_init(target_phys_addr_t espaddr, int it_shift, |
664 | cfb9de9c | Paul Brook | espdma_memory_read_write dma_memory_read, |
665 | cfb9de9c | Paul Brook | espdma_memory_read_write dma_memory_write, |
666 | cfb9de9c | Paul Brook | void *dma_opaque, qemu_irq irq, qemu_irq *reset)
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667 | 6f7e9aec | bellard | { |
668 | cfb9de9c | Paul Brook | DeviceState *dev; |
669 | cfb9de9c | Paul Brook | SysBusDevice *s; |
670 | ee6847d1 | Gerd Hoffmann | ESPState *esp; |
671 | cfb9de9c | Paul Brook | |
672 | cfb9de9c | Paul Brook | dev = qdev_create(NULL, "esp"); |
673 | ee6847d1 | Gerd Hoffmann | esp = DO_UPCAST(ESPState, busdev.qdev, dev); |
674 | ee6847d1 | Gerd Hoffmann | esp->dma_memory_read = dma_memory_read; |
675 | ee6847d1 | Gerd Hoffmann | esp->dma_memory_write = dma_memory_write; |
676 | ee6847d1 | Gerd Hoffmann | esp->dma_opaque = dma_opaque; |
677 | ee6847d1 | Gerd Hoffmann | esp->it_shift = it_shift; |
678 | cfb9de9c | Paul Brook | qdev_init(dev); |
679 | cfb9de9c | Paul Brook | s = sysbus_from_qdev(dev); |
680 | cfb9de9c | Paul Brook | sysbus_connect_irq(s, 0, irq);
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681 | cfb9de9c | Paul Brook | sysbus_mmio_map(s, 0, espaddr);
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682 | 74ff8d90 | Blue Swirl | *reset = qdev_get_gpio_in(dev, 0);
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683 | cfb9de9c | Paul Brook | } |
684 | 6f7e9aec | bellard | |
685 | cfb9de9c | Paul Brook | static void esp_init1(SysBusDevice *dev) |
686 | cfb9de9c | Paul Brook | { |
687 | cfb9de9c | Paul Brook | ESPState *s = FROM_SYSBUS(ESPState, dev); |
688 | cfb9de9c | Paul Brook | int esp_io_memory;
|
689 | 6f7e9aec | bellard | |
690 | cfb9de9c | Paul Brook | sysbus_init_irq(dev, &s->irq); |
691 | cfb9de9c | Paul Brook | assert(s->it_shift != -1);
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692 | 6f7e9aec | bellard | |
693 | 1eed09cb | Avi Kivity | esp_io_memory = cpu_register_io_memory(esp_mem_read, esp_mem_write, s); |
694 | cfb9de9c | Paul Brook | sysbus_init_mmio(dev, ESP_REGS << s->it_shift, esp_io_memory); |
695 | 6f7e9aec | bellard | |
696 | 6f7e9aec | bellard | esp_reset(s); |
697 | 6f7e9aec | bellard | |
698 | cfb9de9c | Paul Brook | register_savevm("esp", -1, 3, esp_save, esp_load, s); |
699 | a08d4367 | Jan Kiszka | qemu_register_reset(esp_reset, s); |
700 | 6f7e9aec | bellard | |
701 | 067a3ddc | Paul Brook | qdev_init_gpio_in(&dev->qdev, parent_esp_reset, 1);
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702 | 2d069bab | blueswir1 | |
703 | cfb9de9c | Paul Brook | scsi_bus_new(&dev->qdev, esp_scsi_attach); |
704 | 67e999be | bellard | } |
705 | cfb9de9c | Paul Brook | |
706 | cfb9de9c | Paul Brook | static void esp_register_devices(void) |
707 | cfb9de9c | Paul Brook | { |
708 | cfb9de9c | Paul Brook | sysbus_register_dev("esp", sizeof(ESPState), esp_init1); |
709 | cfb9de9c | Paul Brook | } |
710 | cfb9de9c | Paul Brook | |
711 | cfb9de9c | Paul Brook | device_init(esp_register_devices) |