root / target-mips / op_helper.c @ 6b5435d7
History | View | Annotate | Download (45.1 kB)
1 | 6af0bf9c | bellard | /*
|
---|---|---|---|
2 | 6af0bf9c | bellard | * MIPS emulation helpers for qemu.
|
3 | 5fafdf24 | ths | *
|
4 | 6af0bf9c | bellard | * Copyright (c) 2004-2005 Jocelyn Mayer
|
5 | 6af0bf9c | bellard | *
|
6 | 6af0bf9c | bellard | * This library is free software; you can redistribute it and/or
|
7 | 6af0bf9c | bellard | * modify it under the terms of the GNU Lesser General Public
|
8 | 6af0bf9c | bellard | * License as published by the Free Software Foundation; either
|
9 | 6af0bf9c | bellard | * version 2 of the License, or (at your option) any later version.
|
10 | 6af0bf9c | bellard | *
|
11 | 6af0bf9c | bellard | * This library is distributed in the hope that it will be useful,
|
12 | 6af0bf9c | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 | 6af0bf9c | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
14 | 6af0bf9c | bellard | * Lesser General Public License for more details.
|
15 | 6af0bf9c | bellard | *
|
16 | 6af0bf9c | bellard | * You should have received a copy of the GNU Lesser General Public
|
17 | 6af0bf9c | bellard | * License along with this library; if not, write to the Free Software
|
18 | 6af0bf9c | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
19 | 6af0bf9c | bellard | */
|
20 | 2d0e944d | ths | #include <stdlib.h> |
21 | 6af0bf9c | bellard | #include "exec.h" |
22 | 6af0bf9c | bellard | |
23 | 05f778c8 | ths | #include "host-utils.h" |
24 | 05f778c8 | ths | |
25 | 273af660 | ths | #ifdef __s390__
|
26 | 273af660 | ths | # define GETPC() ((void*)((unsigned long)__builtin_return_address(0) & 0x7fffffffUL)) |
27 | 273af660 | ths | #else
|
28 | 273af660 | ths | # define GETPC() (__builtin_return_address(0)) |
29 | 273af660 | ths | #endif
|
30 | 4ad40f36 | bellard | |
31 | 6af0bf9c | bellard | /*****************************************************************************/
|
32 | 6af0bf9c | bellard | /* Exceptions processing helpers */
|
33 | 6af0bf9c | bellard | |
34 | 6af0bf9c | bellard | void do_raise_exception_err (uint32_t exception, int error_code) |
35 | 6af0bf9c | bellard | { |
36 | 6af0bf9c | bellard | #if 1 |
37 | 6af0bf9c | bellard | if (logfile && exception < 0x100) |
38 | 6af0bf9c | bellard | fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
|
39 | 6af0bf9c | bellard | #endif
|
40 | 6af0bf9c | bellard | env->exception_index = exception; |
41 | 6af0bf9c | bellard | env->error_code = error_code; |
42 | 6af0bf9c | bellard | T0 = 0;
|
43 | 6af0bf9c | bellard | cpu_loop_exit(); |
44 | 6af0bf9c | bellard | } |
45 | 6af0bf9c | bellard | |
46 | 6af0bf9c | bellard | void do_raise_exception (uint32_t exception)
|
47 | 6af0bf9c | bellard | { |
48 | 6af0bf9c | bellard | do_raise_exception_err(exception, 0);
|
49 | 6af0bf9c | bellard | } |
50 | 6af0bf9c | bellard | |
51 | 4ad40f36 | bellard | void do_restore_state (void *pc_ptr) |
52 | 4ad40f36 | bellard | { |
53 | 4ad40f36 | bellard | TranslationBlock *tb; |
54 | 4ad40f36 | bellard | unsigned long pc = (unsigned long) pc_ptr; |
55 | 4ad40f36 | bellard | |
56 | 4ad40f36 | bellard | tb = tb_find_pc (pc); |
57 | 4ad40f36 | bellard | cpu_restore_state (tb, env, pc, NULL);
|
58 | 4ad40f36 | bellard | } |
59 | 4ad40f36 | bellard | |
60 | e397ee33 | ths | void do_raise_exception_direct_err (uint32_t exception, int error_code) |
61 | 4ad40f36 | bellard | { |
62 | 4ad40f36 | bellard | do_restore_state (GETPC ()); |
63 | e397ee33 | ths | do_raise_exception_err (exception, error_code); |
64 | e397ee33 | ths | } |
65 | e397ee33 | ths | |
66 | e397ee33 | ths | void do_raise_exception_direct (uint32_t exception)
|
67 | e397ee33 | ths | { |
68 | e397ee33 | ths | do_raise_exception_direct_err (exception, 0);
|
69 | 4ad40f36 | bellard | } |
70 | 4ad40f36 | bellard | |
71 | d26bc211 | ths | #if defined(TARGET_MIPS64)
|
72 | c570fd16 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
|
73 | c570fd16 | ths | /* Those might call libgcc functions. */
|
74 | c570fd16 | ths | void do_dsll (void) |
75 | c570fd16 | ths | { |
76 | c570fd16 | ths | T0 = T0 << T1; |
77 | c570fd16 | ths | } |
78 | c570fd16 | ths | |
79 | c570fd16 | ths | void do_dsll32 (void) |
80 | c570fd16 | ths | { |
81 | c570fd16 | ths | T0 = T0 << (T1 + 32);
|
82 | c570fd16 | ths | } |
83 | c570fd16 | ths | |
84 | c570fd16 | ths | void do_dsra (void) |
85 | c570fd16 | ths | { |
86 | c570fd16 | ths | T0 = (int64_t)T0 >> T1; |
87 | c570fd16 | ths | } |
88 | c570fd16 | ths | |
89 | c570fd16 | ths | void do_dsra32 (void) |
90 | c570fd16 | ths | { |
91 | c570fd16 | ths | T0 = (int64_t)T0 >> (T1 + 32);
|
92 | c570fd16 | ths | } |
93 | c570fd16 | ths | |
94 | c570fd16 | ths | void do_dsrl (void) |
95 | c570fd16 | ths | { |
96 | c570fd16 | ths | T0 = T0 >> T1; |
97 | c570fd16 | ths | } |
98 | c570fd16 | ths | |
99 | c570fd16 | ths | void do_dsrl32 (void) |
100 | c570fd16 | ths | { |
101 | c570fd16 | ths | T0 = T0 >> (T1 + 32);
|
102 | c570fd16 | ths | } |
103 | c570fd16 | ths | |
104 | c570fd16 | ths | void do_drotr (void) |
105 | c570fd16 | ths | { |
106 | c570fd16 | ths | target_ulong tmp; |
107 | c570fd16 | ths | |
108 | c570fd16 | ths | if (T1) {
|
109 | c6d6dd7c | ths | tmp = T0 << (0x40 - T1);
|
110 | c6d6dd7c | ths | T0 = (T0 >> T1) | tmp; |
111 | 5a63bcb2 | ths | } |
112 | c570fd16 | ths | } |
113 | c570fd16 | ths | |
114 | c570fd16 | ths | void do_drotr32 (void) |
115 | c570fd16 | ths | { |
116 | c570fd16 | ths | target_ulong tmp; |
117 | c570fd16 | ths | |
118 | c6d6dd7c | ths | tmp = T0 << (0x40 - (32 + T1)); |
119 | c6d6dd7c | ths | T0 = (T0 >> (32 + T1)) | tmp;
|
120 | c570fd16 | ths | } |
121 | c570fd16 | ths | |
122 | c570fd16 | ths | void do_dsllv (void) |
123 | c570fd16 | ths | { |
124 | c570fd16 | ths | T0 = T1 << (T0 & 0x3F);
|
125 | c570fd16 | ths | } |
126 | c570fd16 | ths | |
127 | c570fd16 | ths | void do_dsrav (void) |
128 | c570fd16 | ths | { |
129 | c570fd16 | ths | T0 = (int64_t)T1 >> (T0 & 0x3F);
|
130 | c570fd16 | ths | } |
131 | c570fd16 | ths | |
132 | c570fd16 | ths | void do_dsrlv (void) |
133 | c570fd16 | ths | { |
134 | c570fd16 | ths | T0 = T1 >> (T0 & 0x3F);
|
135 | c570fd16 | ths | } |
136 | c570fd16 | ths | |
137 | c570fd16 | ths | void do_drotrv (void) |
138 | c570fd16 | ths | { |
139 | c570fd16 | ths | target_ulong tmp; |
140 | c570fd16 | ths | |
141 | c570fd16 | ths | T0 &= 0x3F;
|
142 | c570fd16 | ths | if (T0) {
|
143 | c6d6dd7c | ths | tmp = T1 << (0x40 - T0);
|
144 | c6d6dd7c | ths | T0 = (T1 >> T0) | tmp; |
145 | c570fd16 | ths | } else
|
146 | c6d6dd7c | ths | T0 = T1; |
147 | c570fd16 | ths | } |
148 | 05f778c8 | ths | |
149 | 05f778c8 | ths | void do_dclo (void) |
150 | 05f778c8 | ths | { |
151 | 05f778c8 | ths | T0 = clo64(T0); |
152 | 05f778c8 | ths | } |
153 | 05f778c8 | ths | |
154 | 05f778c8 | ths | void do_dclz (void) |
155 | 05f778c8 | ths | { |
156 | 05f778c8 | ths | T0 = clz64(T0); |
157 | 05f778c8 | ths | } |
158 | 05f778c8 | ths | |
159 | c570fd16 | ths | #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
160 | d26bc211 | ths | #endif /* TARGET_MIPS64 */ |
161 | c570fd16 | ths | |
162 | 6af0bf9c | bellard | /* 64 bits arithmetic for 32 bits hosts */
|
163 | c570fd16 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
|
164 | aa343735 | ths | static always_inline uint64_t get_HILO (void) |
165 | 6af0bf9c | bellard | { |
166 | ead9360e | ths | return (env->HI[0][env->current_tc] << 32) | (uint32_t)env->LO[0][env->current_tc]; |
167 | 6af0bf9c | bellard | } |
168 | 6af0bf9c | bellard | |
169 | aa343735 | ths | static always_inline void set_HILO (uint64_t HILO) |
170 | 6af0bf9c | bellard | { |
171 | ead9360e | ths | env->LO[0][env->current_tc] = (int32_t)HILO;
|
172 | ead9360e | ths | env->HI[0][env->current_tc] = (int32_t)(HILO >> 32); |
173 | 6af0bf9c | bellard | } |
174 | 6af0bf9c | bellard | |
175 | e9c71dd1 | ths | static always_inline void set_HIT0_LO (uint64_t HILO) |
176 | e9c71dd1 | ths | { |
177 | e9c71dd1 | ths | env->LO[0][env->current_tc] = (int32_t)(HILO & 0xFFFFFFFF); |
178 | e9c71dd1 | ths | T0 = env->HI[0][env->current_tc] = (int32_t)(HILO >> 32); |
179 | e9c71dd1 | ths | } |
180 | e9c71dd1 | ths | |
181 | e9c71dd1 | ths | static always_inline void set_HI_LOT0 (uint64_t HILO) |
182 | e9c71dd1 | ths | { |
183 | e9c71dd1 | ths | T0 = env->LO[0][env->current_tc] = (int32_t)(HILO & 0xFFFFFFFF); |
184 | e9c71dd1 | ths | env->HI[0][env->current_tc] = (int32_t)(HILO >> 32); |
185 | e9c71dd1 | ths | } |
186 | e9c71dd1 | ths | |
187 | 6af0bf9c | bellard | void do_mult (void) |
188 | 6af0bf9c | bellard | { |
189 | 4ad40f36 | bellard | set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
190 | 6af0bf9c | bellard | } |
191 | 6af0bf9c | bellard | |
192 | 6af0bf9c | bellard | void do_multu (void) |
193 | 6af0bf9c | bellard | { |
194 | c570fd16 | ths | set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
195 | 6af0bf9c | bellard | } |
196 | 6af0bf9c | bellard | |
197 | 6af0bf9c | bellard | void do_madd (void) |
198 | 6af0bf9c | bellard | { |
199 | 6af0bf9c | bellard | int64_t tmp; |
200 | 6af0bf9c | bellard | |
201 | 4ad40f36 | bellard | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
202 | 6af0bf9c | bellard | set_HILO((int64_t)get_HILO() + tmp); |
203 | 6af0bf9c | bellard | } |
204 | 6af0bf9c | bellard | |
205 | 6af0bf9c | bellard | void do_maddu (void) |
206 | 6af0bf9c | bellard | { |
207 | 6af0bf9c | bellard | uint64_t tmp; |
208 | 6af0bf9c | bellard | |
209 | c570fd16 | ths | tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
210 | 6af0bf9c | bellard | set_HILO(get_HILO() + tmp); |
211 | 6af0bf9c | bellard | } |
212 | 6af0bf9c | bellard | |
213 | 6af0bf9c | bellard | void do_msub (void) |
214 | 6af0bf9c | bellard | { |
215 | 6af0bf9c | bellard | int64_t tmp; |
216 | 6af0bf9c | bellard | |
217 | 4ad40f36 | bellard | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
218 | 6af0bf9c | bellard | set_HILO((int64_t)get_HILO() - tmp); |
219 | 6af0bf9c | bellard | } |
220 | 6af0bf9c | bellard | |
221 | 6af0bf9c | bellard | void do_msubu (void) |
222 | 6af0bf9c | bellard | { |
223 | 6af0bf9c | bellard | uint64_t tmp; |
224 | 6af0bf9c | bellard | |
225 | c570fd16 | ths | tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
226 | 6af0bf9c | bellard | set_HILO(get_HILO() - tmp); |
227 | 6af0bf9c | bellard | } |
228 | e9c71dd1 | ths | |
229 | e9c71dd1 | ths | /* Multiplication variants of the vr54xx. */
|
230 | e9c71dd1 | ths | void do_muls (void) |
231 | e9c71dd1 | ths | { |
232 | e9c71dd1 | ths | set_HI_LOT0(0 - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
|
233 | e9c71dd1 | ths | } |
234 | e9c71dd1 | ths | |
235 | e9c71dd1 | ths | void do_mulsu (void) |
236 | e9c71dd1 | ths | { |
237 | e9c71dd1 | ths | set_HI_LOT0(0 - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
|
238 | e9c71dd1 | ths | } |
239 | e9c71dd1 | ths | |
240 | e9c71dd1 | ths | void do_macc (void) |
241 | e9c71dd1 | ths | { |
242 | e9c71dd1 | ths | set_HI_LOT0(((int64_t)get_HILO()) + ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); |
243 | e9c71dd1 | ths | } |
244 | e9c71dd1 | ths | |
245 | e9c71dd1 | ths | void do_macchi (void) |
246 | e9c71dd1 | ths | { |
247 | e9c71dd1 | ths | set_HIT0_LO(((int64_t)get_HILO()) + ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); |
248 | e9c71dd1 | ths | } |
249 | e9c71dd1 | ths | |
250 | e9c71dd1 | ths | void do_maccu (void) |
251 | e9c71dd1 | ths | { |
252 | e9c71dd1 | ths | set_HI_LOT0(((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); |
253 | e9c71dd1 | ths | } |
254 | e9c71dd1 | ths | |
255 | e9c71dd1 | ths | void do_macchiu (void) |
256 | e9c71dd1 | ths | { |
257 | e9c71dd1 | ths | set_HIT0_LO(((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); |
258 | e9c71dd1 | ths | } |
259 | e9c71dd1 | ths | |
260 | e9c71dd1 | ths | void do_msac (void) |
261 | e9c71dd1 | ths | { |
262 | e9c71dd1 | ths | set_HI_LOT0(((int64_t)get_HILO()) - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); |
263 | e9c71dd1 | ths | } |
264 | e9c71dd1 | ths | |
265 | e9c71dd1 | ths | void do_msachi (void) |
266 | e9c71dd1 | ths | { |
267 | e9c71dd1 | ths | set_HIT0_LO(((int64_t)get_HILO()) - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); |
268 | e9c71dd1 | ths | } |
269 | e9c71dd1 | ths | |
270 | e9c71dd1 | ths | void do_msacu (void) |
271 | e9c71dd1 | ths | { |
272 | e9c71dd1 | ths | set_HI_LOT0(((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); |
273 | e9c71dd1 | ths | } |
274 | e9c71dd1 | ths | |
275 | e9c71dd1 | ths | void do_msachiu (void) |
276 | e9c71dd1 | ths | { |
277 | e9c71dd1 | ths | set_HIT0_LO(((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); |
278 | e9c71dd1 | ths | } |
279 | e9c71dd1 | ths | |
280 | e9c71dd1 | ths | void do_mulhi (void) |
281 | e9c71dd1 | ths | { |
282 | e9c71dd1 | ths | set_HIT0_LO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
283 | e9c71dd1 | ths | } |
284 | e9c71dd1 | ths | |
285 | e9c71dd1 | ths | void do_mulhiu (void) |
286 | e9c71dd1 | ths | { |
287 | e9c71dd1 | ths | set_HIT0_LO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
288 | e9c71dd1 | ths | } |
289 | e9c71dd1 | ths | |
290 | e9c71dd1 | ths | void do_mulshi (void) |
291 | e9c71dd1 | ths | { |
292 | e9c71dd1 | ths | set_HIT0_LO(0 - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
|
293 | e9c71dd1 | ths | } |
294 | e9c71dd1 | ths | |
295 | e9c71dd1 | ths | void do_mulshiu (void) |
296 | e9c71dd1 | ths | { |
297 | e9c71dd1 | ths | set_HIT0_LO(0 - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
|
298 | e9c71dd1 | ths | } |
299 | e9c71dd1 | ths | #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
300 | 6af0bf9c | bellard | |
301 | 80c27194 | ths | #if HOST_LONG_BITS < 64 |
302 | 80c27194 | ths | void do_div (void) |
303 | 80c27194 | ths | { |
304 | 80c27194 | ths | /* 64bit datatypes because we may see overflow/underflow. */
|
305 | 80c27194 | ths | if (T1 != 0) { |
306 | ead9360e | ths | env->LO[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 / (int32_t)T1);
|
307 | ead9360e | ths | env->HI[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 % (int32_t)T1);
|
308 | 80c27194 | ths | } |
309 | 80c27194 | ths | } |
310 | 80c27194 | ths | #endif
|
311 | 80c27194 | ths | |
312 | d26bc211 | ths | #if defined(TARGET_MIPS64)
|
313 | c570fd16 | ths | void do_ddiv (void) |
314 | c570fd16 | ths | { |
315 | c570fd16 | ths | if (T1 != 0) { |
316 | 306ab3e8 | ths | int64_t arg0 = (int64_t)T0; |
317 | 306ab3e8 | ths | int64_t arg1 = (int64_t)T1; |
318 | 306ab3e8 | ths | if (arg0 == ((int64_t)-1 << 63) && arg1 == (int64_t)-1) { |
319 | 306ab3e8 | ths | env->LO[0][env->current_tc] = arg0;
|
320 | 306ab3e8 | ths | env->HI[0][env->current_tc] = 0; |
321 | 306ab3e8 | ths | } else {
|
322 | 306ab3e8 | ths | lldiv_t res = lldiv(arg0, arg1); |
323 | 306ab3e8 | ths | env->LO[0][env->current_tc] = res.quot;
|
324 | 306ab3e8 | ths | env->HI[0][env->current_tc] = res.rem;
|
325 | 306ab3e8 | ths | } |
326 | c570fd16 | ths | } |
327 | c570fd16 | ths | } |
328 | c570fd16 | ths | |
329 | 12a4b2aa | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
|
330 | c570fd16 | ths | void do_ddivu (void) |
331 | c570fd16 | ths | { |
332 | c570fd16 | ths | if (T1 != 0) { |
333 | ead9360e | ths | env->LO[0][env->current_tc] = T0 / T1;
|
334 | ead9360e | ths | env->HI[0][env->current_tc] = T0 % T1;
|
335 | c570fd16 | ths | } |
336 | c570fd16 | ths | } |
337 | c570fd16 | ths | #endif
|
338 | d26bc211 | ths | #endif /* TARGET_MIPS64 */ |
339 | c570fd16 | ths | |
340 | 5fafdf24 | ths | #if defined(CONFIG_USER_ONLY)
|
341 | 873eb012 | ths | void do_mfc0_random (void) |
342 | 048f6b4d | bellard | { |
343 | 873eb012 | ths | cpu_abort(env, "mfc0 random\n");
|
344 | 048f6b4d | bellard | } |
345 | 873eb012 | ths | |
346 | 873eb012 | ths | void do_mfc0_count (void) |
347 | 873eb012 | ths | { |
348 | 873eb012 | ths | cpu_abort(env, "mfc0 count\n");
|
349 | 873eb012 | ths | } |
350 | 873eb012 | ths | |
351 | 8c0fdd85 | ths | void cpu_mips_store_count(CPUState *env, uint32_t value)
|
352 | 048f6b4d | bellard | { |
353 | 8c0fdd85 | ths | cpu_abort(env, "mtc0 count\n");
|
354 | 8c0fdd85 | ths | } |
355 | 8c0fdd85 | ths | |
356 | 8c0fdd85 | ths | void cpu_mips_store_compare(CPUState *env, uint32_t value)
|
357 | 8c0fdd85 | ths | { |
358 | 8c0fdd85 | ths | cpu_abort(env, "mtc0 compare\n");
|
359 | 8c0fdd85 | ths | } |
360 | 8c0fdd85 | ths | |
361 | 42532189 | ths | void cpu_mips_start_count(CPUState *env)
|
362 | 42532189 | ths | { |
363 | 42532189 | ths | cpu_abort(env, "start count\n");
|
364 | 42532189 | ths | } |
365 | 42532189 | ths | |
366 | 42532189 | ths | void cpu_mips_stop_count(CPUState *env)
|
367 | 42532189 | ths | { |
368 | 42532189 | ths | cpu_abort(env, "stop count\n");
|
369 | 42532189 | ths | } |
370 | 42532189 | ths | |
371 | 4de9b249 | ths | void cpu_mips_update_irq(CPUState *env)
|
372 | 4de9b249 | ths | { |
373 | 4de9b249 | ths | cpu_abort(env, "mtc0 status / mtc0 cause\n");
|
374 | 4de9b249 | ths | } |
375 | 4de9b249 | ths | |
376 | 8c0fdd85 | ths | void do_mtc0_status_debug(uint32_t old, uint32_t val)
|
377 | 8c0fdd85 | ths | { |
378 | 7a387fff | ths | cpu_abort(env, "mtc0 status debug\n");
|
379 | 8c0fdd85 | ths | } |
380 | 8c0fdd85 | ths | |
381 | 7a387fff | ths | void do_mtc0_status_irqraise_debug (void) |
382 | 8c0fdd85 | ths | { |
383 | 7a387fff | ths | cpu_abort(env, "mtc0 status irqraise debug\n");
|
384 | 048f6b4d | bellard | } |
385 | 048f6b4d | bellard | |
386 | 8c0fdd85 | ths | void cpu_mips_tlb_flush (CPUState *env, int flush_global) |
387 | 8c0fdd85 | ths | { |
388 | 8c0fdd85 | ths | cpu_abort(env, "mips_tlb_flush\n");
|
389 | 8c0fdd85 | ths | } |
390 | 8c0fdd85 | ths | |
391 | 048f6b4d | bellard | #else
|
392 | 048f6b4d | bellard | |
393 | 6af0bf9c | bellard | /* CP0 helpers */
|
394 | 873eb012 | ths | void do_mfc0_random (void) |
395 | 6af0bf9c | bellard | { |
396 | 5dc4b744 | ths | T0 = (int32_t)cpu_mips_get_random(env); |
397 | 873eb012 | ths | } |
398 | 6af0bf9c | bellard | |
399 | 873eb012 | ths | void do_mfc0_count (void) |
400 | 873eb012 | ths | { |
401 | 5dc4b744 | ths | T0 = (int32_t)cpu_mips_get_count(env); |
402 | 6af0bf9c | bellard | } |
403 | 6af0bf9c | bellard | |
404 | 8c0fdd85 | ths | void do_mtc0_status_debug(uint32_t old, uint32_t val)
|
405 | 6af0bf9c | bellard | { |
406 | f41c52f1 | ths | fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x",
|
407 | f41c52f1 | ths | old, old & env->CP0_Cause & CP0Ca_IP_mask, |
408 | f41c52f1 | ths | val, val & env->CP0_Cause & CP0Ca_IP_mask, |
409 | f41c52f1 | ths | env->CP0_Cause); |
410 | 623a930e | ths | switch (env->hflags & MIPS_HFLAG_KSU) {
|
411 | 623a930e | ths | case MIPS_HFLAG_UM: fputs(", UM\n", logfile); break; |
412 | 623a930e | ths | case MIPS_HFLAG_SM: fputs(", SM\n", logfile); break; |
413 | 623a930e | ths | case MIPS_HFLAG_KM: fputs("\n", logfile); break; |
414 | 623a930e | ths | default: cpu_abort(env, "Invalid MMU mode!\n"); break; |
415 | 623a930e | ths | } |
416 | 8c0fdd85 | ths | } |
417 | 8c0fdd85 | ths | |
418 | 8c0fdd85 | ths | void do_mtc0_status_irqraise_debug(void) |
419 | 8c0fdd85 | ths | { |
420 | 8c0fdd85 | ths | fprintf(logfile, "Raise pending IRQs\n");
|
421 | 6af0bf9c | bellard | } |
422 | 6af0bf9c | bellard | |
423 | 6ea83fed | bellard | void fpu_handle_exception(void) |
424 | 6ea83fed | bellard | { |
425 | 6ea83fed | bellard | #ifdef CONFIG_SOFTFLOAT
|
426 | ead9360e | ths | int flags = get_float_exception_flags(&env->fpu->fp_status);
|
427 | 6ea83fed | bellard | unsigned int cpuflags = 0, enable, cause = 0; |
428 | 6ea83fed | bellard | |
429 | ead9360e | ths | enable = GET_FP_ENABLE(env->fpu->fcr31); |
430 | 6ea83fed | bellard | |
431 | 3b46e624 | ths | /* determine current flags */
|
432 | 6ea83fed | bellard | if (flags & float_flag_invalid) {
|
433 | 6ea83fed | bellard | cpuflags |= FP_INVALID; |
434 | 6ea83fed | bellard | cause |= FP_INVALID & enable; |
435 | 6ea83fed | bellard | } |
436 | 6ea83fed | bellard | if (flags & float_flag_divbyzero) {
|
437 | 3b46e624 | ths | cpuflags |= FP_DIV0; |
438 | 6ea83fed | bellard | cause |= FP_DIV0 & enable; |
439 | 6ea83fed | bellard | } |
440 | 6ea83fed | bellard | if (flags & float_flag_overflow) {
|
441 | 3b46e624 | ths | cpuflags |= FP_OVERFLOW; |
442 | 6ea83fed | bellard | cause |= FP_OVERFLOW & enable; |
443 | 6ea83fed | bellard | } |
444 | 6ea83fed | bellard | if (flags & float_flag_underflow) {
|
445 | 3b46e624 | ths | cpuflags |= FP_UNDERFLOW; |
446 | 6ea83fed | bellard | cause |= FP_UNDERFLOW & enable; |
447 | 6ea83fed | bellard | } |
448 | 6ea83fed | bellard | if (flags & float_flag_inexact) {
|
449 | 5fafdf24 | ths | cpuflags |= FP_INEXACT; |
450 | 6ea83fed | bellard | cause |= FP_INEXACT & enable; |
451 | 6ea83fed | bellard | } |
452 | ead9360e | ths | SET_FP_FLAGS(env->fpu->fcr31, cpuflags); |
453 | ead9360e | ths | SET_FP_CAUSE(env->fpu->fcr31, cause); |
454 | 6ea83fed | bellard | #else
|
455 | ead9360e | ths | SET_FP_FLAGS(env->fpu->fcr31, 0);
|
456 | ead9360e | ths | SET_FP_CAUSE(env->fpu->fcr31, 0);
|
457 | 6ea83fed | bellard | #endif
|
458 | 6ea83fed | bellard | } |
459 | 6ea83fed | bellard | |
460 | 6af0bf9c | bellard | /* TLB management */
|
461 | 814b9a47 | ths | void cpu_mips_tlb_flush (CPUState *env, int flush_global) |
462 | 814b9a47 | ths | { |
463 | 814b9a47 | ths | /* Flush qemu's TLB and discard all shadowed entries. */
|
464 | 814b9a47 | ths | tlb_flush (env, flush_global); |
465 | ead9360e | ths | env->tlb->tlb_in_use = env->tlb->nb_tlb; |
466 | 814b9a47 | ths | } |
467 | 814b9a47 | ths | |
468 | 29929e34 | ths | static void r4k_mips_tlb_flush_extra (CPUState *env, int first) |
469 | 814b9a47 | ths | { |
470 | 814b9a47 | ths | /* Discard entries from env->tlb[first] onwards. */
|
471 | ead9360e | ths | while (env->tlb->tlb_in_use > first) {
|
472 | ead9360e | ths | r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
|
473 | 814b9a47 | ths | } |
474 | 814b9a47 | ths | } |
475 | 814b9a47 | ths | |
476 | 29929e34 | ths | static void r4k_fill_tlb (int idx) |
477 | 6af0bf9c | bellard | { |
478 | 29929e34 | ths | r4k_tlb_t *tlb; |
479 | 6af0bf9c | bellard | |
480 | 6af0bf9c | bellard | /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
|
481 | ead9360e | ths | tlb = &env->tlb->mmu.r4k.tlb[idx]; |
482 | f2e9ebef | ths | tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
|
483 | d26bc211 | ths | #if defined(TARGET_MIPS64)
|
484 | e034e2c3 | ths | tlb->VPN &= env->SEGMask; |
485 | 100ce988 | ths | #endif
|
486 | 98c1b82b | pbrook | tlb->ASID = env->CP0_EntryHi & 0xFF;
|
487 | 3b1c8be4 | ths | tlb->PageMask = env->CP0_PageMask; |
488 | 6af0bf9c | bellard | tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
|
489 | 98c1b82b | pbrook | tlb->V0 = (env->CP0_EntryLo0 & 2) != 0; |
490 | 98c1b82b | pbrook | tlb->D0 = (env->CP0_EntryLo0 & 4) != 0; |
491 | 98c1b82b | pbrook | tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7; |
492 | 6af0bf9c | bellard | tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12; |
493 | 98c1b82b | pbrook | tlb->V1 = (env->CP0_EntryLo1 & 2) != 0; |
494 | 98c1b82b | pbrook | tlb->D1 = (env->CP0_EntryLo1 & 4) != 0; |
495 | 98c1b82b | pbrook | tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7; |
496 | 6af0bf9c | bellard | tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12; |
497 | 6af0bf9c | bellard | } |
498 | 6af0bf9c | bellard | |
499 | 29929e34 | ths | void r4k_do_tlbwi (void) |
500 | 6af0bf9c | bellard | { |
501 | 814b9a47 | ths | /* Discard cached TLB entries. We could avoid doing this if the
|
502 | 814b9a47 | ths | tlbwi is just upgrading access permissions on the current entry;
|
503 | 814b9a47 | ths | that might be a further win. */
|
504 | ead9360e | ths | r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb); |
505 | 814b9a47 | ths | |
506 | ead9360e | ths | r4k_invalidate_tlb(env, env->CP0_Index % env->tlb->nb_tlb, 0);
|
507 | ead9360e | ths | r4k_fill_tlb(env->CP0_Index % env->tlb->nb_tlb); |
508 | 6af0bf9c | bellard | } |
509 | 6af0bf9c | bellard | |
510 | 29929e34 | ths | void r4k_do_tlbwr (void) |
511 | 6af0bf9c | bellard | { |
512 | 6af0bf9c | bellard | int r = cpu_mips_get_random(env);
|
513 | 6af0bf9c | bellard | |
514 | 29929e34 | ths | r4k_invalidate_tlb(env, r, 1);
|
515 | 29929e34 | ths | r4k_fill_tlb(r); |
516 | 6af0bf9c | bellard | } |
517 | 6af0bf9c | bellard | |
518 | 29929e34 | ths | void r4k_do_tlbp (void) |
519 | 6af0bf9c | bellard | { |
520 | 29929e34 | ths | r4k_tlb_t *tlb; |
521 | f2e9ebef | ths | target_ulong mask; |
522 | 6af0bf9c | bellard | target_ulong tag; |
523 | f2e9ebef | ths | target_ulong VPN; |
524 | 6af0bf9c | bellard | uint8_t ASID; |
525 | 6af0bf9c | bellard | int i;
|
526 | 6af0bf9c | bellard | |
527 | 3d9fb9fe | bellard | ASID = env->CP0_EntryHi & 0xFF;
|
528 | ead9360e | ths | for (i = 0; i < env->tlb->nb_tlb; i++) { |
529 | ead9360e | ths | tlb = &env->tlb->mmu.r4k.tlb[i]; |
530 | f2e9ebef | ths | /* 1k pages are not supported. */
|
531 | f2e9ebef | ths | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
|
532 | f2e9ebef | ths | tag = env->CP0_EntryHi & ~mask; |
533 | f2e9ebef | ths | VPN = tlb->VPN & ~mask; |
534 | 6af0bf9c | bellard | /* Check ASID, virtual page number & size */
|
535 | f2e9ebef | ths | if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { |
536 | 6af0bf9c | bellard | /* TLB match */
|
537 | 9c2149c8 | ths | env->CP0_Index = i; |
538 | 6af0bf9c | bellard | break;
|
539 | 6af0bf9c | bellard | } |
540 | 6af0bf9c | bellard | } |
541 | ead9360e | ths | if (i == env->tlb->nb_tlb) {
|
542 | 814b9a47 | ths | /* No match. Discard any shadow entries, if any of them match. */
|
543 | ead9360e | ths | for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
|
544 | ead9360e | ths | tlb = &env->tlb->mmu.r4k.tlb[i]; |
545 | f2e9ebef | ths | /* 1k pages are not supported. */
|
546 | f2e9ebef | ths | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
|
547 | f2e9ebef | ths | tag = env->CP0_EntryHi & ~mask; |
548 | f2e9ebef | ths | VPN = tlb->VPN & ~mask; |
549 | 814b9a47 | ths | /* Check ASID, virtual page number & size */
|
550 | f2e9ebef | ths | if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { |
551 | 29929e34 | ths | r4k_mips_tlb_flush_extra (env, i); |
552 | 814b9a47 | ths | break;
|
553 | 814b9a47 | ths | } |
554 | 814b9a47 | ths | } |
555 | 814b9a47 | ths | |
556 | 9c2149c8 | ths | env->CP0_Index |= 0x80000000;
|
557 | 6af0bf9c | bellard | } |
558 | 6af0bf9c | bellard | } |
559 | 6af0bf9c | bellard | |
560 | 29929e34 | ths | void r4k_do_tlbr (void) |
561 | 6af0bf9c | bellard | { |
562 | 29929e34 | ths | r4k_tlb_t *tlb; |
563 | 09c56b84 | pbrook | uint8_t ASID; |
564 | 6af0bf9c | bellard | |
565 | 09c56b84 | pbrook | ASID = env->CP0_EntryHi & 0xFF;
|
566 | ead9360e | ths | tlb = &env->tlb->mmu.r4k.tlb[env->CP0_Index % env->tlb->nb_tlb]; |
567 | 4ad40f36 | bellard | |
568 | 4ad40f36 | bellard | /* If this will change the current ASID, flush qemu's TLB. */
|
569 | 814b9a47 | ths | if (ASID != tlb->ASID)
|
570 | 814b9a47 | ths | cpu_mips_tlb_flush (env, 1);
|
571 | 814b9a47 | ths | |
572 | ead9360e | ths | r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); |
573 | 4ad40f36 | bellard | |
574 | 6af0bf9c | bellard | env->CP0_EntryHi = tlb->VPN | tlb->ASID; |
575 | 3b1c8be4 | ths | env->CP0_PageMask = tlb->PageMask; |
576 | 7495fd0f | ths | env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) | |
577 | 7495fd0f | ths | (tlb->C0 << 3) | (tlb->PFN[0] >> 6); |
578 | 7495fd0f | ths | env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) | |
579 | 7495fd0f | ths | (tlb->C1 << 3) | (tlb->PFN[1] >> 6); |
580 | 6af0bf9c | bellard | } |
581 | 6af0bf9c | bellard | |
582 | 048f6b4d | bellard | #endif /* !CONFIG_USER_ONLY */ |
583 | 048f6b4d | bellard | |
584 | c570fd16 | ths | void dump_ldst (const unsigned char *func) |
585 | 6af0bf9c | bellard | { |
586 | 6af0bf9c | bellard | if (loglevel)
|
587 | 3594c774 | ths | fprintf(logfile, "%s => " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, T0, T1); |
588 | 6af0bf9c | bellard | } |
589 | 6af0bf9c | bellard | |
590 | 6af0bf9c | bellard | void dump_sc (void) |
591 | 6af0bf9c | bellard | { |
592 | 6af0bf9c | bellard | if (loglevel) {
|
593 | 3594c774 | ths | fprintf(logfile, "%s " TARGET_FMT_lx " at " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", __func__, |
594 | 6af0bf9c | bellard | T1, T0, env->CP0_LLAddr); |
595 | 6af0bf9c | bellard | } |
596 | 6af0bf9c | bellard | } |
597 | 6af0bf9c | bellard | |
598 | f41c52f1 | ths | void debug_pre_eret (void) |
599 | 6af0bf9c | bellard | { |
600 | f41c52f1 | ths | fprintf(logfile, "ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
601 | ead9360e | ths | env->PC[env->current_tc], env->CP0_EPC); |
602 | f41c52f1 | ths | if (env->CP0_Status & (1 << CP0St_ERL)) |
603 | f41c52f1 | ths | fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
|
604 | f41c52f1 | ths | if (env->hflags & MIPS_HFLAG_DM)
|
605 | f41c52f1 | ths | fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
|
606 | f41c52f1 | ths | fputs("\n", logfile);
|
607 | f41c52f1 | ths | } |
608 | f41c52f1 | ths | |
609 | f41c52f1 | ths | void debug_post_eret (void) |
610 | f41c52f1 | ths | { |
611 | 744e0915 | ths | fprintf(logfile, " => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
612 | ead9360e | ths | env->PC[env->current_tc], env->CP0_EPC); |
613 | f41c52f1 | ths | if (env->CP0_Status & (1 << CP0St_ERL)) |
614 | f41c52f1 | ths | fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
|
615 | f41c52f1 | ths | if (env->hflags & MIPS_HFLAG_DM)
|
616 | f41c52f1 | ths | fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
|
617 | 623a930e | ths | switch (env->hflags & MIPS_HFLAG_KSU) {
|
618 | 623a930e | ths | case MIPS_HFLAG_UM: fputs(", UM\n", logfile); break; |
619 | 623a930e | ths | case MIPS_HFLAG_SM: fputs(", SM\n", logfile); break; |
620 | 623a930e | ths | case MIPS_HFLAG_KM: fputs("\n", logfile); break; |
621 | 623a930e | ths | default: cpu_abort(env, "Invalid MMU mode!\n"); break; |
622 | 623a930e | ths | } |
623 | 6af0bf9c | bellard | } |
624 | 6af0bf9c | bellard | |
625 | 6af0bf9c | bellard | void do_pmon (int function) |
626 | 6af0bf9c | bellard | { |
627 | 6af0bf9c | bellard | function /= 2;
|
628 | 6af0bf9c | bellard | switch (function) {
|
629 | 6af0bf9c | bellard | case 2: /* TODO: char inbyte(int waitflag); */ |
630 | ead9360e | ths | if (env->gpr[4][env->current_tc] == 0) |
631 | ead9360e | ths | env->gpr[2][env->current_tc] = -1; |
632 | 6af0bf9c | bellard | /* Fall through */
|
633 | 6af0bf9c | bellard | case 11: /* TODO: char inbyte (void); */ |
634 | ead9360e | ths | env->gpr[2][env->current_tc] = -1; |
635 | 6af0bf9c | bellard | break;
|
636 | 6af0bf9c | bellard | case 3: |
637 | 6af0bf9c | bellard | case 12: |
638 | ead9360e | ths | printf("%c", (char)(env->gpr[4][env->current_tc] & 0xFF)); |
639 | 6af0bf9c | bellard | break;
|
640 | 6af0bf9c | bellard | case 17: |
641 | 6af0bf9c | bellard | break;
|
642 | 6af0bf9c | bellard | case 158: |
643 | 6af0bf9c | bellard | { |
644 | ead9360e | ths | unsigned char *fmt = (void *)(unsigned long)env->gpr[4][env->current_tc]; |
645 | 6af0bf9c | bellard | printf("%s", fmt);
|
646 | 6af0bf9c | bellard | } |
647 | 6af0bf9c | bellard | break;
|
648 | 6af0bf9c | bellard | } |
649 | 6af0bf9c | bellard | } |
650 | e37e863f | bellard | |
651 | 5fafdf24 | ths | #if !defined(CONFIG_USER_ONLY)
|
652 | e37e863f | bellard | |
653 | 4ad40f36 | bellard | static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr); |
654 | 4ad40f36 | bellard | |
655 | e37e863f | bellard | #define MMUSUFFIX _mmu
|
656 | 4ad40f36 | bellard | #define ALIGNED_ONLY
|
657 | e37e863f | bellard | |
658 | e37e863f | bellard | #define SHIFT 0 |
659 | e37e863f | bellard | #include "softmmu_template.h" |
660 | e37e863f | bellard | |
661 | e37e863f | bellard | #define SHIFT 1 |
662 | e37e863f | bellard | #include "softmmu_template.h" |
663 | e37e863f | bellard | |
664 | e37e863f | bellard | #define SHIFT 2 |
665 | e37e863f | bellard | #include "softmmu_template.h" |
666 | e37e863f | bellard | |
667 | e37e863f | bellard | #define SHIFT 3 |
668 | e37e863f | bellard | #include "softmmu_template.h" |
669 | e37e863f | bellard | |
670 | 4ad40f36 | bellard | static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr) |
671 | 4ad40f36 | bellard | { |
672 | 4ad40f36 | bellard | env->CP0_BadVAddr = addr; |
673 | 4ad40f36 | bellard | do_restore_state (retaddr); |
674 | 4ad40f36 | bellard | do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
|
675 | 4ad40f36 | bellard | } |
676 | 4ad40f36 | bellard | |
677 | 6ebbf390 | j_mayer | void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr) |
678 | e37e863f | bellard | { |
679 | e37e863f | bellard | TranslationBlock *tb; |
680 | e37e863f | bellard | CPUState *saved_env; |
681 | e37e863f | bellard | unsigned long pc; |
682 | e37e863f | bellard | int ret;
|
683 | e37e863f | bellard | |
684 | e37e863f | bellard | /* XXX: hack to restore env in all cases, even if not called from
|
685 | e37e863f | bellard | generated code */
|
686 | e37e863f | bellard | saved_env = env; |
687 | e37e863f | bellard | env = cpu_single_env; |
688 | 6ebbf390 | j_mayer | ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
|
689 | e37e863f | bellard | if (ret) {
|
690 | e37e863f | bellard | if (retaddr) {
|
691 | e37e863f | bellard | /* now we have a real cpu fault */
|
692 | e37e863f | bellard | pc = (unsigned long)retaddr; |
693 | e37e863f | bellard | tb = tb_find_pc(pc); |
694 | e37e863f | bellard | if (tb) {
|
695 | e37e863f | bellard | /* the PC is inside the translated code. It means that we have
|
696 | e37e863f | bellard | a virtual CPU fault */
|
697 | e37e863f | bellard | cpu_restore_state(tb, env, pc, NULL);
|
698 | e37e863f | bellard | } |
699 | e37e863f | bellard | } |
700 | e37e863f | bellard | do_raise_exception_err(env->exception_index, env->error_code); |
701 | e37e863f | bellard | } |
702 | e37e863f | bellard | env = saved_env; |
703 | e37e863f | bellard | } |
704 | e37e863f | bellard | |
705 | 647de6ca | ths | void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
706 | 647de6ca | ths | int unused)
|
707 | 647de6ca | ths | { |
708 | 647de6ca | ths | if (is_exec)
|
709 | 647de6ca | ths | do_raise_exception(EXCP_IBE); |
710 | 647de6ca | ths | else
|
711 | 647de6ca | ths | do_raise_exception(EXCP_DBE); |
712 | 647de6ca | ths | } |
713 | e37e863f | bellard | #endif
|
714 | fd4a04eb | ths | |
715 | fd4a04eb | ths | /* Complex FPU operations which may need stack space. */
|
716 | fd4a04eb | ths | |
717 | f090c9d4 | pbrook | #define FLOAT_ONE32 make_float32(0x3f8 << 20) |
718 | f090c9d4 | pbrook | #define FLOAT_ONE64 make_float64(0x3ffULL << 52) |
719 | f090c9d4 | pbrook | #define FLOAT_TWO32 make_float32(1 << 30) |
720 | f090c9d4 | pbrook | #define FLOAT_TWO64 make_float64(1ULL << 62) |
721 | 54454097 | ths | #define FLOAT_QNAN32 0x7fbfffff |
722 | 54454097 | ths | #define FLOAT_QNAN64 0x7ff7ffffffffffffULL |
723 | 54454097 | ths | #define FLOAT_SNAN32 0x7fffffff |
724 | 54454097 | ths | #define FLOAT_SNAN64 0x7fffffffffffffffULL |
725 | 8dfdb87c | ths | |
726 | fd4a04eb | ths | /* convert MIPS rounding mode in FCR31 to IEEE library */
|
727 | fd4a04eb | ths | unsigned int ieee_rm[] = { |
728 | fd4a04eb | ths | float_round_nearest_even, |
729 | fd4a04eb | ths | float_round_to_zero, |
730 | fd4a04eb | ths | float_round_up, |
731 | fd4a04eb | ths | float_round_down |
732 | fd4a04eb | ths | }; |
733 | fd4a04eb | ths | |
734 | fd4a04eb | ths | #define RESTORE_ROUNDING_MODE \
|
735 | ead9360e | ths | set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
|
736 | fd4a04eb | ths | |
737 | ead9360e | ths | void do_cfc1 (int reg) |
738 | fd4a04eb | ths | { |
739 | ead9360e | ths | switch (reg) {
|
740 | ead9360e | ths | case 0: |
741 | ead9360e | ths | T0 = (int32_t)env->fpu->fcr0; |
742 | ead9360e | ths | break;
|
743 | ead9360e | ths | case 25: |
744 | ead9360e | ths | T0 = ((env->fpu->fcr31 >> 24) & 0xfe) | ((env->fpu->fcr31 >> 23) & 0x1); |
745 | ead9360e | ths | break;
|
746 | ead9360e | ths | case 26: |
747 | ead9360e | ths | T0 = env->fpu->fcr31 & 0x0003f07c;
|
748 | ead9360e | ths | break;
|
749 | ead9360e | ths | case 28: |
750 | ead9360e | ths | T0 = (env->fpu->fcr31 & 0x00000f83) | ((env->fpu->fcr31 >> 22) & 0x4); |
751 | ead9360e | ths | break;
|
752 | ead9360e | ths | default:
|
753 | ead9360e | ths | T0 = (int32_t)env->fpu->fcr31; |
754 | ead9360e | ths | break;
|
755 | ead9360e | ths | } |
756 | ead9360e | ths | } |
757 | ead9360e | ths | |
758 | ead9360e | ths | void do_ctc1 (int reg) |
759 | ead9360e | ths | { |
760 | ead9360e | ths | switch(reg) {
|
761 | fd4a04eb | ths | case 25: |
762 | fd4a04eb | ths | if (T0 & 0xffffff00) |
763 | fd4a04eb | ths | return;
|
764 | ead9360e | ths | env->fpu->fcr31 = (env->fpu->fcr31 & 0x017fffff) | ((T0 & 0xfe) << 24) | |
765 | fd4a04eb | ths | ((T0 & 0x1) << 23); |
766 | fd4a04eb | ths | break;
|
767 | fd4a04eb | ths | case 26: |
768 | fd4a04eb | ths | if (T0 & 0x007c0000) |
769 | fd4a04eb | ths | return;
|
770 | ead9360e | ths | env->fpu->fcr31 = (env->fpu->fcr31 & 0xfffc0f83) | (T0 & 0x0003f07c); |
771 | fd4a04eb | ths | break;
|
772 | fd4a04eb | ths | case 28: |
773 | fd4a04eb | ths | if (T0 & 0x007c0000) |
774 | fd4a04eb | ths | return;
|
775 | ead9360e | ths | env->fpu->fcr31 = (env->fpu->fcr31 & 0xfefff07c) | (T0 & 0x00000f83) | |
776 | fd4a04eb | ths | ((T0 & 0x4) << 22); |
777 | fd4a04eb | ths | break;
|
778 | fd4a04eb | ths | case 31: |
779 | fd4a04eb | ths | if (T0 & 0x007c0000) |
780 | fd4a04eb | ths | return;
|
781 | ead9360e | ths | env->fpu->fcr31 = T0; |
782 | fd4a04eb | ths | break;
|
783 | fd4a04eb | ths | default:
|
784 | fd4a04eb | ths | return;
|
785 | fd4a04eb | ths | } |
786 | fd4a04eb | ths | /* set rounding mode */
|
787 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
788 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
789 | ead9360e | ths | if ((GET_FP_ENABLE(env->fpu->fcr31) | 0x20) & GET_FP_CAUSE(env->fpu->fcr31)) |
790 | fd4a04eb | ths | do_raise_exception(EXCP_FPE); |
791 | fd4a04eb | ths | } |
792 | fd4a04eb | ths | |
793 | aa343735 | ths | static always_inline char ieee_ex_to_mips(char xcpt) |
794 | fd4a04eb | ths | { |
795 | fd4a04eb | ths | return (xcpt & float_flag_inexact) >> 5 | |
796 | fd4a04eb | ths | (xcpt & float_flag_underflow) >> 3 |
|
797 | fd4a04eb | ths | (xcpt & float_flag_overflow) >> 1 |
|
798 | fd4a04eb | ths | (xcpt & float_flag_divbyzero) << 1 |
|
799 | fd4a04eb | ths | (xcpt & float_flag_invalid) << 4;
|
800 | fd4a04eb | ths | } |
801 | fd4a04eb | ths | |
802 | aa343735 | ths | static always_inline char mips_ex_to_ieee(char xcpt) |
803 | fd4a04eb | ths | { |
804 | fd4a04eb | ths | return (xcpt & FP_INEXACT) << 5 | |
805 | fd4a04eb | ths | (xcpt & FP_UNDERFLOW) << 3 |
|
806 | fd4a04eb | ths | (xcpt & FP_OVERFLOW) << 1 |
|
807 | fd4a04eb | ths | (xcpt & FP_DIV0) >> 1 |
|
808 | fd4a04eb | ths | (xcpt & FP_INVALID) >> 4;
|
809 | fd4a04eb | ths | } |
810 | fd4a04eb | ths | |
811 | aa343735 | ths | static always_inline void update_fcr31(void) |
812 | fd4a04eb | ths | { |
813 | ead9360e | ths | int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->fpu->fp_status));
|
814 | fd4a04eb | ths | |
815 | ead9360e | ths | SET_FP_CAUSE(env->fpu->fcr31, tmp); |
816 | ead9360e | ths | if (GET_FP_ENABLE(env->fpu->fcr31) & tmp)
|
817 | fd4a04eb | ths | do_raise_exception(EXCP_FPE); |
818 | fd4a04eb | ths | else
|
819 | ead9360e | ths | UPDATE_FP_FLAGS(env->fpu->fcr31, tmp); |
820 | fd4a04eb | ths | } |
821 | fd4a04eb | ths | |
822 | fd4a04eb | ths | #define FLOAT_OP(name, p) void do_float_##name##_##p(void) |
823 | fd4a04eb | ths | |
824 | fd4a04eb | ths | FLOAT_OP(cvtd, s) |
825 | fd4a04eb | ths | { |
826 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
827 | ead9360e | ths | FDT2 = float32_to_float64(FST0, &env->fpu->fp_status); |
828 | fd4a04eb | ths | update_fcr31(); |
829 | fd4a04eb | ths | } |
830 | fd4a04eb | ths | FLOAT_OP(cvtd, w) |
831 | fd4a04eb | ths | { |
832 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
833 | ead9360e | ths | FDT2 = int32_to_float64(WT0, &env->fpu->fp_status); |
834 | fd4a04eb | ths | update_fcr31(); |
835 | fd4a04eb | ths | } |
836 | fd4a04eb | ths | FLOAT_OP(cvtd, l) |
837 | fd4a04eb | ths | { |
838 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
839 | ead9360e | ths | FDT2 = int64_to_float64(DT0, &env->fpu->fp_status); |
840 | fd4a04eb | ths | update_fcr31(); |
841 | fd4a04eb | ths | } |
842 | fd4a04eb | ths | FLOAT_OP(cvtl, d) |
843 | fd4a04eb | ths | { |
844 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
845 | ead9360e | ths | DT2 = float64_to_int64(FDT0, &env->fpu->fp_status); |
846 | fd4a04eb | ths | update_fcr31(); |
847 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
848 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
849 | fd4a04eb | ths | } |
850 | fd4a04eb | ths | FLOAT_OP(cvtl, s) |
851 | fd4a04eb | ths | { |
852 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
853 | ead9360e | ths | DT2 = float32_to_int64(FST0, &env->fpu->fp_status); |
854 | fd4a04eb | ths | update_fcr31(); |
855 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
856 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
857 | fd4a04eb | ths | } |
858 | fd4a04eb | ths | |
859 | fd4a04eb | ths | FLOAT_OP(cvtps, pw) |
860 | fd4a04eb | ths | { |
861 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
862 | ead9360e | ths | FST2 = int32_to_float32(WT0, &env->fpu->fp_status); |
863 | ead9360e | ths | FSTH2 = int32_to_float32(WTH0, &env->fpu->fp_status); |
864 | fd4a04eb | ths | update_fcr31(); |
865 | fd4a04eb | ths | } |
866 | fd4a04eb | ths | FLOAT_OP(cvtpw, ps) |
867 | fd4a04eb | ths | { |
868 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
869 | ead9360e | ths | WT2 = float32_to_int32(FST0, &env->fpu->fp_status); |
870 | ead9360e | ths | WTH2 = float32_to_int32(FSTH0, &env->fpu->fp_status); |
871 | fd4a04eb | ths | update_fcr31(); |
872 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
873 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
874 | fd4a04eb | ths | } |
875 | fd4a04eb | ths | FLOAT_OP(cvts, d) |
876 | fd4a04eb | ths | { |
877 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
878 | ead9360e | ths | FST2 = float64_to_float32(FDT0, &env->fpu->fp_status); |
879 | fd4a04eb | ths | update_fcr31(); |
880 | fd4a04eb | ths | } |
881 | fd4a04eb | ths | FLOAT_OP(cvts, w) |
882 | fd4a04eb | ths | { |
883 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
884 | ead9360e | ths | FST2 = int32_to_float32(WT0, &env->fpu->fp_status); |
885 | fd4a04eb | ths | update_fcr31(); |
886 | fd4a04eb | ths | } |
887 | fd4a04eb | ths | FLOAT_OP(cvts, l) |
888 | fd4a04eb | ths | { |
889 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
890 | ead9360e | ths | FST2 = int64_to_float32(DT0, &env->fpu->fp_status); |
891 | fd4a04eb | ths | update_fcr31(); |
892 | fd4a04eb | ths | } |
893 | fd4a04eb | ths | FLOAT_OP(cvts, pl) |
894 | fd4a04eb | ths | { |
895 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
896 | fd4a04eb | ths | WT2 = WT0; |
897 | fd4a04eb | ths | update_fcr31(); |
898 | fd4a04eb | ths | } |
899 | fd4a04eb | ths | FLOAT_OP(cvts, pu) |
900 | fd4a04eb | ths | { |
901 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
902 | fd4a04eb | ths | WT2 = WTH0; |
903 | fd4a04eb | ths | update_fcr31(); |
904 | fd4a04eb | ths | } |
905 | fd4a04eb | ths | FLOAT_OP(cvtw, s) |
906 | fd4a04eb | ths | { |
907 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
908 | ead9360e | ths | WT2 = float32_to_int32(FST0, &env->fpu->fp_status); |
909 | fd4a04eb | ths | update_fcr31(); |
910 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
911 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
912 | fd4a04eb | ths | } |
913 | fd4a04eb | ths | FLOAT_OP(cvtw, d) |
914 | fd4a04eb | ths | { |
915 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
916 | ead9360e | ths | WT2 = float64_to_int32(FDT0, &env->fpu->fp_status); |
917 | fd4a04eb | ths | update_fcr31(); |
918 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
919 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
920 | fd4a04eb | ths | } |
921 | fd4a04eb | ths | |
922 | fd4a04eb | ths | FLOAT_OP(roundl, d) |
923 | fd4a04eb | ths | { |
924 | ead9360e | ths | set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status); |
925 | ead9360e | ths | DT2 = float64_to_int64(FDT0, &env->fpu->fp_status); |
926 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
927 | fd4a04eb | ths | update_fcr31(); |
928 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
929 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
930 | fd4a04eb | ths | } |
931 | fd4a04eb | ths | FLOAT_OP(roundl, s) |
932 | fd4a04eb | ths | { |
933 | ead9360e | ths | set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status); |
934 | ead9360e | ths | DT2 = float32_to_int64(FST0, &env->fpu->fp_status); |
935 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
936 | fd4a04eb | ths | update_fcr31(); |
937 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
938 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
939 | fd4a04eb | ths | } |
940 | fd4a04eb | ths | FLOAT_OP(roundw, d) |
941 | fd4a04eb | ths | { |
942 | ead9360e | ths | set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status); |
943 | ead9360e | ths | WT2 = float64_to_int32(FDT0, &env->fpu->fp_status); |
944 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
945 | fd4a04eb | ths | update_fcr31(); |
946 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
947 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
948 | fd4a04eb | ths | } |
949 | fd4a04eb | ths | FLOAT_OP(roundw, s) |
950 | fd4a04eb | ths | { |
951 | ead9360e | ths | set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status); |
952 | ead9360e | ths | WT2 = float32_to_int32(FST0, &env->fpu->fp_status); |
953 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
954 | fd4a04eb | ths | update_fcr31(); |
955 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
956 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
957 | fd4a04eb | ths | } |
958 | fd4a04eb | ths | |
959 | fd4a04eb | ths | FLOAT_OP(truncl, d) |
960 | fd4a04eb | ths | { |
961 | ead9360e | ths | DT2 = float64_to_int64_round_to_zero(FDT0, &env->fpu->fp_status); |
962 | fd4a04eb | ths | update_fcr31(); |
963 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
964 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
965 | fd4a04eb | ths | } |
966 | fd4a04eb | ths | FLOAT_OP(truncl, s) |
967 | fd4a04eb | ths | { |
968 | ead9360e | ths | DT2 = float32_to_int64_round_to_zero(FST0, &env->fpu->fp_status); |
969 | fd4a04eb | ths | update_fcr31(); |
970 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
971 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
972 | fd4a04eb | ths | } |
973 | fd4a04eb | ths | FLOAT_OP(truncw, d) |
974 | fd4a04eb | ths | { |
975 | ead9360e | ths | WT2 = float64_to_int32_round_to_zero(FDT0, &env->fpu->fp_status); |
976 | fd4a04eb | ths | update_fcr31(); |
977 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
978 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
979 | fd4a04eb | ths | } |
980 | fd4a04eb | ths | FLOAT_OP(truncw, s) |
981 | fd4a04eb | ths | { |
982 | ead9360e | ths | WT2 = float32_to_int32_round_to_zero(FST0, &env->fpu->fp_status); |
983 | fd4a04eb | ths | update_fcr31(); |
984 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
985 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
986 | fd4a04eb | ths | } |
987 | fd4a04eb | ths | |
988 | fd4a04eb | ths | FLOAT_OP(ceill, d) |
989 | fd4a04eb | ths | { |
990 | ead9360e | ths | set_float_rounding_mode(float_round_up, &env->fpu->fp_status); |
991 | ead9360e | ths | DT2 = float64_to_int64(FDT0, &env->fpu->fp_status); |
992 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
993 | fd4a04eb | ths | update_fcr31(); |
994 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
995 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
996 | fd4a04eb | ths | } |
997 | fd4a04eb | ths | FLOAT_OP(ceill, s) |
998 | fd4a04eb | ths | { |
999 | ead9360e | ths | set_float_rounding_mode(float_round_up, &env->fpu->fp_status); |
1000 | ead9360e | ths | DT2 = float32_to_int64(FST0, &env->fpu->fp_status); |
1001 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
1002 | fd4a04eb | ths | update_fcr31(); |
1003 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
1004 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
1005 | fd4a04eb | ths | } |
1006 | fd4a04eb | ths | FLOAT_OP(ceilw, d) |
1007 | fd4a04eb | ths | { |
1008 | ead9360e | ths | set_float_rounding_mode(float_round_up, &env->fpu->fp_status); |
1009 | ead9360e | ths | WT2 = float64_to_int32(FDT0, &env->fpu->fp_status); |
1010 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
1011 | fd4a04eb | ths | update_fcr31(); |
1012 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
1013 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
1014 | fd4a04eb | ths | } |
1015 | fd4a04eb | ths | FLOAT_OP(ceilw, s) |
1016 | fd4a04eb | ths | { |
1017 | ead9360e | ths | set_float_rounding_mode(float_round_up, &env->fpu->fp_status); |
1018 | ead9360e | ths | WT2 = float32_to_int32(FST0, &env->fpu->fp_status); |
1019 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
1020 | fd4a04eb | ths | update_fcr31(); |
1021 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
1022 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
1023 | fd4a04eb | ths | } |
1024 | fd4a04eb | ths | |
1025 | fd4a04eb | ths | FLOAT_OP(floorl, d) |
1026 | fd4a04eb | ths | { |
1027 | ead9360e | ths | set_float_rounding_mode(float_round_down, &env->fpu->fp_status); |
1028 | ead9360e | ths | DT2 = float64_to_int64(FDT0, &env->fpu->fp_status); |
1029 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
1030 | fd4a04eb | ths | update_fcr31(); |
1031 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
1032 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
1033 | fd4a04eb | ths | } |
1034 | fd4a04eb | ths | FLOAT_OP(floorl, s) |
1035 | fd4a04eb | ths | { |
1036 | ead9360e | ths | set_float_rounding_mode(float_round_down, &env->fpu->fp_status); |
1037 | ead9360e | ths | DT2 = float32_to_int64(FST0, &env->fpu->fp_status); |
1038 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
1039 | fd4a04eb | ths | update_fcr31(); |
1040 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
1041 | 54454097 | ths | DT2 = FLOAT_SNAN64; |
1042 | fd4a04eb | ths | } |
1043 | fd4a04eb | ths | FLOAT_OP(floorw, d) |
1044 | fd4a04eb | ths | { |
1045 | ead9360e | ths | set_float_rounding_mode(float_round_down, &env->fpu->fp_status); |
1046 | ead9360e | ths | WT2 = float64_to_int32(FDT0, &env->fpu->fp_status); |
1047 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
1048 | fd4a04eb | ths | update_fcr31(); |
1049 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
1050 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
1051 | fd4a04eb | ths | } |
1052 | fd4a04eb | ths | FLOAT_OP(floorw, s) |
1053 | fd4a04eb | ths | { |
1054 | ead9360e | ths | set_float_rounding_mode(float_round_down, &env->fpu->fp_status); |
1055 | ead9360e | ths | WT2 = float32_to_int32(FST0, &env->fpu->fp_status); |
1056 | fd4a04eb | ths | RESTORE_ROUNDING_MODE; |
1057 | fd4a04eb | ths | update_fcr31(); |
1058 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
1059 | 54454097 | ths | WT2 = FLOAT_SNAN32; |
1060 | fd4a04eb | ths | } |
1061 | fd4a04eb | ths | |
1062 | 8dfdb87c | ths | /* MIPS specific unary operations */
|
1063 | 8dfdb87c | ths | FLOAT_OP(recip, d) |
1064 | 8dfdb87c | ths | { |
1065 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1066 | ead9360e | ths | FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status); |
1067 | 8dfdb87c | ths | update_fcr31(); |
1068 | 8dfdb87c | ths | } |
1069 | 8dfdb87c | ths | FLOAT_OP(recip, s) |
1070 | 8dfdb87c | ths | { |
1071 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1072 | ead9360e | ths | FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status); |
1073 | 8dfdb87c | ths | update_fcr31(); |
1074 | 57fa1fb3 | ths | } |
1075 | 57fa1fb3 | ths | |
1076 | 8dfdb87c | ths | FLOAT_OP(rsqrt, d) |
1077 | 8dfdb87c | ths | { |
1078 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1079 | ead9360e | ths | FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status); |
1080 | ead9360e | ths | FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status); |
1081 | 8dfdb87c | ths | update_fcr31(); |
1082 | 8dfdb87c | ths | } |
1083 | 8dfdb87c | ths | FLOAT_OP(rsqrt, s) |
1084 | 8dfdb87c | ths | { |
1085 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1086 | ead9360e | ths | FST2 = float32_sqrt(FST0, &env->fpu->fp_status); |
1087 | ead9360e | ths | FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status); |
1088 | 8dfdb87c | ths | update_fcr31(); |
1089 | 8dfdb87c | ths | } |
1090 | 8dfdb87c | ths | |
1091 | 8dfdb87c | ths | FLOAT_OP(recip1, d) |
1092 | 8dfdb87c | ths | { |
1093 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1094 | ead9360e | ths | FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status); |
1095 | 8dfdb87c | ths | update_fcr31(); |
1096 | 8dfdb87c | ths | } |
1097 | 8dfdb87c | ths | FLOAT_OP(recip1, s) |
1098 | 8dfdb87c | ths | { |
1099 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1100 | ead9360e | ths | FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status); |
1101 | 8dfdb87c | ths | update_fcr31(); |
1102 | 8dfdb87c | ths | } |
1103 | 8dfdb87c | ths | FLOAT_OP(recip1, ps) |
1104 | 8dfdb87c | ths | { |
1105 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1106 | ead9360e | ths | FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status); |
1107 | ead9360e | ths | FSTH2 = float32_div(FLOAT_ONE32, FSTH0, &env->fpu->fp_status); |
1108 | 8dfdb87c | ths | update_fcr31(); |
1109 | 8dfdb87c | ths | } |
1110 | 8dfdb87c | ths | |
1111 | 8dfdb87c | ths | FLOAT_OP(rsqrt1, d) |
1112 | 8dfdb87c | ths | { |
1113 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1114 | ead9360e | ths | FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status); |
1115 | ead9360e | ths | FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status); |
1116 | 8dfdb87c | ths | update_fcr31(); |
1117 | 8dfdb87c | ths | } |
1118 | 8dfdb87c | ths | FLOAT_OP(rsqrt1, s) |
1119 | 8dfdb87c | ths | { |
1120 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1121 | ead9360e | ths | FST2 = float32_sqrt(FST0, &env->fpu->fp_status); |
1122 | ead9360e | ths | FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status); |
1123 | 8dfdb87c | ths | update_fcr31(); |
1124 | 8dfdb87c | ths | } |
1125 | 8dfdb87c | ths | FLOAT_OP(rsqrt1, ps) |
1126 | 8dfdb87c | ths | { |
1127 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1128 | ead9360e | ths | FST2 = float32_sqrt(FST0, &env->fpu->fp_status); |
1129 | ead9360e | ths | FSTH2 = float32_sqrt(FSTH0, &env->fpu->fp_status); |
1130 | ead9360e | ths | FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status); |
1131 | ead9360e | ths | FSTH2 = float32_div(FLOAT_ONE32, FSTH2, &env->fpu->fp_status); |
1132 | 8dfdb87c | ths | update_fcr31(); |
1133 | 57fa1fb3 | ths | } |
1134 | 57fa1fb3 | ths | |
1135 | fd4a04eb | ths | /* binary operations */
|
1136 | fd4a04eb | ths | #define FLOAT_BINOP(name) \
|
1137 | fd4a04eb | ths | FLOAT_OP(name, d) \ |
1138 | fd4a04eb | ths | { \ |
1139 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status); \
|
1140 | ead9360e | ths | FDT2 = float64_ ## name (FDT0, FDT1, &env->fpu->fp_status); \ |
1141 | ead9360e | ths | update_fcr31(); \ |
1142 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
|
1143 | 5747c073 | pbrook | DT2 = FLOAT_QNAN64; \ |
1144 | fd4a04eb | ths | } \ |
1145 | fd4a04eb | ths | FLOAT_OP(name, s) \ |
1146 | fd4a04eb | ths | { \ |
1147 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status); \
|
1148 | ead9360e | ths | FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \ |
1149 | ead9360e | ths | update_fcr31(); \ |
1150 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
|
1151 | 5747c073 | pbrook | WT2 = FLOAT_QNAN32; \ |
1152 | fd4a04eb | ths | } \ |
1153 | fd4a04eb | ths | FLOAT_OP(name, ps) \ |
1154 | fd4a04eb | ths | { \ |
1155 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status); \
|
1156 | ead9360e | ths | FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \ |
1157 | ead9360e | ths | FSTH2 = float32_ ## name (FSTH0, FSTH1, &env->fpu->fp_status); \ |
1158 | fd4a04eb | ths | update_fcr31(); \ |
1159 | ead9360e | ths | if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) { \
|
1160 | 5747c073 | pbrook | WT2 = FLOAT_QNAN32; \ |
1161 | 5747c073 | pbrook | WTH2 = FLOAT_QNAN32; \ |
1162 | 3a5b360d | ths | } \ |
1163 | fd4a04eb | ths | } |
1164 | fd4a04eb | ths | FLOAT_BINOP(add) |
1165 | fd4a04eb | ths | FLOAT_BINOP(sub) |
1166 | fd4a04eb | ths | FLOAT_BINOP(mul) |
1167 | fd4a04eb | ths | FLOAT_BINOP(div) |
1168 | fd4a04eb | ths | #undef FLOAT_BINOP
|
1169 | fd4a04eb | ths | |
1170 | 8dfdb87c | ths | /* MIPS specific binary operations */
|
1171 | 8dfdb87c | ths | FLOAT_OP(recip2, d) |
1172 | 8dfdb87c | ths | { |
1173 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1174 | ead9360e | ths | FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status); |
1175 | 5747c073 | pbrook | FDT2 = float64_chs(float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status)); |
1176 | 8dfdb87c | ths | update_fcr31(); |
1177 | 8dfdb87c | ths | } |
1178 | 8dfdb87c | ths | FLOAT_OP(recip2, s) |
1179 | 8dfdb87c | ths | { |
1180 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1181 | ead9360e | ths | FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status); |
1182 | 5747c073 | pbrook | FST2 = float32_chs(float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status)); |
1183 | 8dfdb87c | ths | update_fcr31(); |
1184 | 8dfdb87c | ths | } |
1185 | 8dfdb87c | ths | FLOAT_OP(recip2, ps) |
1186 | 8dfdb87c | ths | { |
1187 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1188 | ead9360e | ths | FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status); |
1189 | ead9360e | ths | FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status); |
1190 | 5747c073 | pbrook | FST2 = float32_chs(float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status)); |
1191 | 5747c073 | pbrook | FSTH2 = float32_chs(float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status)); |
1192 | 8dfdb87c | ths | update_fcr31(); |
1193 | 8dfdb87c | ths | } |
1194 | 8dfdb87c | ths | |
1195 | 8dfdb87c | ths | FLOAT_OP(rsqrt2, d) |
1196 | 8dfdb87c | ths | { |
1197 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1198 | ead9360e | ths | FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status); |
1199 | ead9360e | ths | FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status); |
1200 | 5747c073 | pbrook | FDT2 = float64_chs(float64_div(FDT2, FLOAT_TWO64, &env->fpu->fp_status)); |
1201 | 8dfdb87c | ths | update_fcr31(); |
1202 | 8dfdb87c | ths | } |
1203 | 8dfdb87c | ths | FLOAT_OP(rsqrt2, s) |
1204 | 8dfdb87c | ths | { |
1205 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1206 | ead9360e | ths | FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status); |
1207 | ead9360e | ths | FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status); |
1208 | 5747c073 | pbrook | FST2 = float32_chs(float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status)); |
1209 | 8dfdb87c | ths | update_fcr31(); |
1210 | 8dfdb87c | ths | } |
1211 | 8dfdb87c | ths | FLOAT_OP(rsqrt2, ps) |
1212 | 8dfdb87c | ths | { |
1213 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1214 | ead9360e | ths | FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status); |
1215 | ead9360e | ths | FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status); |
1216 | ead9360e | ths | FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status); |
1217 | ead9360e | ths | FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status); |
1218 | 5747c073 | pbrook | FST2 = float32_chs(float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status)); |
1219 | 5747c073 | pbrook | FSTH2 = float32_chs(float32_div(FSTH2, FLOAT_TWO32, &env->fpu->fp_status)); |
1220 | 8dfdb87c | ths | update_fcr31(); |
1221 | 57fa1fb3 | ths | } |
1222 | 57fa1fb3 | ths | |
1223 | fd4a04eb | ths | FLOAT_OP(addr, ps) |
1224 | fd4a04eb | ths | { |
1225 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1226 | ead9360e | ths | FST2 = float32_add (FST0, FSTH0, &env->fpu->fp_status); |
1227 | ead9360e | ths | FSTH2 = float32_add (FST1, FSTH1, &env->fpu->fp_status); |
1228 | fd4a04eb | ths | update_fcr31(); |
1229 | fd4a04eb | ths | } |
1230 | fd4a04eb | ths | |
1231 | 57fa1fb3 | ths | FLOAT_OP(mulr, ps) |
1232 | 57fa1fb3 | ths | { |
1233 | ead9360e | ths | set_float_exception_flags(0, &env->fpu->fp_status);
|
1234 | ead9360e | ths | FST2 = float32_mul (FST0, FSTH0, &env->fpu->fp_status); |
1235 | ead9360e | ths | FSTH2 = float32_mul (FST1, FSTH1, &env->fpu->fp_status); |
1236 | 57fa1fb3 | ths | update_fcr31(); |
1237 | 57fa1fb3 | ths | } |
1238 | 57fa1fb3 | ths | |
1239 | 8dfdb87c | ths | /* compare operations */
|
1240 | fd4a04eb | ths | #define FOP_COND_D(op, cond) \
|
1241 | fd4a04eb | ths | void do_cmp_d_ ## op (long cc) \ |
1242 | fd4a04eb | ths | { \ |
1243 | fd4a04eb | ths | int c = cond; \
|
1244 | fd4a04eb | ths | update_fcr31(); \ |
1245 | fd4a04eb | ths | if (c) \
|
1246 | ead9360e | ths | SET_FP_COND(cc, env->fpu); \ |
1247 | fd4a04eb | ths | else \
|
1248 | ead9360e | ths | CLEAR_FP_COND(cc, env->fpu); \ |
1249 | fd4a04eb | ths | } \ |
1250 | fd4a04eb | ths | void do_cmpabs_d_ ## op (long cc) \ |
1251 | fd4a04eb | ths | { \ |
1252 | fd4a04eb | ths | int c; \
|
1253 | 6b5435d7 | ths | FDT0 = float64_abs(FDT0); \ |
1254 | 6b5435d7 | ths | FDT1 = float64_abs(FDT1); \ |
1255 | fd4a04eb | ths | c = cond; \ |
1256 | fd4a04eb | ths | update_fcr31(); \ |
1257 | fd4a04eb | ths | if (c) \
|
1258 | ead9360e | ths | SET_FP_COND(cc, env->fpu); \ |
1259 | fd4a04eb | ths | else \
|
1260 | ead9360e | ths | CLEAR_FP_COND(cc, env->fpu); \ |
1261 | fd4a04eb | ths | } |
1262 | fd4a04eb | ths | |
1263 | fd4a04eb | ths | int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM) |
1264 | fd4a04eb | ths | { |
1265 | fd4a04eb | ths | if (float64_is_signaling_nan(a) ||
|
1266 | fd4a04eb | ths | float64_is_signaling_nan(b) || |
1267 | fd4a04eb | ths | (sig && (float64_is_nan(a) || float64_is_nan(b)))) { |
1268 | fd4a04eb | ths | float_raise(float_flag_invalid, status); |
1269 | fd4a04eb | ths | return 1; |
1270 | fd4a04eb | ths | } else if (float64_is_nan(a) || float64_is_nan(b)) { |
1271 | fd4a04eb | ths | return 1; |
1272 | fd4a04eb | ths | } else {
|
1273 | fd4a04eb | ths | return 0; |
1274 | fd4a04eb | ths | } |
1275 | fd4a04eb | ths | } |
1276 | fd4a04eb | ths | |
1277 | fd4a04eb | ths | /* NOTE: the comma operator will make "cond" to eval to false,
|
1278 | fd4a04eb | ths | * but float*_is_unordered() is still called. */
|
1279 | ead9360e | ths | FOP_COND_D(f, (float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status), 0)) |
1280 | ead9360e | ths | FOP_COND_D(un, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status))
|
1281 | ead9360e | ths | FOP_COND_D(eq, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
|
1282 | ead9360e | ths | FOP_COND_D(ueq, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
|
1283 | ead9360e | ths | FOP_COND_D(olt, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
|
1284 | ead9360e | ths | FOP_COND_D(ult, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
|
1285 | ead9360e | ths | FOP_COND_D(ole, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
|
1286 | ead9360e | ths | FOP_COND_D(ule, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
|
1287 | fd4a04eb | ths | /* NOTE: the comma operator will make "cond" to eval to false,
|
1288 | fd4a04eb | ths | * but float*_is_unordered() is still called. */
|
1289 | ead9360e | ths | FOP_COND_D(sf, (float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status), 0)) |
1290 | ead9360e | ths | FOP_COND_D(ngle,float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status))
|
1291 | ead9360e | ths | FOP_COND_D(seq, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
|
1292 | ead9360e | ths | FOP_COND_D(ngl, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
|
1293 | ead9360e | ths | FOP_COND_D(lt, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
|
1294 | ead9360e | ths | FOP_COND_D(nge, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
|
1295 | ead9360e | ths | FOP_COND_D(le, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
|
1296 | ead9360e | ths | FOP_COND_D(ngt, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
|
1297 | fd4a04eb | ths | |
1298 | fd4a04eb | ths | #define FOP_COND_S(op, cond) \
|
1299 | fd4a04eb | ths | void do_cmp_s_ ## op (long cc) \ |
1300 | fd4a04eb | ths | { \ |
1301 | fd4a04eb | ths | int c = cond; \
|
1302 | fd4a04eb | ths | update_fcr31(); \ |
1303 | fd4a04eb | ths | if (c) \
|
1304 | ead9360e | ths | SET_FP_COND(cc, env->fpu); \ |
1305 | fd4a04eb | ths | else \
|
1306 | ead9360e | ths | CLEAR_FP_COND(cc, env->fpu); \ |
1307 | fd4a04eb | ths | } \ |
1308 | fd4a04eb | ths | void do_cmpabs_s_ ## op (long cc) \ |
1309 | fd4a04eb | ths | { \ |
1310 | fd4a04eb | ths | int c; \
|
1311 | 5747c073 | pbrook | FST0 = float32_abs(FST0); \ |
1312 | 5747c073 | pbrook | FST1 = float32_abs(FST1); \ |
1313 | fd4a04eb | ths | c = cond; \ |
1314 | fd4a04eb | ths | update_fcr31(); \ |
1315 | fd4a04eb | ths | if (c) \
|
1316 | ead9360e | ths | SET_FP_COND(cc, env->fpu); \ |
1317 | fd4a04eb | ths | else \
|
1318 | ead9360e | ths | CLEAR_FP_COND(cc, env->fpu); \ |
1319 | fd4a04eb | ths | } |
1320 | fd4a04eb | ths | |
1321 | fd4a04eb | ths | flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
|
1322 | fd4a04eb | ths | { |
1323 | fd4a04eb | ths | if (float32_is_signaling_nan(a) ||
|
1324 | fd4a04eb | ths | float32_is_signaling_nan(b) || |
1325 | fd4a04eb | ths | (sig && (float32_is_nan(a) || float32_is_nan(b)))) { |
1326 | fd4a04eb | ths | float_raise(float_flag_invalid, status); |
1327 | fd4a04eb | ths | return 1; |
1328 | fd4a04eb | ths | } else if (float32_is_nan(a) || float32_is_nan(b)) { |
1329 | fd4a04eb | ths | return 1; |
1330 | fd4a04eb | ths | } else {
|
1331 | fd4a04eb | ths | return 0; |
1332 | fd4a04eb | ths | } |
1333 | fd4a04eb | ths | } |
1334 | fd4a04eb | ths | |
1335 | fd4a04eb | ths | /* NOTE: the comma operator will make "cond" to eval to false,
|
1336 | fd4a04eb | ths | * but float*_is_unordered() is still called. */
|
1337 | ead9360e | ths | FOP_COND_S(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0)) |
1338 | ead9360e | ths | FOP_COND_S(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status))
|
1339 | ead9360e | ths | FOP_COND_S(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
|
1340 | ead9360e | ths | FOP_COND_S(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
|
1341 | ead9360e | ths | FOP_COND_S(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
|
1342 | ead9360e | ths | FOP_COND_S(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
|
1343 | ead9360e | ths | FOP_COND_S(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
|
1344 | ead9360e | ths | FOP_COND_S(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
|
1345 | fd4a04eb | ths | /* NOTE: the comma operator will make "cond" to eval to false,
|
1346 | fd4a04eb | ths | * but float*_is_unordered() is still called. */
|
1347 | ead9360e | ths | FOP_COND_S(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0)) |
1348 | ead9360e | ths | FOP_COND_S(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status))
|
1349 | ead9360e | ths | FOP_COND_S(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
|
1350 | ead9360e | ths | FOP_COND_S(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
|
1351 | ead9360e | ths | FOP_COND_S(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
|
1352 | ead9360e | ths | FOP_COND_S(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
|
1353 | ead9360e | ths | FOP_COND_S(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
|
1354 | ead9360e | ths | FOP_COND_S(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
|
1355 | fd4a04eb | ths | |
1356 | fd4a04eb | ths | #define FOP_COND_PS(op, condl, condh) \
|
1357 | fd4a04eb | ths | void do_cmp_ps_ ## op (long cc) \ |
1358 | fd4a04eb | ths | { \ |
1359 | fd4a04eb | ths | int cl = condl; \
|
1360 | fd4a04eb | ths | int ch = condh; \
|
1361 | fd4a04eb | ths | update_fcr31(); \ |
1362 | fd4a04eb | ths | if (cl) \
|
1363 | ead9360e | ths | SET_FP_COND(cc, env->fpu); \ |
1364 | fd4a04eb | ths | else \
|
1365 | ead9360e | ths | CLEAR_FP_COND(cc, env->fpu); \ |
1366 | fd4a04eb | ths | if (ch) \
|
1367 | ead9360e | ths | SET_FP_COND(cc + 1, env->fpu); \
|
1368 | fd4a04eb | ths | else \
|
1369 | ead9360e | ths | CLEAR_FP_COND(cc + 1, env->fpu); \
|
1370 | fd4a04eb | ths | } \ |
1371 | fd4a04eb | ths | void do_cmpabs_ps_ ## op (long cc) \ |
1372 | fd4a04eb | ths | { \ |
1373 | fd4a04eb | ths | int cl, ch; \
|
1374 | 5747c073 | pbrook | FST0 = float32_abs(FST0); \ |
1375 | 5747c073 | pbrook | FSTH0 = float32_abs(FSTH0); \ |
1376 | 5747c073 | pbrook | FST1 = float32_abs(FST1); \ |
1377 | 5747c073 | pbrook | FSTH1 = float32_abs(FSTH1); \ |
1378 | fd4a04eb | ths | cl = condl; \ |
1379 | fd4a04eb | ths | ch = condh; \ |
1380 | fd4a04eb | ths | update_fcr31(); \ |
1381 | fd4a04eb | ths | if (cl) \
|
1382 | ead9360e | ths | SET_FP_COND(cc, env->fpu); \ |
1383 | fd4a04eb | ths | else \
|
1384 | ead9360e | ths | CLEAR_FP_COND(cc, env->fpu); \ |
1385 | fd4a04eb | ths | if (ch) \
|
1386 | ead9360e | ths | SET_FP_COND(cc + 1, env->fpu); \
|
1387 | fd4a04eb | ths | else \
|
1388 | ead9360e | ths | CLEAR_FP_COND(cc + 1, env->fpu); \
|
1389 | fd4a04eb | ths | } |
1390 | fd4a04eb | ths | |
1391 | fd4a04eb | ths | /* NOTE: the comma operator will make "cond" to eval to false,
|
1392 | fd4a04eb | ths | * but float*_is_unordered() is still called. */
|
1393 | ead9360e | ths | FOP_COND_PS(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0), |
1394 | ead9360e | ths | (float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status), 0)) |
1395 | ead9360e | ths | FOP_COND_PS(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status),
|
1396 | ead9360e | ths | float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status))
|
1397 | ead9360e | ths | FOP_COND_PS(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status),
|
1398 | ead9360e | ths | !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
|
1399 | ead9360e | ths | FOP_COND_PS(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status),
|
1400 | ead9360e | ths | float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
|
1401 | ead9360e | ths | FOP_COND_PS(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status),
|
1402 | ead9360e | ths | !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
|
1403 | ead9360e | ths | FOP_COND_PS(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status),
|
1404 | ead9360e | ths | float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
|
1405 | ead9360e | ths | FOP_COND_PS(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status),
|
1406 | ead9360e | ths | !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
|
1407 | ead9360e | ths | FOP_COND_PS(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status),
|
1408 | ead9360e | ths | float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
|
1409 | fd4a04eb | ths | /* NOTE: the comma operator will make "cond" to eval to false,
|
1410 | fd4a04eb | ths | * but float*_is_unordered() is still called. */
|
1411 | ead9360e | ths | FOP_COND_PS(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0), |
1412 | ead9360e | ths | (float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status), 0)) |
1413 | ead9360e | ths | FOP_COND_PS(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status),
|
1414 | ead9360e | ths | float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status))
|
1415 | ead9360e | ths | FOP_COND_PS(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status),
|
1416 | ead9360e | ths | !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
|
1417 | ead9360e | ths | FOP_COND_PS(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status),
|
1418 | ead9360e | ths | float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
|
1419 | ead9360e | ths | FOP_COND_PS(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status),
|
1420 | ead9360e | ths | !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
|
1421 | ead9360e | ths | FOP_COND_PS(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status),
|
1422 | ead9360e | ths | float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
|
1423 | ead9360e | ths | FOP_COND_PS(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status),
|
1424 | ead9360e | ths | !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
|
1425 | ead9360e | ths | FOP_COND_PS(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status),
|
1426 | ead9360e | ths | float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status)) |