root / target-mips / op_mem.c @ 6b5435d7
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1 | 6af0bf9c | bellard | /*
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2 | 6af0bf9c | bellard | * MIPS emulation memory micro-operations for qemu.
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3 | 5fafdf24 | ths | *
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4 | 6af0bf9c | bellard | * Copyright (c) 2004-2005 Jocelyn Mayer
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5 | 6af0bf9c | bellard | *
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6 | 6af0bf9c | bellard | * This library is free software; you can redistribute it and/or
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7 | 6af0bf9c | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 6af0bf9c | bellard | * License as published by the Free Software Foundation; either
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9 | 6af0bf9c | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 6af0bf9c | bellard | *
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11 | 6af0bf9c | bellard | * This library is distributed in the hope that it will be useful,
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12 | 6af0bf9c | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 6af0bf9c | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 6af0bf9c | bellard | * Lesser General Public License for more details.
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15 | 6af0bf9c | bellard | *
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16 | 6af0bf9c | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 6af0bf9c | bellard | * License along with this library; if not, write to the Free Software
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18 | 6af0bf9c | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 6af0bf9c | bellard | */
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20 | 6af0bf9c | bellard | |
21 | 6af0bf9c | bellard | /* Standard loads and stores */
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22 | 6af0bf9c | bellard | void glue(op_lb, MEMSUFFIX) (void) |
23 | 6af0bf9c | bellard | { |
24 | 6af0bf9c | bellard | T0 = glue(ldsb, MEMSUFFIX)(T0); |
25 | 8f6f6026 | ths | FORCE_RET(); |
26 | 6af0bf9c | bellard | } |
27 | 6af0bf9c | bellard | |
28 | 6af0bf9c | bellard | void glue(op_lbu, MEMSUFFIX) (void) |
29 | 6af0bf9c | bellard | { |
30 | 6af0bf9c | bellard | T0 = glue(ldub, MEMSUFFIX)(T0); |
31 | 8f6f6026 | ths | FORCE_RET(); |
32 | 6af0bf9c | bellard | } |
33 | 6af0bf9c | bellard | |
34 | 6af0bf9c | bellard | void glue(op_sb, MEMSUFFIX) (void) |
35 | 6af0bf9c | bellard | { |
36 | 6af0bf9c | bellard | glue(stb, MEMSUFFIX)(T0, T1); |
37 | 8f6f6026 | ths | FORCE_RET(); |
38 | 6af0bf9c | bellard | } |
39 | 6af0bf9c | bellard | |
40 | 6af0bf9c | bellard | void glue(op_lh, MEMSUFFIX) (void) |
41 | 6af0bf9c | bellard | { |
42 | 6af0bf9c | bellard | T0 = glue(ldsw, MEMSUFFIX)(T0); |
43 | 8f6f6026 | ths | FORCE_RET(); |
44 | 6af0bf9c | bellard | } |
45 | 6af0bf9c | bellard | |
46 | 6af0bf9c | bellard | void glue(op_lhu, MEMSUFFIX) (void) |
47 | 6af0bf9c | bellard | { |
48 | 6af0bf9c | bellard | T0 = glue(lduw, MEMSUFFIX)(T0); |
49 | 8f6f6026 | ths | FORCE_RET(); |
50 | 6af0bf9c | bellard | } |
51 | 6af0bf9c | bellard | |
52 | 6af0bf9c | bellard | void glue(op_sh, MEMSUFFIX) (void) |
53 | 6af0bf9c | bellard | { |
54 | 6af0bf9c | bellard | glue(stw, MEMSUFFIX)(T0, T1); |
55 | 8f6f6026 | ths | FORCE_RET(); |
56 | 6af0bf9c | bellard | } |
57 | 6af0bf9c | bellard | |
58 | 6af0bf9c | bellard | void glue(op_lw, MEMSUFFIX) (void) |
59 | 6af0bf9c | bellard | { |
60 | 6af0bf9c | bellard | T0 = glue(ldl, MEMSUFFIX)(T0); |
61 | 8f6f6026 | ths | FORCE_RET(); |
62 | 6af0bf9c | bellard | } |
63 | 6af0bf9c | bellard | |
64 | d796321b | bellard | void glue(op_lwu, MEMSUFFIX) (void) |
65 | d796321b | bellard | { |
66 | c811cf2c | ths | T0 = (uint32_t)glue(ldl, MEMSUFFIX)(T0); |
67 | 8f6f6026 | ths | FORCE_RET(); |
68 | d796321b | bellard | } |
69 | d796321b | bellard | |
70 | 6af0bf9c | bellard | void glue(op_sw, MEMSUFFIX) (void) |
71 | 6af0bf9c | bellard | { |
72 | 6af0bf9c | bellard | glue(stl, MEMSUFFIX)(T0, T1); |
73 | 8f6f6026 | ths | FORCE_RET(); |
74 | 6af0bf9c | bellard | } |
75 | 6af0bf9c | bellard | |
76 | 4ad40f36 | bellard | /* "half" load and stores. We must do the memory access inline,
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77 | 4ad40f36 | bellard | or fault handling won't work. */
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78 | 4e9f8537 | ths | |
79 | 4e9f8537 | ths | #ifdef TARGET_WORDS_BIGENDIAN
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80 | 4e9f8537 | ths | #define GET_LMASK(v) ((v) & 3) |
81 | 4e9f8537 | ths | #define GET_OFFSET(addr, offset) (addr + (offset))
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82 | 4e9f8537 | ths | #else
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83 | 4e9f8537 | ths | #define GET_LMASK(v) (((v) & 3) ^ 3) |
84 | 4e9f8537 | ths | #define GET_OFFSET(addr, offset) (addr - (offset))
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85 | 4e9f8537 | ths | #endif
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86 | 4e9f8537 | ths | |
87 | 6af0bf9c | bellard | void glue(op_lwl, MEMSUFFIX) (void) |
88 | 6af0bf9c | bellard | { |
89 | 4e9f8537 | ths | target_ulong tmp; |
90 | 4e9f8537 | ths | |
91 | 4e9f8537 | ths | tmp = glue(ldub, MEMSUFFIX)(T0); |
92 | 7d307e9e | ths | T1 = (T1 & 0x00FFFFFF) | (tmp << 24); |
93 | 4e9f8537 | ths | |
94 | 4e9f8537 | ths | if (GET_LMASK(T0) <= 2) { |
95 | 4e9f8537 | ths | tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, 1));
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96 | 4e9f8537 | ths | T1 = (T1 & 0xFF00FFFF) | (tmp << 16); |
97 | 4e9f8537 | ths | } |
98 | 4e9f8537 | ths | |
99 | 4e9f8537 | ths | if (GET_LMASK(T0) <= 1) { |
100 | 4e9f8537 | ths | tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, 2));
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101 | 4e9f8537 | ths | T1 = (T1 & 0xFFFF00FF) | (tmp << 8); |
102 | 4e9f8537 | ths | } |
103 | 4e9f8537 | ths | |
104 | 4e9f8537 | ths | if (GET_LMASK(T0) == 0) { |
105 | 4e9f8537 | ths | tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, 3));
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106 | 4e9f8537 | ths | T1 = (T1 & 0xFFFFFF00) | tmp;
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107 | 4e9f8537 | ths | } |
108 | 7d307e9e | ths | T1 = (int32_t)T1; |
109 | 8f6f6026 | ths | FORCE_RET(); |
110 | 6af0bf9c | bellard | } |
111 | 6af0bf9c | bellard | |
112 | 6af0bf9c | bellard | void glue(op_lwr, MEMSUFFIX) (void) |
113 | 6af0bf9c | bellard | { |
114 | 4e9f8537 | ths | target_ulong tmp; |
115 | 4e9f8537 | ths | |
116 | 4e9f8537 | ths | tmp = glue(ldub, MEMSUFFIX)(T0); |
117 | 4e9f8537 | ths | T1 = (T1 & 0xFFFFFF00) | tmp;
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118 | 4e9f8537 | ths | |
119 | 4e9f8537 | ths | if (GET_LMASK(T0) >= 1) { |
120 | 4e9f8537 | ths | tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, -1));
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121 | 4e9f8537 | ths | T1 = (T1 & 0xFFFF00FF) | (tmp << 8); |
122 | 4e9f8537 | ths | } |
123 | 4e9f8537 | ths | |
124 | 4e9f8537 | ths | if (GET_LMASK(T0) >= 2) { |
125 | 4e9f8537 | ths | tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, -2));
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126 | 4e9f8537 | ths | T1 = (T1 & 0xFF00FFFF) | (tmp << 16); |
127 | 4e9f8537 | ths | } |
128 | 4e9f8537 | ths | |
129 | 4e9f8537 | ths | if (GET_LMASK(T0) == 3) { |
130 | 4e9f8537 | ths | tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, -3));
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131 | 4e9f8537 | ths | T1 = (T1 & 0x00FFFFFF) | (tmp << 24); |
132 | 4e9f8537 | ths | } |
133 | 7d307e9e | ths | T1 = (int32_t)T1; |
134 | 8f6f6026 | ths | FORCE_RET(); |
135 | 6af0bf9c | bellard | } |
136 | 6af0bf9c | bellard | |
137 | 6af0bf9c | bellard | void glue(op_swl, MEMSUFFIX) (void) |
138 | 6af0bf9c | bellard | { |
139 | 4e9f8537 | ths | glue(stb, MEMSUFFIX)(T0, (uint8_t)(T1 >> 24));
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140 | 4e9f8537 | ths | |
141 | 4e9f8537 | ths | if (GET_LMASK(T0) <= 2) |
142 | 4e9f8537 | ths | glue(stb, MEMSUFFIX)(GET_OFFSET(T0, 1), (uint8_t)(T1 >> 16)); |
143 | 4e9f8537 | ths | |
144 | 4e9f8537 | ths | if (GET_LMASK(T0) <= 1) |
145 | 4e9f8537 | ths | glue(stb, MEMSUFFIX)(GET_OFFSET(T0, 2), (uint8_t)(T1 >> 8)); |
146 | 4e9f8537 | ths | |
147 | 4e9f8537 | ths | if (GET_LMASK(T0) == 0) |
148 | 4e9f8537 | ths | glue(stb, MEMSUFFIX)(GET_OFFSET(T0, 3), (uint8_t)T1);
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149 | 4e9f8537 | ths | |
150 | 8f6f6026 | ths | FORCE_RET(); |
151 | 6af0bf9c | bellard | } |
152 | 6af0bf9c | bellard | |
153 | 6af0bf9c | bellard | void glue(op_swr, MEMSUFFIX) (void) |
154 | 6af0bf9c | bellard | { |
155 | 4e9f8537 | ths | glue(stb, MEMSUFFIX)(T0, (uint8_t)T1); |
156 | 4e9f8537 | ths | |
157 | 4e9f8537 | ths | if (GET_LMASK(T0) >= 1) |
158 | 4e9f8537 | ths | glue(stb, MEMSUFFIX)(GET_OFFSET(T0, -1), (uint8_t)(T1 >> 8)); |
159 | 4e9f8537 | ths | |
160 | 4e9f8537 | ths | if (GET_LMASK(T0) >= 2) |
161 | 4e9f8537 | ths | glue(stb, MEMSUFFIX)(GET_OFFSET(T0, -2), (uint8_t)(T1 >> 16)); |
162 | 4e9f8537 | ths | |
163 | 4e9f8537 | ths | if (GET_LMASK(T0) == 3) |
164 | 4e9f8537 | ths | glue(stb, MEMSUFFIX)(GET_OFFSET(T0, -3), (uint8_t)(T1 >> 24)); |
165 | 4e9f8537 | ths | |
166 | 8f6f6026 | ths | FORCE_RET(); |
167 | 6af0bf9c | bellard | } |
168 | 6af0bf9c | bellard | |
169 | 6af0bf9c | bellard | void glue(op_ll, MEMSUFFIX) (void) |
170 | 6af0bf9c | bellard | { |
171 | 6af0bf9c | bellard | T1 = T0; |
172 | 6af0bf9c | bellard | T0 = glue(ldl, MEMSUFFIX)(T0); |
173 | 6af0bf9c | bellard | env->CP0_LLAddr = T1; |
174 | 8f6f6026 | ths | FORCE_RET(); |
175 | 6af0bf9c | bellard | } |
176 | 6af0bf9c | bellard | |
177 | 6af0bf9c | bellard | void glue(op_sc, MEMSUFFIX) (void) |
178 | 6af0bf9c | bellard | { |
179 | 6af0bf9c | bellard | CALL_FROM_TB0(dump_sc); |
180 | 62c5609a | ths | if (T0 & 0x3) { |
181 | 62c5609a | ths | env->CP0_BadVAddr = T0; |
182 | 62c5609a | ths | CALL_FROM_TB1(do_raise_exception, EXCP_AdES); |
183 | 62c5609a | ths | } |
184 | 6af0bf9c | bellard | if (T0 == env->CP0_LLAddr) {
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185 | 6af0bf9c | bellard | glue(stl, MEMSUFFIX)(T0, T1); |
186 | 6af0bf9c | bellard | T0 = 1;
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187 | 6af0bf9c | bellard | } else {
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188 | 6af0bf9c | bellard | T0 = 0;
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189 | 6af0bf9c | bellard | } |
190 | 8f6f6026 | ths | FORCE_RET(); |
191 | 6af0bf9c | bellard | } |
192 | 6ea83fed | bellard | |
193 | d26bc211 | ths | #if defined(TARGET_MIPS64)
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194 | c570fd16 | ths | void glue(op_ld, MEMSUFFIX) (void) |
195 | c570fd16 | ths | { |
196 | c570fd16 | ths | T0 = glue(ldq, MEMSUFFIX)(T0); |
197 | 8f6f6026 | ths | FORCE_RET(); |
198 | c570fd16 | ths | } |
199 | c570fd16 | ths | |
200 | c570fd16 | ths | void glue(op_sd, MEMSUFFIX) (void) |
201 | c570fd16 | ths | { |
202 | c570fd16 | ths | glue(stq, MEMSUFFIX)(T0, T1); |
203 | 8f6f6026 | ths | FORCE_RET(); |
204 | c570fd16 | ths | } |
205 | c570fd16 | ths | |
206 | c570fd16 | ths | /* "half" load and stores. We must do the memory access inline,
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207 | c570fd16 | ths | or fault handling won't work. */
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208 | 4e9f8537 | ths | |
209 | 4e9f8537 | ths | #ifdef TARGET_WORDS_BIGENDIAN
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210 | 4e9f8537 | ths | #define GET_LMASK64(v) ((v) & 7) |
211 | 4e9f8537 | ths | #else
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212 | 4e9f8537 | ths | #define GET_LMASK64(v) (((v) & 7) ^ 7) |
213 | 4e9f8537 | ths | #endif
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214 | 4e9f8537 | ths | |
215 | c570fd16 | ths | void glue(op_ldl, MEMSUFFIX) (void) |
216 | c570fd16 | ths | { |
217 | 4e9f8537 | ths | uint64_t tmp; |
218 | 4e9f8537 | ths | |
219 | 4e9f8537 | ths | tmp = glue(ldub, MEMSUFFIX)(T0); |
220 | 4e9f8537 | ths | T1 = (T1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56); |
221 | 4e9f8537 | ths | |
222 | 4e9f8537 | ths | if (GET_LMASK64(T0) <= 6) { |
223 | 4e9f8537 | ths | tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, 1));
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224 | 4e9f8537 | ths | T1 = (T1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48); |
225 | 4e9f8537 | ths | } |
226 | 4e9f8537 | ths | |
227 | 4e9f8537 | ths | if (GET_LMASK64(T0) <= 5) { |
228 | 4e9f8537 | ths | tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, 2));
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229 | 4e9f8537 | ths | T1 = (T1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40); |
230 | 4e9f8537 | ths | } |
231 | 4e9f8537 | ths | |
232 | 4e9f8537 | ths | if (GET_LMASK64(T0) <= 4) { |
233 | 4e9f8537 | ths | tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, 3));
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234 | 4e9f8537 | ths | T1 = (T1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32); |
235 | 4e9f8537 | ths | } |
236 | 4e9f8537 | ths | |
237 | 4e9f8537 | ths | if (GET_LMASK64(T0) <= 3) { |
238 | 4e9f8537 | ths | tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, 4));
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239 | 4e9f8537 | ths | T1 = (T1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24); |
240 | 4e9f8537 | ths | } |
241 | 4e9f8537 | ths | |
242 | 4e9f8537 | ths | if (GET_LMASK64(T0) <= 2) { |
243 | 4e9f8537 | ths | tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, 5));
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244 | 4e9f8537 | ths | T1 = (T1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16); |
245 | 4e9f8537 | ths | } |
246 | 4e9f8537 | ths | |
247 | 4e9f8537 | ths | if (GET_LMASK64(T0) <= 1) { |
248 | 4e9f8537 | ths | tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, 6));
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249 | 4e9f8537 | ths | T1 = (T1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8); |
250 | 4e9f8537 | ths | } |
251 | 4e9f8537 | ths | |
252 | 4e9f8537 | ths | if (GET_LMASK64(T0) == 0) { |
253 | 4e9f8537 | ths | tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, 7));
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254 | 4e9f8537 | ths | T1 = (T1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
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255 | 4e9f8537 | ths | } |
256 | 4e9f8537 | ths | |
257 | 8f6f6026 | ths | FORCE_RET(); |
258 | c570fd16 | ths | } |
259 | c570fd16 | ths | |
260 | c570fd16 | ths | void glue(op_ldr, MEMSUFFIX) (void) |
261 | c570fd16 | ths | { |
262 | 4e9f8537 | ths | uint64_t tmp; |
263 | 4e9f8537 | ths | |
264 | 4e9f8537 | ths | tmp = glue(ldub, MEMSUFFIX)(T0); |
265 | 4e9f8537 | ths | T1 = (T1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
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266 | 4e9f8537 | ths | |
267 | 4e9f8537 | ths | if (GET_LMASK64(T0) >= 1) { |
268 | 4e9f8537 | ths | tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, -1));
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269 | 4e9f8537 | ths | T1 = (T1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8); |
270 | 4e9f8537 | ths | } |
271 | 4e9f8537 | ths | |
272 | 4e9f8537 | ths | if (GET_LMASK64(T0) >= 2) { |
273 | 4e9f8537 | ths | tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, -2));
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274 | 4e9f8537 | ths | T1 = (T1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16); |
275 | 4e9f8537 | ths | } |
276 | 4e9f8537 | ths | |
277 | 4e9f8537 | ths | if (GET_LMASK64(T0) >= 3) { |
278 | 4e9f8537 | ths | tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, -3));
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279 | 4e9f8537 | ths | T1 = (T1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24); |
280 | 4e9f8537 | ths | } |
281 | 4e9f8537 | ths | |
282 | 4e9f8537 | ths | if (GET_LMASK64(T0) >= 4) { |
283 | 4e9f8537 | ths | tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, -4));
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284 | 4e9f8537 | ths | T1 = (T1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32); |
285 | 4e9f8537 | ths | } |
286 | 4e9f8537 | ths | |
287 | 4e9f8537 | ths | if (GET_LMASK64(T0) >= 5) { |
288 | 4e9f8537 | ths | tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, -5));
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289 | 4e9f8537 | ths | T1 = (T1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40); |
290 | 4e9f8537 | ths | } |
291 | 4e9f8537 | ths | |
292 | 4e9f8537 | ths | if (GET_LMASK64(T0) >= 6) { |
293 | 4e9f8537 | ths | tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, -6));
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294 | 4e9f8537 | ths | T1 = (T1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48); |
295 | 4e9f8537 | ths | } |
296 | 4e9f8537 | ths | |
297 | 4e9f8537 | ths | if (GET_LMASK64(T0) == 7) { |
298 | 4e9f8537 | ths | tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, -7));
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299 | 4e9f8537 | ths | T1 = (T1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56); |
300 | 4e9f8537 | ths | } |
301 | 4e9f8537 | ths | |
302 | 8f6f6026 | ths | FORCE_RET(); |
303 | c570fd16 | ths | } |
304 | c570fd16 | ths | |
305 | c570fd16 | ths | void glue(op_sdl, MEMSUFFIX) (void) |
306 | c570fd16 | ths | { |
307 | 4e9f8537 | ths | glue(stb, MEMSUFFIX)(T0, (uint8_t)(T1 >> 56));
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308 | 4e9f8537 | ths | |
309 | 4e9f8537 | ths | if (GET_LMASK64(T0) <= 6) |
310 | 4e9f8537 | ths | glue(stb, MEMSUFFIX)(GET_OFFSET(T0, 1), (uint8_t)(T1 >> 48)); |
311 | 4e9f8537 | ths | |
312 | 4e9f8537 | ths | if (GET_LMASK64(T0) <= 5) |
313 | 4e9f8537 | ths | glue(stb, MEMSUFFIX)(GET_OFFSET(T0, 2), (uint8_t)(T1 >> 40)); |
314 | 4e9f8537 | ths | |
315 | 4e9f8537 | ths | if (GET_LMASK64(T0) <= 4) |
316 | 4e9f8537 | ths | glue(stb, MEMSUFFIX)(GET_OFFSET(T0, 3), (uint8_t)(T1 >> 32)); |
317 | 4e9f8537 | ths | |
318 | 4e9f8537 | ths | if (GET_LMASK64(T0) <= 3) |
319 | 4e9f8537 | ths | glue(stb, MEMSUFFIX)(GET_OFFSET(T0, 4), (uint8_t)(T1 >> 24)); |
320 | 4e9f8537 | ths | |
321 | 4e9f8537 | ths | if (GET_LMASK64(T0) <= 2) |
322 | 4e9f8537 | ths | glue(stb, MEMSUFFIX)(GET_OFFSET(T0, 5), (uint8_t)(T1 >> 16)); |
323 | 4e9f8537 | ths | |
324 | 4e9f8537 | ths | if (GET_LMASK64(T0) <= 1) |
325 | 4e9f8537 | ths | glue(stb, MEMSUFFIX)(GET_OFFSET(T0, 6), (uint8_t)(T1 >> 8)); |
326 | 4e9f8537 | ths | |
327 | 4e9f8537 | ths | if (GET_LMASK64(T0) <= 0) |
328 | 4e9f8537 | ths | glue(stb, MEMSUFFIX)(GET_OFFSET(T0, 7), (uint8_t)T1);
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329 | 4e9f8537 | ths | |
330 | 8f6f6026 | ths | FORCE_RET(); |
331 | c570fd16 | ths | } |
332 | c570fd16 | ths | |
333 | c570fd16 | ths | void glue(op_sdr, MEMSUFFIX) (void) |
334 | c570fd16 | ths | { |
335 | 4e9f8537 | ths | glue(stb, MEMSUFFIX)(T0, (uint8_t)T1); |
336 | 4e9f8537 | ths | |
337 | 4e9f8537 | ths | if (GET_LMASK64(T0) >= 1) |
338 | 4e9f8537 | ths | glue(stb, MEMSUFFIX)(GET_OFFSET(T0, -1), (uint8_t)(T1 >> 8)); |
339 | 4e9f8537 | ths | |
340 | 4e9f8537 | ths | if (GET_LMASK64(T0) >= 2) |
341 | 4e9f8537 | ths | glue(stb, MEMSUFFIX)(GET_OFFSET(T0, -2), (uint8_t)(T1 >> 16)); |
342 | 4e9f8537 | ths | |
343 | 4e9f8537 | ths | if (GET_LMASK64(T0) >= 3) |
344 | 4e9f8537 | ths | glue(stb, MEMSUFFIX)(GET_OFFSET(T0, -3), (uint8_t)(T1 >> 24)); |
345 | 4e9f8537 | ths | |
346 | 4e9f8537 | ths | if (GET_LMASK64(T0) >= 4) |
347 | 4e9f8537 | ths | glue(stb, MEMSUFFIX)(GET_OFFSET(T0, -4), (uint8_t)(T1 >> 32)); |
348 | 4e9f8537 | ths | |
349 | 4e9f8537 | ths | if (GET_LMASK64(T0) >= 5) |
350 | 4e9f8537 | ths | glue(stb, MEMSUFFIX)(GET_OFFSET(T0, -5), (uint8_t)(T1 >> 40)); |
351 | 4e9f8537 | ths | |
352 | 4e9f8537 | ths | if (GET_LMASK64(T0) >= 6) |
353 | 4e9f8537 | ths | glue(stb, MEMSUFFIX)(GET_OFFSET(T0, -6), (uint8_t)(T1 >> 48)); |
354 | 4e9f8537 | ths | |
355 | 4e9f8537 | ths | if (GET_LMASK64(T0) == 7) |
356 | 4e9f8537 | ths | glue(stb, MEMSUFFIX)(GET_OFFSET(T0, -7), (uint8_t)(T1 >> 56)); |
357 | 4e9f8537 | ths | |
358 | 8f6f6026 | ths | FORCE_RET(); |
359 | c570fd16 | ths | } |
360 | c570fd16 | ths | |
361 | c570fd16 | ths | void glue(op_lld, MEMSUFFIX) (void) |
362 | c570fd16 | ths | { |
363 | c570fd16 | ths | T1 = T0; |
364 | c570fd16 | ths | T0 = glue(ldq, MEMSUFFIX)(T0); |
365 | c570fd16 | ths | env->CP0_LLAddr = T1; |
366 | 8f6f6026 | ths | FORCE_RET(); |
367 | c570fd16 | ths | } |
368 | c570fd16 | ths | |
369 | c570fd16 | ths | void glue(op_scd, MEMSUFFIX) (void) |
370 | c570fd16 | ths | { |
371 | c570fd16 | ths | CALL_FROM_TB0(dump_sc); |
372 | 62c5609a | ths | if (T0 & 0x7) { |
373 | 62c5609a | ths | env->CP0_BadVAddr = T0; |
374 | 62c5609a | ths | CALL_FROM_TB1(do_raise_exception, EXCP_AdES); |
375 | 62c5609a | ths | } |
376 | c570fd16 | ths | if (T0 == env->CP0_LLAddr) {
|
377 | c570fd16 | ths | glue(stq, MEMSUFFIX)(T0, T1); |
378 | c570fd16 | ths | T0 = 1;
|
379 | c570fd16 | ths | } else {
|
380 | c570fd16 | ths | T0 = 0;
|
381 | c570fd16 | ths | } |
382 | 8f6f6026 | ths | FORCE_RET(); |
383 | c570fd16 | ths | } |
384 | d26bc211 | ths | #endif /* TARGET_MIPS64 */ |
385 | c570fd16 | ths | |
386 | 6ea83fed | bellard | void glue(op_lwc1, MEMSUFFIX) (void) |
387 | 6ea83fed | bellard | { |
388 | 6ea83fed | bellard | WT0 = glue(ldl, MEMSUFFIX)(T0); |
389 | 8f6f6026 | ths | FORCE_RET(); |
390 | 6ea83fed | bellard | } |
391 | 6ea83fed | bellard | void glue(op_swc1, MEMSUFFIX) (void) |
392 | 6ea83fed | bellard | { |
393 | 6ea83fed | bellard | glue(stl, MEMSUFFIX)(T0, WT0); |
394 | 8f6f6026 | ths | FORCE_RET(); |
395 | 6ea83fed | bellard | } |
396 | 6ea83fed | bellard | void glue(op_ldc1, MEMSUFFIX) (void) |
397 | 6ea83fed | bellard | { |
398 | 6ea83fed | bellard | DT0 = glue(ldq, MEMSUFFIX)(T0); |
399 | 8f6f6026 | ths | FORCE_RET(); |
400 | 6ea83fed | bellard | } |
401 | 6ea83fed | bellard | void glue(op_sdc1, MEMSUFFIX) (void) |
402 | 6ea83fed | bellard | { |
403 | 6ea83fed | bellard | glue(stq, MEMSUFFIX)(T0, DT0); |
404 | 8f6f6026 | ths | FORCE_RET(); |
405 | 6ea83fed | bellard | } |
406 | 5a5012ec | ths | void glue(op_luxc1, MEMSUFFIX) (void) |
407 | 5a5012ec | ths | { |
408 | 93b12ccc | ths | DT0 = glue(ldq, MEMSUFFIX)(T0 & ~0x7);
|
409 | 8f6f6026 | ths | FORCE_RET(); |
410 | 5a5012ec | ths | } |
411 | 5a5012ec | ths | void glue(op_suxc1, MEMSUFFIX) (void) |
412 | 5a5012ec | ths | { |
413 | 93b12ccc | ths | glue(stq, MEMSUFFIX)(T0 & ~0x7, DT0);
|
414 | 8f6f6026 | ths | FORCE_RET(); |
415 | 5a5012ec | ths | } |