Revision 6c009fa4
| b/hw/piix_pci.c | ||
|---|---|---|
| 35 | 35 |
|
| 36 | 36 |
struct PCII440FXState {
|
| 37 | 37 |
PCIDevice dev; |
| 38 |
target_phys_addr_t isa_page_descs[384 / 4]; |
|
| 39 |
uint8_t smm_enabled; |
|
| 38 | 40 |
}; |
| 39 | 41 |
|
| 40 | 42 |
static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val) |
| ... | ... | |
| 61 | 63 |
return (irq_num + slot_addend) & 3; |
| 62 | 64 |
} |
| 63 | 65 |
|
| 64 |
static target_phys_addr_t isa_page_descs[384 / 4]; |
|
| 65 |
static uint8_t smm_enabled; |
|
| 66 | 66 |
static int pci_irq_levels[4]; |
| 67 | 67 |
|
| 68 | 68 |
static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r) |
| ... | ... | |
| 86 | 86 |
/* XXX: should distinguish read/write cases */ |
| 87 | 87 |
for(addr = start; addr < end; addr += 4096) {
|
| 88 | 88 |
cpu_register_physical_memory(addr, 4096, |
| 89 |
isa_page_descs[(addr - 0xa0000) >> 12]); |
|
| 89 |
d->isa_page_descs[(addr - 0xa0000) >> 12]);
|
|
| 90 | 90 |
} |
| 91 | 91 |
break; |
| 92 | 92 |
} |
| ... | ... | |
| 103 | 103 |
update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r); |
| 104 | 104 |
} |
| 105 | 105 |
smram = d->dev.config[0x72]; |
| 106 |
if ((smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
|
|
| 106 |
if ((d->smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
|
|
| 107 | 107 |
cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000); |
| 108 | 108 |
} else {
|
| 109 | 109 |
for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
|
| 110 | 110 |
cpu_register_physical_memory(addr, 4096, |
| 111 |
isa_page_descs[(addr - 0xa0000) >> 12]); |
|
| 111 |
d->isa_page_descs[(addr - 0xa0000) >> 12]);
|
|
| 112 | 112 |
} |
| 113 | 113 |
} |
| 114 | 114 |
} |
| ... | ... | |
| 116 | 116 |
void i440fx_set_smm(PCII440FXState *d, int val) |
| 117 | 117 |
{
|
| 118 | 118 |
val = (val != 0); |
| 119 |
if (smm_enabled != val) {
|
|
| 120 |
smm_enabled = val; |
|
| 119 |
if (d->smm_enabled != val) {
|
|
| 120 |
d->smm_enabled = val;
|
|
| 121 | 121 |
i440fx_update_memory_mappings(d); |
| 122 | 122 |
} |
| 123 | 123 |
} |
| ... | ... | |
| 130 | 130 |
{
|
| 131 | 131 |
int i; |
| 132 | 132 |
for(i = 0; i < 96; i++) {
|
| 133 |
isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000); |
|
| 133 |
d->isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
|
|
| 134 | 134 |
} |
| 135 | 135 |
} |
| 136 | 136 |
|
| ... | ... | |
| 151 | 151 |
int i; |
| 152 | 152 |
|
| 153 | 153 |
pci_device_save(&d->dev, f); |
| 154 |
qemu_put_8s(f, &smm_enabled); |
|
| 154 |
qemu_put_8s(f, &d->smm_enabled);
|
|
| 155 | 155 |
|
| 156 | 156 |
for (i = 0; i < 4; i++) |
| 157 | 157 |
qemu_put_be32(f, pci_irq_levels[i]); |
| ... | ... | |
| 168 | 168 |
if (ret < 0) |
| 169 | 169 |
return ret; |
| 170 | 170 |
i440fx_update_memory_mappings(d); |
| 171 |
qemu_get_8s(f, &smm_enabled); |
|
| 171 |
qemu_get_8s(f, &d->smm_enabled);
|
|
| 172 | 172 |
|
| 173 | 173 |
if (version_id >= 2) |
| 174 | 174 |
for (i = 0; i < 4; i++) |
Also available in: Unified diff