Revision 6c073553
| b/target-sparc/translate.c | ||
|---|---|---|
| 2221 | 2221 |
|
| 2222 | 2222 |
tcg_temp_free_i32(r_tl); |
| 2223 | 2223 |
} |
| 2224 |
|
|
| 2225 |
static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2, |
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| 2226 |
int width, bool cc, bool left) |
|
| 2227 |
{
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|
| 2228 |
TCGv lo1, lo2, t1, t2; |
|
| 2229 |
uint64_t amask, tabl, tabr; |
|
| 2230 |
int shift, imask, omask; |
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| 2231 |
|
|
| 2232 |
if (cc) {
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|
| 2233 |
tcg_gen_mov_tl(cpu_cc_src, s1); |
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| 2234 |
tcg_gen_mov_tl(cpu_cc_src2, s2); |
|
| 2235 |
tcg_gen_sub_tl(cpu_cc_dst, s1, s2); |
|
| 2236 |
tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB); |
|
| 2237 |
dc->cc_op = CC_OP_SUB; |
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| 2238 |
} |
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| 2239 |
|
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| 2240 |
/* Theory of operation: there are two tables, left and right (not to |
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| 2241 |
be confused with the left and right versions of the opcode). These |
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| 2242 |
are indexed by the low 3 bits of the inputs. To make things "easy", |
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| 2243 |
these tables are loaded into two constants, TABL and TABR below. |
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| 2244 |
The operation index = (input & imask) << shift calculates the index |
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| 2245 |
into the constant, while val = (table >> index) & omask calculates |
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| 2246 |
the value we're looking for. */ |
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| 2247 |
switch (width) {
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| 2248 |
case 8: |
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| 2249 |
imask = 0x7; |
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| 2250 |
shift = 3; |
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| 2251 |
omask = 0xff; |
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| 2252 |
if (left) {
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|
| 2253 |
tabl = 0x80c0e0f0f8fcfeffULL; |
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| 2254 |
tabr = 0xff7f3f1f0f070301ULL; |
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| 2255 |
} else {
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| 2256 |
tabl = 0x0103070f1f3f7fffULL; |
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| 2257 |
tabr = 0xfffefcf8f0e0c080ULL; |
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| 2258 |
} |
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| 2259 |
break; |
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| 2260 |
case 16: |
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| 2261 |
imask = 0x6; |
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| 2262 |
shift = 1; |
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| 2263 |
omask = 0xf; |
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| 2264 |
if (left) {
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|
| 2265 |
tabl = 0x8cef; |
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| 2266 |
tabr = 0xf731; |
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| 2267 |
} else {
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|
| 2268 |
tabl = 0x137f; |
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| 2269 |
tabr = 0xfec8; |
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| 2270 |
} |
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| 2271 |
break; |
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| 2272 |
case 32: |
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| 2273 |
imask = 0x4; |
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| 2274 |
shift = 0; |
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| 2275 |
omask = 0x3; |
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| 2276 |
if (left) {
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| 2277 |
tabl = (2 << 2) | 3; |
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| 2278 |
tabr = (3 << 2) | 1; |
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| 2279 |
} else {
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| 2280 |
tabl = (1 << 2) | 3; |
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| 2281 |
tabr = (3 << 2) | 2; |
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| 2282 |
} |
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| 2283 |
break; |
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| 2284 |
default: |
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| 2285 |
abort(); |
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| 2286 |
} |
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| 2287 |
|
|
| 2288 |
lo1 = tcg_temp_new(); |
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| 2289 |
lo2 = tcg_temp_new(); |
|
| 2290 |
tcg_gen_andi_tl(lo1, s1, imask); |
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| 2291 |
tcg_gen_andi_tl(lo2, s2, imask); |
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| 2292 |
tcg_gen_shli_tl(lo1, lo1, shift); |
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| 2293 |
tcg_gen_shli_tl(lo2, lo2, shift); |
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| 2294 |
|
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| 2295 |
t1 = tcg_const_tl(tabl); |
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| 2296 |
t2 = tcg_const_tl(tabr); |
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| 2297 |
tcg_gen_shr_tl(lo1, t1, lo1); |
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| 2298 |
tcg_gen_shr_tl(lo2, t2, lo2); |
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| 2299 |
tcg_gen_andi_tl(dst, lo1, omask); |
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| 2300 |
tcg_gen_andi_tl(lo2, lo2, omask); |
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| 2301 |
|
|
| 2302 |
amask = -8; |
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| 2303 |
if (AM_CHECK(dc)) {
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|
| 2304 |
amask &= 0xffffffffULL; |
|
| 2305 |
} |
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| 2306 |
tcg_gen_andi_tl(s1, s1, amask); |
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| 2307 |
tcg_gen_andi_tl(s2, s2, amask); |
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| 2308 |
|
|
| 2309 |
/* We want to compute |
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| 2310 |
dst = (s1 == s2 ? lo1 : lo1 & lo2). |
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| 2311 |
We've already done dst = lo1, so this reduces to |
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| 2312 |
dst &= (s1 == s2 ? -1 : lo2) |
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| 2313 |
Which we perform by |
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| 2314 |
lo2 |= -(s1 == s2) |
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| 2315 |
dst &= lo2 |
|
| 2316 |
*/ |
|
| 2317 |
tcg_gen_setcond_tl(TCG_COND_EQ, t1, s1, s2); |
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| 2318 |
tcg_gen_neg_tl(t1, t1); |
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| 2319 |
tcg_gen_or_tl(lo2, lo2, t1); |
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| 2320 |
tcg_gen_and_tl(dst, dst, lo2); |
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| 2321 |
|
|
| 2322 |
tcg_temp_free(lo1); |
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| 2323 |
tcg_temp_free(lo2); |
|
| 2324 |
tcg_temp_free(t1); |
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| 2325 |
tcg_temp_free(t2); |
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| 2326 |
} |
|
| 2224 | 2327 |
#endif |
| 2225 | 2328 |
|
| 2226 | 2329 |
#define CHECK_IU_FEATURE(dc, FEATURE) \ |
| ... | ... | |
| 3954 | 4057 |
|
| 3955 | 4058 |
switch (opf) {
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| 3956 | 4059 |
case 0x000: /* VIS I edge8cc */ |
| 4060 |
CHECK_FPU_FEATURE(dc, VIS1); |
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| 4061 |
gen_movl_reg_TN(rs1, cpu_src1); |
|
| 4062 |
gen_movl_reg_TN(rs2, cpu_src2); |
|
| 4063 |
gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 0); |
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| 4064 |
gen_movl_TN_reg(rd, cpu_dst); |
|
| 4065 |
break; |
|
| 3957 | 4066 |
case 0x001: /* VIS II edge8n */ |
| 4067 |
CHECK_FPU_FEATURE(dc, VIS2); |
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| 4068 |
gen_movl_reg_TN(rs1, cpu_src1); |
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| 4069 |
gen_movl_reg_TN(rs2, cpu_src2); |
|
| 4070 |
gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 0); |
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| 4071 |
gen_movl_TN_reg(rd, cpu_dst); |
|
| 4072 |
break; |
|
| 3958 | 4073 |
case 0x002: /* VIS I edge8lcc */ |
| 4074 |
CHECK_FPU_FEATURE(dc, VIS1); |
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| 4075 |
gen_movl_reg_TN(rs1, cpu_src1); |
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| 4076 |
gen_movl_reg_TN(rs2, cpu_src2); |
|
| 4077 |
gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 1); |
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| 4078 |
gen_movl_TN_reg(rd, cpu_dst); |
|
| 4079 |
break; |
|
| 3959 | 4080 |
case 0x003: /* VIS II edge8ln */ |
| 4081 |
CHECK_FPU_FEATURE(dc, VIS2); |
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| 4082 |
gen_movl_reg_TN(rs1, cpu_src1); |
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| 4083 |
gen_movl_reg_TN(rs2, cpu_src2); |
|
| 4084 |
gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 1); |
|
| 4085 |
gen_movl_TN_reg(rd, cpu_dst); |
|
| 4086 |
break; |
|
| 3960 | 4087 |
case 0x004: /* VIS I edge16cc */ |
| 4088 |
CHECK_FPU_FEATURE(dc, VIS1); |
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| 4089 |
gen_movl_reg_TN(rs1, cpu_src1); |
|
| 4090 |
gen_movl_reg_TN(rs2, cpu_src2); |
|
| 4091 |
gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 0); |
|
| 4092 |
gen_movl_TN_reg(rd, cpu_dst); |
|
| 4093 |
break; |
|
| 3961 | 4094 |
case 0x005: /* VIS II edge16n */ |
| 4095 |
CHECK_FPU_FEATURE(dc, VIS2); |
|
| 4096 |
gen_movl_reg_TN(rs1, cpu_src1); |
|
| 4097 |
gen_movl_reg_TN(rs2, cpu_src2); |
|
| 4098 |
gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 0); |
|
| 4099 |
gen_movl_TN_reg(rd, cpu_dst); |
|
| 4100 |
break; |
|
| 3962 | 4101 |
case 0x006: /* VIS I edge16lcc */ |
| 4102 |
CHECK_FPU_FEATURE(dc, VIS1); |
|
| 4103 |
gen_movl_reg_TN(rs1, cpu_src1); |
|
| 4104 |
gen_movl_reg_TN(rs2, cpu_src2); |
|
| 4105 |
gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 1); |
|
| 4106 |
gen_movl_TN_reg(rd, cpu_dst); |
|
| 4107 |
break; |
|
| 3963 | 4108 |
case 0x007: /* VIS II edge16ln */ |
| 4109 |
CHECK_FPU_FEATURE(dc, VIS2); |
|
| 4110 |
gen_movl_reg_TN(rs1, cpu_src1); |
|
| 4111 |
gen_movl_reg_TN(rs2, cpu_src2); |
|
| 4112 |
gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 1); |
|
| 4113 |
gen_movl_TN_reg(rd, cpu_dst); |
|
| 4114 |
break; |
|
| 3964 | 4115 |
case 0x008: /* VIS I edge32cc */ |
| 4116 |
CHECK_FPU_FEATURE(dc, VIS1); |
|
| 4117 |
gen_movl_reg_TN(rs1, cpu_src1); |
|
| 4118 |
gen_movl_reg_TN(rs2, cpu_src2); |
|
| 4119 |
gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 0); |
|
| 4120 |
gen_movl_TN_reg(rd, cpu_dst); |
|
| 4121 |
break; |
|
| 3965 | 4122 |
case 0x009: /* VIS II edge32n */ |
| 4123 |
CHECK_FPU_FEATURE(dc, VIS2); |
|
| 4124 |
gen_movl_reg_TN(rs1, cpu_src1); |
|
| 4125 |
gen_movl_reg_TN(rs2, cpu_src2); |
|
| 4126 |
gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 0); |
|
| 4127 |
gen_movl_TN_reg(rd, cpu_dst); |
|
| 4128 |
break; |
|
| 3966 | 4129 |
case 0x00a: /* VIS I edge32lcc */ |
| 4130 |
CHECK_FPU_FEATURE(dc, VIS1); |
|
| 4131 |
gen_movl_reg_TN(rs1, cpu_src1); |
|
| 4132 |
gen_movl_reg_TN(rs2, cpu_src2); |
|
| 4133 |
gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 1); |
|
| 4134 |
gen_movl_TN_reg(rd, cpu_dst); |
|
| 4135 |
break; |
|
| 3967 | 4136 |
case 0x00b: /* VIS II edge32ln */ |
| 3968 |
// XXX |
|
| 3969 |
goto illegal_insn; |
|
| 4137 |
CHECK_FPU_FEATURE(dc, VIS2); |
|
| 4138 |
gen_movl_reg_TN(rs1, cpu_src1); |
|
| 4139 |
gen_movl_reg_TN(rs2, cpu_src2); |
|
| 4140 |
gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 1); |
|
| 4141 |
gen_movl_TN_reg(rd, cpu_dst); |
|
| 4142 |
break; |
|
| 3970 | 4143 |
case 0x010: /* VIS I array8 */ |
| 3971 | 4144 |
CHECK_FPU_FEATURE(dc, VIS1); |
| 3972 | 4145 |
cpu_src1 = get_src1(insn, cpu_src1); |
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