root / hw / lm32_boards.c @ 6c7796e5
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1 | d821732a | Michael Walle | /*
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2 | d821732a | Michael Walle | * QEMU models for LatticeMico32 uclinux and evr32 boards.
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3 | d821732a | Michael Walle | *
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4 | d821732a | Michael Walle | * Copyright (c) 2010 Michael Walle <michael@walle.cc>
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5 | d821732a | Michael Walle | *
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6 | d821732a | Michael Walle | * This library is free software; you can redistribute it and/or
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7 | d821732a | Michael Walle | * modify it under the terms of the GNU Lesser General Public
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8 | d821732a | Michael Walle | * License as published by the Free Software Foundation; either
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9 | d821732a | Michael Walle | * version 2 of the License, or (at your option) any later version.
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10 | d821732a | Michael Walle | *
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11 | d821732a | Michael Walle | * This library is distributed in the hope that it will be useful,
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12 | d821732a | Michael Walle | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | d821732a | Michael Walle | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | d821732a | Michael Walle | * Lesser General Public License for more details.
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15 | d821732a | Michael Walle | *
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16 | d821732a | Michael Walle | * You should have received a copy of the GNU Lesser General Public
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17 | d821732a | Michael Walle | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | d821732a | Michael Walle | */
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19 | d821732a | Michael Walle | |
20 | d821732a | Michael Walle | #include "sysbus.h" |
21 | d821732a | Michael Walle | #include "hw.h" |
22 | d821732a | Michael Walle | #include "net.h" |
23 | d821732a | Michael Walle | #include "flash.h" |
24 | d821732a | Michael Walle | #include "devices.h" |
25 | d821732a | Michael Walle | #include "boards.h" |
26 | d821732a | Michael Walle | #include "loader.h" |
27 | d821732a | Michael Walle | #include "blockdev.h" |
28 | d821732a | Michael Walle | #include "elf.h" |
29 | d821732a | Michael Walle | #include "lm32_hwsetup.h" |
30 | d821732a | Michael Walle | #include "lm32.h" |
31 | d821732a | Michael Walle | |
32 | d821732a | Michael Walle | typedef struct { |
33 | d821732a | Michael Walle | CPUState *env; |
34 | d821732a | Michael Walle | target_phys_addr_t bootstrap_pc; |
35 | d821732a | Michael Walle | target_phys_addr_t flash_base; |
36 | d821732a | Michael Walle | target_phys_addr_t hwsetup_base; |
37 | d821732a | Michael Walle | target_phys_addr_t initrd_base; |
38 | d821732a | Michael Walle | size_t initrd_size; |
39 | d821732a | Michael Walle | target_phys_addr_t cmdline_base; |
40 | d821732a | Michael Walle | } ResetInfo; |
41 | d821732a | Michael Walle | |
42 | d821732a | Michael Walle | static void cpu_irq_handler(void *opaque, int irq, int level) |
43 | d821732a | Michael Walle | { |
44 | d821732a | Michael Walle | CPUState *env = opaque; |
45 | d821732a | Michael Walle | |
46 | d821732a | Michael Walle | if (level) {
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47 | d821732a | Michael Walle | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
48 | d821732a | Michael Walle | } else {
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49 | d821732a | Michael Walle | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
50 | d821732a | Michael Walle | } |
51 | d821732a | Michael Walle | } |
52 | d821732a | Michael Walle | |
53 | d821732a | Michael Walle | static void main_cpu_reset(void *opaque) |
54 | d821732a | Michael Walle | { |
55 | d821732a | Michael Walle | ResetInfo *reset_info = opaque; |
56 | d821732a | Michael Walle | CPUState *env = reset_info->env; |
57 | d821732a | Michael Walle | |
58 | d821732a | Michael Walle | cpu_reset(env); |
59 | d821732a | Michael Walle | |
60 | d821732a | Michael Walle | /* init defaults */
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61 | d821732a | Michael Walle | env->pc = (uint32_t)reset_info->bootstrap_pc; |
62 | d821732a | Michael Walle | env->regs[R_R1] = (uint32_t)reset_info->hwsetup_base; |
63 | d821732a | Michael Walle | env->regs[R_R2] = (uint32_t)reset_info->cmdline_base; |
64 | d821732a | Michael Walle | env->regs[R_R3] = (uint32_t)reset_info->initrd_base; |
65 | d821732a | Michael Walle | env->regs[R_R4] = (uint32_t)(reset_info->initrd_base + |
66 | d821732a | Michael Walle | reset_info->initrd_size); |
67 | d821732a | Michael Walle | env->eba = reset_info->flash_base; |
68 | d821732a | Michael Walle | env->deba = reset_info->flash_base; |
69 | d821732a | Michael Walle | } |
70 | d821732a | Michael Walle | |
71 | d821732a | Michael Walle | static void lm32_evr_init(ram_addr_t ram_size_not_used, |
72 | d821732a | Michael Walle | const char *boot_device, |
73 | d821732a | Michael Walle | const char *kernel_filename, |
74 | d821732a | Michael Walle | const char *kernel_cmdline, |
75 | d821732a | Michael Walle | const char *initrd_filename, const char *cpu_model) |
76 | d821732a | Michael Walle | { |
77 | d821732a | Michael Walle | CPUState *env; |
78 | d821732a | Michael Walle | DriveInfo *dinfo; |
79 | d821732a | Michael Walle | ram_addr_t phys_ram; |
80 | d821732a | Michael Walle | ram_addr_t phys_flash; |
81 | d821732a | Michael Walle | qemu_irq *cpu_irq, irq[32];
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82 | d821732a | Michael Walle | ResetInfo *reset_info; |
83 | d821732a | Michael Walle | int i;
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84 | d821732a | Michael Walle | |
85 | d821732a | Michael Walle | /* memory map */
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86 | d821732a | Michael Walle | target_phys_addr_t flash_base = 0x04000000;
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87 | d821732a | Michael Walle | size_t flash_sector_size = 256 * 1024; |
88 | d821732a | Michael Walle | size_t flash_size = 32 * 1024 * 1024; |
89 | d821732a | Michael Walle | target_phys_addr_t ram_base = 0x08000000;
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90 | d821732a | Michael Walle | size_t ram_size = 64 * 1024 * 1024; |
91 | d821732a | Michael Walle | target_phys_addr_t timer0_base = 0x80002000;
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92 | d821732a | Michael Walle | target_phys_addr_t uart0_base = 0x80006000;
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93 | d821732a | Michael Walle | target_phys_addr_t timer1_base = 0x8000a000;
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94 | d821732a | Michael Walle | int uart0_irq = 0; |
95 | d821732a | Michael Walle | int timer0_irq = 1; |
96 | d821732a | Michael Walle | int timer1_irq = 3; |
97 | d821732a | Michael Walle | |
98 | d821732a | Michael Walle | reset_info = qemu_mallocz(sizeof(ResetInfo));
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99 | d821732a | Michael Walle | |
100 | d821732a | Michael Walle | if (cpu_model == NULL) { |
101 | d821732a | Michael Walle | cpu_model = "lm32-full";
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102 | d821732a | Michael Walle | } |
103 | d821732a | Michael Walle | env = cpu_init(cpu_model); |
104 | d821732a | Michael Walle | reset_info->env = env; |
105 | d821732a | Michael Walle | |
106 | d821732a | Michael Walle | reset_info->flash_base = flash_base; |
107 | d821732a | Michael Walle | |
108 | d821732a | Michael Walle | phys_ram = qemu_ram_alloc(NULL, "lm32_evr.sdram", ram_size); |
109 | d821732a | Michael Walle | cpu_register_physical_memory(ram_base, ram_size, phys_ram | IO_MEM_RAM); |
110 | d821732a | Michael Walle | |
111 | d821732a | Michael Walle | phys_flash = qemu_ram_alloc(NULL, "lm32_evr.flash", flash_size); |
112 | d821732a | Michael Walle | dinfo = drive_get(IF_PFLASH, 0, 0); |
113 | d821732a | Michael Walle | /* Spansion S29NS128P */
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114 | d821732a | Michael Walle | pflash_cfi02_register(flash_base, phys_flash, |
115 | d821732a | Michael Walle | dinfo ? dinfo->bdrv : NULL, flash_sector_size,
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116 | d821732a | Michael Walle | flash_size / flash_sector_size, 1, 2, |
117 | d821732a | Michael Walle | 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1); |
118 | d821732a | Michael Walle | |
119 | d821732a | Michael Walle | /* create irq lines */
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120 | d821732a | Michael Walle | cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
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121 | d821732a | Michael Walle | env->pic_state = lm32_pic_init(*cpu_irq); |
122 | d821732a | Michael Walle | for (i = 0; i < 32; i++) { |
123 | d821732a | Michael Walle | irq[i] = qdev_get_gpio_in(env->pic_state, i); |
124 | d821732a | Michael Walle | } |
125 | d821732a | Michael Walle | |
126 | d821732a | Michael Walle | sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
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127 | d821732a | Michael Walle | sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
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128 | d821732a | Michael Walle | sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
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129 | d821732a | Michael Walle | |
130 | d821732a | Michael Walle | /* make sure juart isn't the first chardev */
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131 | d821732a | Michael Walle | env->juart_state = lm32_juart_init(); |
132 | d821732a | Michael Walle | |
133 | d821732a | Michael Walle | reset_info->bootstrap_pc = flash_base; |
134 | d821732a | Michael Walle | |
135 | d821732a | Michael Walle | if (kernel_filename) {
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136 | d821732a | Michael Walle | uint64_t entry; |
137 | d821732a | Michael Walle | int kernel_size;
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138 | d821732a | Michael Walle | |
139 | d821732a | Michael Walle | kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL, |
140 | d821732a | Michael Walle | 1, ELF_MACHINE, 0); |
141 | d821732a | Michael Walle | reset_info->bootstrap_pc = entry; |
142 | d821732a | Michael Walle | |
143 | d821732a | Michael Walle | if (kernel_size < 0) { |
144 | d821732a | Michael Walle | kernel_size = load_image_targphys(kernel_filename, ram_base, |
145 | d821732a | Michael Walle | ram_size); |
146 | d821732a | Michael Walle | reset_info->bootstrap_pc = ram_base; |
147 | d821732a | Michael Walle | } |
148 | d821732a | Michael Walle | |
149 | d821732a | Michael Walle | if (kernel_size < 0) { |
150 | d821732a | Michael Walle | fprintf(stderr, "qemu: could not load kernel '%s'\n",
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151 | d821732a | Michael Walle | kernel_filename); |
152 | d821732a | Michael Walle | exit(1);
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153 | d821732a | Michael Walle | } |
154 | d821732a | Michael Walle | } |
155 | d821732a | Michael Walle | |
156 | d821732a | Michael Walle | qemu_register_reset(main_cpu_reset, reset_info); |
157 | d821732a | Michael Walle | } |
158 | d821732a | Michael Walle | |
159 | d821732a | Michael Walle | static void lm32_uclinux_init(ram_addr_t ram_size_not_used, |
160 | d821732a | Michael Walle | const char *boot_device, |
161 | d821732a | Michael Walle | const char *kernel_filename, |
162 | d821732a | Michael Walle | const char *kernel_cmdline, |
163 | d821732a | Michael Walle | const char *initrd_filename, const char *cpu_model) |
164 | d821732a | Michael Walle | { |
165 | d821732a | Michael Walle | CPUState *env; |
166 | d821732a | Michael Walle | DriveInfo *dinfo; |
167 | d821732a | Michael Walle | ram_addr_t phys_ram; |
168 | d821732a | Michael Walle | ram_addr_t phys_flash; |
169 | d821732a | Michael Walle | qemu_irq *cpu_irq, irq[32];
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170 | d821732a | Michael Walle | HWSetup *hw; |
171 | d821732a | Michael Walle | ResetInfo *reset_info; |
172 | d821732a | Michael Walle | int i;
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173 | d821732a | Michael Walle | |
174 | d821732a | Michael Walle | /* memory map */
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175 | d821732a | Michael Walle | target_phys_addr_t flash_base = 0x04000000;
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176 | d821732a | Michael Walle | size_t flash_sector_size = 256 * 1024; |
177 | d821732a | Michael Walle | size_t flash_size = 32 * 1024 * 1024; |
178 | d821732a | Michael Walle | target_phys_addr_t ram_base = 0x08000000;
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179 | d821732a | Michael Walle | size_t ram_size = 64 * 1024 * 1024; |
180 | d821732a | Michael Walle | target_phys_addr_t uart0_base = 0x80000000;
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181 | d821732a | Michael Walle | target_phys_addr_t timer0_base = 0x80002000;
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182 | d821732a | Michael Walle | target_phys_addr_t timer1_base = 0x80010000;
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183 | d821732a | Michael Walle | target_phys_addr_t timer2_base = 0x80012000;
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184 | d821732a | Michael Walle | int uart0_irq = 0; |
185 | d821732a | Michael Walle | int timer0_irq = 1; |
186 | d821732a | Michael Walle | int timer1_irq = 20; |
187 | d821732a | Michael Walle | int timer2_irq = 21; |
188 | d821732a | Michael Walle | target_phys_addr_t hwsetup_base = 0x0bffe000;
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189 | d821732a | Michael Walle | target_phys_addr_t cmdline_base = 0x0bfff000;
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190 | d821732a | Michael Walle | target_phys_addr_t initrd_base = 0x08400000;
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191 | d821732a | Michael Walle | size_t initrd_max = 0x01000000;
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192 | d821732a | Michael Walle | |
193 | d821732a | Michael Walle | reset_info = qemu_mallocz(sizeof(ResetInfo));
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194 | d821732a | Michael Walle | |
195 | d821732a | Michael Walle | if (cpu_model == NULL) { |
196 | d821732a | Michael Walle | cpu_model = "lm32-full";
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197 | d821732a | Michael Walle | } |
198 | d821732a | Michael Walle | env = cpu_init(cpu_model); |
199 | d821732a | Michael Walle | reset_info->env = env; |
200 | d821732a | Michael Walle | |
201 | d821732a | Michael Walle | reset_info->flash_base = flash_base; |
202 | d821732a | Michael Walle | |
203 | d821732a | Michael Walle | phys_ram = qemu_ram_alloc(NULL, "lm32_uclinux.sdram", ram_size); |
204 | d821732a | Michael Walle | cpu_register_physical_memory(ram_base, ram_size, phys_ram | IO_MEM_RAM); |
205 | d821732a | Michael Walle | |
206 | d821732a | Michael Walle | phys_flash = qemu_ram_alloc(NULL, "lm32_uclinux.flash", flash_size); |
207 | d821732a | Michael Walle | dinfo = drive_get(IF_PFLASH, 0, 0); |
208 | d821732a | Michael Walle | /* Spansion S29NS128P */
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209 | d821732a | Michael Walle | pflash_cfi02_register(flash_base, phys_flash, |
210 | d821732a | Michael Walle | dinfo ? dinfo->bdrv : NULL, flash_sector_size,
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211 | d821732a | Michael Walle | flash_size / flash_sector_size, 1, 2, |
212 | d821732a | Michael Walle | 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1); |
213 | d821732a | Michael Walle | |
214 | d821732a | Michael Walle | /* create irq lines */
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215 | d821732a | Michael Walle | cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
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216 | d821732a | Michael Walle | env->pic_state = lm32_pic_init(*cpu_irq); |
217 | d821732a | Michael Walle | for (i = 0; i < 32; i++) { |
218 | d821732a | Michael Walle | irq[i] = qdev_get_gpio_in(env->pic_state, i); |
219 | d821732a | Michael Walle | } |
220 | d821732a | Michael Walle | |
221 | d821732a | Michael Walle | sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
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222 | d821732a | Michael Walle | sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
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223 | d821732a | Michael Walle | sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
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224 | d821732a | Michael Walle | sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]);
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225 | d821732a | Michael Walle | |
226 | d821732a | Michael Walle | /* make sure juart isn't the first chardev */
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227 | d821732a | Michael Walle | env->juart_state = lm32_juart_init(); |
228 | d821732a | Michael Walle | |
229 | d821732a | Michael Walle | reset_info->bootstrap_pc = flash_base; |
230 | d821732a | Michael Walle | |
231 | d821732a | Michael Walle | if (kernel_filename) {
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232 | d821732a | Michael Walle | uint64_t entry; |
233 | d821732a | Michael Walle | int kernel_size;
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234 | d821732a | Michael Walle | |
235 | d821732a | Michael Walle | kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL, |
236 | d821732a | Michael Walle | 1, ELF_MACHINE, 0); |
237 | d821732a | Michael Walle | reset_info->bootstrap_pc = entry; |
238 | d821732a | Michael Walle | |
239 | d821732a | Michael Walle | if (kernel_size < 0) { |
240 | d821732a | Michael Walle | kernel_size = load_image_targphys(kernel_filename, ram_base, |
241 | d821732a | Michael Walle | ram_size); |
242 | d821732a | Michael Walle | reset_info->bootstrap_pc = ram_base; |
243 | d821732a | Michael Walle | } |
244 | d821732a | Michael Walle | |
245 | d821732a | Michael Walle | if (kernel_size < 0) { |
246 | d821732a | Michael Walle | fprintf(stderr, "qemu: could not load kernel '%s'\n",
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247 | d821732a | Michael Walle | kernel_filename); |
248 | d821732a | Michael Walle | exit(1);
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249 | d821732a | Michael Walle | } |
250 | d821732a | Michael Walle | } |
251 | d821732a | Michael Walle | |
252 | d821732a | Michael Walle | /* generate a rom with the hardware description */
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253 | d821732a | Michael Walle | hw = hwsetup_init(); |
254 | d821732a | Michael Walle | hwsetup_add_cpu(hw, "LM32", 75000000); |
255 | d821732a | Michael Walle | hwsetup_add_flash(hw, "flash", flash_base, flash_size);
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256 | d821732a | Michael Walle | hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size);
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257 | d821732a | Michael Walle | hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq);
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258 | d821732a | Michael Walle | hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq);
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259 | d821732a | Michael Walle | hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq);
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260 | d821732a | Michael Walle | hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq);
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261 | d821732a | Michael Walle | hwsetup_add_trailer(hw); |
262 | d821732a | Michael Walle | hwsetup_create_rom(hw, hwsetup_base); |
263 | d821732a | Michael Walle | hwsetup_free(hw); |
264 | d821732a | Michael Walle | |
265 | d821732a | Michael Walle | reset_info->hwsetup_base = hwsetup_base; |
266 | d821732a | Michael Walle | |
267 | d821732a | Michael Walle | if (kernel_cmdline && strlen(kernel_cmdline)) {
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268 | d821732a | Michael Walle | pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
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269 | d821732a | Michael Walle | kernel_cmdline); |
270 | d821732a | Michael Walle | reset_info->cmdline_base = cmdline_base; |
271 | d821732a | Michael Walle | } |
272 | d821732a | Michael Walle | |
273 | d821732a | Michael Walle | if (initrd_filename) {
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274 | d821732a | Michael Walle | size_t initrd_size; |
275 | d821732a | Michael Walle | initrd_size = load_image_targphys(initrd_filename, initrd_base, |
276 | d821732a | Michael Walle | initrd_max); |
277 | d821732a | Michael Walle | reset_info->initrd_base = initrd_base; |
278 | d821732a | Michael Walle | reset_info->initrd_size = initrd_size; |
279 | d821732a | Michael Walle | } |
280 | d821732a | Michael Walle | |
281 | d821732a | Michael Walle | qemu_register_reset(main_cpu_reset, reset_info); |
282 | d821732a | Michael Walle | } |
283 | d821732a | Michael Walle | |
284 | d821732a | Michael Walle | static QEMUMachine lm32_evr_machine = {
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285 | d821732a | Michael Walle | .name = "lm32-evr",
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286 | d821732a | Michael Walle | .desc = "LatticeMico32 EVR32 eval system",
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287 | d821732a | Michael Walle | .init = lm32_evr_init, |
288 | d821732a | Michael Walle | .is_default = 1
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289 | d821732a | Michael Walle | }; |
290 | d821732a | Michael Walle | |
291 | d821732a | Michael Walle | static QEMUMachine lm32_uclinux_machine = {
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292 | d821732a | Michael Walle | .name = "lm32-uclinux",
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293 | d821732a | Michael Walle | .desc = "lm32 platform for uClinux and u-boot by Theobroma Systems",
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294 | d821732a | Michael Walle | .init = lm32_uclinux_init, |
295 | d821732a | Michael Walle | .is_default = 0
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296 | d821732a | Michael Walle | }; |
297 | d821732a | Michael Walle | |
298 | d821732a | Michael Walle | static void lm32_machine_init(void) |
299 | d821732a | Michael Walle | { |
300 | d821732a | Michael Walle | qemu_register_machine(&lm32_uclinux_machine); |
301 | d821732a | Michael Walle | qemu_register_machine(&lm32_evr_machine); |
302 | d821732a | Michael Walle | } |
303 | d821732a | Michael Walle | |
304 | d821732a | Michael Walle | machine_init(lm32_machine_init); |