root / hw / piix_pci.c @ 6c7796e5
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1 | 502a5395 | pbrook | /*
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2 | 502a5395 | pbrook | * QEMU i440FX/PIIX3 PCI Bridge Emulation
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3 | 502a5395 | pbrook | *
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4 | 502a5395 | pbrook | * Copyright (c) 2006 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 502a5395 | pbrook | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 502a5395 | pbrook | * of this software and associated documentation files (the "Software"), to deal
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8 | 502a5395 | pbrook | * in the Software without restriction, including without limitation the rights
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9 | 502a5395 | pbrook | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 502a5395 | pbrook | * copies of the Software, and to permit persons to whom the Software is
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11 | 502a5395 | pbrook | * furnished to do so, subject to the following conditions:
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12 | 502a5395 | pbrook | *
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13 | 502a5395 | pbrook | * The above copyright notice and this permission notice shall be included in
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14 | 502a5395 | pbrook | * all copies or substantial portions of the Software.
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15 | 502a5395 | pbrook | *
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16 | 502a5395 | pbrook | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 502a5395 | pbrook | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 502a5395 | pbrook | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 502a5395 | pbrook | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 502a5395 | pbrook | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 502a5395 | pbrook | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 502a5395 | pbrook | * THE SOFTWARE.
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23 | 502a5395 | pbrook | */
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24 | 502a5395 | pbrook | |
25 | 87ecb68b | pbrook | #include "hw.h" |
26 | 87ecb68b | pbrook | #include "pc.h" |
27 | 87ecb68b | pbrook | #include "pci.h" |
28 | 4f5e19e6 | Isaku Yamahata | #include "pci_host.h" |
29 | f75247f1 | Gerd Hoffmann | #include "isa.h" |
30 | 8a14daa5 | Gerd Hoffmann | #include "sysbus.h" |
31 | bf1b0071 | Blue Swirl | #include "range.h" |
32 | 41445300 | Anthony PERARD | #include "xen.h" |
33 | 87ecb68b | pbrook | |
34 | 56594fe3 | Isaku Yamahata | /*
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35 | 56594fe3 | Isaku Yamahata | * I440FX chipset data sheet.
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36 | 56594fe3 | Isaku Yamahata | * http://download.intel.com/design/chipsets/datashts/29054901.pdf
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37 | 56594fe3 | Isaku Yamahata | */
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38 | 56594fe3 | Isaku Yamahata | |
39 | 502a5395 | pbrook | typedef PCIHostState I440FXState;
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40 | 502a5395 | pbrook | |
41 | ab431c28 | Isaku Yamahata | #define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */ |
42 | e735b55a | Isaku Yamahata | #define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ |
43 | bf09551a | Stefano Stabellini | #define XEN_PIIX_NUM_PIRQS 128ULL |
44 | ab431c28 | Isaku Yamahata | #define PIIX_PIRQC 0x60 |
45 | e735b55a | Isaku Yamahata | |
46 | fd37d881 | Juan Quintela | typedef struct PIIX3State { |
47 | fd37d881 | Juan Quintela | PCIDevice dev; |
48 | ab431c28 | Isaku Yamahata | |
49 | ab431c28 | Isaku Yamahata | /*
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50 | ab431c28 | Isaku Yamahata | * bitmap to track pic levels.
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51 | ab431c28 | Isaku Yamahata | * The pic level is the logical OR of all the PCI irqs mapped to it
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52 | ab431c28 | Isaku Yamahata | * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
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53 | ab431c28 | Isaku Yamahata | *
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54 | ab431c28 | Isaku Yamahata | * PIRQ is mapped to PIC pins, we track it by
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55 | ab431c28 | Isaku Yamahata | * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
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56 | ab431c28 | Isaku Yamahata | * pic_irq * PIIX_NUM_PIRQS + pirq
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57 | ab431c28 | Isaku Yamahata | */
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58 | ab431c28 | Isaku Yamahata | #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64 |
59 | ab431c28 | Isaku Yamahata | #error "unable to encode pic state in 64bit in pic_levels." |
60 | ab431c28 | Isaku Yamahata | #endif
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61 | ab431c28 | Isaku Yamahata | uint64_t pic_levels; |
62 | ab431c28 | Isaku Yamahata | |
63 | bd7dce87 | Juan Quintela | qemu_irq *pic; |
64 | e735b55a | Isaku Yamahata | |
65 | e735b55a | Isaku Yamahata | /* This member isn't used. Just for save/load compatibility */
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66 | e735b55a | Isaku Yamahata | int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; |
67 | 7cd9eee0 | Gerd Hoffmann | } PIIX3State; |
68 | bd7dce87 | Juan Quintela | |
69 | 0a3bacf3 | Juan Quintela | struct PCII440FXState {
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70 | 0a3bacf3 | Juan Quintela | PCIDevice dev; |
71 | c227f099 | Anthony Liguori | target_phys_addr_t isa_page_descs[384 / 4]; |
72 | 6c009fa4 | Juan Quintela | uint8_t smm_enabled; |
73 | 7cd9eee0 | Gerd Hoffmann | PIIX3State *piix3; |
74 | 0a3bacf3 | Juan Quintela | }; |
75 | 0a3bacf3 | Juan Quintela | |
76 | f2c688bb | Isaku Yamahata | |
77 | f2c688bb | Isaku Yamahata | #define I440FX_PAM 0x59 |
78 | f2c688bb | Isaku Yamahata | #define I440FX_PAM_SIZE 7 |
79 | f2c688bb | Isaku Yamahata | #define I440FX_SMRAM 0x72 |
80 | f2c688bb | Isaku Yamahata | |
81 | ab431c28 | Isaku Yamahata | static void piix3_set_irq(void *opaque, int pirq, int level); |
82 | bf09551a | Stefano Stabellini | static void piix3_write_config_xen(PCIDevice *dev, |
83 | bf09551a | Stefano Stabellini | uint32_t address, uint32_t val, int len);
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84 | d2b59317 | pbrook | |
85 | d2b59317 | pbrook | /* return the global irq number corresponding to a given device irq
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86 | d2b59317 | pbrook | pin. We could also use the bus number to have a more precise
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87 | d2b59317 | pbrook | mapping. */
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88 | ab431c28 | Isaku Yamahata | static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) |
89 | d2b59317 | pbrook | { |
90 | d2b59317 | pbrook | int slot_addend;
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91 | d2b59317 | pbrook | slot_addend = (pci_dev->devfn >> 3) - 1; |
92 | ab431c28 | Isaku Yamahata | return (pci_intx + slot_addend) & 3; |
93 | d2b59317 | pbrook | } |
94 | 502a5395 | pbrook | |
95 | 0a3bacf3 | Juan Quintela | static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r) |
96 | 84631fd7 | bellard | { |
97 | 84631fd7 | bellard | uint32_t addr; |
98 | 84631fd7 | bellard | |
99 | 84631fd7 | bellard | // printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
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100 | 84631fd7 | bellard | switch(r) {
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101 | 84631fd7 | bellard | case 3: |
102 | 84631fd7 | bellard | /* RAM */
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103 | 5fafdf24 | ths | cpu_register_physical_memory(start, end - start, |
104 | 84631fd7 | bellard | start); |
105 | 84631fd7 | bellard | break;
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106 | 84631fd7 | bellard | case 1: |
107 | 84631fd7 | bellard | /* ROM (XXX: not quite correct) */
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108 | 5fafdf24 | ths | cpu_register_physical_memory(start, end - start, |
109 | 84631fd7 | bellard | start | IO_MEM_ROM); |
110 | 84631fd7 | bellard | break;
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111 | 84631fd7 | bellard | case 2: |
112 | 84631fd7 | bellard | case 0: |
113 | 84631fd7 | bellard | /* XXX: should distinguish read/write cases */
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114 | 84631fd7 | bellard | for(addr = start; addr < end; addr += 4096) { |
115 | 5fafdf24 | ths | cpu_register_physical_memory(addr, 4096,
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116 | 6c009fa4 | Juan Quintela | d->isa_page_descs[(addr - 0xa0000) >> 12]); |
117 | 84631fd7 | bellard | } |
118 | 84631fd7 | bellard | break;
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119 | 84631fd7 | bellard | } |
120 | 84631fd7 | bellard | } |
121 | ee0ea1d0 | bellard | |
122 | 0a3bacf3 | Juan Quintela | static void i440fx_update_memory_mappings(PCII440FXState *d) |
123 | ee0ea1d0 | bellard | { |
124 | ee0ea1d0 | bellard | int i, r;
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125 | 84631fd7 | bellard | uint32_t smram, addr; |
126 | 84631fd7 | bellard | |
127 | f2c688bb | Isaku Yamahata | update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3); |
128 | 84631fd7 | bellard | for(i = 0; i < 12; i++) { |
129 | f2c688bb | Isaku Yamahata | r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3; |
130 | 84631fd7 | bellard | update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r); |
131 | ee0ea1d0 | bellard | } |
132 | f2c688bb | Isaku Yamahata | smram = d->dev.config[I440FX_SMRAM]; |
133 | 6c009fa4 | Juan Quintela | if ((d->smm_enabled && (smram & 0x08)) || (smram & 0x40)) { |
134 | 84631fd7 | bellard | cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000); |
135 | 84631fd7 | bellard | } else {
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136 | 84631fd7 | bellard | for(addr = 0xa0000; addr < 0xc0000; addr += 4096) { |
137 | 5fafdf24 | ths | cpu_register_physical_memory(addr, 4096,
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138 | 6c009fa4 | Juan Quintela | d->isa_page_descs[(addr - 0xa0000) >> 12]); |
139 | ee0ea1d0 | bellard | } |
140 | ee0ea1d0 | bellard | } |
141 | ee0ea1d0 | bellard | } |
142 | ee0ea1d0 | bellard | |
143 | f885f1ea | Isaku Yamahata | static void i440fx_set_smm(int val, void *arg) |
144 | ee0ea1d0 | bellard | { |
145 | f885f1ea | Isaku Yamahata | PCII440FXState *d = arg; |
146 | f885f1ea | Isaku Yamahata | |
147 | ee0ea1d0 | bellard | val = (val != 0);
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148 | 6c009fa4 | Juan Quintela | if (d->smm_enabled != val) {
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149 | 6c009fa4 | Juan Quintela | d->smm_enabled = val; |
150 | ee0ea1d0 | bellard | i440fx_update_memory_mappings(d); |
151 | ee0ea1d0 | bellard | } |
152 | ee0ea1d0 | bellard | } |
153 | ee0ea1d0 | bellard | |
154 | ee0ea1d0 | bellard | |
155 | ee0ea1d0 | bellard | /* XXX: suppress when better memory API. We make the assumption that
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156 | ee0ea1d0 | bellard | no device (in particular the VGA) changes the memory mappings in
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157 | ee0ea1d0 | bellard | the 0xa0000-0x100000 range */
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158 | 0a3bacf3 | Juan Quintela | void i440fx_init_memory_mappings(PCII440FXState *d)
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159 | ee0ea1d0 | bellard | { |
160 | ee0ea1d0 | bellard | int i;
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161 | ee0ea1d0 | bellard | for(i = 0; i < 96; i++) { |
162 | 6c009fa4 | Juan Quintela | d->isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000); |
163 | ee0ea1d0 | bellard | } |
164 | ee0ea1d0 | bellard | } |
165 | ee0ea1d0 | bellard | |
166 | 0a3bacf3 | Juan Quintela | static void i440fx_write_config(PCIDevice *dev, |
167 | ee0ea1d0 | bellard | uint32_t address, uint32_t val, int len)
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168 | ee0ea1d0 | bellard | { |
169 | 0a3bacf3 | Juan Quintela | PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev); |
170 | 0a3bacf3 | Juan Quintela | |
171 | ee0ea1d0 | bellard | /* XXX: implement SMRAM.D_LOCK */
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172 | 0a3bacf3 | Juan Quintela | pci_default_write_config(dev, address, val, len); |
173 | 4da5fcd3 | Isaku Yamahata | if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
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174 | 4da5fcd3 | Isaku Yamahata | range_covers_byte(address, len, I440FX_SMRAM)) { |
175 | ee0ea1d0 | bellard | i440fx_update_memory_mappings(d); |
176 | 4da5fcd3 | Isaku Yamahata | } |
177 | ee0ea1d0 | bellard | } |
178 | ee0ea1d0 | bellard | |
179 | 0c7d19e5 | Juan Quintela | static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id) |
180 | ee0ea1d0 | bellard | { |
181 | 0a3bacf3 | Juan Quintela | PCII440FXState *d = opaque; |
182 | 52fc1d83 | balrog | int ret, i;
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183 | ee0ea1d0 | bellard | |
184 | 0a3bacf3 | Juan Quintela | ret = pci_device_load(&d->dev, f); |
185 | ee0ea1d0 | bellard | if (ret < 0) |
186 | ee0ea1d0 | bellard | return ret;
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187 | ee0ea1d0 | bellard | i440fx_update_memory_mappings(d); |
188 | 6c009fa4 | Juan Quintela | qemu_get_8s(f, &d->smm_enabled); |
189 | 52fc1d83 | balrog | |
190 | e735b55a | Isaku Yamahata | if (version_id == 2) { |
191 | e735b55a | Isaku Yamahata | for (i = 0; i < PIIX_NUM_PIRQS; i++) { |
192 | e735b55a | Isaku Yamahata | qemu_get_be32(f); /* dummy load for compatibility */
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193 | e735b55a | Isaku Yamahata | } |
194 | e735b55a | Isaku Yamahata | } |
195 | 52fc1d83 | balrog | |
196 | ee0ea1d0 | bellard | return 0; |
197 | ee0ea1d0 | bellard | } |
198 | ee0ea1d0 | bellard | |
199 | e59fb374 | Juan Quintela | static int i440fx_post_load(void *opaque, int version_id) |
200 | 0c7d19e5 | Juan Quintela | { |
201 | 0c7d19e5 | Juan Quintela | PCII440FXState *d = opaque; |
202 | 0c7d19e5 | Juan Quintela | |
203 | 0c7d19e5 | Juan Quintela | i440fx_update_memory_mappings(d); |
204 | 0c7d19e5 | Juan Quintela | return 0; |
205 | 0c7d19e5 | Juan Quintela | } |
206 | 0c7d19e5 | Juan Quintela | |
207 | 0c7d19e5 | Juan Quintela | static const VMStateDescription vmstate_i440fx = { |
208 | 0c7d19e5 | Juan Quintela | .name = "I440FX",
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209 | 0c7d19e5 | Juan Quintela | .version_id = 3,
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210 | 0c7d19e5 | Juan Quintela | .minimum_version_id = 3,
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211 | 0c7d19e5 | Juan Quintela | .minimum_version_id_old = 1,
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212 | 0c7d19e5 | Juan Quintela | .load_state_old = i440fx_load_old, |
213 | 752ff2fa | Juan Quintela | .post_load = i440fx_post_load, |
214 | 0c7d19e5 | Juan Quintela | .fields = (VMStateField []) { |
215 | 0c7d19e5 | Juan Quintela | VMSTATE_PCI_DEVICE(dev, PCII440FXState), |
216 | 0c7d19e5 | Juan Quintela | VMSTATE_UINT8(smm_enabled, PCII440FXState), |
217 | 0c7d19e5 | Juan Quintela | VMSTATE_END_OF_LIST() |
218 | 0c7d19e5 | Juan Quintela | } |
219 | 0c7d19e5 | Juan Quintela | }; |
220 | 0c7d19e5 | Juan Quintela | |
221 | 81a322d4 | Gerd Hoffmann | static int i440fx_pcihost_initfn(SysBusDevice *dev) |
222 | 502a5395 | pbrook | { |
223 | 8a14daa5 | Gerd Hoffmann | I440FXState *s = FROM_SYSBUS(I440FXState, dev); |
224 | 502a5395 | pbrook | |
225 | f08b32fe | Isaku Yamahata | pci_host_conf_register_ioport(0xcf8, s);
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226 | 502a5395 | pbrook | |
227 | 4f5e19e6 | Isaku Yamahata | pci_host_data_register_ioport(0xcfc, s);
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228 | 81a322d4 | Gerd Hoffmann | return 0; |
229 | 8a14daa5 | Gerd Hoffmann | } |
230 | 502a5395 | pbrook | |
231 | 0a3bacf3 | Juan Quintela | static int i440fx_initfn(PCIDevice *dev) |
232 | 8a14daa5 | Gerd Hoffmann | { |
233 | 0a3bacf3 | Juan Quintela | PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev); |
234 | ee0ea1d0 | bellard | |
235 | f2c688bb | Isaku Yamahata | d->dev.config[I440FX_SMRAM] = 0x02;
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236 | ee0ea1d0 | bellard | |
237 | f885f1ea | Isaku Yamahata | cpu_smm_register(&i440fx_set_smm, d); |
238 | 81a322d4 | Gerd Hoffmann | return 0; |
239 | 8a14daa5 | Gerd Hoffmann | } |
240 | 8a14daa5 | Gerd Hoffmann | |
241 | 41445300 | Anthony PERARD | static PCIBus *i440fx_common_init(const char *device_name, |
242 | 41445300 | Anthony PERARD | PCII440FXState **pi440fx_state, |
243 | 41445300 | Anthony PERARD | int *piix3_devfn,
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244 | 41445300 | Anthony PERARD | qemu_irq *pic, ram_addr_t ram_size) |
245 | 8a14daa5 | Gerd Hoffmann | { |
246 | 8a14daa5 | Gerd Hoffmann | DeviceState *dev; |
247 | 8a14daa5 | Gerd Hoffmann | PCIBus *b; |
248 | 8a14daa5 | Gerd Hoffmann | PCIDevice *d; |
249 | 8a14daa5 | Gerd Hoffmann | I440FXState *s; |
250 | 7cd9eee0 | Gerd Hoffmann | PIIX3State *piix3; |
251 | 8a14daa5 | Gerd Hoffmann | |
252 | 8a14daa5 | Gerd Hoffmann | dev = qdev_create(NULL, "i440FX-pcihost"); |
253 | 8a14daa5 | Gerd Hoffmann | s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev)); |
254 | 7cd9eee0 | Gerd Hoffmann | b = pci_bus_new(&s->busdev.qdev, NULL, 0); |
255 | 8a14daa5 | Gerd Hoffmann | s->bus = b; |
256 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
257 | 8a14daa5 | Gerd Hoffmann | |
258 | 41445300 | Anthony PERARD | d = pci_create_simple(b, 0, device_name);
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259 | 0a3bacf3 | Juan Quintela | *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d); |
260 | 8a14daa5 | Gerd Hoffmann | |
261 | bf09551a | Stefano Stabellini | /* Xen supports additional interrupt routes from the PCI devices to
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262 | bf09551a | Stefano Stabellini | * the IOAPIC: the four pins of each PCI device on the bus are also
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263 | bf09551a | Stefano Stabellini | * connected to the IOAPIC directly.
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264 | bf09551a | Stefano Stabellini | * These additional routes can be discovered through ACPI. */
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265 | bf09551a | Stefano Stabellini | if (xen_enabled()) {
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266 | bf09551a | Stefano Stabellini | piix3 = DO_UPCAST(PIIX3State, dev, |
267 | bf09551a | Stefano Stabellini | pci_create_simple_multifunction(b, -1, true, "PIIX3-xen")); |
268 | bf09551a | Stefano Stabellini | pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq, |
269 | bf09551a | Stefano Stabellini | piix3, XEN_PIIX_NUM_PIRQS); |
270 | bf09551a | Stefano Stabellini | } else {
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271 | bf09551a | Stefano Stabellini | piix3 = DO_UPCAST(PIIX3State, dev, |
272 | bf09551a | Stefano Stabellini | pci_create_simple_multifunction(b, -1, true, "PIIX3")); |
273 | bf09551a | Stefano Stabellini | pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3, |
274 | bf09551a | Stefano Stabellini | PIIX_NUM_PIRQS); |
275 | bf09551a | Stefano Stabellini | } |
276 | 7cd9eee0 | Gerd Hoffmann | piix3->pic = pic; |
277 | 41445300 | Anthony PERARD | |
278 | 7cd9eee0 | Gerd Hoffmann | (*pi440fx_state)->piix3 = piix3; |
279 | 7cd9eee0 | Gerd Hoffmann | |
280 | 7cd9eee0 | Gerd Hoffmann | *piix3_devfn = piix3->dev.devfn; |
281 | 85a750ca | Juan Quintela | |
282 | ec5f92ce | Bernhard M. Wiedemann | ram_size = ram_size / 8 / 1024 / 1024; |
283 | ec5f92ce | Bernhard M. Wiedemann | if (ram_size > 255) |
284 | ec5f92ce | Bernhard M. Wiedemann | ram_size = 255;
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285 | ec5f92ce | Bernhard M. Wiedemann | (*pi440fx_state)->dev.config[0x57]=ram_size;
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286 | ec5f92ce | Bernhard M. Wiedemann | |
287 | 502a5395 | pbrook | return b;
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288 | 502a5395 | pbrook | } |
289 | 502a5395 | pbrook | |
290 | 41445300 | Anthony PERARD | PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
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291 | 41445300 | Anthony PERARD | qemu_irq *pic, ram_addr_t ram_size) |
292 | 41445300 | Anthony PERARD | { |
293 | 41445300 | Anthony PERARD | PCIBus *b; |
294 | 41445300 | Anthony PERARD | |
295 | 41445300 | Anthony PERARD | b = i440fx_common_init("i440FX", pi440fx_state, piix3_devfn, pic, ram_size);
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296 | 41445300 | Anthony PERARD | return b;
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297 | 41445300 | Anthony PERARD | } |
298 | 41445300 | Anthony PERARD | |
299 | 502a5395 | pbrook | /* PIIX3 PCI to ISA bridge */
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300 | ab431c28 | Isaku Yamahata | static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) |
301 | ab431c28 | Isaku Yamahata | { |
302 | ab431c28 | Isaku Yamahata | qemu_set_irq(piix3->pic[pic_irq], |
303 | ab431c28 | Isaku Yamahata | !!(piix3->pic_levels & |
304 | 09de0f46 | TeLeMan | (((1ULL << PIIX_NUM_PIRQS) - 1) << |
305 | ab431c28 | Isaku Yamahata | (pic_irq * PIIX_NUM_PIRQS)))); |
306 | ab431c28 | Isaku Yamahata | } |
307 | 502a5395 | pbrook | |
308 | afe3ef1d | Isaku Yamahata | static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) |
309 | ab431c28 | Isaku Yamahata | { |
310 | ab431c28 | Isaku Yamahata | int pic_irq;
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311 | ab431c28 | Isaku Yamahata | uint64_t mask; |
312 | ab431c28 | Isaku Yamahata | |
313 | ab431c28 | Isaku Yamahata | pic_irq = piix3->dev.config[PIIX_PIRQC + pirq]; |
314 | ab431c28 | Isaku Yamahata | if (pic_irq >= PIIX_NUM_PIC_IRQS) {
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315 | ab431c28 | Isaku Yamahata | return;
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316 | ab431c28 | Isaku Yamahata | } |
317 | ab431c28 | Isaku Yamahata | |
318 | ab431c28 | Isaku Yamahata | mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
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319 | ab431c28 | Isaku Yamahata | piix3->pic_levels &= ~mask; |
320 | ab431c28 | Isaku Yamahata | piix3->pic_levels |= mask * !!level; |
321 | ab431c28 | Isaku Yamahata | |
322 | afe3ef1d | Isaku Yamahata | piix3_set_irq_pic(piix3, pic_irq); |
323 | ab431c28 | Isaku Yamahata | } |
324 | ab431c28 | Isaku Yamahata | |
325 | ab431c28 | Isaku Yamahata | static void piix3_set_irq(void *opaque, int pirq, int level) |
326 | 502a5395 | pbrook | { |
327 | 7cd9eee0 | Gerd Hoffmann | PIIX3State *piix3 = opaque; |
328 | afe3ef1d | Isaku Yamahata | piix3_set_irq_level(piix3, pirq, level); |
329 | ab431c28 | Isaku Yamahata | } |
330 | 502a5395 | pbrook | |
331 | ab431c28 | Isaku Yamahata | /* irq routing is changed. so rebuild bitmap */
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332 | ab431c28 | Isaku Yamahata | static void piix3_update_irq_levels(PIIX3State *piix3) |
333 | ab431c28 | Isaku Yamahata | { |
334 | ab431c28 | Isaku Yamahata | int pirq;
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335 | ab431c28 | Isaku Yamahata | |
336 | ab431c28 | Isaku Yamahata | piix3->pic_levels = 0;
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337 | ab431c28 | Isaku Yamahata | for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) { |
338 | ab431c28 | Isaku Yamahata | piix3_set_irq_level(piix3, pirq, |
339 | afe3ef1d | Isaku Yamahata | pci_bus_get_irq_level(piix3->dev.bus, pirq)); |
340 | ab431c28 | Isaku Yamahata | } |
341 | ab431c28 | Isaku Yamahata | } |
342 | ab431c28 | Isaku Yamahata | |
343 | ab431c28 | Isaku Yamahata | static void piix3_write_config(PCIDevice *dev, |
344 | ab431c28 | Isaku Yamahata | uint32_t address, uint32_t val, int len)
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345 | ab431c28 | Isaku Yamahata | { |
346 | ab431c28 | Isaku Yamahata | pci_default_write_config(dev, address, val, len); |
347 | ab431c28 | Isaku Yamahata | if (ranges_overlap(address, len, PIIX_PIRQC, 4)) { |
348 | ab431c28 | Isaku Yamahata | PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev); |
349 | ab431c28 | Isaku Yamahata | int pic_irq;
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350 | ab431c28 | Isaku Yamahata | piix3_update_irq_levels(piix3); |
351 | ab431c28 | Isaku Yamahata | for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) { |
352 | ab431c28 | Isaku Yamahata | piix3_set_irq_pic(piix3, pic_irq); |
353 | d2b59317 | pbrook | } |
354 | 502a5395 | pbrook | } |
355 | 502a5395 | pbrook | } |
356 | 502a5395 | pbrook | |
357 | bf09551a | Stefano Stabellini | static void piix3_write_config_xen(PCIDevice *dev, |
358 | bf09551a | Stefano Stabellini | uint32_t address, uint32_t val, int len)
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359 | bf09551a | Stefano Stabellini | { |
360 | bf09551a | Stefano Stabellini | xen_piix_pci_write_config_client(address, val, len); |
361 | bf09551a | Stefano Stabellini | piix3_write_config(dev, address, val, len); |
362 | bf09551a | Stefano Stabellini | } |
363 | bf09551a | Stefano Stabellini | |
364 | 15a1956a | Gleb Natapov | static void piix3_reset(void *opaque) |
365 | 502a5395 | pbrook | { |
366 | fd37d881 | Juan Quintela | PIIX3State *d = opaque; |
367 | fd37d881 | Juan Quintela | uint8_t *pci_conf = d->dev.config; |
368 | 502a5395 | pbrook | |
369 | 502a5395 | pbrook | pci_conf[0x04] = 0x07; // master, memory and I/O |
370 | 502a5395 | pbrook | pci_conf[0x05] = 0x00; |
371 | 502a5395 | pbrook | pci_conf[0x06] = 0x00; |
372 | 502a5395 | pbrook | pci_conf[0x07] = 0x02; // PCI_status_devsel_medium |
373 | 502a5395 | pbrook | pci_conf[0x4c] = 0x4d; |
374 | 502a5395 | pbrook | pci_conf[0x4e] = 0x03; |
375 | 502a5395 | pbrook | pci_conf[0x4f] = 0x00; |
376 | 502a5395 | pbrook | pci_conf[0x60] = 0x80; |
377 | 477afee3 | aurel32 | pci_conf[0x61] = 0x80; |
378 | 477afee3 | aurel32 | pci_conf[0x62] = 0x80; |
379 | 477afee3 | aurel32 | pci_conf[0x63] = 0x80; |
380 | 502a5395 | pbrook | pci_conf[0x69] = 0x02; |
381 | 502a5395 | pbrook | pci_conf[0x70] = 0x80; |
382 | 502a5395 | pbrook | pci_conf[0x76] = 0x0c; |
383 | 502a5395 | pbrook | pci_conf[0x77] = 0x0c; |
384 | 502a5395 | pbrook | pci_conf[0x78] = 0x02; |
385 | 502a5395 | pbrook | pci_conf[0x79] = 0x00; |
386 | 502a5395 | pbrook | pci_conf[0x80] = 0x00; |
387 | 502a5395 | pbrook | pci_conf[0x82] = 0x00; |
388 | 502a5395 | pbrook | pci_conf[0xa0] = 0x08; |
389 | 502a5395 | pbrook | pci_conf[0xa2] = 0x00; |
390 | 502a5395 | pbrook | pci_conf[0xa3] = 0x00; |
391 | 502a5395 | pbrook | pci_conf[0xa4] = 0x00; |
392 | 502a5395 | pbrook | pci_conf[0xa5] = 0x00; |
393 | 502a5395 | pbrook | pci_conf[0xa6] = 0x00; |
394 | 502a5395 | pbrook | pci_conf[0xa7] = 0x00; |
395 | 502a5395 | pbrook | pci_conf[0xa8] = 0x0f; |
396 | 502a5395 | pbrook | pci_conf[0xaa] = 0x00; |
397 | 502a5395 | pbrook | pci_conf[0xab] = 0x00; |
398 | 502a5395 | pbrook | pci_conf[0xac] = 0x00; |
399 | 502a5395 | pbrook | pci_conf[0xae] = 0x00; |
400 | ab431c28 | Isaku Yamahata | |
401 | ab431c28 | Isaku Yamahata | d->pic_levels = 0;
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402 | ab431c28 | Isaku Yamahata | } |
403 | ab431c28 | Isaku Yamahata | |
404 | ab431c28 | Isaku Yamahata | static int piix3_post_load(void *opaque, int version_id) |
405 | ab431c28 | Isaku Yamahata | { |
406 | ab431c28 | Isaku Yamahata | PIIX3State *piix3 = opaque; |
407 | ab431c28 | Isaku Yamahata | piix3_update_irq_levels(piix3); |
408 | ab431c28 | Isaku Yamahata | return 0; |
409 | e735b55a | Isaku Yamahata | } |
410 | 15a1956a | Gleb Natapov | |
411 | e735b55a | Isaku Yamahata | static void piix3_pre_save(void *opaque) |
412 | e735b55a | Isaku Yamahata | { |
413 | e735b55a | Isaku Yamahata | int i;
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414 | e735b55a | Isaku Yamahata | PIIX3State *piix3 = opaque; |
415 | e735b55a | Isaku Yamahata | |
416 | e735b55a | Isaku Yamahata | for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) { |
417 | e735b55a | Isaku Yamahata | piix3->pci_irq_levels_vmstate[i] = |
418 | e735b55a | Isaku Yamahata | pci_bus_get_irq_level(piix3->dev.bus, i); |
419 | e735b55a | Isaku Yamahata | } |
420 | 502a5395 | pbrook | } |
421 | 502a5395 | pbrook | |
422 | d1f171bd | Juan Quintela | static const VMStateDescription vmstate_piix3 = { |
423 | d1f171bd | Juan Quintela | .name = "PIIX3",
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424 | d1f171bd | Juan Quintela | .version_id = 3,
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425 | d1f171bd | Juan Quintela | .minimum_version_id = 2,
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426 | d1f171bd | Juan Quintela | .minimum_version_id_old = 2,
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427 | ab431c28 | Isaku Yamahata | .post_load = piix3_post_load, |
428 | e735b55a | Isaku Yamahata | .pre_save = piix3_pre_save, |
429 | d1f171bd | Juan Quintela | .fields = (VMStateField []) { |
430 | d1f171bd | Juan Quintela | VMSTATE_PCI_DEVICE(dev, PIIX3State), |
431 | e735b55a | Isaku Yamahata | VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State, |
432 | e735b55a | Isaku Yamahata | PIIX_NUM_PIRQS, 3),
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433 | d1f171bd | Juan Quintela | VMSTATE_END_OF_LIST() |
434 | da64182c | Juan Quintela | } |
435 | d1f171bd | Juan Quintela | }; |
436 | 1941d19c | bellard | |
437 | fd37d881 | Juan Quintela | static int piix3_initfn(PCIDevice *dev) |
438 | 502a5395 | pbrook | { |
439 | fd37d881 | Juan Quintela | PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev); |
440 | 502a5395 | pbrook | |
441 | fd37d881 | Juan Quintela | isa_bus_new(&d->dev.qdev); |
442 | a08d4367 | Jan Kiszka | qemu_register_reset(piix3_reset, d); |
443 | 81a322d4 | Gerd Hoffmann | return 0; |
444 | 502a5395 | pbrook | } |
445 | 5c2b87e3 | ths | |
446 | 8a14daa5 | Gerd Hoffmann | static PCIDeviceInfo i440fx_info[] = {
|
447 | 8a14daa5 | Gerd Hoffmann | { |
448 | 8a14daa5 | Gerd Hoffmann | .qdev.name = "i440FX",
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449 | 8a14daa5 | Gerd Hoffmann | .qdev.desc = "Host bridge",
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450 | 0a3bacf3 | Juan Quintela | .qdev.size = sizeof(PCII440FXState),
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451 | be73cfe2 | Juan Quintela | .qdev.vmsd = &vmstate_i440fx, |
452 | 8a14daa5 | Gerd Hoffmann | .qdev.no_user = 1,
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453 | 0965f12d | Gerd Hoffmann | .no_hotplug = 1,
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454 | 8a14daa5 | Gerd Hoffmann | .init = i440fx_initfn, |
455 | 8a14daa5 | Gerd Hoffmann | .config_write = i440fx_write_config, |
456 | 3a9d8549 | Isaku Yamahata | .vendor_id = PCI_VENDOR_ID_INTEL, |
457 | 3a9d8549 | Isaku Yamahata | .device_id = PCI_DEVICE_ID_INTEL_82441, |
458 | 3a9d8549 | Isaku Yamahata | .revision = 0x02,
|
459 | 3a9d8549 | Isaku Yamahata | .class_id = PCI_CLASS_BRIDGE_HOST, |
460 | 8a14daa5 | Gerd Hoffmann | },{ |
461 | 8a14daa5 | Gerd Hoffmann | .qdev.name = "PIIX3",
|
462 | 8a14daa5 | Gerd Hoffmann | .qdev.desc = "ISA bridge",
|
463 | fd37d881 | Juan Quintela | .qdev.size = sizeof(PIIX3State),
|
464 | be73cfe2 | Juan Quintela | .qdev.vmsd = &vmstate_piix3, |
465 | 8a14daa5 | Gerd Hoffmann | .qdev.no_user = 1,
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466 | 0965f12d | Gerd Hoffmann | .no_hotplug = 1,
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467 | 8a14daa5 | Gerd Hoffmann | .init = piix3_initfn, |
468 | ab431c28 | Isaku Yamahata | .config_write = piix3_write_config, |
469 | 3a9d8549 | Isaku Yamahata | .vendor_id = PCI_VENDOR_ID_INTEL, |
470 | 3a9d8549 | Isaku Yamahata | .device_id = PCI_DEVICE_ID_INTEL_82371SB_0, // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
|
471 | 3a9d8549 | Isaku Yamahata | .class_id = PCI_CLASS_BRIDGE_ISA, |
472 | 8a14daa5 | Gerd Hoffmann | },{ |
473 | bf09551a | Stefano Stabellini | .qdev.name = "PIIX3-xen",
|
474 | bf09551a | Stefano Stabellini | .qdev.desc = "ISA bridge",
|
475 | bf09551a | Stefano Stabellini | .qdev.size = sizeof(PIIX3State),
|
476 | bf09551a | Stefano Stabellini | .qdev.vmsd = &vmstate_piix3, |
477 | bf09551a | Stefano Stabellini | .qdev.no_user = 1,
|
478 | bf09551a | Stefano Stabellini | .no_hotplug = 1,
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479 | bf09551a | Stefano Stabellini | .init = piix3_initfn, |
480 | bf09551a | Stefano Stabellini | .config_write = piix3_write_config_xen, |
481 | bf09551a | Stefano Stabellini | },{ |
482 | 8a14daa5 | Gerd Hoffmann | /* end of list */
|
483 | 8a14daa5 | Gerd Hoffmann | } |
484 | 8a14daa5 | Gerd Hoffmann | }; |
485 | 8a14daa5 | Gerd Hoffmann | |
486 | 8a14daa5 | Gerd Hoffmann | static SysBusDeviceInfo i440fx_pcihost_info = {
|
487 | 8a14daa5 | Gerd Hoffmann | .init = i440fx_pcihost_initfn, |
488 | 8a14daa5 | Gerd Hoffmann | .qdev.name = "i440FX-pcihost",
|
489 | 779206de | Gleb Natapov | .qdev.fw_name = "pci",
|
490 | 8a14daa5 | Gerd Hoffmann | .qdev.size = sizeof(I440FXState),
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491 | 8a14daa5 | Gerd Hoffmann | .qdev.no_user = 1,
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492 | 8a14daa5 | Gerd Hoffmann | }; |
493 | 8a14daa5 | Gerd Hoffmann | |
494 | 8a14daa5 | Gerd Hoffmann | static void i440fx_register(void) |
495 | 8a14daa5 | Gerd Hoffmann | { |
496 | 8a14daa5 | Gerd Hoffmann | sysbus_register_withprop(&i440fx_pcihost_info); |
497 | 8a14daa5 | Gerd Hoffmann | pci_qdev_register_many(i440fx_info); |
498 | 8a14daa5 | Gerd Hoffmann | } |
499 | 8a14daa5 | Gerd Hoffmann | device_init(i440fx_register); |