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1 | 2c0262af | bellard | /*
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2 | 2c0262af | bellard | * i386 helpers (without register variable usage)
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3 | 2c0262af | bellard | *
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4 | 2c0262af | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 2c0262af | bellard | *
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6 | 2c0262af | bellard | * This library is free software; you can redistribute it and/or
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7 | 2c0262af | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 2c0262af | bellard | * License as published by the Free Software Foundation; either
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9 | 2c0262af | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 2c0262af | bellard | *
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11 | 2c0262af | bellard | * This library is distributed in the hope that it will be useful,
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12 | 2c0262af | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 2c0262af | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 2c0262af | bellard | * Lesser General Public License for more details.
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15 | 2c0262af | bellard | *
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16 | 2c0262af | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 2c0262af | bellard | * License along with this library; if not, write to the Free Software
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18 | 2c0262af | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 2c0262af | bellard | */
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20 | 2c0262af | bellard | #include <stdarg.h> |
21 | 2c0262af | bellard | #include <stdlib.h> |
22 | 2c0262af | bellard | #include <stdio.h> |
23 | 2c0262af | bellard | #include <string.h> |
24 | 2c0262af | bellard | #include <inttypes.h> |
25 | 2c0262af | bellard | #include <signal.h> |
26 | 2c0262af | bellard | #include <assert.h> |
27 | 2c0262af | bellard | #include <sys/mman.h> |
28 | 2c0262af | bellard | |
29 | 2c0262af | bellard | #include "cpu.h" |
30 | 2c0262af | bellard | #include "exec-all.h" |
31 | 2c0262af | bellard | |
32 | 2c0262af | bellard | //#define DEBUG_MMU
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33 | 2c0262af | bellard | |
34 | 2c0262af | bellard | CPUX86State *cpu_x86_init(void)
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35 | 2c0262af | bellard | { |
36 | 2c0262af | bellard | CPUX86State *env; |
37 | 2c0262af | bellard | int i;
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38 | 2c0262af | bellard | static int inited; |
39 | 2c0262af | bellard | |
40 | 2c0262af | bellard | cpu_exec_init(); |
41 | 2c0262af | bellard | |
42 | 2c0262af | bellard | env = malloc(sizeof(CPUX86State));
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43 | 2c0262af | bellard | if (!env)
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44 | 2c0262af | bellard | return NULL; |
45 | 2c0262af | bellard | memset(env, 0, sizeof(CPUX86State)); |
46 | 2c0262af | bellard | /* basic FPU init */
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47 | 2c0262af | bellard | for(i = 0;i < 8; i++) |
48 | 2c0262af | bellard | env->fptags[i] = 1;
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49 | 2c0262af | bellard | env->fpuc = 0x37f;
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50 | 2c0262af | bellard | /* flags setup : we activate the IRQs by default as in user mode */
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51 | 2c0262af | bellard | env->eflags = 0x2 | IF_MASK;
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52 | 2c0262af | bellard | |
53 | 2c0262af | bellard | tlb_flush(env); |
54 | 2c0262af | bellard | #ifdef CONFIG_SOFTMMU
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55 | 2c0262af | bellard | env->hflags |= HF_SOFTMMU_MASK; |
56 | 2c0262af | bellard | #endif
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57 | 2c0262af | bellard | /* init various static tables */
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58 | 2c0262af | bellard | if (!inited) {
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59 | 2c0262af | bellard | inited = 1;
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60 | 2c0262af | bellard | optimize_flags_init(); |
61 | 2c0262af | bellard | } |
62 | 2c0262af | bellard | return env;
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63 | 2c0262af | bellard | } |
64 | 2c0262af | bellard | |
65 | 2c0262af | bellard | void cpu_x86_close(CPUX86State *env)
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66 | 2c0262af | bellard | { |
67 | 2c0262af | bellard | free(env); |
68 | 2c0262af | bellard | } |
69 | 2c0262af | bellard | |
70 | 2c0262af | bellard | /***********************************************************/
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71 | 2c0262af | bellard | /* x86 debug */
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72 | 2c0262af | bellard | |
73 | 2c0262af | bellard | static const char *cc_op_str[] = { |
74 | 2c0262af | bellard | "DYNAMIC",
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75 | 2c0262af | bellard | "EFLAGS",
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76 | b7f0f463 | bellard | "MULB",
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77 | b7f0f463 | bellard | "MULW",
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78 | b7f0f463 | bellard | "MULL",
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79 | 2c0262af | bellard | "ADDB",
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80 | 2c0262af | bellard | "ADDW",
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81 | 2c0262af | bellard | "ADDL",
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82 | 2c0262af | bellard | "ADCB",
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83 | 2c0262af | bellard | "ADCW",
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84 | 2c0262af | bellard | "ADCL",
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85 | 2c0262af | bellard | "SUBB",
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86 | 2c0262af | bellard | "SUBW",
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87 | 2c0262af | bellard | "SUBL",
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88 | 2c0262af | bellard | "SBBB",
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89 | 2c0262af | bellard | "SBBW",
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90 | 2c0262af | bellard | "SBBL",
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91 | 2c0262af | bellard | "LOGICB",
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92 | 2c0262af | bellard | "LOGICW",
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93 | 2c0262af | bellard | "LOGICL",
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94 | 2c0262af | bellard | "INCB",
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95 | 2c0262af | bellard | "INCW",
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96 | 2c0262af | bellard | "INCL",
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97 | 2c0262af | bellard | "DECB",
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98 | 2c0262af | bellard | "DECW",
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99 | 2c0262af | bellard | "DECL",
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100 | 2c0262af | bellard | "SHLB",
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101 | 2c0262af | bellard | "SHLW",
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102 | 2c0262af | bellard | "SHLL",
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103 | 2c0262af | bellard | "SARB",
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104 | 2c0262af | bellard | "SARW",
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105 | 2c0262af | bellard | "SARL",
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106 | 2c0262af | bellard | }; |
107 | 2c0262af | bellard | |
108 | 2c0262af | bellard | void cpu_x86_dump_state(CPUX86State *env, FILE *f, int flags) |
109 | 2c0262af | bellard | { |
110 | 246d897f | bellard | int eflags, i;
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111 | 2c0262af | bellard | char cc_op_name[32]; |
112 | 246d897f | bellard | static const char *seg_name[6] = { "ES", "CS", "SS", "DS", "FS", "GS" }; |
113 | 2c0262af | bellard | |
114 | 2c0262af | bellard | eflags = env->eflags; |
115 | 2c0262af | bellard | fprintf(f, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
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116 | 2c0262af | bellard | "ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
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117 | 5e809a80 | bellard | "EIP=%08x EFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d\n",
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118 | 2c0262af | bellard | env->regs[R_EAX], env->regs[R_EBX], env->regs[R_ECX], env->regs[R_EDX], |
119 | 2c0262af | bellard | env->regs[R_ESI], env->regs[R_EDI], env->regs[R_EBP], env->regs[R_ESP], |
120 | 2c0262af | bellard | env->eip, eflags, |
121 | 2c0262af | bellard | eflags & DF_MASK ? 'D' : '-', |
122 | 2c0262af | bellard | eflags & CC_O ? 'O' : '-', |
123 | 2c0262af | bellard | eflags & CC_S ? 'S' : '-', |
124 | 2c0262af | bellard | eflags & CC_Z ? 'Z' : '-', |
125 | 2c0262af | bellard | eflags & CC_A ? 'A' : '-', |
126 | 2c0262af | bellard | eflags & CC_P ? 'P' : '-', |
127 | 246d897f | bellard | eflags & CC_C ? 'C' : '-', |
128 | 5e809a80 | bellard | env->hflags & HF_CPL_MASK, |
129 | 5e809a80 | bellard | (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1);
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130 | 246d897f | bellard | for(i = 0; i < 6; i++) { |
131 | 246d897f | bellard | SegmentCache *sc = &env->segs[i]; |
132 | 246d897f | bellard | fprintf(f, "%s =%04x %08x %08x %08x\n",
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133 | 246d897f | bellard | seg_name[i], |
134 | 246d897f | bellard | sc->selector, |
135 | 246d897f | bellard | (int)sc->base,
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136 | 246d897f | bellard | sc->limit, |
137 | 246d897f | bellard | sc->flags); |
138 | 246d897f | bellard | } |
139 | 246d897f | bellard | fprintf(f, "LDT=%04x %08x %08x %08x\n",
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140 | 246d897f | bellard | env->ldt.selector, |
141 | 246d897f | bellard | (int)env->ldt.base,
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142 | 246d897f | bellard | env->ldt.limit, |
143 | 246d897f | bellard | env->ldt.flags); |
144 | 246d897f | bellard | fprintf(f, "TR =%04x %08x %08x %08x\n",
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145 | 246d897f | bellard | env->tr.selector, |
146 | 246d897f | bellard | (int)env->tr.base,
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147 | 246d897f | bellard | env->tr.limit, |
148 | 246d897f | bellard | env->tr.flags); |
149 | 246d897f | bellard | fprintf(f, "GDT= %08x %08x\n",
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150 | 246d897f | bellard | (int)env->gdt.base, env->gdt.limit);
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151 | 246d897f | bellard | fprintf(f, "IDT= %08x %08x\n",
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152 | 246d897f | bellard | (int)env->idt.base, env->idt.limit);
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153 | 246d897f | bellard | fprintf(f, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n",
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154 | 246d897f | bellard | env->cr[0], env->cr[2], env->cr[3], env->cr[4]); |
155 | 246d897f | bellard | |
156 | 2c0262af | bellard | if (flags & X86_DUMP_CCOP) {
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157 | 2c0262af | bellard | if ((unsigned)env->cc_op < CC_OP_NB) |
158 | 2c0262af | bellard | strcpy(cc_op_name, cc_op_str[env->cc_op]); |
159 | 2c0262af | bellard | else
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160 | 2c0262af | bellard | snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op); |
161 | 2c0262af | bellard | fprintf(f, "CCS=%08x CCD=%08x CCO=%-8s\n",
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162 | 2c0262af | bellard | env->cc_src, env->cc_dst, cc_op_name); |
163 | 2c0262af | bellard | } |
164 | 2c0262af | bellard | if (flags & X86_DUMP_FPU) {
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165 | 2c0262af | bellard | fprintf(f, "ST0=%f ST1=%f ST2=%f ST3=%f\n",
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166 | 2c0262af | bellard | (double)env->fpregs[0], |
167 | 2c0262af | bellard | (double)env->fpregs[1], |
168 | 2c0262af | bellard | (double)env->fpregs[2], |
169 | 2c0262af | bellard | (double)env->fpregs[3]); |
170 | 2c0262af | bellard | fprintf(f, "ST4=%f ST5=%f ST6=%f ST7=%f\n",
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171 | 2c0262af | bellard | (double)env->fpregs[4], |
172 | 2c0262af | bellard | (double)env->fpregs[5], |
173 | 2c0262af | bellard | (double)env->fpregs[7], |
174 | 2c0262af | bellard | (double)env->fpregs[8]); |
175 | 2c0262af | bellard | } |
176 | 2c0262af | bellard | } |
177 | 2c0262af | bellard | |
178 | 2c0262af | bellard | /***********************************************************/
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179 | 2c0262af | bellard | /* x86 mmu */
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180 | 2c0262af | bellard | /* XXX: add PGE support */
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181 | 2c0262af | bellard | |
182 | 2c0262af | bellard | /* called when cr3 or PG bit are modified */
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183 | 2c0262af | bellard | static int last_pg_state = -1; |
184 | 461c0471 | bellard | static uint32_t a20_mask;
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185 | 461c0471 | bellard | int a20_enabled;
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186 | 461c0471 | bellard | |
187 | 461c0471 | bellard | void cpu_x86_set_a20(CPUX86State *env, int a20_state) |
188 | 461c0471 | bellard | { |
189 | 461c0471 | bellard | a20_state = (a20_state != 0);
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190 | 461c0471 | bellard | if (a20_state != a20_enabled) {
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191 | b7f0f463 | bellard | #if defined(DEBUG_MMU)
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192 | b7f0f463 | bellard | printf("A20 update: a20=%d\n", a20_state);
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193 | b7f0f463 | bellard | #endif
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194 | 6bb70571 | bellard | /* if the cpu is currently executing code, we must unlink it and
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195 | 6bb70571 | bellard | all the potentially executing TB */
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196 | 6bb70571 | bellard | cpu_interrupt(env, 0);
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197 | 6bb70571 | bellard | |
198 | 461c0471 | bellard | /* when a20 is changed, all the MMU mappings are invalid, so
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199 | 461c0471 | bellard | we must flush everything */
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200 | 461c0471 | bellard | tlb_flush(env); |
201 | 461c0471 | bellard | a20_enabled = a20_state; |
202 | 461c0471 | bellard | if (a20_enabled)
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203 | 461c0471 | bellard | a20_mask = 0xffffffff;
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204 | 461c0471 | bellard | else
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205 | 461c0471 | bellard | a20_mask = 0xffefffff;
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206 | 461c0471 | bellard | } |
207 | 461c0471 | bellard | } |
208 | 461c0471 | bellard | |
209 | 2c0262af | bellard | void cpu_x86_update_cr0(CPUX86State *env)
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210 | 2c0262af | bellard | { |
211 | 2c0262af | bellard | int pg_state, pe_state;
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212 | 2c0262af | bellard | |
213 | b7f0f463 | bellard | #if defined(DEBUG_MMU)
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214 | 2c0262af | bellard | printf("CR0 update: CR0=0x%08x\n", env->cr[0]); |
215 | 2c0262af | bellard | #endif
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216 | 2c0262af | bellard | pg_state = env->cr[0] & CR0_PG_MASK;
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217 | 2c0262af | bellard | if (pg_state != last_pg_state) {
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218 | 2c0262af | bellard | tlb_flush(env); |
219 | 2c0262af | bellard | last_pg_state = pg_state; |
220 | 2c0262af | bellard | } |
221 | 436d8b89 | bellard | /* update PE flag in hidden flags */
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222 | 436d8b89 | bellard | pe_state = (env->cr[0] & CR0_PE_MASK);
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223 | 436d8b89 | bellard | env->hflags = (env->hflags & ~HF_PE_MASK) | (pe_state << HF_PE_SHIFT); |
224 | 436d8b89 | bellard | /* ensure that ADDSEG is always set in real mode */
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225 | 436d8b89 | bellard | env->hflags |= ((pe_state ^ 1) << HF_ADDSEG_SHIFT);
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226 | 2c0262af | bellard | } |
227 | 2c0262af | bellard | |
228 | 2c0262af | bellard | void cpu_x86_update_cr3(CPUX86State *env)
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229 | 2c0262af | bellard | { |
230 | 2c0262af | bellard | if (env->cr[0] & CR0_PG_MASK) { |
231 | 2c0262af | bellard | #if defined(DEBUG_MMU)
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232 | 2c0262af | bellard | printf("CR3 update: CR3=%08x\n", env->cr[3]); |
233 | 2c0262af | bellard | #endif
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234 | 2c0262af | bellard | tlb_flush(env); |
235 | 2c0262af | bellard | } |
236 | 2c0262af | bellard | } |
237 | 2c0262af | bellard | |
238 | 2c0262af | bellard | void cpu_x86_init_mmu(CPUX86State *env)
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239 | 2c0262af | bellard | { |
240 | 461c0471 | bellard | a20_enabled = 1;
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241 | 461c0471 | bellard | a20_mask = 0xffffffff;
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242 | 461c0471 | bellard | |
243 | 2c0262af | bellard | last_pg_state = -1;
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244 | 2c0262af | bellard | cpu_x86_update_cr0(env); |
245 | 2c0262af | bellard | } |
246 | 2c0262af | bellard | |
247 | 2c0262af | bellard | /* XXX: also flush 4MB pages */
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248 | 2c0262af | bellard | void cpu_x86_flush_tlb(CPUX86State *env, uint32_t addr)
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249 | 2c0262af | bellard | { |
250 | 2c0262af | bellard | tlb_flush_page(env, addr); |
251 | 2c0262af | bellard | } |
252 | 2c0262af | bellard | |
253 | 2c0262af | bellard | /* return value:
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254 | 2c0262af | bellard | -1 = cannot handle fault
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255 | 2c0262af | bellard | 0 = nothing more to do
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256 | 2c0262af | bellard | 1 = generate PF fault
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257 | 2c0262af | bellard | 2 = soft MMU activation required for this block
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258 | 2c0262af | bellard | */
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259 | 61382a50 | bellard | int cpu_x86_handle_mmu_fault(CPUX86State *env, uint32_t addr,
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260 | 61382a50 | bellard | int is_write, int is_user, int is_softmmu) |
261 | 2c0262af | bellard | { |
262 | 2c0262af | bellard | uint8_t *pde_ptr, *pte_ptr; |
263 | 2c0262af | bellard | uint32_t pde, pte, virt_addr; |
264 | 61382a50 | bellard | int error_code, is_dirty, prot, page_size, ret;
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265 | 436d8b89 | bellard | unsigned long paddr, vaddr, page_offset; |
266 | 2c0262af | bellard | |
267 | 436d8b89 | bellard | #if defined(DEBUG_MMU)
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268 | 2c0262af | bellard | printf("MMU fault: addr=0x%08x w=%d u=%d eip=%08x\n",
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269 | 2c0262af | bellard | addr, is_write, is_user, env->eip); |
270 | 2c0262af | bellard | #endif
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271 | 2c0262af | bellard | |
272 | 2c0262af | bellard | if (env->user_mode_only) {
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273 | 2c0262af | bellard | /* user mode only emulation */
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274 | 2c0262af | bellard | error_code = 0;
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275 | 2c0262af | bellard | goto do_fault;
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276 | 2c0262af | bellard | } |
277 | 2c0262af | bellard | |
278 | 2c0262af | bellard | if (!(env->cr[0] & CR0_PG_MASK)) { |
279 | 2c0262af | bellard | pte = addr; |
280 | 461c0471 | bellard | virt_addr = addr & TARGET_PAGE_MASK; |
281 | 2c0262af | bellard | prot = PROT_READ | PROT_WRITE; |
282 | 2c0262af | bellard | page_size = 4096;
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283 | 2c0262af | bellard | goto do_mapping;
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284 | 2c0262af | bellard | } |
285 | 2c0262af | bellard | |
286 | 2c0262af | bellard | /* page directory entry */
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287 | 461c0471 | bellard | pde_ptr = phys_ram_base + |
288 | 461c0471 | bellard | (((env->cr[3] & ~0xfff) + ((addr >> 20) & ~3)) & a20_mask); |
289 | 61382a50 | bellard | pde = ldl_raw(pde_ptr); |
290 | 2c0262af | bellard | if (!(pde & PG_PRESENT_MASK)) {
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291 | 2c0262af | bellard | error_code = 0;
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292 | 2c0262af | bellard | goto do_fault;
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293 | 2c0262af | bellard | } |
294 | 2c0262af | bellard | if (is_user) {
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295 | 2c0262af | bellard | if (!(pde & PG_USER_MASK))
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296 | 2c0262af | bellard | goto do_fault_protect;
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297 | 2c0262af | bellard | if (is_write && !(pde & PG_RW_MASK))
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298 | 2c0262af | bellard | goto do_fault_protect;
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299 | 2c0262af | bellard | } else {
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300 | 2c0262af | bellard | if ((env->cr[0] & CR0_WP_MASK) && (pde & PG_USER_MASK) && |
301 | 2c0262af | bellard | is_write && !(pde & PG_RW_MASK)) |
302 | 2c0262af | bellard | goto do_fault_protect;
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303 | 2c0262af | bellard | } |
304 | 2c0262af | bellard | /* if PSE bit is set, then we use a 4MB page */
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305 | 2c0262af | bellard | if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) { |
306 | 2c0262af | bellard | is_dirty = is_write && !(pde & PG_DIRTY_MASK); |
307 | 777aca2f | bellard | if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
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308 | 2c0262af | bellard | pde |= PG_ACCESSED_MASK; |
309 | 2c0262af | bellard | if (is_dirty)
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310 | 2c0262af | bellard | pde |= PG_DIRTY_MASK; |
311 | 61382a50 | bellard | stl_raw(pde_ptr, pde); |
312 | 2c0262af | bellard | } |
313 | 2c0262af | bellard | |
314 | 2c0262af | bellard | pte = pde & ~0x003ff000; /* align to 4MB */ |
315 | 2c0262af | bellard | page_size = 4096 * 1024; |
316 | 2c0262af | bellard | virt_addr = addr & ~0x003fffff;
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317 | 2c0262af | bellard | } else {
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318 | 2c0262af | bellard | if (!(pde & PG_ACCESSED_MASK)) {
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319 | 2c0262af | bellard | pde |= PG_ACCESSED_MASK; |
320 | 61382a50 | bellard | stl_raw(pde_ptr, pde); |
321 | 2c0262af | bellard | } |
322 | 2c0262af | bellard | |
323 | 2c0262af | bellard | /* page directory entry */
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324 | 461c0471 | bellard | pte_ptr = phys_ram_base + |
325 | 461c0471 | bellard | (((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & a20_mask); |
326 | 61382a50 | bellard | pte = ldl_raw(pte_ptr); |
327 | 2c0262af | bellard | if (!(pte & PG_PRESENT_MASK)) {
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328 | 2c0262af | bellard | error_code = 0;
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329 | 2c0262af | bellard | goto do_fault;
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330 | 2c0262af | bellard | } |
331 | 2c0262af | bellard | if (is_user) {
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332 | 2c0262af | bellard | if (!(pte & PG_USER_MASK))
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333 | 2c0262af | bellard | goto do_fault_protect;
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334 | 2c0262af | bellard | if (is_write && !(pte & PG_RW_MASK))
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335 | 2c0262af | bellard | goto do_fault_protect;
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336 | 2c0262af | bellard | } else {
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337 | 2c0262af | bellard | if ((env->cr[0] & CR0_WP_MASK) && (pte & PG_USER_MASK) && |
338 | 2c0262af | bellard | is_write && !(pte & PG_RW_MASK)) |
339 | 2c0262af | bellard | goto do_fault_protect;
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340 | 2c0262af | bellard | } |
341 | 2c0262af | bellard | is_dirty = is_write && !(pte & PG_DIRTY_MASK); |
342 | 2c0262af | bellard | if (!(pte & PG_ACCESSED_MASK) || is_dirty) {
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343 | 2c0262af | bellard | pte |= PG_ACCESSED_MASK; |
344 | 2c0262af | bellard | if (is_dirty)
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345 | 2c0262af | bellard | pte |= PG_DIRTY_MASK; |
346 | 61382a50 | bellard | stl_raw(pte_ptr, pte); |
347 | 2c0262af | bellard | } |
348 | 2c0262af | bellard | page_size = 4096;
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349 | 2c0262af | bellard | virt_addr = addr & ~0xfff;
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350 | 2c0262af | bellard | } |
351 | c8135d9a | bellard | |
352 | 2c0262af | bellard | /* the page can be put in the TLB */
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353 | 2c0262af | bellard | prot = PROT_READ; |
354 | c8135d9a | bellard | if (pte & PG_DIRTY_MASK) {
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355 | c8135d9a | bellard | /* only set write access if already dirty... otherwise wait
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356 | c8135d9a | bellard | for dirty access */
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357 | c8135d9a | bellard | if (is_user) {
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358 | c8135d9a | bellard | if (pte & PG_RW_MASK)
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359 | c8135d9a | bellard | prot |= PROT_WRITE; |
360 | c8135d9a | bellard | } else {
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361 | c8135d9a | bellard | if (!(env->cr[0] & CR0_WP_MASK) || !(pte & PG_USER_MASK) || |
362 | c8135d9a | bellard | (pte & PG_RW_MASK)) |
363 | c8135d9a | bellard | prot |= PROT_WRITE; |
364 | c8135d9a | bellard | } |
365 | 2c0262af | bellard | } |
366 | 777aca2f | bellard | |
367 | 2c0262af | bellard | do_mapping:
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368 | 461c0471 | bellard | pte = pte & a20_mask; |
369 | 2c0262af | bellard | |
370 | 436d8b89 | bellard | /* Even if 4MB pages, we map only one 4KB page in the cache to
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371 | 436d8b89 | bellard | avoid filling it too fast */
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372 | 436d8b89 | bellard | page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
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373 | 436d8b89 | bellard | paddr = (pte & TARGET_PAGE_MASK) + page_offset; |
374 | 436d8b89 | bellard | vaddr = virt_addr + page_offset; |
375 | 436d8b89 | bellard | |
376 | 436d8b89 | bellard | ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu); |
377 | 2c0262af | bellard | return ret;
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378 | 2c0262af | bellard | do_fault_protect:
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379 | 2c0262af | bellard | error_code = PG_ERROR_P_MASK; |
380 | 2c0262af | bellard | do_fault:
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381 | 2c0262af | bellard | env->cr[2] = addr;
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382 | 2c0262af | bellard | env->error_code = (is_write << PG_ERROR_W_BIT) | error_code; |
383 | 2c0262af | bellard | if (is_user)
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384 | 2c0262af | bellard | env->error_code |= PG_ERROR_U_MASK; |
385 | 2c0262af | bellard | return 1; |
386 | 2c0262af | bellard | } |