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1 | 7a3f1944 | bellard | /*
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2 | 7a3f1944 | bellard | SPARC translation
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3 | 7a3f1944 | bellard | |
4 | 7a3f1944 | bellard | Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
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5 | bd497938 | bellard | Copyright (C) 2003 Fabrice Bellard
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6 | 7a3f1944 | bellard | |
7 | 7a3f1944 | bellard | This library is free software; you can redistribute it and/or
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8 | 7a3f1944 | bellard | modify it under the terms of the GNU Lesser General Public
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9 | 7a3f1944 | bellard | License as published by the Free Software Foundation; either
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10 | 7a3f1944 | bellard | version 2 of the License, or (at your option) any later version.
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11 | 7a3f1944 | bellard | |
12 | 7a3f1944 | bellard | This library is distributed in the hope that it will be useful,
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13 | 7a3f1944 | bellard | but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 7a3f1944 | bellard | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 7a3f1944 | bellard | Lesser General Public License for more details.
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16 | 7a3f1944 | bellard | |
17 | 7a3f1944 | bellard | You should have received a copy of the GNU Lesser General Public
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18 | 7a3f1944 | bellard | License along with this library; if not, write to the Free Software
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19 | 7a3f1944 | bellard | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 | 7a3f1944 | bellard | */
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21 | 7a3f1944 | bellard | |
22 | 7a3f1944 | bellard | /*
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23 | 7a3f1944 | bellard | TODO-list:
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24 | 7a3f1944 | bellard | |
25 | bd497938 | bellard | NPC/PC static optimisations (use JUMP_TB when possible)
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26 | 7a3f1944 | bellard | FPU-Instructions
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27 | 7a3f1944 | bellard | Privileged instructions
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28 | bd497938 | bellard | Coprocessor-Instructions
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29 | 7a3f1944 | bellard | Optimize synthetic instructions
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30 | 7a3f1944 | bellard | Optional alignment and privileged instruction check
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31 | bd497938 | bellard | */
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32 | 7a3f1944 | bellard | |
33 | 7a3f1944 | bellard | #include <stdarg.h> |
34 | 7a3f1944 | bellard | #include <stdlib.h> |
35 | 7a3f1944 | bellard | #include <stdio.h> |
36 | 7a3f1944 | bellard | #include <string.h> |
37 | 7a3f1944 | bellard | #include <inttypes.h> |
38 | 7a3f1944 | bellard | |
39 | 7a3f1944 | bellard | #include "cpu.h" |
40 | 7a3f1944 | bellard | #include "exec-all.h" |
41 | 7a3f1944 | bellard | #include "disas.h" |
42 | 7a3f1944 | bellard | |
43 | 7a3f1944 | bellard | #define DEBUG_DISAS
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44 | 7a3f1944 | bellard | |
45 | 7a3f1944 | bellard | typedef struct DisasContext { |
46 | cf495bcf | bellard | uint8_t *pc; /* NULL means dynamic value */
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47 | cf495bcf | bellard | uint8_t *npc; /* NULL means dynamic value */
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48 | cf495bcf | bellard | int is_br;
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49 | cf495bcf | bellard | struct TranslationBlock *tb;
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50 | 7a3f1944 | bellard | } DisasContext; |
51 | 7a3f1944 | bellard | |
52 | 7a3f1944 | bellard | static uint16_t *gen_opc_ptr;
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53 | 7a3f1944 | bellard | static uint32_t *gen_opparam_ptr;
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54 | 7a3f1944 | bellard | extern FILE *logfile;
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55 | 7a3f1944 | bellard | extern int loglevel; |
56 | 7a3f1944 | bellard | |
57 | 7a3f1944 | bellard | enum {
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58 | 7a3f1944 | bellard | #define DEF(s,n,copy_size) INDEX_op_ ## s, |
59 | 7a3f1944 | bellard | #include "opc.h" |
60 | 7a3f1944 | bellard | #undef DEF
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61 | cf495bcf | bellard | NB_OPS |
62 | 7a3f1944 | bellard | }; |
63 | 7a3f1944 | bellard | |
64 | 7a3f1944 | bellard | #include "gen-op.h" |
65 | 7a3f1944 | bellard | |
66 | 7a3f1944 | bellard | #define GET_FIELD(X, FROM, TO) \
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67 | 7a3f1944 | bellard | ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1)) |
68 | 7a3f1944 | bellard | |
69 | 7a3f1944 | bellard | #define IS_IMM (insn & (1<<13)) |
70 | 7a3f1944 | bellard | |
71 | cf495bcf | bellard | static void disas_sparc_insn(DisasContext * dc); |
72 | 7a3f1944 | bellard | |
73 | 7a3f1944 | bellard | static GenOpFunc *gen_op_movl_TN_reg[2][32] = { |
74 | cf495bcf | bellard | { |
75 | cf495bcf | bellard | gen_op_movl_g0_T0, |
76 | cf495bcf | bellard | gen_op_movl_g1_T0, |
77 | cf495bcf | bellard | gen_op_movl_g2_T0, |
78 | cf495bcf | bellard | gen_op_movl_g3_T0, |
79 | cf495bcf | bellard | gen_op_movl_g4_T0, |
80 | cf495bcf | bellard | gen_op_movl_g5_T0, |
81 | cf495bcf | bellard | gen_op_movl_g6_T0, |
82 | cf495bcf | bellard | gen_op_movl_g7_T0, |
83 | cf495bcf | bellard | gen_op_movl_o0_T0, |
84 | cf495bcf | bellard | gen_op_movl_o1_T0, |
85 | cf495bcf | bellard | gen_op_movl_o2_T0, |
86 | cf495bcf | bellard | gen_op_movl_o3_T0, |
87 | cf495bcf | bellard | gen_op_movl_o4_T0, |
88 | cf495bcf | bellard | gen_op_movl_o5_T0, |
89 | cf495bcf | bellard | gen_op_movl_o6_T0, |
90 | cf495bcf | bellard | gen_op_movl_o7_T0, |
91 | cf495bcf | bellard | gen_op_movl_l0_T0, |
92 | cf495bcf | bellard | gen_op_movl_l1_T0, |
93 | cf495bcf | bellard | gen_op_movl_l2_T0, |
94 | cf495bcf | bellard | gen_op_movl_l3_T0, |
95 | cf495bcf | bellard | gen_op_movl_l4_T0, |
96 | cf495bcf | bellard | gen_op_movl_l5_T0, |
97 | cf495bcf | bellard | gen_op_movl_l6_T0, |
98 | cf495bcf | bellard | gen_op_movl_l7_T0, |
99 | cf495bcf | bellard | gen_op_movl_i0_T0, |
100 | cf495bcf | bellard | gen_op_movl_i1_T0, |
101 | cf495bcf | bellard | gen_op_movl_i2_T0, |
102 | cf495bcf | bellard | gen_op_movl_i3_T0, |
103 | cf495bcf | bellard | gen_op_movl_i4_T0, |
104 | cf495bcf | bellard | gen_op_movl_i5_T0, |
105 | cf495bcf | bellard | gen_op_movl_i6_T0, |
106 | cf495bcf | bellard | gen_op_movl_i7_T0, |
107 | cf495bcf | bellard | }, |
108 | cf495bcf | bellard | { |
109 | cf495bcf | bellard | gen_op_movl_g0_T1, |
110 | cf495bcf | bellard | gen_op_movl_g1_T1, |
111 | cf495bcf | bellard | gen_op_movl_g2_T1, |
112 | cf495bcf | bellard | gen_op_movl_g3_T1, |
113 | cf495bcf | bellard | gen_op_movl_g4_T1, |
114 | cf495bcf | bellard | gen_op_movl_g5_T1, |
115 | cf495bcf | bellard | gen_op_movl_g6_T1, |
116 | cf495bcf | bellard | gen_op_movl_g7_T1, |
117 | cf495bcf | bellard | gen_op_movl_o0_T1, |
118 | cf495bcf | bellard | gen_op_movl_o1_T1, |
119 | cf495bcf | bellard | gen_op_movl_o2_T1, |
120 | cf495bcf | bellard | gen_op_movl_o3_T1, |
121 | cf495bcf | bellard | gen_op_movl_o4_T1, |
122 | cf495bcf | bellard | gen_op_movl_o5_T1, |
123 | cf495bcf | bellard | gen_op_movl_o6_T1, |
124 | cf495bcf | bellard | gen_op_movl_o7_T1, |
125 | cf495bcf | bellard | gen_op_movl_l0_T1, |
126 | cf495bcf | bellard | gen_op_movl_l1_T1, |
127 | cf495bcf | bellard | gen_op_movl_l2_T1, |
128 | cf495bcf | bellard | gen_op_movl_l3_T1, |
129 | cf495bcf | bellard | gen_op_movl_l4_T1, |
130 | cf495bcf | bellard | gen_op_movl_l5_T1, |
131 | cf495bcf | bellard | gen_op_movl_l6_T1, |
132 | cf495bcf | bellard | gen_op_movl_l7_T1, |
133 | cf495bcf | bellard | gen_op_movl_i0_T1, |
134 | cf495bcf | bellard | gen_op_movl_i1_T1, |
135 | cf495bcf | bellard | gen_op_movl_i2_T1, |
136 | cf495bcf | bellard | gen_op_movl_i3_T1, |
137 | cf495bcf | bellard | gen_op_movl_i4_T1, |
138 | cf495bcf | bellard | gen_op_movl_i5_T1, |
139 | cf495bcf | bellard | gen_op_movl_i6_T1, |
140 | cf495bcf | bellard | gen_op_movl_i7_T1, |
141 | cf495bcf | bellard | } |
142 | 7a3f1944 | bellard | }; |
143 | 7a3f1944 | bellard | |
144 | 7a3f1944 | bellard | static GenOpFunc *gen_op_movl_reg_TN[3][32] = { |
145 | cf495bcf | bellard | { |
146 | cf495bcf | bellard | gen_op_movl_T0_g0, |
147 | cf495bcf | bellard | gen_op_movl_T0_g1, |
148 | cf495bcf | bellard | gen_op_movl_T0_g2, |
149 | cf495bcf | bellard | gen_op_movl_T0_g3, |
150 | cf495bcf | bellard | gen_op_movl_T0_g4, |
151 | cf495bcf | bellard | gen_op_movl_T0_g5, |
152 | cf495bcf | bellard | gen_op_movl_T0_g6, |
153 | cf495bcf | bellard | gen_op_movl_T0_g7, |
154 | cf495bcf | bellard | gen_op_movl_T0_o0, |
155 | cf495bcf | bellard | gen_op_movl_T0_o1, |
156 | cf495bcf | bellard | gen_op_movl_T0_o2, |
157 | cf495bcf | bellard | gen_op_movl_T0_o3, |
158 | cf495bcf | bellard | gen_op_movl_T0_o4, |
159 | cf495bcf | bellard | gen_op_movl_T0_o5, |
160 | cf495bcf | bellard | gen_op_movl_T0_o6, |
161 | cf495bcf | bellard | gen_op_movl_T0_o7, |
162 | cf495bcf | bellard | gen_op_movl_T0_l0, |
163 | cf495bcf | bellard | gen_op_movl_T0_l1, |
164 | cf495bcf | bellard | gen_op_movl_T0_l2, |
165 | cf495bcf | bellard | gen_op_movl_T0_l3, |
166 | cf495bcf | bellard | gen_op_movl_T0_l4, |
167 | cf495bcf | bellard | gen_op_movl_T0_l5, |
168 | cf495bcf | bellard | gen_op_movl_T0_l6, |
169 | cf495bcf | bellard | gen_op_movl_T0_l7, |
170 | cf495bcf | bellard | gen_op_movl_T0_i0, |
171 | cf495bcf | bellard | gen_op_movl_T0_i1, |
172 | cf495bcf | bellard | gen_op_movl_T0_i2, |
173 | cf495bcf | bellard | gen_op_movl_T0_i3, |
174 | cf495bcf | bellard | gen_op_movl_T0_i4, |
175 | cf495bcf | bellard | gen_op_movl_T0_i5, |
176 | cf495bcf | bellard | gen_op_movl_T0_i6, |
177 | cf495bcf | bellard | gen_op_movl_T0_i7, |
178 | cf495bcf | bellard | }, |
179 | cf495bcf | bellard | { |
180 | cf495bcf | bellard | gen_op_movl_T1_g0, |
181 | cf495bcf | bellard | gen_op_movl_T1_g1, |
182 | cf495bcf | bellard | gen_op_movl_T1_g2, |
183 | cf495bcf | bellard | gen_op_movl_T1_g3, |
184 | cf495bcf | bellard | gen_op_movl_T1_g4, |
185 | cf495bcf | bellard | gen_op_movl_T1_g5, |
186 | cf495bcf | bellard | gen_op_movl_T1_g6, |
187 | cf495bcf | bellard | gen_op_movl_T1_g7, |
188 | cf495bcf | bellard | gen_op_movl_T1_o0, |
189 | cf495bcf | bellard | gen_op_movl_T1_o1, |
190 | cf495bcf | bellard | gen_op_movl_T1_o2, |
191 | cf495bcf | bellard | gen_op_movl_T1_o3, |
192 | cf495bcf | bellard | gen_op_movl_T1_o4, |
193 | cf495bcf | bellard | gen_op_movl_T1_o5, |
194 | cf495bcf | bellard | gen_op_movl_T1_o6, |
195 | cf495bcf | bellard | gen_op_movl_T1_o7, |
196 | cf495bcf | bellard | gen_op_movl_T1_l0, |
197 | cf495bcf | bellard | gen_op_movl_T1_l1, |
198 | cf495bcf | bellard | gen_op_movl_T1_l2, |
199 | cf495bcf | bellard | gen_op_movl_T1_l3, |
200 | cf495bcf | bellard | gen_op_movl_T1_l4, |
201 | cf495bcf | bellard | gen_op_movl_T1_l5, |
202 | cf495bcf | bellard | gen_op_movl_T1_l6, |
203 | cf495bcf | bellard | gen_op_movl_T1_l7, |
204 | cf495bcf | bellard | gen_op_movl_T1_i0, |
205 | cf495bcf | bellard | gen_op_movl_T1_i1, |
206 | cf495bcf | bellard | gen_op_movl_T1_i2, |
207 | cf495bcf | bellard | gen_op_movl_T1_i3, |
208 | cf495bcf | bellard | gen_op_movl_T1_i4, |
209 | cf495bcf | bellard | gen_op_movl_T1_i5, |
210 | cf495bcf | bellard | gen_op_movl_T1_i6, |
211 | cf495bcf | bellard | gen_op_movl_T1_i7, |
212 | cf495bcf | bellard | }, |
213 | cf495bcf | bellard | { |
214 | cf495bcf | bellard | gen_op_movl_T2_g0, |
215 | cf495bcf | bellard | gen_op_movl_T2_g1, |
216 | cf495bcf | bellard | gen_op_movl_T2_g2, |
217 | cf495bcf | bellard | gen_op_movl_T2_g3, |
218 | cf495bcf | bellard | gen_op_movl_T2_g4, |
219 | cf495bcf | bellard | gen_op_movl_T2_g5, |
220 | cf495bcf | bellard | gen_op_movl_T2_g6, |
221 | cf495bcf | bellard | gen_op_movl_T2_g7, |
222 | cf495bcf | bellard | gen_op_movl_T2_o0, |
223 | cf495bcf | bellard | gen_op_movl_T2_o1, |
224 | cf495bcf | bellard | gen_op_movl_T2_o2, |
225 | cf495bcf | bellard | gen_op_movl_T2_o3, |
226 | cf495bcf | bellard | gen_op_movl_T2_o4, |
227 | cf495bcf | bellard | gen_op_movl_T2_o5, |
228 | cf495bcf | bellard | gen_op_movl_T2_o6, |
229 | cf495bcf | bellard | gen_op_movl_T2_o7, |
230 | cf495bcf | bellard | gen_op_movl_T2_l0, |
231 | cf495bcf | bellard | gen_op_movl_T2_l1, |
232 | cf495bcf | bellard | gen_op_movl_T2_l2, |
233 | cf495bcf | bellard | gen_op_movl_T2_l3, |
234 | cf495bcf | bellard | gen_op_movl_T2_l4, |
235 | cf495bcf | bellard | gen_op_movl_T2_l5, |
236 | cf495bcf | bellard | gen_op_movl_T2_l6, |
237 | cf495bcf | bellard | gen_op_movl_T2_l7, |
238 | cf495bcf | bellard | gen_op_movl_T2_i0, |
239 | cf495bcf | bellard | gen_op_movl_T2_i1, |
240 | cf495bcf | bellard | gen_op_movl_T2_i2, |
241 | cf495bcf | bellard | gen_op_movl_T2_i3, |
242 | cf495bcf | bellard | gen_op_movl_T2_i4, |
243 | cf495bcf | bellard | gen_op_movl_T2_i5, |
244 | cf495bcf | bellard | gen_op_movl_T2_i6, |
245 | cf495bcf | bellard | gen_op_movl_T2_i7, |
246 | cf495bcf | bellard | } |
247 | 7a3f1944 | bellard | }; |
248 | 7a3f1944 | bellard | |
249 | 7a3f1944 | bellard | static GenOpFunc1 *gen_op_movl_TN_im[3] = { |
250 | cf495bcf | bellard | gen_op_movl_T0_im, |
251 | cf495bcf | bellard | gen_op_movl_T1_im, |
252 | cf495bcf | bellard | gen_op_movl_T2_im |
253 | 7a3f1944 | bellard | }; |
254 | 7a3f1944 | bellard | |
255 | cf495bcf | bellard | static inline void gen_movl_imm_TN(int reg, int imm) |
256 | 7a3f1944 | bellard | { |
257 | cf495bcf | bellard | gen_op_movl_TN_im[reg] (imm); |
258 | 7a3f1944 | bellard | } |
259 | 7a3f1944 | bellard | |
260 | cf495bcf | bellard | static inline void gen_movl_imm_T1(int val) |
261 | 7a3f1944 | bellard | { |
262 | cf495bcf | bellard | gen_movl_imm_TN(1, val);
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263 | 7a3f1944 | bellard | } |
264 | 7a3f1944 | bellard | |
265 | cf495bcf | bellard | static inline void gen_movl_imm_T0(int val) |
266 | 7a3f1944 | bellard | { |
267 | cf495bcf | bellard | gen_movl_imm_TN(0, val);
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268 | 7a3f1944 | bellard | } |
269 | 7a3f1944 | bellard | |
270 | cf495bcf | bellard | static inline void gen_movl_reg_TN(int reg, int t) |
271 | 7a3f1944 | bellard | { |
272 | cf495bcf | bellard | if (reg)
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273 | cf495bcf | bellard | gen_op_movl_reg_TN[t][reg] (); |
274 | cf495bcf | bellard | else
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275 | cf495bcf | bellard | gen_movl_imm_TN(t, 0);
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276 | 7a3f1944 | bellard | } |
277 | 7a3f1944 | bellard | |
278 | cf495bcf | bellard | static inline void gen_movl_reg_T0(int reg) |
279 | 7a3f1944 | bellard | { |
280 | cf495bcf | bellard | gen_movl_reg_TN(reg, 0);
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281 | 7a3f1944 | bellard | } |
282 | 7a3f1944 | bellard | |
283 | cf495bcf | bellard | static inline void gen_movl_reg_T1(int reg) |
284 | 7a3f1944 | bellard | { |
285 | cf495bcf | bellard | gen_movl_reg_TN(reg, 1);
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286 | 7a3f1944 | bellard | } |
287 | 7a3f1944 | bellard | |
288 | cf495bcf | bellard | static inline void gen_movl_reg_T2(int reg) |
289 | 7a3f1944 | bellard | { |
290 | cf495bcf | bellard | gen_movl_reg_TN(reg, 2);
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291 | 7a3f1944 | bellard | } |
292 | 7a3f1944 | bellard | |
293 | cf495bcf | bellard | static inline void gen_movl_TN_reg(int reg, int t) |
294 | 7a3f1944 | bellard | { |
295 | cf495bcf | bellard | if (reg)
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296 | cf495bcf | bellard | gen_op_movl_TN_reg[t][reg] (); |
297 | 7a3f1944 | bellard | } |
298 | 7a3f1944 | bellard | |
299 | cf495bcf | bellard | static inline void gen_movl_T0_reg(int reg) |
300 | 7a3f1944 | bellard | { |
301 | cf495bcf | bellard | gen_movl_TN_reg(reg, 0);
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302 | 7a3f1944 | bellard | } |
303 | 7a3f1944 | bellard | |
304 | cf495bcf | bellard | static inline void gen_movl_T1_reg(int reg) |
305 | 7a3f1944 | bellard | { |
306 | cf495bcf | bellard | gen_movl_TN_reg(reg, 1);
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307 | 7a3f1944 | bellard | } |
308 | 7a3f1944 | bellard | |
309 | cf495bcf | bellard | static void gen_cond(int cond) |
310 | 7a3f1944 | bellard | { |
311 | 7a3f1944 | bellard | switch (cond) {
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312 | cf495bcf | bellard | case 0x0: |
313 | cf495bcf | bellard | gen_op_movl_T2_0(); |
314 | cf495bcf | bellard | break;
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315 | cf495bcf | bellard | case 0x1: |
316 | cf495bcf | bellard | gen_op_eval_be(); |
317 | cf495bcf | bellard | break;
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318 | cf495bcf | bellard | case 0x2: |
319 | cf495bcf | bellard | gen_op_eval_ble(); |
320 | cf495bcf | bellard | break;
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321 | cf495bcf | bellard | case 0x3: |
322 | cf495bcf | bellard | gen_op_eval_bl(); |
323 | cf495bcf | bellard | break;
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324 | cf495bcf | bellard | case 0x4: |
325 | cf495bcf | bellard | gen_op_eval_bleu(); |
326 | cf495bcf | bellard | break;
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327 | cf495bcf | bellard | case 0x5: |
328 | cf495bcf | bellard | gen_op_eval_bcs(); |
329 | cf495bcf | bellard | break;
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330 | cf495bcf | bellard | case 0x6: |
331 | cf495bcf | bellard | gen_op_eval_bneg(); |
332 | cf495bcf | bellard | break;
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333 | cf495bcf | bellard | case 0x7: |
334 | cf495bcf | bellard | gen_op_eval_bvs(); |
335 | cf495bcf | bellard | break;
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336 | cf495bcf | bellard | case 0x8: |
337 | cf495bcf | bellard | gen_op_movl_T2_1(); |
338 | cf495bcf | bellard | break;
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339 | cf495bcf | bellard | case 0x9: |
340 | cf495bcf | bellard | gen_op_eval_bne(); |
341 | cf495bcf | bellard | break;
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342 | cf495bcf | bellard | case 0xa: |
343 | cf495bcf | bellard | gen_op_eval_bg(); |
344 | cf495bcf | bellard | break;
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345 | cf495bcf | bellard | case 0xb: |
346 | cf495bcf | bellard | gen_op_eval_bge(); |
347 | cf495bcf | bellard | break;
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348 | cf495bcf | bellard | case 0xc: |
349 | cf495bcf | bellard | gen_op_eval_bgu(); |
350 | cf495bcf | bellard | break;
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351 | cf495bcf | bellard | case 0xd: |
352 | cf495bcf | bellard | gen_op_eval_bcc(); |
353 | cf495bcf | bellard | break;
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354 | cf495bcf | bellard | case 0xe: |
355 | cf495bcf | bellard | gen_op_eval_bpos(); |
356 | cf495bcf | bellard | break;
|
357 | cf495bcf | bellard | default:
|
358 | cf495bcf | bellard | case 0xf: |
359 | cf495bcf | bellard | gen_op_eval_bvc(); |
360 | cf495bcf | bellard | break;
|
361 | 7a3f1944 | bellard | } |
362 | 7a3f1944 | bellard | } |
363 | 7a3f1944 | bellard | |
364 | cf495bcf | bellard | |
365 | cf495bcf | bellard | static void do_branch(DisasContext * dc, uint32_t target, uint32_t insn) |
366 | 7a3f1944 | bellard | { |
367 | cf495bcf | bellard | unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); |
368 | cf495bcf | bellard | target += (uint32_t) dc->pc; |
369 | cf495bcf | bellard | if (cond == 0x0) { |
370 | cf495bcf | bellard | /* unconditional not taken */
|
371 | cf495bcf | bellard | if (a) {
|
372 | cf495bcf | bellard | dc->pc = dc->npc + 4;
|
373 | cf495bcf | bellard | dc->npc = dc->pc + 4;
|
374 | cf495bcf | bellard | } else {
|
375 | cf495bcf | bellard | dc->pc = dc->npc; |
376 | cf495bcf | bellard | dc->npc = dc->pc + 4;
|
377 | cf495bcf | bellard | } |
378 | cf495bcf | bellard | } else if (cond == 0x8) { |
379 | cf495bcf | bellard | /* unconditional taken */
|
380 | cf495bcf | bellard | if (a) {
|
381 | cf495bcf | bellard | dc->pc = (uint8_t *) target; |
382 | cf495bcf | bellard | dc->npc = dc->pc + 4;
|
383 | cf495bcf | bellard | } else {
|
384 | cf495bcf | bellard | dc->pc = dc->npc; |
385 | cf495bcf | bellard | dc->npc = (uint8_t *) target; |
386 | cf495bcf | bellard | } |
387 | cf495bcf | bellard | } else {
|
388 | cf495bcf | bellard | gen_cond(cond); |
389 | cf495bcf | bellard | if (a) {
|
390 | cf495bcf | bellard | gen_op_generic_branch_a((uint32_t) target, |
391 | cf495bcf | bellard | (uint32_t) (dc->npc)); |
392 | cf495bcf | bellard | dc->is_br = 1;
|
393 | cf495bcf | bellard | dc->pc = NULL;
|
394 | cf495bcf | bellard | dc->npc = NULL;
|
395 | cf495bcf | bellard | } else {
|
396 | cf495bcf | bellard | dc->pc = dc->npc; |
397 | cf495bcf | bellard | gen_op_generic_branch((uint32_t) target, |
398 | cf495bcf | bellard | (uint32_t) (dc->npc + 4));
|
399 | cf495bcf | bellard | dc->npc = NULL;
|
400 | cf495bcf | bellard | } |
401 | cf495bcf | bellard | } |
402 | 7a3f1944 | bellard | } |
403 | 7a3f1944 | bellard | |
404 | cf495bcf | bellard | #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1) |
405 | 7a3f1944 | bellard | |
406 | cf495bcf | bellard | static int sign_extend(int x, int len) |
407 | 7a3f1944 | bellard | { |
408 | cf495bcf | bellard | len = 32 - len;
|
409 | cf495bcf | bellard | return (x << len) >> len;
|
410 | 7a3f1944 | bellard | } |
411 | 7a3f1944 | bellard | |
412 | cf495bcf | bellard | static inline void save_state(DisasContext * dc) |
413 | 7a3f1944 | bellard | { |
414 | cf495bcf | bellard | gen_op_jmp_im((uint32_t)dc->pc); |
415 | cf495bcf | bellard | if (dc->npc != NULL) |
416 | cf495bcf | bellard | gen_op_movl_npc_im((long) dc->npc);
|
417 | cf495bcf | bellard | } |
418 | 7a3f1944 | bellard | |
419 | cf495bcf | bellard | static void disas_sparc_insn(DisasContext * dc) |
420 | cf495bcf | bellard | { |
421 | cf495bcf | bellard | unsigned int insn, opc, rs1, rs2, rd; |
422 | 7a3f1944 | bellard | |
423 | cf495bcf | bellard | insn = ldl_code(dc->pc); |
424 | cf495bcf | bellard | opc = GET_FIELD(insn, 0, 1); |
425 | 7a3f1944 | bellard | |
426 | cf495bcf | bellard | rd = GET_FIELD(insn, 2, 6); |
427 | cf495bcf | bellard | switch (opc) {
|
428 | cf495bcf | bellard | case 0: /* branches/sethi */ |
429 | cf495bcf | bellard | { |
430 | cf495bcf | bellard | unsigned int xop = GET_FIELD(insn, 7, 9); |
431 | cf495bcf | bellard | int target;
|
432 | cf495bcf | bellard | target = GET_FIELD(insn, 10, 31); |
433 | cf495bcf | bellard | switch (xop) {
|
434 | cf495bcf | bellard | case 0x0: |
435 | cf495bcf | bellard | case 0x1: /* UNIMPL */ |
436 | cf495bcf | bellard | goto illegal_insn;
|
437 | cf495bcf | bellard | case 0x2: /* BN+x */ |
438 | 7a3f1944 | bellard | { |
439 | cf495bcf | bellard | target <<= 2;
|
440 | cf495bcf | bellard | target = sign_extend(target, 22);
|
441 | cf495bcf | bellard | do_branch(dc, target, insn); |
442 | cf495bcf | bellard | goto jmp_insn;
|
443 | 7a3f1944 | bellard | } |
444 | cf495bcf | bellard | case 0x3: /* FBN+x */ |
445 | cf495bcf | bellard | break;
|
446 | cf495bcf | bellard | case 0x4: /* SETHI */ |
447 | cf495bcf | bellard | gen_movl_imm_T0(target << 10);
|
448 | cf495bcf | bellard | gen_movl_T0_reg(rd); |
449 | cf495bcf | bellard | break;
|
450 | cf495bcf | bellard | case 0x5: /*CBN+x */ |
451 | cf495bcf | bellard | break;
|
452 | cf495bcf | bellard | } |
453 | cf495bcf | bellard | break;
|
454 | cf495bcf | bellard | } |
455 | cf495bcf | bellard | case 1: |
456 | cf495bcf | bellard | /*CALL*/ {
|
457 | cf495bcf | bellard | unsigned int target = GET_FIELDs(insn, 2, 31) << 2; |
458 | cf495bcf | bellard | |
459 | cf495bcf | bellard | gen_op_movl_T0_im((long) (dc->pc));
|
460 | cf495bcf | bellard | gen_movl_T0_reg(15);
|
461 | cf495bcf | bellard | target = (long) dc->pc + target;
|
462 | cf495bcf | bellard | dc->pc = dc->npc; |
463 | cf495bcf | bellard | dc->npc = (uint8_t *) target; |
464 | cf495bcf | bellard | } |
465 | cf495bcf | bellard | goto jmp_insn;
|
466 | cf495bcf | bellard | case 2: /* FPU & Logical Operations */ |
467 | cf495bcf | bellard | { |
468 | cf495bcf | bellard | unsigned int xop = GET_FIELD(insn, 7, 12); |
469 | cf495bcf | bellard | if (xop == 0x3a) { /* generate trap */ |
470 | cf495bcf | bellard | int cond;
|
471 | cf495bcf | bellard | rs1 = GET_FIELD(insn, 13, 17); |
472 | cf495bcf | bellard | gen_movl_reg_T0(rs1); |
473 | cf495bcf | bellard | if (IS_IMM) {
|
474 | cf495bcf | bellard | gen_movl_imm_T1(GET_FIELD(insn, 25, 31)); |
475 | cf495bcf | bellard | } else {
|
476 | cf495bcf | bellard | rs2 = GET_FIELD(insn, 27, 31); |
477 | cf495bcf | bellard | gen_movl_reg_T1(rs2); |
478 | cf495bcf | bellard | } |
479 | cf495bcf | bellard | gen_op_add_T1_T0(); |
480 | cf495bcf | bellard | save_state(dc); |
481 | cf495bcf | bellard | cond = GET_FIELD(insn, 3, 6); |
482 | cf495bcf | bellard | if (cond == 0x8) { |
483 | cf495bcf | bellard | gen_op_trap_T0(); |
484 | cf495bcf | bellard | dc->is_br = 1;
|
485 | cf495bcf | bellard | goto jmp_insn;
|
486 | cf495bcf | bellard | } else {
|
487 | cf495bcf | bellard | gen_op_trapcc_T0(); |
488 | cf495bcf | bellard | } |
489 | cf495bcf | bellard | } else if (xop == 0x28) { |
490 | cf495bcf | bellard | rs1 = GET_FIELD(insn, 13, 17); |
491 | cf495bcf | bellard | switch(rs1) {
|
492 | cf495bcf | bellard | case 0: /* rdy */ |
493 | cf495bcf | bellard | gen_op_rdy(); |
494 | cf495bcf | bellard | gen_movl_T0_reg(rd); |
495 | cf495bcf | bellard | break;
|
496 | cf495bcf | bellard | default:
|
497 | cf495bcf | bellard | goto illegal_insn;
|
498 | cf495bcf | bellard | } |
499 | cf495bcf | bellard | } else if (xop == 0x34 || xop == 0x35) { /* FPU Operations */ |
500 | cf495bcf | bellard | goto illegal_insn;
|
501 | cf495bcf | bellard | } else {
|
502 | cf495bcf | bellard | rs1 = GET_FIELD(insn, 13, 17); |
503 | cf495bcf | bellard | gen_movl_reg_T0(rs1); |
504 | cf495bcf | bellard | if (IS_IMM) { /* immediate */ |
505 | cf495bcf | bellard | rs2 = GET_FIELDs(insn, 19, 31); |
506 | cf495bcf | bellard | gen_movl_imm_T1(rs2); |
507 | cf495bcf | bellard | } else { /* register */ |
508 | cf495bcf | bellard | rs2 = GET_FIELD(insn, 27, 31); |
509 | cf495bcf | bellard | gen_movl_reg_T1(rs2); |
510 | cf495bcf | bellard | } |
511 | cf495bcf | bellard | if (xop < 0x20) { |
512 | cf495bcf | bellard | switch (xop & ~0x10) { |
513 | cf495bcf | bellard | case 0x0: |
514 | cf495bcf | bellard | if (xop & 0x10) |
515 | cf495bcf | bellard | gen_op_add_T1_T0_cc(); |
516 | cf495bcf | bellard | else
|
517 | cf495bcf | bellard | gen_op_add_T1_T0(); |
518 | cf495bcf | bellard | break;
|
519 | cf495bcf | bellard | case 0x1: |
520 | cf495bcf | bellard | gen_op_and_T1_T0(); |
521 | cf495bcf | bellard | if (xop & 0x10) |
522 | cf495bcf | bellard | gen_op_logic_T0_cc(); |
523 | cf495bcf | bellard | break;
|
524 | cf495bcf | bellard | case 0x2: |
525 | cf495bcf | bellard | gen_op_or_T1_T0(); |
526 | cf495bcf | bellard | if (xop & 0x10) |
527 | cf495bcf | bellard | gen_op_logic_T0_cc(); |
528 | cf495bcf | bellard | break;
|
529 | cf495bcf | bellard | case 0x3: |
530 | cf495bcf | bellard | gen_op_xor_T1_T0(); |
531 | cf495bcf | bellard | if (xop & 0x10) |
532 | cf495bcf | bellard | gen_op_logic_T0_cc(); |
533 | cf495bcf | bellard | break;
|
534 | cf495bcf | bellard | case 0x4: |
535 | cf495bcf | bellard | if (xop & 0x10) |
536 | cf495bcf | bellard | gen_op_sub_T1_T0_cc(); |
537 | cf495bcf | bellard | else
|
538 | cf495bcf | bellard | gen_op_sub_T1_T0(); |
539 | cf495bcf | bellard | break;
|
540 | cf495bcf | bellard | case 0x5: |
541 | cf495bcf | bellard | gen_op_andn_T1_T0(); |
542 | cf495bcf | bellard | if (xop & 0x10) |
543 | cf495bcf | bellard | gen_op_logic_T0_cc(); |
544 | cf495bcf | bellard | break;
|
545 | cf495bcf | bellard | case 0x6: |
546 | cf495bcf | bellard | gen_op_orn_T1_T0(); |
547 | cf495bcf | bellard | if (xop & 0x10) |
548 | cf495bcf | bellard | gen_op_logic_T0_cc(); |
549 | cf495bcf | bellard | break;
|
550 | cf495bcf | bellard | case 0x7: |
551 | cf495bcf | bellard | gen_op_xnor_T1_T0(); |
552 | cf495bcf | bellard | if (xop & 0x10) |
553 | cf495bcf | bellard | gen_op_logic_T0_cc(); |
554 | cf495bcf | bellard | break;
|
555 | cf495bcf | bellard | case 0x8: |
556 | cf495bcf | bellard | gen_op_addx_T1_T0(); |
557 | cf495bcf | bellard | if (xop & 0x10) |
558 | cf495bcf | bellard | gen_op_set_flags(); |
559 | cf495bcf | bellard | break;
|
560 | cf495bcf | bellard | case 0xa: |
561 | cf495bcf | bellard | gen_op_umul_T1_T0(); |
562 | cf495bcf | bellard | if (xop & 0x10) |
563 | cf495bcf | bellard | gen_op_logic_T0_cc(); |
564 | cf495bcf | bellard | break;
|
565 | cf495bcf | bellard | case 0xb: |
566 | cf495bcf | bellard | gen_op_smul_T1_T0(); |
567 | cf495bcf | bellard | if (xop & 0x10) |
568 | cf495bcf | bellard | gen_op_logic_T0_cc(); |
569 | cf495bcf | bellard | break;
|
570 | cf495bcf | bellard | case 0xc: |
571 | cf495bcf | bellard | gen_op_subx_T1_T0(); |
572 | cf495bcf | bellard | if (xop & 0x10) |
573 | cf495bcf | bellard | gen_op_set_flags(); |
574 | cf495bcf | bellard | break;
|
575 | cf495bcf | bellard | case 0xe: |
576 | cf495bcf | bellard | gen_op_udiv_T1_T0(); |
577 | cf495bcf | bellard | if (xop & 0x10) |
578 | cf495bcf | bellard | gen_op_div_cc(); |
579 | cf495bcf | bellard | break;
|
580 | cf495bcf | bellard | case 0xf: |
581 | cf495bcf | bellard | gen_op_sdiv_T1_T0(); |
582 | cf495bcf | bellard | if (xop & 0x10) |
583 | cf495bcf | bellard | gen_op_div_cc(); |
584 | cf495bcf | bellard | break;
|
585 | cf495bcf | bellard | default:
|
586 | cf495bcf | bellard | goto illegal_insn;
|
587 | cf495bcf | bellard | } |
588 | cf495bcf | bellard | gen_movl_T0_reg(rd); |
589 | cf495bcf | bellard | } else {
|
590 | cf495bcf | bellard | switch (xop) {
|
591 | cf495bcf | bellard | case 0x24: /* mulscc */ |
592 | cf495bcf | bellard | gen_op_mulscc_T1_T0(); |
593 | cf495bcf | bellard | gen_movl_T0_reg(rd); |
594 | cf495bcf | bellard | break;
|
595 | cf495bcf | bellard | case 0x25: /* SLL */ |
596 | cf495bcf | bellard | gen_op_sll(); |
597 | cf495bcf | bellard | gen_movl_T0_reg(rd); |
598 | cf495bcf | bellard | break;
|
599 | cf495bcf | bellard | case 0x26: |
600 | cf495bcf | bellard | gen_op_srl(); |
601 | cf495bcf | bellard | gen_movl_T0_reg(rd); |
602 | cf495bcf | bellard | break;
|
603 | cf495bcf | bellard | case 0x27: |
604 | cf495bcf | bellard | gen_op_sra(); |
605 | cf495bcf | bellard | gen_movl_T0_reg(rd); |
606 | cf495bcf | bellard | break;
|
607 | cf495bcf | bellard | case 0x30: |
608 | cf495bcf | bellard | { |
609 | cf495bcf | bellard | gen_op_xor_T1_T0(); |
610 | cf495bcf | bellard | switch(rd) {
|
611 | cf495bcf | bellard | case 0: |
612 | cf495bcf | bellard | gen_op_wry(); |
613 | cf495bcf | bellard | break;
|
614 | cf495bcf | bellard | default:
|
615 | cf495bcf | bellard | goto illegal_insn;
|
616 | cf495bcf | bellard | } |
617 | cf495bcf | bellard | } |
618 | cf495bcf | bellard | break;
|
619 | cf495bcf | bellard | case 0x38: /* jmpl */ |
620 | cf495bcf | bellard | { |
621 | cf495bcf | bellard | gen_op_add_T1_T0(); |
622 | cf495bcf | bellard | gen_op_movl_npc_T0(); |
623 | cf495bcf | bellard | if (rd != 0) { |
624 | cf495bcf | bellard | gen_op_movl_T0_im((long) (dc->pc));
|
625 | cf495bcf | bellard | gen_movl_T0_reg(rd); |
626 | cf495bcf | bellard | } |
627 | cf495bcf | bellard | dc->pc = dc->npc; |
628 | cf495bcf | bellard | dc->npc = NULL;
|
629 | cf495bcf | bellard | } |
630 | cf495bcf | bellard | goto jmp_insn;
|
631 | cf495bcf | bellard | case 0x3b: /* flush */ |
632 | cf495bcf | bellard | /* nothing to do */
|
633 | cf495bcf | bellard | break;
|
634 | cf495bcf | bellard | case 0x3c: /* save */ |
635 | cf495bcf | bellard | save_state(dc); |
636 | cf495bcf | bellard | gen_op_add_T1_T0(); |
637 | cf495bcf | bellard | gen_op_save(); |
638 | cf495bcf | bellard | gen_movl_T0_reg(rd); |
639 | cf495bcf | bellard | break;
|
640 | cf495bcf | bellard | case 0x3d: /* restore */ |
641 | cf495bcf | bellard | save_state(dc); |
642 | cf495bcf | bellard | gen_op_add_T1_T0(); |
643 | cf495bcf | bellard | gen_op_restore(); |
644 | cf495bcf | bellard | gen_movl_T0_reg(rd); |
645 | cf495bcf | bellard | break;
|
646 | cf495bcf | bellard | default:
|
647 | cf495bcf | bellard | goto illegal_insn;
|
648 | cf495bcf | bellard | } |
649 | cf495bcf | bellard | } |
650 | cf495bcf | bellard | } |
651 | cf495bcf | bellard | break;
|
652 | cf495bcf | bellard | } |
653 | cf495bcf | bellard | case 3: /* load/store instructions */ |
654 | cf495bcf | bellard | { |
655 | cf495bcf | bellard | unsigned int xop = GET_FIELD(insn, 7, 12); |
656 | cf495bcf | bellard | rs1 = GET_FIELD(insn, 13, 17); |
657 | cf495bcf | bellard | gen_movl_reg_T0(rs1); |
658 | cf495bcf | bellard | if (IS_IMM) { /* immediate */ |
659 | cf495bcf | bellard | rs2 = GET_FIELDs(insn, 19, 31); |
660 | cf495bcf | bellard | gen_movl_imm_T1(rs2); |
661 | cf495bcf | bellard | } else { /* register */ |
662 | cf495bcf | bellard | rs2 = GET_FIELD(insn, 27, 31); |
663 | cf495bcf | bellard | gen_movl_reg_T1(rs2); |
664 | cf495bcf | bellard | } |
665 | cf495bcf | bellard | gen_op_add_T1_T0(); |
666 | cf495bcf | bellard | if (xop < 4 || xop > 7) { |
667 | cf495bcf | bellard | switch (xop) {
|
668 | cf495bcf | bellard | case 0x0: /* load word */ |
669 | cf495bcf | bellard | gen_op_ld(); |
670 | cf495bcf | bellard | break;
|
671 | cf495bcf | bellard | case 0x1: /* load unsigned byte */ |
672 | cf495bcf | bellard | gen_op_ldub(); |
673 | cf495bcf | bellard | break;
|
674 | cf495bcf | bellard | case 0x2: /* load unsigned halfword */ |
675 | cf495bcf | bellard | gen_op_lduh(); |
676 | cf495bcf | bellard | break;
|
677 | cf495bcf | bellard | case 0x3: /* load double word */ |
678 | cf495bcf | bellard | gen_op_ldd(); |
679 | cf495bcf | bellard | gen_movl_T0_reg(rd + 1);
|
680 | cf495bcf | bellard | break;
|
681 | cf495bcf | bellard | case 0x9: /* load signed byte */ |
682 | cf495bcf | bellard | gen_op_ldsb(); |
683 | cf495bcf | bellard | break;
|
684 | cf495bcf | bellard | case 0xa: /* load signed halfword */ |
685 | cf495bcf | bellard | gen_op_ldsh(); |
686 | cf495bcf | bellard | break;
|
687 | cf495bcf | bellard | case 0xd: /* ldstub -- XXX: should be atomically */ |
688 | cf495bcf | bellard | gen_op_ldstub(); |
689 | cf495bcf | bellard | break;
|
690 | cf495bcf | bellard | case 0x0f: /* swap register with memory. Also atomically */ |
691 | cf495bcf | bellard | gen_op_swap(); |
692 | cf495bcf | bellard | break;
|
693 | 7a3f1944 | bellard | } |
694 | cf495bcf | bellard | gen_movl_T1_reg(rd); |
695 | cf495bcf | bellard | } else if (xop < 8) { |
696 | cf495bcf | bellard | gen_movl_reg_T1(rd); |
697 | cf495bcf | bellard | switch (xop) {
|
698 | cf495bcf | bellard | case 0x4: |
699 | cf495bcf | bellard | gen_op_st(); |
700 | cf495bcf | bellard | break;
|
701 | cf495bcf | bellard | case 0x5: |
702 | cf495bcf | bellard | gen_op_stb(); |
703 | cf495bcf | bellard | break;
|
704 | cf495bcf | bellard | case 0x6: |
705 | cf495bcf | bellard | gen_op_sth(); |
706 | cf495bcf | bellard | break;
|
707 | cf495bcf | bellard | case 0x7: |
708 | cf495bcf | bellard | gen_movl_reg_T2(rd + 1);
|
709 | cf495bcf | bellard | gen_op_std(); |
710 | cf495bcf | bellard | break;
|
711 | 7a3f1944 | bellard | } |
712 | cf495bcf | bellard | } |
713 | 7a3f1944 | bellard | } |
714 | cf495bcf | bellard | } |
715 | cf495bcf | bellard | /* default case for non jump instructions */
|
716 | cf495bcf | bellard | if (dc->npc != NULL) { |
717 | cf495bcf | bellard | dc->pc = dc->npc; |
718 | cf495bcf | bellard | dc->npc = dc->npc + 4;
|
719 | cf495bcf | bellard | } else {
|
720 | cf495bcf | bellard | dc->pc = NULL;
|
721 | cf495bcf | bellard | gen_op_next_insn(); |
722 | cf495bcf | bellard | } |
723 | cf495bcf | bellard | jmp_insn:;
|
724 | cf495bcf | bellard | return;
|
725 | cf495bcf | bellard | illegal_insn:
|
726 | cf495bcf | bellard | gen_op_jmp_im((uint32_t)dc->pc); |
727 | cf495bcf | bellard | if (dc->npc != NULL) |
728 | cf495bcf | bellard | gen_op_movl_npc_im((long) dc->npc);
|
729 | cf495bcf | bellard | gen_op_exception(TT_ILL_INSN); |
730 | cf495bcf | bellard | dc->is_br = 1;
|
731 | 7a3f1944 | bellard | } |
732 | 7a3f1944 | bellard | |
733 | cf495bcf | bellard | static inline int gen_intermediate_code_internal(TranslationBlock * tb, |
734 | cf495bcf | bellard | int spc)
|
735 | 7a3f1944 | bellard | { |
736 | cf495bcf | bellard | uint8_t *pc_start, *last_pc; |
737 | cf495bcf | bellard | uint16_t *gen_opc_end; |
738 | cf495bcf | bellard | DisasContext dc1, *dc = &dc1; |
739 | cf495bcf | bellard | |
740 | cf495bcf | bellard | memset(dc, 0, sizeof(DisasContext)); |
741 | cf495bcf | bellard | if (spc) {
|
742 | cf495bcf | bellard | printf("SearchPC not yet supported\n");
|
743 | cf495bcf | bellard | exit(0);
|
744 | cf495bcf | bellard | } |
745 | cf495bcf | bellard | dc->tb = tb; |
746 | cf495bcf | bellard | pc_start = (uint8_t *) tb->pc; |
747 | cf495bcf | bellard | dc->pc = pc_start; |
748 | cf495bcf | bellard | dc->npc = (uint8_t *) tb->cs_base; |
749 | cf495bcf | bellard | |
750 | cf495bcf | bellard | gen_opc_ptr = gen_opc_buf; |
751 | cf495bcf | bellard | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
752 | cf495bcf | bellard | gen_opparam_ptr = gen_opparam_buf; |
753 | cf495bcf | bellard | |
754 | cf495bcf | bellard | do {
|
755 | cf495bcf | bellard | last_pc = dc->pc; |
756 | cf495bcf | bellard | disas_sparc_insn(dc); |
757 | cf495bcf | bellard | if (dc->is_br)
|
758 | cf495bcf | bellard | break;
|
759 | cf495bcf | bellard | /* if the next PC is different, we abort now */
|
760 | cf495bcf | bellard | if (dc->pc != (last_pc + 4)) |
761 | cf495bcf | bellard | break;
|
762 | cf495bcf | bellard | } while ((gen_opc_ptr < gen_opc_end) &&
|
763 | cf495bcf | bellard | (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
|
764 | cf495bcf | bellard | if (dc->pc != NULL) |
765 | cf495bcf | bellard | gen_op_jmp_im((long) dc->pc);
|
766 | cf495bcf | bellard | if (dc->npc != NULL) |
767 | cf495bcf | bellard | gen_op_movl_npc_im((long) dc->npc);
|
768 | cf495bcf | bellard | gen_op_movl_T0_0(); |
769 | cf495bcf | bellard | gen_op_exit_tb(); |
770 | cf495bcf | bellard | |
771 | cf495bcf | bellard | *gen_opc_ptr = INDEX_op_end; |
772 | 7a3f1944 | bellard | #ifdef DEBUG_DISAS
|
773 | cf495bcf | bellard | if (loglevel) {
|
774 | cf495bcf | bellard | fprintf(logfile, "--------------\n");
|
775 | cf495bcf | bellard | fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
|
776 | cf495bcf | bellard | disas(logfile, pc_start, last_pc + 4 - pc_start, 0, 0); |
777 | cf495bcf | bellard | fprintf(logfile, "\n");
|
778 | cf495bcf | bellard | fprintf(logfile, "OP:\n");
|
779 | cf495bcf | bellard | dump_ops(gen_opc_buf, gen_opparam_buf); |
780 | cf495bcf | bellard | fprintf(logfile, "\n");
|
781 | cf495bcf | bellard | } |
782 | 7a3f1944 | bellard | #endif
|
783 | 7a3f1944 | bellard | |
784 | cf495bcf | bellard | return 0; |
785 | 7a3f1944 | bellard | } |
786 | 7a3f1944 | bellard | |
787 | cf495bcf | bellard | int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
|
788 | 7a3f1944 | bellard | { |
789 | cf495bcf | bellard | return gen_intermediate_code_internal(tb, 0); |
790 | 7a3f1944 | bellard | } |
791 | 7a3f1944 | bellard | |
792 | cf495bcf | bellard | int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
|
793 | 7a3f1944 | bellard | { |
794 | cf495bcf | bellard | return gen_intermediate_code_internal(tb, 1); |
795 | 7a3f1944 | bellard | } |
796 | 7a3f1944 | bellard | |
797 | cf495bcf | bellard | CPUSPARCState *cpu_sparc_init(void)
|
798 | 7a3f1944 | bellard | { |
799 | cf495bcf | bellard | CPUSPARCState *env; |
800 | cf495bcf | bellard | |
801 | cf495bcf | bellard | cpu_exec_init(); |
802 | cf495bcf | bellard | |
803 | cf495bcf | bellard | if (!(env = malloc(sizeof(CPUSPARCState)))) |
804 | cf495bcf | bellard | return (NULL); |
805 | cf495bcf | bellard | memset(env, 0, sizeof(*env)); |
806 | cf495bcf | bellard | env->cwp = 0;
|
807 | cf495bcf | bellard | env->wim = 1;
|
808 | cf495bcf | bellard | env->regwptr = env->regbase + (env->cwp * 16);
|
809 | cf495bcf | bellard | env->user_mode_only = 1;
|
810 | cf495bcf | bellard | return (env);
|
811 | 7a3f1944 | bellard | } |
812 | 7a3f1944 | bellard | |
813 | 7a3f1944 | bellard | #define GET_FLAG(a,b) ((env->psr & a)?b:'-') |
814 | 7a3f1944 | bellard | |
815 | cf495bcf | bellard | void cpu_sparc_dump_state(CPUSPARCState * env, FILE * f, int flags) |
816 | 7a3f1944 | bellard | { |
817 | cf495bcf | bellard | int i, x;
|
818 | cf495bcf | bellard | |
819 | cf495bcf | bellard | fprintf(f, "pc: 0x%08x npc: 0x%08x\n", (int) env->pc, (int) env->npc); |
820 | cf495bcf | bellard | fprintf(f, "General Registers:\n");
|
821 | cf495bcf | bellard | for (i = 0; i < 4; i++) |
822 | cf495bcf | bellard | fprintf(f, "%%g%c: 0x%08x\t", i + '0', env->gregs[i]); |
823 | cf495bcf | bellard | fprintf(f, "\n");
|
824 | cf495bcf | bellard | for (; i < 8; i++) |
825 | cf495bcf | bellard | fprintf(f, "%%g%c: 0x%08x\t", i + '0', env->gregs[i]); |
826 | cf495bcf | bellard | fprintf(f, "\nCurrent Register Window:\n");
|
827 | cf495bcf | bellard | for (x = 0; x < 3; x++) { |
828 | cf495bcf | bellard | for (i = 0; i < 4; i++) |
829 | cf495bcf | bellard | fprintf(f, "%%%c%d: 0x%08x\t",
|
830 | cf495bcf | bellard | (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i, |
831 | cf495bcf | bellard | env->regwptr[i + x * 8]);
|
832 | cf495bcf | bellard | fprintf(f, "\n");
|
833 | cf495bcf | bellard | for (; i < 8; i++) |
834 | cf495bcf | bellard | fprintf(f, "%%%c%d: 0x%08x\t",
|
835 | cf495bcf | bellard | (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i, |
836 | cf495bcf | bellard | env->regwptr[i + x * 8]);
|
837 | cf495bcf | bellard | fprintf(f, "\n");
|
838 | cf495bcf | bellard | } |
839 | cf495bcf | bellard | fprintf(f, "psr: 0x%08x -> %c%c%c%c wim: 0x%08x\n", env->psr | env->cwp,
|
840 | cf495bcf | bellard | GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'), |
841 | cf495bcf | bellard | GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'), |
842 | cf495bcf | bellard | env->wim); |
843 | 7a3f1944 | bellard | } |