root / hw / sun4m.c @ 6cc721cf
History | View | Annotate | Download (9.8 kB)
1 | 420557e8 | bellard | /*
|
---|---|---|---|
2 | 420557e8 | bellard | * QEMU Sun4m System Emulator
|
3 | 420557e8 | bellard | *
|
4 | b81b3b10 | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
|
5 | 420557e8 | bellard | *
|
6 | 420557e8 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 | 420557e8 | bellard | * of this software and associated documentation files (the "Software"), to deal
|
8 | 420557e8 | bellard | * in the Software without restriction, including without limitation the rights
|
9 | 420557e8 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 | 420557e8 | bellard | * copies of the Software, and to permit persons to whom the Software is
|
11 | 420557e8 | bellard | * furnished to do so, subject to the following conditions:
|
12 | 420557e8 | bellard | *
|
13 | 420557e8 | bellard | * The above copyright notice and this permission notice shall be included in
|
14 | 420557e8 | bellard | * all copies or substantial portions of the Software.
|
15 | 420557e8 | bellard | *
|
16 | 420557e8 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 | 420557e8 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 | 420557e8 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 | 420557e8 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 | 420557e8 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 | 420557e8 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 | 420557e8 | bellard | * THE SOFTWARE.
|
23 | 420557e8 | bellard | */
|
24 | 420557e8 | bellard | #include "vl.h" |
25 | 420557e8 | bellard | #include "m48t08.h" |
26 | 420557e8 | bellard | |
27 | 420557e8 | bellard | #define KERNEL_LOAD_ADDR 0x00004000 |
28 | b6f479d3 | bellard | #define CMDLINE_ADDR 0x007ff000 |
29 | 713c45fa | bellard | #define INITRD_LOAD_ADDR 0x00800000 |
30 | e80cfcfc | bellard | #define PROM_ADDR 0xffd00000 |
31 | 8d5f07fa | bellard | #define PROM_FILENAMEB "proll.bin" |
32 | 8d5f07fa | bellard | #define PROM_FILENAMEE "proll.elf" |
33 | e80cfcfc | bellard | #define PHYS_JJ_EEPROM 0x71200000 /* m48t08 */ |
34 | 420557e8 | bellard | #define PHYS_JJ_IDPROM_OFF 0x1FD8 |
35 | 420557e8 | bellard | #define PHYS_JJ_EEPROM_SIZE 0x2000 |
36 | e80cfcfc | bellard | // IRQs are not PIL ones, but master interrupt controller register
|
37 | e80cfcfc | bellard | // bits
|
38 | e80cfcfc | bellard | #define PHYS_JJ_IOMMU 0x10000000 /* I/O MMU */ |
39 | 6f7e9aec | bellard | #define PHYS_JJ_TCX_FB 0x50000000 /* TCX frame buffer */ |
40 | 3475187d | bellard | #define PHYS_JJ_SLAVIO 0x70000000 /* Slavio base */ |
41 | 6f7e9aec | bellard | #define PHYS_JJ_ESPDMA 0x78400000 /* ESP DMA controller */ |
42 | 6f7e9aec | bellard | #define PHYS_JJ_ESP 0x78800000 /* ESP SCSI */ |
43 | 6f7e9aec | bellard | #define PHYS_JJ_ESP_IRQ 18 |
44 | e80cfcfc | bellard | #define PHYS_JJ_LEDMA 0x78400010 /* Lance DMA controller */ |
45 | e80cfcfc | bellard | #define PHYS_JJ_LE 0x78C00000 /* Lance ethernet */ |
46 | e80cfcfc | bellard | #define PHYS_JJ_LE_IRQ 16 |
47 | e80cfcfc | bellard | #define PHYS_JJ_CLOCK 0x71D00000 /* Per-CPU timer/counter, L14 */ |
48 | e80cfcfc | bellard | #define PHYS_JJ_CLOCK_IRQ 7 |
49 | e80cfcfc | bellard | #define PHYS_JJ_CLOCK1 0x71D10000 /* System timer/counter, L10 */ |
50 | e80cfcfc | bellard | #define PHYS_JJ_CLOCK1_IRQ 19 |
51 | e80cfcfc | bellard | #define PHYS_JJ_INTR0 0x71E00000 /* Per-CPU interrupt control registers */ |
52 | 8d5f07fa | bellard | #define PHYS_JJ_INTR_G 0x71E10000 /* Master interrupt control registers */ |
53 | e80cfcfc | bellard | #define PHYS_JJ_MS_KBD 0x71000000 /* Mouse and keyboard */ |
54 | e80cfcfc | bellard | #define PHYS_JJ_MS_KBD_IRQ 14 |
55 | e80cfcfc | bellard | #define PHYS_JJ_SER 0x71100000 /* Serial */ |
56 | e80cfcfc | bellard | #define PHYS_JJ_SER_IRQ 15 |
57 | e80cfcfc | bellard | #define PHYS_JJ_FDC 0x71400000 /* Floppy */ |
58 | e80cfcfc | bellard | #define PHYS_JJ_FLOPPY_IRQ 22 |
59 | 3475187d | bellard | #define PHYS_JJ_ME_IRQ 30 /* Module error, power fail */ |
60 | 420557e8 | bellard | |
61 | 420557e8 | bellard | /* TSC handling */
|
62 | 420557e8 | bellard | |
63 | 420557e8 | bellard | uint64_t cpu_get_tsc() |
64 | 420557e8 | bellard | { |
65 | 420557e8 | bellard | return qemu_get_clock(vm_clock);
|
66 | 420557e8 | bellard | } |
67 | 420557e8 | bellard | |
68 | 6f7e9aec | bellard | int DMA_get_channel_mode (int nchan) |
69 | 6f7e9aec | bellard | { |
70 | 6f7e9aec | bellard | return 0; |
71 | 6f7e9aec | bellard | } |
72 | 6f7e9aec | bellard | int DMA_read_memory (int nchan, void *buf, int pos, int size) |
73 | 6f7e9aec | bellard | { |
74 | 6f7e9aec | bellard | return 0; |
75 | 6f7e9aec | bellard | } |
76 | 6f7e9aec | bellard | int DMA_write_memory (int nchan, void *buf, int pos, int size) |
77 | 6f7e9aec | bellard | { |
78 | 6f7e9aec | bellard | return 0; |
79 | 6f7e9aec | bellard | } |
80 | 6f7e9aec | bellard | void DMA_hold_DREQ (int nchan) {} |
81 | 6f7e9aec | bellard | void DMA_release_DREQ (int nchan) {} |
82 | 6f7e9aec | bellard | void DMA_schedule(int nchan) {} |
83 | 6f7e9aec | bellard | void DMA_run (void) {} |
84 | 6f7e9aec | bellard | void DMA_init (int high_page_enable) {} |
85 | 6f7e9aec | bellard | void DMA_register_channel (int nchan, |
86 | 6f7e9aec | bellard | DMA_transfer_handler transfer_handler, |
87 | 6f7e9aec | bellard | void *opaque)
|
88 | 6f7e9aec | bellard | { |
89 | 6f7e9aec | bellard | } |
90 | 6f7e9aec | bellard | |
91 | 6f7e9aec | bellard | static void nvram_set_word (m48t08_t *nvram, uint32_t addr, uint16_t value) |
92 | 6f7e9aec | bellard | { |
93 | 6f7e9aec | bellard | m48t08_write(nvram, addr++, (value >> 8) & 0xff); |
94 | 6f7e9aec | bellard | m48t08_write(nvram, addr++, value & 0xff);
|
95 | 6f7e9aec | bellard | } |
96 | 6f7e9aec | bellard | |
97 | 6f7e9aec | bellard | static void nvram_set_lword (m48t08_t *nvram, uint32_t addr, uint32_t value) |
98 | 6f7e9aec | bellard | { |
99 | 6f7e9aec | bellard | m48t08_write(nvram, addr++, value >> 24);
|
100 | 6f7e9aec | bellard | m48t08_write(nvram, addr++, (value >> 16) & 0xff); |
101 | 6f7e9aec | bellard | m48t08_write(nvram, addr++, (value >> 8) & 0xff); |
102 | 6f7e9aec | bellard | m48t08_write(nvram, addr++, value & 0xff);
|
103 | 6f7e9aec | bellard | } |
104 | 6f7e9aec | bellard | |
105 | 6f7e9aec | bellard | static void nvram_set_string (m48t08_t *nvram, uint32_t addr, |
106 | 6f7e9aec | bellard | const unsigned char *str, uint32_t max) |
107 | 6f7e9aec | bellard | { |
108 | 6f7e9aec | bellard | unsigned int i; |
109 | 6f7e9aec | bellard | |
110 | 6f7e9aec | bellard | for (i = 0; i < max && str[i] != '\0'; i++) { |
111 | 6f7e9aec | bellard | m48t08_write(nvram, addr + i, str[i]); |
112 | 6f7e9aec | bellard | } |
113 | 6f7e9aec | bellard | m48t08_write(nvram, addr + max - 1, '\0'); |
114 | 6f7e9aec | bellard | } |
115 | 420557e8 | bellard | |
116 | 420557e8 | bellard | static m48t08_t *nvram;
|
117 | 420557e8 | bellard | |
118 | 6f7e9aec | bellard | extern int nographic; |
119 | 6f7e9aec | bellard | |
120 | 6f7e9aec | bellard | static void nvram_init(m48t08_t *nvram, uint8_t *macaddr, const char *cmdline, |
121 | 6f7e9aec | bellard | int boot_device, uint32_t RAM_size,
|
122 | 6f7e9aec | bellard | uint32_t kernel_size, |
123 | 6f7e9aec | bellard | int width, int height, int depth) |
124 | e80cfcfc | bellard | { |
125 | e80cfcfc | bellard | unsigned char tmp = 0; |
126 | e80cfcfc | bellard | int i, j;
|
127 | e80cfcfc | bellard | |
128 | 6f7e9aec | bellard | // Try to match PPC NVRAM
|
129 | 6f7e9aec | bellard | nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16); |
130 | 6f7e9aec | bellard | nvram_set_lword(nvram, 0x10, 0x00000001); /* structure v1 */ |
131 | 6f7e9aec | bellard | // NVRAM_size, arch not applicable
|
132 | 6f7e9aec | bellard | m48t08_write(nvram, 0x2F, nographic & 0xff); |
133 | 6f7e9aec | bellard | nvram_set_lword(nvram, 0x30, RAM_size);
|
134 | 6f7e9aec | bellard | m48t08_write(nvram, 0x34, boot_device & 0xff); |
135 | 6f7e9aec | bellard | nvram_set_lword(nvram, 0x38, KERNEL_LOAD_ADDR);
|
136 | 6f7e9aec | bellard | nvram_set_lword(nvram, 0x3C, kernel_size);
|
137 | b6f479d3 | bellard | if (cmdline) {
|
138 | b6f479d3 | bellard | strcpy(phys_ram_base + CMDLINE_ADDR, cmdline); |
139 | 6f7e9aec | bellard | nvram_set_lword(nvram, 0x40, CMDLINE_ADDR);
|
140 | 6f7e9aec | bellard | nvram_set_lword(nvram, 0x44, strlen(cmdline));
|
141 | b6f479d3 | bellard | } |
142 | 6f7e9aec | bellard | // initrd_image, initrd_size passed differently
|
143 | 6f7e9aec | bellard | nvram_set_word(nvram, 0x54, width);
|
144 | 6f7e9aec | bellard | nvram_set_word(nvram, 0x56, height);
|
145 | 6f7e9aec | bellard | nvram_set_word(nvram, 0x58, depth);
|
146 | b6f479d3 | bellard | |
147 | 6f7e9aec | bellard | // Sun4m specific use
|
148 | e80cfcfc | bellard | i = 0x1fd8;
|
149 | e80cfcfc | bellard | m48t08_write(nvram, i++, 0x01);
|
150 | e80cfcfc | bellard | m48t08_write(nvram, i++, 0x80); /* Sun4m OBP */ |
151 | e80cfcfc | bellard | j = 0;
|
152 | e80cfcfc | bellard | m48t08_write(nvram, i++, macaddr[j++]); |
153 | e80cfcfc | bellard | m48t08_write(nvram, i++, macaddr[j++]); |
154 | e80cfcfc | bellard | m48t08_write(nvram, i++, macaddr[j++]); |
155 | e80cfcfc | bellard | m48t08_write(nvram, i++, macaddr[j++]); |
156 | e80cfcfc | bellard | m48t08_write(nvram, i++, macaddr[j++]); |
157 | e80cfcfc | bellard | m48t08_write(nvram, i, macaddr[j]); |
158 | e80cfcfc | bellard | |
159 | e80cfcfc | bellard | /* Calculate checksum */
|
160 | e80cfcfc | bellard | for (i = 0x1fd8; i < 0x1fe7; i++) { |
161 | e80cfcfc | bellard | tmp ^= m48t08_read(nvram, i); |
162 | e80cfcfc | bellard | } |
163 | e80cfcfc | bellard | m48t08_write(nvram, 0x1fe7, tmp);
|
164 | e80cfcfc | bellard | } |
165 | e80cfcfc | bellard | |
166 | e80cfcfc | bellard | static void *slavio_intctl; |
167 | e80cfcfc | bellard | |
168 | e80cfcfc | bellard | void pic_info()
|
169 | e80cfcfc | bellard | { |
170 | e80cfcfc | bellard | slavio_pic_info(slavio_intctl); |
171 | e80cfcfc | bellard | } |
172 | e80cfcfc | bellard | |
173 | e80cfcfc | bellard | void irq_info()
|
174 | e80cfcfc | bellard | { |
175 | e80cfcfc | bellard | slavio_irq_info(slavio_intctl); |
176 | e80cfcfc | bellard | } |
177 | e80cfcfc | bellard | |
178 | e80cfcfc | bellard | void pic_set_irq(int irq, int level) |
179 | e80cfcfc | bellard | { |
180 | e80cfcfc | bellard | slavio_pic_set_irq(slavio_intctl, irq, level); |
181 | e80cfcfc | bellard | } |
182 | e80cfcfc | bellard | |
183 | e80cfcfc | bellard | static void *tcx; |
184 | e80cfcfc | bellard | |
185 | e80cfcfc | bellard | void vga_update_display()
|
186 | e80cfcfc | bellard | { |
187 | e80cfcfc | bellard | tcx_update_display(tcx); |
188 | e80cfcfc | bellard | } |
189 | e80cfcfc | bellard | |
190 | e80cfcfc | bellard | void vga_invalidate_display()
|
191 | e80cfcfc | bellard | { |
192 | e80cfcfc | bellard | tcx_invalidate_display(tcx); |
193 | e80cfcfc | bellard | } |
194 | e80cfcfc | bellard | |
195 | e80cfcfc | bellard | void vga_screen_dump(const char *filename) |
196 | e80cfcfc | bellard | { |
197 | e80cfcfc | bellard | tcx_screen_dump(tcx, filename); |
198 | e80cfcfc | bellard | } |
199 | e80cfcfc | bellard | |
200 | e80cfcfc | bellard | static void *iommu; |
201 | e80cfcfc | bellard | |
202 | e80cfcfc | bellard | uint32_t iommu_translate(uint32_t addr) |
203 | e80cfcfc | bellard | { |
204 | e80cfcfc | bellard | return iommu_translate_local(iommu, addr);
|
205 | e80cfcfc | bellard | } |
206 | e80cfcfc | bellard | |
207 | 3475187d | bellard | static void *slavio_misc; |
208 | 3475187d | bellard | |
209 | 3475187d | bellard | void qemu_system_powerdown(void) |
210 | 3475187d | bellard | { |
211 | 3475187d | bellard | slavio_set_power_fail(slavio_misc, 1);
|
212 | 3475187d | bellard | } |
213 | 3475187d | bellard | |
214 | 420557e8 | bellard | /* Sun4m hardware initialisation */
|
215 | c0e564d5 | bellard | static void sun4m_init(int ram_size, int vga_ram_size, int boot_device, |
216 | c0e564d5 | bellard | DisplayState *ds, const char **fd_filename, int snapshot, |
217 | c0e564d5 | bellard | const char *kernel_filename, const char *kernel_cmdline, |
218 | c0e564d5 | bellard | const char *initrd_filename) |
219 | 420557e8 | bellard | { |
220 | 420557e8 | bellard | char buf[1024]; |
221 | 8d5f07fa | bellard | int ret, linux_boot;
|
222 | 713c45fa | bellard | unsigned int i; |
223 | 6f7e9aec | bellard | long vram_size = 0x100000, prom_offset, initrd_size, kernel_size; |
224 | 420557e8 | bellard | |
225 | 420557e8 | bellard | linux_boot = (kernel_filename != NULL);
|
226 | 420557e8 | bellard | |
227 | 420557e8 | bellard | /* allocate RAM */
|
228 | 420557e8 | bellard | cpu_register_physical_memory(0, ram_size, 0); |
229 | 420557e8 | bellard | |
230 | e80cfcfc | bellard | iommu = iommu_init(PHYS_JJ_IOMMU); |
231 | e80cfcfc | bellard | slavio_intctl = slavio_intctl_init(PHYS_JJ_INTR0, PHYS_JJ_INTR_G); |
232 | 6f7e9aec | bellard | tcx = tcx_init(ds, PHYS_JJ_TCX_FB, phys_ram_base + ram_size, ram_size, vram_size, graphic_width, graphic_height); |
233 | 8d5f07fa | bellard | lance_init(&nd_table[0], PHYS_JJ_LE_IRQ, PHYS_JJ_LE, PHYS_JJ_LEDMA);
|
234 | e80cfcfc | bellard | nvram = m48t08_init(PHYS_JJ_EEPROM, PHYS_JJ_EEPROM_SIZE); |
235 | e80cfcfc | bellard | slavio_timer_init(PHYS_JJ_CLOCK, PHYS_JJ_CLOCK_IRQ, PHYS_JJ_CLOCK1, PHYS_JJ_CLOCK1_IRQ); |
236 | e80cfcfc | bellard | slavio_serial_ms_kbd_init(PHYS_JJ_MS_KBD, PHYS_JJ_MS_KBD_IRQ); |
237 | b81b3b10 | bellard | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
238 | b81b3b10 | bellard | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
239 | b81b3b10 | bellard | slavio_serial_init(PHYS_JJ_SER, PHYS_JJ_SER_IRQ, serial_hds[1], serial_hds[0]); |
240 | e80cfcfc | bellard | fdctrl_init(PHYS_JJ_FLOPPY_IRQ, 0, 1, PHYS_JJ_FDC, fd_table); |
241 | 6f7e9aec | bellard | esp_init(bs_table, PHYS_JJ_ESP_IRQ, PHYS_JJ_ESP, PHYS_JJ_ESPDMA); |
242 | 3475187d | bellard | slavio_misc = slavio_misc_init(PHYS_JJ_SLAVIO, PHYS_JJ_ME_IRQ); |
243 | 420557e8 | bellard | |
244 | e80cfcfc | bellard | prom_offset = ram_size + vram_size; |
245 | e80cfcfc | bellard | |
246 | e80cfcfc | bellard | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEE); |
247 | e80cfcfc | bellard | ret = load_elf(buf, phys_ram_base + prom_offset); |
248 | e80cfcfc | bellard | if (ret < 0) { |
249 | 8d5f07fa | bellard | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEB); |
250 | e80cfcfc | bellard | ret = load_image(buf, phys_ram_base + prom_offset); |
251 | e80cfcfc | bellard | } |
252 | e80cfcfc | bellard | if (ret < 0) { |
253 | e80cfcfc | bellard | fprintf(stderr, "qemu: could not load prom '%s'\n",
|
254 | e80cfcfc | bellard | buf); |
255 | e80cfcfc | bellard | exit(1);
|
256 | e80cfcfc | bellard | } |
257 | e80cfcfc | bellard | cpu_register_physical_memory(PROM_ADDR, (ret + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK, |
258 | e80cfcfc | bellard | prom_offset | IO_MEM_ROM); |
259 | e80cfcfc | bellard | |
260 | 6f7e9aec | bellard | kernel_size = 0;
|
261 | e80cfcfc | bellard | if (linux_boot) {
|
262 | 6f7e9aec | bellard | kernel_size = load_elf(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
263 | 6f7e9aec | bellard | if (kernel_size < 0) |
264 | 6f7e9aec | bellard | kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
265 | 6f7e9aec | bellard | if (kernel_size < 0) |
266 | 6f7e9aec | bellard | kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
267 | 6f7e9aec | bellard | if (kernel_size < 0) { |
268 | 420557e8 | bellard | fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
269 | e80cfcfc | bellard | kernel_filename); |
270 | e80cfcfc | bellard | exit(1);
|
271 | 420557e8 | bellard | } |
272 | 713c45fa | bellard | |
273 | 713c45fa | bellard | /* load initrd */
|
274 | 713c45fa | bellard | initrd_size = 0;
|
275 | 713c45fa | bellard | if (initrd_filename) {
|
276 | 713c45fa | bellard | initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR); |
277 | 713c45fa | bellard | if (initrd_size < 0) { |
278 | 713c45fa | bellard | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
279 | 713c45fa | bellard | initrd_filename); |
280 | 713c45fa | bellard | exit(1);
|
281 | 713c45fa | bellard | } |
282 | 713c45fa | bellard | } |
283 | 713c45fa | bellard | if (initrd_size > 0) { |
284 | 713c45fa | bellard | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
285 | 713c45fa | bellard | if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
|
286 | 713c45fa | bellard | == 0x48647253) { // HdrS |
287 | 713c45fa | bellard | stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
|
288 | 713c45fa | bellard | stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
|
289 | 713c45fa | bellard | break;
|
290 | 713c45fa | bellard | } |
291 | 713c45fa | bellard | } |
292 | 713c45fa | bellard | } |
293 | 420557e8 | bellard | } |
294 | 6f7e9aec | bellard | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, boot_device, ram_size, kernel_size, graphic_width, graphic_height, graphic_depth);
|
295 | 420557e8 | bellard | } |
296 | c0e564d5 | bellard | |
297 | c0e564d5 | bellard | QEMUMachine sun4m_machine = { |
298 | c0e564d5 | bellard | "sun4m",
|
299 | c0e564d5 | bellard | "Sun4m platform",
|
300 | c0e564d5 | bellard | sun4m_init, |
301 | c0e564d5 | bellard | }; |