root / hw / tcx.c @ 6cc721cf
History | View | Annotate | Download (7.7 kB)
1 | 420557e8 | bellard | /*
|
---|---|---|---|
2 | 6f7e9aec | bellard | * QEMU TCX Frame buffer
|
3 | 420557e8 | bellard | *
|
4 | 6f7e9aec | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
|
5 | 420557e8 | bellard | *
|
6 | 420557e8 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 | 420557e8 | bellard | * of this software and associated documentation files (the "Software"), to deal
|
8 | 420557e8 | bellard | * in the Software without restriction, including without limitation the rights
|
9 | 420557e8 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 | 420557e8 | bellard | * copies of the Software, and to permit persons to whom the Software is
|
11 | 420557e8 | bellard | * furnished to do so, subject to the following conditions:
|
12 | 420557e8 | bellard | *
|
13 | 420557e8 | bellard | * The above copyright notice and this permission notice shall be included in
|
14 | 420557e8 | bellard | * all copies or substantial portions of the Software.
|
15 | 420557e8 | bellard | *
|
16 | 420557e8 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 | 420557e8 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 | 420557e8 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 | 420557e8 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 | 420557e8 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 | 420557e8 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 | 420557e8 | bellard | * THE SOFTWARE.
|
23 | 420557e8 | bellard | */
|
24 | 420557e8 | bellard | #include "vl.h" |
25 | 420557e8 | bellard | |
26 | 420557e8 | bellard | #define MAXX 1024 |
27 | 420557e8 | bellard | #define MAXY 768 |
28 | 6f7e9aec | bellard | #define TCX_DAC_NREGS 16 |
29 | 420557e8 | bellard | |
30 | 420557e8 | bellard | typedef struct TCXState { |
31 | 8d5f07fa | bellard | uint32_t addr; |
32 | 420557e8 | bellard | DisplayState *ds; |
33 | 8d5f07fa | bellard | uint8_t *vram; |
34 | e80cfcfc | bellard | unsigned long vram_offset; |
35 | 6f7e9aec | bellard | uint16_t width, height; |
36 | e80cfcfc | bellard | uint8_t r[256], g[256], b[256]; |
37 | 6f7e9aec | bellard | uint8_t dac_index, dac_state; |
38 | 420557e8 | bellard | } TCXState; |
39 | 420557e8 | bellard | |
40 | e80cfcfc | bellard | static void tcx_draw_line32(TCXState *s1, uint8_t *d, |
41 | e80cfcfc | bellard | const uint8_t *s, int width) |
42 | 420557e8 | bellard | { |
43 | e80cfcfc | bellard | int x;
|
44 | e80cfcfc | bellard | uint8_t val; |
45 | e80cfcfc | bellard | |
46 | e80cfcfc | bellard | for(x = 0; x < width; x++) { |
47 | e80cfcfc | bellard | val = *s++; |
48 | e80cfcfc | bellard | *d++ = s1->b[val]; |
49 | 6f7e9aec | bellard | *d++ = s1->g[val]; |
50 | 6f7e9aec | bellard | *d++ = s1->r[val]; |
51 | e80cfcfc | bellard | d++; |
52 | e80cfcfc | bellard | } |
53 | 420557e8 | bellard | } |
54 | 420557e8 | bellard | |
55 | e80cfcfc | bellard | static void tcx_draw_line24(TCXState *s1, uint8_t *d, |
56 | e80cfcfc | bellard | const uint8_t *s, int width) |
57 | e80cfcfc | bellard | { |
58 | e80cfcfc | bellard | int x;
|
59 | e80cfcfc | bellard | uint8_t val; |
60 | 8d5f07fa | bellard | |
61 | e80cfcfc | bellard | for(x = 0; x < width; x++) { |
62 | e80cfcfc | bellard | val = *s++; |
63 | e80cfcfc | bellard | *d++ = s1->b[val]; |
64 | 6f7e9aec | bellard | *d++ = s1->g[val]; |
65 | 6f7e9aec | bellard | *d++ = s1->r[val]; |
66 | e80cfcfc | bellard | } |
67 | e80cfcfc | bellard | } |
68 | e80cfcfc | bellard | |
69 | e80cfcfc | bellard | static void tcx_draw_line8(TCXState *s1, uint8_t *d, |
70 | e80cfcfc | bellard | const uint8_t *s, int width) |
71 | 420557e8 | bellard | { |
72 | e80cfcfc | bellard | int x;
|
73 | e80cfcfc | bellard | uint8_t val; |
74 | e80cfcfc | bellard | |
75 | e80cfcfc | bellard | for(x = 0; x < width; x++) { |
76 | e80cfcfc | bellard | val = *s++; |
77 | e80cfcfc | bellard | /* XXX translate between palettes? */
|
78 | e80cfcfc | bellard | *d++ = val; |
79 | 420557e8 | bellard | } |
80 | 420557e8 | bellard | } |
81 | 420557e8 | bellard | |
82 | e80cfcfc | bellard | /* Fixed line length 1024 allows us to do nice tricks not possible on
|
83 | e80cfcfc | bellard | VGA... */
|
84 | e80cfcfc | bellard | void tcx_update_display(void *opaque) |
85 | 420557e8 | bellard | { |
86 | e80cfcfc | bellard | TCXState *ts = opaque; |
87 | e80cfcfc | bellard | uint32_t page; |
88 | e80cfcfc | bellard | int y, page_min, page_max, y_start, dd, ds;
|
89 | e80cfcfc | bellard | uint8_t *d, *s; |
90 | e80cfcfc | bellard | void (*f)(TCXState *s1, uint8_t *d, const uint8_t *s, int width); |
91 | e80cfcfc | bellard | |
92 | e80cfcfc | bellard | if (ts->ds->depth == 0) |
93 | e80cfcfc | bellard | return;
|
94 | 6f7e9aec | bellard | page = ts->vram_offset; |
95 | e80cfcfc | bellard | y_start = -1;
|
96 | e80cfcfc | bellard | page_min = 0x7fffffff;
|
97 | e80cfcfc | bellard | page_max = -1;
|
98 | e80cfcfc | bellard | d = ts->ds->data; |
99 | 6f7e9aec | bellard | s = ts->vram; |
100 | e80cfcfc | bellard | dd = ts->ds->linesize; |
101 | e80cfcfc | bellard | ds = 1024;
|
102 | e80cfcfc | bellard | |
103 | e80cfcfc | bellard | switch (ts->ds->depth) {
|
104 | e80cfcfc | bellard | case 32: |
105 | e80cfcfc | bellard | f = tcx_draw_line32; |
106 | e80cfcfc | bellard | break;
|
107 | e80cfcfc | bellard | case 24: |
108 | e80cfcfc | bellard | f = tcx_draw_line24; |
109 | e80cfcfc | bellard | break;
|
110 | e80cfcfc | bellard | default:
|
111 | e80cfcfc | bellard | case 8: |
112 | e80cfcfc | bellard | f = tcx_draw_line8; |
113 | e80cfcfc | bellard | break;
|
114 | e80cfcfc | bellard | case 0: |
115 | e80cfcfc | bellard | return;
|
116 | e80cfcfc | bellard | } |
117 | 662f3c86 | bellard | |
118 | 6f7e9aec | bellard | for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) { |
119 | 0a962c02 | bellard | if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) {
|
120 | e80cfcfc | bellard | if (y_start < 0) |
121 | e80cfcfc | bellard | y_start = y; |
122 | e80cfcfc | bellard | if (page < page_min)
|
123 | e80cfcfc | bellard | page_min = page; |
124 | e80cfcfc | bellard | if (page > page_max)
|
125 | e80cfcfc | bellard | page_max = page; |
126 | 6f7e9aec | bellard | f(ts, d, s, ts->width); |
127 | e80cfcfc | bellard | d += dd; |
128 | e80cfcfc | bellard | s += ds; |
129 | 6f7e9aec | bellard | f(ts, d, s, ts->width); |
130 | e80cfcfc | bellard | d += dd; |
131 | e80cfcfc | bellard | s += ds; |
132 | 6f7e9aec | bellard | f(ts, d, s, ts->width); |
133 | e80cfcfc | bellard | d += dd; |
134 | e80cfcfc | bellard | s += ds; |
135 | 6f7e9aec | bellard | f(ts, d, s, ts->width); |
136 | e80cfcfc | bellard | d += dd; |
137 | e80cfcfc | bellard | s += ds; |
138 | e80cfcfc | bellard | } else {
|
139 | e80cfcfc | bellard | if (y_start >= 0) { |
140 | e80cfcfc | bellard | /* flush to display */
|
141 | e80cfcfc | bellard | dpy_update(ts->ds, 0, y_start,
|
142 | 6f7e9aec | bellard | ts->width, y - y_start); |
143 | e80cfcfc | bellard | y_start = -1;
|
144 | e80cfcfc | bellard | } |
145 | e80cfcfc | bellard | d += dd * 4;
|
146 | e80cfcfc | bellard | s += ds * 4;
|
147 | e80cfcfc | bellard | } |
148 | e80cfcfc | bellard | } |
149 | e80cfcfc | bellard | if (y_start >= 0) { |
150 | e80cfcfc | bellard | /* flush to display */
|
151 | e80cfcfc | bellard | dpy_update(ts->ds, 0, y_start,
|
152 | 6f7e9aec | bellard | ts->width, y - y_start); |
153 | e80cfcfc | bellard | } |
154 | e80cfcfc | bellard | /* reset modified pages */
|
155 | e80cfcfc | bellard | if (page_max != -1) { |
156 | 0a962c02 | bellard | cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE, |
157 | 0a962c02 | bellard | VGA_DIRTY_FLAG); |
158 | e80cfcfc | bellard | } |
159 | 420557e8 | bellard | } |
160 | 420557e8 | bellard | |
161 | e80cfcfc | bellard | void tcx_invalidate_display(void *opaque) |
162 | 420557e8 | bellard | { |
163 | e80cfcfc | bellard | TCXState *s = opaque; |
164 | e80cfcfc | bellard | int i;
|
165 | e80cfcfc | bellard | |
166 | e80cfcfc | bellard | for (i = 0; i < MAXX*MAXY; i += TARGET_PAGE_SIZE) { |
167 | e80cfcfc | bellard | cpu_physical_memory_set_dirty(s->vram_offset + i); |
168 | e80cfcfc | bellard | } |
169 | 420557e8 | bellard | } |
170 | 420557e8 | bellard | |
171 | e80cfcfc | bellard | static void tcx_save(QEMUFile *f, void *opaque) |
172 | 420557e8 | bellard | { |
173 | 420557e8 | bellard | TCXState *s = opaque; |
174 | e80cfcfc | bellard | |
175 | e80cfcfc | bellard | qemu_put_be32s(f, (uint32_t *)&s->addr); |
176 | e80cfcfc | bellard | qemu_put_be32s(f, (uint32_t *)&s->vram); |
177 | 6f7e9aec | bellard | qemu_put_be16s(f, (uint16_t *)&s->height); |
178 | 6f7e9aec | bellard | qemu_put_be16s(f, (uint16_t *)&s->width); |
179 | e80cfcfc | bellard | qemu_put_buffer(f, s->r, 256);
|
180 | e80cfcfc | bellard | qemu_put_buffer(f, s->g, 256);
|
181 | e80cfcfc | bellard | qemu_put_buffer(f, s->b, 256);
|
182 | 6f7e9aec | bellard | qemu_put_8s(f, &s->dac_index); |
183 | 6f7e9aec | bellard | qemu_put_8s(f, &s->dac_state); |
184 | 420557e8 | bellard | } |
185 | 420557e8 | bellard | |
186 | e80cfcfc | bellard | static int tcx_load(QEMUFile *f, void *opaque, int version_id) |
187 | 420557e8 | bellard | { |
188 | e80cfcfc | bellard | TCXState *s = opaque; |
189 | e80cfcfc | bellard | |
190 | e80cfcfc | bellard | if (version_id != 1) |
191 | e80cfcfc | bellard | return -EINVAL;
|
192 | e80cfcfc | bellard | |
193 | e80cfcfc | bellard | qemu_get_be32s(f, (uint32_t *)&s->addr); |
194 | e80cfcfc | bellard | qemu_get_be32s(f, (uint32_t *)&s->vram); |
195 | 6f7e9aec | bellard | qemu_get_be16s(f, (uint16_t *)&s->height); |
196 | 6f7e9aec | bellard | qemu_get_be16s(f, (uint16_t *)&s->width); |
197 | e80cfcfc | bellard | qemu_get_buffer(f, s->r, 256);
|
198 | e80cfcfc | bellard | qemu_get_buffer(f, s->g, 256);
|
199 | e80cfcfc | bellard | qemu_get_buffer(f, s->b, 256);
|
200 | 6f7e9aec | bellard | qemu_get_8s(f, &s->dac_index); |
201 | 6f7e9aec | bellard | qemu_get_8s(f, &s->dac_state); |
202 | e80cfcfc | bellard | return 0; |
203 | 420557e8 | bellard | } |
204 | 420557e8 | bellard | |
205 | e80cfcfc | bellard | static void tcx_reset(void *opaque) |
206 | 420557e8 | bellard | { |
207 | e80cfcfc | bellard | TCXState *s = opaque; |
208 | e80cfcfc | bellard | |
209 | e80cfcfc | bellard | /* Initialize palette */
|
210 | e80cfcfc | bellard | memset(s->r, 0, 256); |
211 | e80cfcfc | bellard | memset(s->g, 0, 256); |
212 | e80cfcfc | bellard | memset(s->b, 0, 256); |
213 | e80cfcfc | bellard | s->r[255] = s->g[255] = s->b[255] = 255; |
214 | e80cfcfc | bellard | memset(s->vram, 0, MAXX*MAXY);
|
215 | 0a962c02 | bellard | cpu_physical_memory_reset_dirty(s->vram_offset, s->vram_offset + MAXX*MAXY, |
216 | 0a962c02 | bellard | VGA_DIRTY_FLAG); |
217 | 6f7e9aec | bellard | s->dac_index = 0;
|
218 | 6f7e9aec | bellard | s->dac_state = 0;
|
219 | 6f7e9aec | bellard | } |
220 | 6f7e9aec | bellard | |
221 | 6f7e9aec | bellard | static uint32_t tcx_dac_readl(void *opaque, target_phys_addr_t addr) |
222 | 6f7e9aec | bellard | { |
223 | 6f7e9aec | bellard | return 0; |
224 | 6f7e9aec | bellard | } |
225 | 6f7e9aec | bellard | |
226 | 6f7e9aec | bellard | static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
227 | 6f7e9aec | bellard | { |
228 | 6f7e9aec | bellard | TCXState *s = opaque; |
229 | 6f7e9aec | bellard | uint32_t saddr; |
230 | 6f7e9aec | bellard | |
231 | 6f7e9aec | bellard | saddr = (addr & (TCX_DAC_NREGS - 1)) >> 2; |
232 | 6f7e9aec | bellard | switch (saddr) {
|
233 | 6f7e9aec | bellard | case 0: |
234 | 6f7e9aec | bellard | s->dac_index = val >> 24;
|
235 | 6f7e9aec | bellard | s->dac_state = 0;
|
236 | 6f7e9aec | bellard | break;
|
237 | 6f7e9aec | bellard | case 1: |
238 | 6f7e9aec | bellard | switch (s->dac_state) {
|
239 | 6f7e9aec | bellard | case 0: |
240 | 6f7e9aec | bellard | s->r[s->dac_index] = val >> 24;
|
241 | 6f7e9aec | bellard | s->dac_state++; |
242 | 6f7e9aec | bellard | break;
|
243 | 6f7e9aec | bellard | case 1: |
244 | 6f7e9aec | bellard | s->g[s->dac_index] = val >> 24;
|
245 | 6f7e9aec | bellard | s->dac_state++; |
246 | 6f7e9aec | bellard | break;
|
247 | 6f7e9aec | bellard | case 2: |
248 | 6f7e9aec | bellard | s->b[s->dac_index] = val >> 24;
|
249 | 6f7e9aec | bellard | default:
|
250 | 6f7e9aec | bellard | s->dac_state = 0;
|
251 | 6f7e9aec | bellard | break;
|
252 | 6f7e9aec | bellard | } |
253 | 6f7e9aec | bellard | break;
|
254 | 6f7e9aec | bellard | default:
|
255 | 6f7e9aec | bellard | break;
|
256 | 6f7e9aec | bellard | } |
257 | 6f7e9aec | bellard | return;
|
258 | 420557e8 | bellard | } |
259 | 420557e8 | bellard | |
260 | 6f7e9aec | bellard | static CPUReadMemoryFunc *tcx_dac_read[3] = { |
261 | 6f7e9aec | bellard | tcx_dac_readl, |
262 | 6f7e9aec | bellard | tcx_dac_readl, |
263 | 6f7e9aec | bellard | tcx_dac_readl, |
264 | 6f7e9aec | bellard | }; |
265 | 6f7e9aec | bellard | |
266 | 6f7e9aec | bellard | static CPUWriteMemoryFunc *tcx_dac_write[3] = { |
267 | 6f7e9aec | bellard | tcx_dac_writel, |
268 | 6f7e9aec | bellard | tcx_dac_writel, |
269 | 6f7e9aec | bellard | tcx_dac_writel, |
270 | 6f7e9aec | bellard | }; |
271 | 6f7e9aec | bellard | |
272 | e80cfcfc | bellard | void *tcx_init(DisplayState *ds, uint32_t addr, uint8_t *vram_base,
|
273 | 6f7e9aec | bellard | unsigned long vram_offset, int vram_size, int width, int height) |
274 | 420557e8 | bellard | { |
275 | 420557e8 | bellard | TCXState *s; |
276 | 6f7e9aec | bellard | int io_memory;
|
277 | 420557e8 | bellard | |
278 | 420557e8 | bellard | s = qemu_mallocz(sizeof(TCXState));
|
279 | 420557e8 | bellard | if (!s)
|
280 | e80cfcfc | bellard | return NULL; |
281 | 420557e8 | bellard | s->ds = ds; |
282 | 8d5f07fa | bellard | s->addr = addr; |
283 | e80cfcfc | bellard | s->vram = vram_base; |
284 | e80cfcfc | bellard | s->vram_offset = vram_offset; |
285 | 6f7e9aec | bellard | s->width = width; |
286 | 6f7e9aec | bellard | s->height = height; |
287 | e80cfcfc | bellard | |
288 | 6f7e9aec | bellard | cpu_register_physical_memory(addr + 0x800000, vram_size, vram_offset);
|
289 | 6f7e9aec | bellard | io_memory = cpu_register_io_memory(0, tcx_dac_read, tcx_dac_write, s);
|
290 | 6f7e9aec | bellard | cpu_register_physical_memory(addr + 0x200000, TCX_DAC_NREGS, io_memory);
|
291 | e80cfcfc | bellard | |
292 | e80cfcfc | bellard | register_savevm("tcx", addr, 1, tcx_save, tcx_load, s); |
293 | e80cfcfc | bellard | qemu_register_reset(tcx_reset, s); |
294 | e80cfcfc | bellard | tcx_reset(s); |
295 | 6f7e9aec | bellard | dpy_resize(s->ds, width, height); |
296 | e80cfcfc | bellard | return s;
|
297 | 420557e8 | bellard | } |
298 | 420557e8 | bellard | |
299 | e80cfcfc | bellard | void tcx_screen_dump(void *opaque, const char *filename) |
300 | 8d5f07fa | bellard | { |
301 | e80cfcfc | bellard | TCXState *s = opaque; |
302 | 8d5f07fa | bellard | FILE *f; |
303 | e80cfcfc | bellard | uint8_t *d, *d1, v; |
304 | 8d5f07fa | bellard | int y, x;
|
305 | 8d5f07fa | bellard | |
306 | 8d5f07fa | bellard | f = fopen(filename, "wb");
|
307 | 8d5f07fa | bellard | if (!f)
|
308 | e80cfcfc | bellard | return;
|
309 | 6f7e9aec | bellard | fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255); |
310 | 6f7e9aec | bellard | d1 = s->vram; |
311 | 6f7e9aec | bellard | for(y = 0; y < s->height; y++) { |
312 | 8d5f07fa | bellard | d = d1; |
313 | 6f7e9aec | bellard | for(x = 0; x < s->width; x++) { |
314 | 8d5f07fa | bellard | v = *d; |
315 | e80cfcfc | bellard | fputc(s->r[v], f); |
316 | e80cfcfc | bellard | fputc(s->g[v], f); |
317 | e80cfcfc | bellard | fputc(s->b[v], f); |
318 | 8d5f07fa | bellard | d++; |
319 | 8d5f07fa | bellard | } |
320 | e80cfcfc | bellard | d1 += MAXX; |
321 | 8d5f07fa | bellard | } |
322 | 8d5f07fa | bellard | fclose(f); |
323 | 8d5f07fa | bellard | return;
|
324 | 8d5f07fa | bellard | } |
325 | 8d5f07fa | bellard | |
326 | 8d5f07fa | bellard |