Archipelago » qemu

/*

 *  UniCore32 translation

 *

 * Copyright (C) 2010-2011 GUAN Xue-tao

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */

#include <stdarg.h>

#include <stdlib.h>

#include <stdio.h>

#include <string.h>

#include <inttypes.h>

#include "cpu.h"

#include "disas.h"

#include "tcg-op.h"

#include "qemu-log.h"

#include "helper.h"

#define GEN_HELPER 1

#include "helper.h"

/* internal defines */

typedef struct DisasContext {

    target_ulong pc;

    int is_jmp;

    /* Nonzero if this instruction has been conditionally skipped.  */

    int condjmp;

    /* The label that will be jumped to when the instruction is skipped.  */

    int condlabel;

    struct TranslationBlock *tb;

    int singlestep_enabled;

} DisasContext;

#define IS_USER(s) 1

/* These instructions trap after executing, so defer them until after the

   conditional executions state has been updated.  */

#define DISAS_SYSCALL 5

static TCGv_ptr cpu_env;

static TCGv_i32 cpu_R[32];

/* FIXME:  These should be removed.  */

static TCGv cpu_F0s, cpu_F1s;

static TCGv_i64 cpu_F0d, cpu_F1d;

#include "gen-icount.h"

static const char *regnames[] = {

      "r00", "r01", "r02", "r03", "r04", "r05", "r06", "r07",

      "r08", "r09", "r10", "r11", "r12", "r13", "r14", "r15",

      "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",

      "r24", "r25", "r26", "r27", "r28", "r29", "r30", "pc" };

/* initialize TCG globals.  */

void uc32_translate_init(void)

{

    int i;

    cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");

    for (i = 0; i < 32; i++) {

        cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,

                                offsetof(CPUState, regs[i]), regnames[i]);

    }

#define GEN_HELPER 2

#include "helper.h"

}

static int num_temps;

/* Allocate a temporary variable.  */

static TCGv_i32 new_tmp(void)

{

    num_temps++;

    return tcg_temp_new_i32();

}

/* Release a temporary variable.  */

static void dead_tmp(TCGv tmp)

{

    tcg_temp_free(tmp);

    num_temps--;

}

static inline TCGv load_cpu_offset(int offset)

{

    TCGv tmp = new_tmp();

    tcg_gen_ld_i32(tmp, cpu_env, offset);

    return tmp;

}

#define load_cpu_field(name) load_cpu_offset(offsetof(CPUState, name))

static inline void store_cpu_offset(TCGv var, int offset)

{

    tcg_gen_st_i32(var, cpu_env, offset);

    dead_tmp(var);

}

#define store_cpu_field(var, name) \

    store_cpu_offset(var, offsetof(CPUState, name))

/* Set a variable to the value of a CPU register.  */

static void load_reg_var(DisasContext *s, TCGv var, int reg)

{

    if (reg == 31) {

        uint32_t addr;

        /* normaly, since we updated PC */

        addr = (long)s->pc;

        tcg_gen_movi_i32(var, addr);

    } else {

        tcg_gen_mov_i32(var, cpu_R[reg]);

    }

}

/* Create a new temporary and set it to the value of a CPU register.  */

static inline TCGv load_reg(DisasContext *s, int reg)

{

    TCGv tmp = new_tmp();

    load_reg_var(s, tmp, reg);

    return tmp;

}

/* Set a CPU register.  The source must be a temporary and will be

   marked as dead.  */

static void store_reg(DisasContext *s, int reg, TCGv var)

{

    if (reg == 31) {

        tcg_gen_andi_i32(var, var, ~3);

        s->is_jmp = DISAS_JUMP;

    }

    tcg_gen_mov_i32(cpu_R[reg], var);

    dead_tmp(var);

}

/* Value extensions.  */

#define gen_uxtb(var)           tcg_gen_ext8u_i32(var, var)

#define gen_uxth(var)           tcg_gen_ext16u_i32(var, var)

#define gen_sxtb(var)           tcg_gen_ext8s_i32(var, var)

#define gen_sxth(var)           tcg_gen_ext16s_i32(var, var)

#define UCOP_REG_M              (((insn) >>  0) & 0x1f)

#define UCOP_REG_N              (((insn) >> 19) & 0x1f)

#define UCOP_REG_D              (((insn) >> 14) & 0x1f)

#define UCOP_REG_S              (((insn) >>  9) & 0x1f)

#define UCOP_REG_LO             (((insn) >> 14) & 0x1f)

#define UCOP_REG_HI             (((insn) >>  9) & 0x1f)

#define UCOP_SH_OP              (((insn) >>  6) & 0x03)

#define UCOP_SH_IM              (((insn) >>  9) & 0x1f)

#define UCOP_OPCODES            (((insn) >> 25) & 0x0f)

#define UCOP_IMM_9              (((insn) >>  0) & 0x1ff)

#define UCOP_IMM10              (((insn) >>  0) & 0x3ff)

#define UCOP_IMM14              (((insn) >>  0) & 0x3fff)

#define UCOP_COND               (((insn) >> 25) & 0x0f)

#define UCOP_CMOV_COND          (((insn) >> 19) & 0x0f)

#define UCOP_CPNUM              (((insn) >> 10) & 0x0f)

#define UCOP_UCF64_FMT          (((insn) >> 24) & 0x03)

#define UCOP_UCF64_FUNC         (((insn) >>  6) & 0x0f)

#define UCOP_UCF64_COND         (((insn) >>  6) & 0x0f)

#define UCOP_SET(i)             ((insn) & (1 << (i)))

#define UCOP_SET_P              UCOP_SET(28)

#define UCOP_SET_U              UCOP_SET(27)

#define UCOP_SET_B              UCOP_SET(26)

#define UCOP_SET_W              UCOP_SET(25)

#define UCOP_SET_L              UCOP_SET(24)

#define UCOP_SET_S              UCOP_SET(24)

#define ILLEGAL         cpu_abort(env,                                  \

                        "Illegal UniCore32 instruction %x at line %d!", \

                        insn, __LINE__)

static inline void gen_set_asr(TCGv var, uint32_t mask)

{

    TCGv tmp_mask = tcg_const_i32(mask);

    gen_helper_asr_write(var, tmp_mask);

    tcg_temp_free_i32(tmp_mask);

}

/* Set NZCV flags from the high 4 bits of var.  */

#define gen_set_nzcv(var) gen_set_asr(var, ASR_NZCV)

static void gen_exception(int excp)

{

    TCGv tmp = new_tmp();

    tcg_gen_movi_i32(tmp, excp);

    gen_helper_exception(tmp);

    dead_tmp(tmp);

}

/* FIXME: Most targets have native widening multiplication.

   It would be good to use that instead of a full wide multiply.  */

/* 32x32->64 multiply.  Marks inputs as dead.  */

static TCGv_i64 gen_mulu_i64_i32(TCGv a, TCGv b)

{

    TCGv_i64 tmp1 = tcg_temp_new_i64();

    TCGv_i64 tmp2 = tcg_temp_new_i64();

    tcg_gen_extu_i32_i64(tmp1, a);

    dead_tmp(a);

    tcg_gen_extu_i32_i64(tmp2, b);

    dead_tmp(b);

    tcg_gen_mul_i64(tmp1, tmp1, tmp2);

    tcg_temp_free_i64(tmp2);

    return tmp1;

}

static TCGv_i64 gen_muls_i64_i32(TCGv a, TCGv b)

{

    TCGv_i64 tmp1 = tcg_temp_new_i64();

    TCGv_i64 tmp2 = tcg_temp_new_i64();

    tcg_gen_ext_i32_i64(tmp1, a);

    dead_tmp(a);

    tcg_gen_ext_i32_i64(tmp2, b);

    dead_tmp(b);

    tcg_gen_mul_i64(tmp1, tmp1, tmp2);

    tcg_temp_free_i64(tmp2);

    return tmp1;

}

#define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF))

/* Set CF to the top bit of var.  */

static void gen_set_CF_bit31(TCGv var)

{

    TCGv tmp = new_tmp();

    tcg_gen_shri_i32(tmp, var, 31);

    gen_set_CF(tmp);

    dead_tmp(tmp);

}

/* Set N and Z flags from var.  */

static inline void gen_logic_CC(TCGv var)

{

    tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, NF));

    tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, ZF));

}

/* dest = T0 + T1 + CF. */

static void gen_add_carry(TCGv dest, TCGv t0, TCGv t1)

{

    TCGv tmp;

    tcg_gen_add_i32(dest, t0, t1);

    tmp = load_cpu_field(CF);

    tcg_gen_add_i32(dest, dest, tmp);

    dead_tmp(tmp);

}

/* dest = T0 - T1 + CF - 1.  */

static void gen_sub_carry(TCGv dest, TCGv t0, TCGv t1)

{

    TCGv tmp;

    tcg_gen_sub_i32(dest, t0, t1);

    tmp = load_cpu_field(CF);

    tcg_gen_add_i32(dest, dest, tmp);

    tcg_gen_subi_i32(dest, dest, 1);

    dead_tmp(tmp);

}

static void shifter_out_im(TCGv var, int shift)

{

    TCGv tmp = new_tmp();

    if (shift == 0) {

        tcg_gen_andi_i32(tmp, var, 1);

    } else {

        tcg_gen_shri_i32(tmp, var, shift);

        if (shift != 31) {

            tcg_gen_andi_i32(tmp, tmp, 1);

        }

    }

    gen_set_CF(tmp);

    dead_tmp(tmp);

}

/* Shift by immediate.  Includes special handling for shift == 0.  */

static inline void gen_uc32_shift_im(TCGv var, int shiftop, int shift,

        int flags)

{

    switch (shiftop) {

    case 0: /* LSL */

        if (shift != 0) {

            if (flags) {

                shifter_out_im(var, 32 - shift);

            }

            tcg_gen_shli_i32(var, var, shift);

        }

        break;

    case 1: /* LSR */

        if (shift == 0) {

            if (flags) {

                tcg_gen_shri_i32(var, var, 31);

                gen_set_CF(var);

            }

            tcg_gen_movi_i32(var, 0);

        } else {

            if (flags) {

                shifter_out_im(var, shift - 1);

            }

            tcg_gen_shri_i32(var, var, shift);

        }

        break;

    case 2: /* ASR */

        if (shift == 0) {

            shift = 32;

        }

        if (flags) {

            shifter_out_im(var, shift - 1);

        }

        if (shift == 32) {

            shift = 31;

        }

        tcg_gen_sari_i32(var, var, shift);

        break;

    case 3: /* ROR/RRX */

        if (shift != 0) {

            if (flags) {

                shifter_out_im(var, shift - 1);

            }

            tcg_gen_rotri_i32(var, var, shift); break;

        } else {

            TCGv tmp = load_cpu_field(CF);

            if (flags) {

                shifter_out_im(var, 0);

            }

            tcg_gen_shri_i32(var, var, 1);

            tcg_gen_shli_i32(tmp, tmp, 31);

            tcg_gen_or_i32(var, var, tmp);

            dead_tmp(tmp);

        }

    }

};

static inline void gen_uc32_shift_reg(TCGv var, int shiftop,

                                     TCGv shift, int flags)

{

    if (flags) {

        switch (shiftop) {

        case 0:

            gen_helper_shl_cc(var, var, shift);

            break;

        case 1:

            gen_helper_shr_cc(var, var, shift);

            break;

        case 2:

            gen_helper_sar_cc(var, var, shift);

            break;

        case 3:

            gen_helper_ror_cc(var, var, shift);

            break;

        }

    } else {

        switch (shiftop) {

        case 0:

            gen_helper_shl(var, var, shift);

            break;

        case 1:

            gen_helper_shr(var, var, shift);

            break;

        case 2:

            gen_helper_sar(var, var, shift);

            break;

        case 3:

            tcg_gen_andi_i32(shift, shift, 0x1f);

            tcg_gen_rotr_i32(var, var, shift);

            break;

        }

    }

    dead_tmp(shift);

}

static void gen_test_cc(int cc, int label)

{

    TCGv tmp;

    TCGv tmp2;

    int inv;

    switch (cc) {

    case 0: /* eq: Z */

        tmp = load_cpu_field(ZF);

        tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);

        break;

    case 1: /* ne: !Z */

        tmp = load_cpu_field(ZF);

        tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);

        break;

    case 2: /* cs: C */

        tmp = load_cpu_field(CF);

        tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);

        break;

    case 3: /* cc: !C */

        tmp = load_cpu_field(CF);

        tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);

        break;

    case 4: /* mi: N */

        tmp = load_cpu_field(NF);

        tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);

        break;

    case 5: /* pl: !N */

        tmp = load_cpu_field(NF);

        tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);

        break;

    case 6: /* vs: V */

        tmp = load_cpu_field(VF);

        tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);

        break;

    case 7: /* vc: !V */

        tmp = load_cpu_field(VF);

        tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);

        break;

    case 8: /* hi: C && !Z */

        inv = gen_new_label();

        tmp = load_cpu_field(CF);

        tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);

        dead_tmp(tmp);

        tmp = load_cpu_field(ZF);

        tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);

        gen_set_label(inv);

        break;

    case 9: /* ls: !C || Z */

        tmp = load_cpu_field(CF);

        tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);

        dead_tmp(tmp);

        tmp = load_cpu_field(ZF);

        tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);

        break;

    case 10: /* ge: N == V -> N ^ V == 0 */

        tmp = load_cpu_field(VF);

        tmp2 = load_cpu_field(NF);

        tcg_gen_xor_i32(tmp, tmp, tmp2);

        dead_tmp(tmp2);

        tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);

        break;

    case 11: /* lt: N != V -> N ^ V != 0 */

        tmp = load_cpu_field(VF);

        tmp2 = load_cpu_field(NF);

        tcg_gen_xor_i32(tmp, tmp, tmp2);

        dead_tmp(tmp2);

        tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);

        break;

    case 12: /* gt: !Z && N == V */

        inv = gen_new_label();

        tmp = load_cpu_field(ZF);

        tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);

        dead_tmp(tmp);

        tmp = load_cpu_field(VF);

        tmp2 = load_cpu_field(NF);

        tcg_gen_xor_i32(tmp, tmp, tmp2);

        dead_tmp(tmp2);

        tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);

        gen_set_label(inv);

        break;

    case 13: /* le: Z || N != V */

        tmp = load_cpu_field(ZF);

        tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);

        dead_tmp(tmp);

        tmp = load_cpu_field(VF);

        tmp2 = load_cpu_field(NF);

        tcg_gen_xor_i32(tmp, tmp, tmp2);

        dead_tmp(tmp2);

        tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);

        break;

    default:

        fprintf(stderr, "Bad condition code 0x%x\n", cc);

        abort();

    }

    dead_tmp(tmp);

}

static const uint8_t table_logic_cc[16] = {

    1, /* and */    1, /* xor */    0, /* sub */    0, /* rsb */

    0, /* add */    0, /* adc */    0, /* sbc */    0, /* rsc */

    1, /* andl */   1, /* xorl */   0, /* cmp */    0, /* cmn */

    1, /* orr */    1, /* mov */    1, /* bic */    1, /* mvn */

};

/* Set PC state from an immediate address.  */

static inline void gen_bx_im(DisasContext *s, uint32_t addr)

{

    s->is_jmp = DISAS_UPDATE;

    tcg_gen_movi_i32(cpu_R[31], addr & ~3);

}

/* Set PC state from var.  var is marked as dead.  */

static inline void gen_bx(DisasContext *s, TCGv var)

{

    s->is_jmp = DISAS_UPDATE;

    tcg_gen_andi_i32(cpu_R[31], var, ~3);

    dead_tmp(var);

}

static inline void store_reg_bx(DisasContext *s, int reg, TCGv var)

{

    store_reg(s, reg, var);

}

static inline TCGv gen_ld8s(TCGv addr, int index)

{

    TCGv tmp = new_tmp();

    tcg_gen_qemu_ld8s(tmp, addr, index);

    return tmp;

}

static inline TCGv gen_ld8u(TCGv addr, int index)

{

    TCGv tmp = new_tmp();

    tcg_gen_qemu_ld8u(tmp, addr, index);

    return tmp;

}

static inline TCGv gen_ld16s(TCGv addr, int index)

{

    TCGv tmp = new_tmp();

    tcg_gen_qemu_ld16s(tmp, addr, index);

    return tmp;

}

static inline TCGv gen_ld16u(TCGv addr, int index)

{

    TCGv tmp = new_tmp();

    tcg_gen_qemu_ld16u(tmp, addr, index);

    return tmp;

}

static inline TCGv gen_ld32(TCGv addr, int index)

{

    TCGv tmp = new_tmp();

    tcg_gen_qemu_ld32u(tmp, addr, index);

    return tmp;

}

static inline TCGv_i64 gen_ld64(TCGv addr, int index)

{

    TCGv_i64 tmp = tcg_temp_new_i64();

    tcg_gen_qemu_ld64(tmp, addr, index);

    return tmp;

}

static inline void gen_st8(TCGv val, TCGv addr, int index)

{

    tcg_gen_qemu_st8(val, addr, index);

    dead_tmp(val);

}

static inline void gen_st16(TCGv val, TCGv addr, int index)

{

    tcg_gen_qemu_st16(val, addr, index);

    dead_tmp(val);

}

static inline void gen_st32(TCGv val, TCGv addr, int index)

{

    tcg_gen_qemu_st32(val, addr, index);

    dead_tmp(val);

}

static inline void gen_st64(TCGv_i64 val, TCGv addr, int index)

{

    tcg_gen_qemu_st64(val, addr, index);

    tcg_temp_free_i64(val);

}

static inline void gen_set_pc_im(uint32_t val)

{

    tcg_gen_movi_i32(cpu_R[31], val);

}

/* Force a TB lookup after an instruction that changes the CPU state.  */

static inline void gen_lookup_tb(DisasContext *s)

{

    tcg_gen_movi_i32(cpu_R[31], s->pc & ~1);

    s->is_jmp = DISAS_UPDATE;

}

static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,

        TCGv var)

{

    int val;

    TCGv offset;

    if (UCOP_SET(29)) {

        /* immediate */

        val = UCOP_IMM14;

        if (!UCOP_SET_U) {

            val = -val;

        }

        if (val != 0) {

            tcg_gen_addi_i32(var, var, val);

        }

    } else {

        /* shift/register */

        offset = load_reg(s, UCOP_REG_M);

        gen_uc32_shift_im(offset, UCOP_SH_OP, UCOP_SH_IM, 0);

        if (!UCOP_SET_U) {

            tcg_gen_sub_i32(var, var, offset);

        } else {

            tcg_gen_add_i32(var, var, offset);

        }

        dead_tmp(offset);

    }

}

static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn,

        TCGv var)

{

    int val;

    TCGv offset;

    if (UCOP_SET(26)) {

        /* immediate */

        val = (insn & 0x1f) | ((insn >> 4) & 0x3e0);

        if (!UCOP_SET_U) {

            val = -val;

        }

        if (val != 0) {

            tcg_gen_addi_i32(var, var, val);

        }

    } else {

        /* register */

        offset = load_reg(s, UCOP_REG_M);

        if (!UCOP_SET_U) {

            tcg_gen_sub_i32(var, var, offset);

        } else {

            tcg_gen_add_i32(var, var, offset);

        }

        dead_tmp(offset);

    }

}

static inline long ucf64_reg_offset(int reg)

{

    if (reg & 1) {

        return offsetof(CPUState, ucf64.regs[reg >> 1])

          + offsetof(CPU_DoubleU, l.upper);

    } else {

        return offsetof(CPUState, ucf64.regs[reg >> 1])

          + offsetof(CPU_DoubleU, l.lower);

    }

}

#define ucf64_gen_ld32(reg)      load_cpu_offset(ucf64_reg_offset(reg))

#define ucf64_gen_st32(var, reg) store_cpu_offset(var, ucf64_reg_offset(reg))

/* UniCore-F64 single load/store I_offset */

static void do_ucf64_ldst_i(CPUState *env, DisasContext *s, uint32_t insn)

{

    int offset;

    TCGv tmp;

    TCGv addr;

    addr = load_reg(s, UCOP_REG_N);

    if (!UCOP_SET_P && !UCOP_SET_W) {

        ILLEGAL;

    }

    if (UCOP_SET_P) {

        offset = UCOP_IMM10 << 2;

        if (!UCOP_SET_U) {

            offset = -offset;

        }

        if (offset != 0) {

            tcg_gen_addi_i32(addr, addr, offset);

        }

    }

    if (UCOP_SET_L) { /* load */

        tmp = gen_ld32(addr, IS_USER(s));

        ucf64_gen_st32(tmp, UCOP_REG_D);

    } else { /* store */

        tmp = ucf64_gen_ld32(UCOP_REG_D);

        gen_st32(tmp, addr, IS_USER(s));

    }

    if (!UCOP_SET_P) {

        offset = UCOP_IMM10 << 2;

        if (!UCOP_SET_U) {

            offset = -offset;

        }

        if (offset != 0) {

            tcg_gen_addi_i32(addr, addr, offset);

        }

    }

    if (UCOP_SET_W) {

        store_reg(s, UCOP_REG_N, addr);

    } else {

        dead_tmp(addr);

    }

}

/* UniCore-F64 load/store multiple words */

static void do_ucf64_ldst_m(CPUState *env, DisasContext *s, uint32_t insn)

{

    unsigned int i;

    int j, n, freg;

    TCGv tmp;

    TCGv addr;

    if (UCOP_REG_D != 0) {

        ILLEGAL;

    }

    if (UCOP_REG_N == 31) {

        ILLEGAL;

    }

    if ((insn << 24) == 0) {

        ILLEGAL;

    }

    addr = load_reg(s, UCOP_REG_N);

    n = 0;

    for (i = 0; i < 8; i++) {

        if (UCOP_SET(i)) {

            n++;

        }

    }

    if (UCOP_SET_U) {

        if (UCOP_SET_P) { /* pre increment */

            tcg_gen_addi_i32(addr, addr, 4);

        } /* unnecessary to do anything when post increment */

    } else {

        if (UCOP_SET_P) { /* pre decrement */

            tcg_gen_addi_i32(addr, addr, -(n * 4));

        } else { /* post decrement */

            if (n != 1) {

                tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));

            }

        }

    }

    freg = ((insn >> 8) & 3) << 3; /* freg should be 0, 8, 16, 24 */

    for (i = 0, j = 0; i < 8; i++, freg++) {

        if (!UCOP_SET(i)) {

            continue;

        }

        if (UCOP_SET_L) { /* load */

            tmp = gen_ld32(addr, IS_USER(s));

            ucf64_gen_st32(tmp, freg);

        } else { /* store */

            tmp = ucf64_gen_ld32(freg);

            gen_st32(tmp, addr, IS_USER(s));

        }

        j++;

        /* unnecessary to add after the last transfer */

        if (j != n) {

            tcg_gen_addi_i32(addr, addr, 4);

        }

    }

    if (UCOP_SET_W) { /* write back */

        if (UCOP_SET_U) {

            if (!UCOP_SET_P) { /* post increment */

                tcg_gen_addi_i32(addr, addr, 4);

            } /* unnecessary to do anything when pre increment */

        } else {

            if (UCOP_SET_P) {

                /* pre decrement */

                if (n != 1) {

                    tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));

                }

            } else {

                /* post decrement */

                tcg_gen_addi_i32(addr, addr, -(n * 4));

            }

        }

        store_reg(s, UCOP_REG_N, addr);

    } else {

        dead_tmp(addr);

    }

}

/* UniCore-F64 mrc/mcr */

static void do_ucf64_trans(CPUState *env, DisasContext *s, uint32_t insn)

{

    TCGv tmp;

    if ((insn & 0xfe0003ff) == 0xe2000000) {

        /* control register */

        if ((UCOP_REG_N != UC32_UCF64_FPSCR) || (UCOP_REG_D == 31)) {

            ILLEGAL;

        }

        if (UCOP_SET(24)) {

            /* CFF */

            tmp = new_tmp();

            gen_helper_ucf64_get_fpscr(tmp, cpu_env);

            store_reg(s, UCOP_REG_D, tmp);

        } else {

            /* CTF */

            tmp = load_reg(s, UCOP_REG_D);

            gen_helper_ucf64_set_fpscr(cpu_env, tmp);

            dead_tmp(tmp);

            gen_lookup_tb(s);

        }

        return;

    }

    if ((insn & 0xfe0003ff) == 0xe0000000) {

        /* general register */

        if (UCOP_REG_D == 31) {

            ILLEGAL;

        }

        if (UCOP_SET(24)) { /* MFF */

            tmp = ucf64_gen_ld32(UCOP_REG_N);

            store_reg(s, UCOP_REG_D, tmp);

        } else { /* MTF */

            tmp = load_reg(s, UCOP_REG_D);

            ucf64_gen_st32(tmp, UCOP_REG_N);

        }

        return;

    }

    if ((insn & 0xfb000000) == 0xe9000000) {

        /* MFFC */

        if (UCOP_REG_D != 31) {

            ILLEGAL;

        }

        if (UCOP_UCF64_COND & 0x8) {

            ILLEGAL;

        }

        tmp = new_tmp();

        tcg_gen_movi_i32(tmp, UCOP_UCF64_COND);

        if (UCOP_SET(26)) {

            tcg_gen_ld_i64(cpu_F0d, cpu_env, ucf64_reg_offset(UCOP_REG_N));

            tcg_gen_ld_i64(cpu_F1d, cpu_env, ucf64_reg_offset(UCOP_REG_M));

            gen_helper_ucf64_cmpd(cpu_F0d, cpu_F1d, tmp, cpu_env);

        } else {

            tcg_gen_ld_i32(cpu_F0s, cpu_env, ucf64_reg_offset(UCOP_REG_N));

            tcg_gen_ld_i32(cpu_F1s, cpu_env, ucf64_reg_offset(UCOP_REG_M));

            gen_helper_ucf64_cmps(cpu_F0s, cpu_F1s, tmp, cpu_env);

        }

        dead_tmp(tmp);

        return;

    }

    ILLEGAL;

}

/* UniCore-F64 convert instructions */

static void do_ucf64_fcvt(CPUState *env, DisasContext *s, uint32_t insn)

{

    if (UCOP_UCF64_FMT == 3) {

        ILLEGAL;

    }

    if (UCOP_REG_N != 0) {

        ILLEGAL;

    }

    switch (UCOP_UCF64_FUNC) {

    case 0: /* cvt.s */

        switch (UCOP_UCF64_FMT) {

        case 1 /* d */:

            tcg_gen_ld_i64(cpu_F0d, cpu_env, ucf64_reg_offset(UCOP_REG_M));

            gen_helper_ucf64_df2sf(cpu_F0s, cpu_F0d, cpu_env);

            tcg_gen_st_i32(cpu_F0s, cpu_env, ucf64_reg_offset(UCOP_REG_D));

            break;

        case 2 /* w */:

            tcg_gen_ld_i32(cpu_F0s, cpu_env, ucf64_reg_offset(UCOP_REG_M));

            gen_helper_ucf64_si2sf(cpu_F0s, cpu_F0s, cpu_env);

            tcg_gen_st_i32(cpu_F0s, cpu_env, ucf64_reg_offset(UCOP_REG_D));

            break;

        default /* s */:

            ILLEGAL;

            break;

        }

        break;

    case 1: /* cvt.d */

        switch (UCOP_UCF64_FMT) {

        case 0 /* s */:

            tcg_gen_ld_i32(cpu_F0s, cpu_env, ucf64_reg_offset(UCOP_REG_M));

            gen_helper_ucf64_sf2df(cpu_F0d, cpu_F0s, cpu_env);

            tcg_gen_st_i64(cpu_F0d, cpu_env, ucf64_reg_offset(UCOP_REG_D));

            break;

        case 2 /* w */:

            tcg_gen_ld_i32(cpu_F0s, cpu_env, ucf64_reg_offset(UCOP_REG_M));

            gen_helper_ucf64_si2df(cpu_F0d, cpu_F0s, cpu_env);

            tcg_gen_st_i64(cpu_F0d, cpu_env, ucf64_reg_offset(UCOP_REG_D));

            break;

        default /* d */:

            ILLEGAL;

            break;