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1 | c896fe29 | bellard | /*
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2 | c896fe29 | bellard | * Tiny Code Generator for QEMU
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3 | c896fe29 | bellard | *
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4 | c896fe29 | bellard | * Copyright (c) 2008 Fabrice Bellard
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5 | c896fe29 | bellard | *
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6 | c896fe29 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | c896fe29 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | c896fe29 | bellard | * in the Software without restriction, including without limitation the rights
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9 | c896fe29 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | c896fe29 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | c896fe29 | bellard | * furnished to do so, subject to the following conditions:
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12 | c896fe29 | bellard | *
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13 | c896fe29 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | c896fe29 | bellard | * all copies or substantial portions of the Software.
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15 | c896fe29 | bellard | *
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16 | c896fe29 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | c896fe29 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | c896fe29 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | c896fe29 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | c896fe29 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | c896fe29 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | c896fe29 | bellard | * THE SOFTWARE.
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23 | c896fe29 | bellard | */
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24 | c896fe29 | bellard | #ifndef DEF2
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25 | c896fe29 | bellard | #define DEF2(name, oargs, iargs, cargs, flags) DEF(name, oargs + iargs + cargs, 0) |
26 | c896fe29 | bellard | #endif
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27 | c896fe29 | bellard | |
28 | c896fe29 | bellard | /* predefined ops */
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29 | c896fe29 | bellard | DEF2(end, 0, 0, 0, 0) /* must be kept first */ |
30 | c896fe29 | bellard | DEF2(nop, 0, 0, 0, 0) |
31 | c896fe29 | bellard | DEF2(nop1, 0, 0, 1, 0) |
32 | c896fe29 | bellard | DEF2(nop2, 0, 0, 2, 0) |
33 | c896fe29 | bellard | DEF2(nop3, 0, 0, 3, 0) |
34 | c896fe29 | bellard | DEF2(nopn, 0, 0, 1, 0) /* variable number of parameters */ |
35 | c896fe29 | bellard | |
36 | 5ff9d6a4 | bellard | DEF2(discard, 1, 0, 0, 0) |
37 | 5ff9d6a4 | bellard | |
38 | c896fe29 | bellard | DEF2(set_label, 0, 0, 1, 0) |
39 | 5ff9d6a4 | bellard | DEF2(call, 0, 1, 2, TCG_OPF_SIDE_EFFECTS) /* variable number of parameters */ |
40 | 5ff9d6a4 | bellard | DEF2(jmp, 0, 1, 0, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
41 | 5ff9d6a4 | bellard | DEF2(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
42 | c896fe29 | bellard | |
43 | c896fe29 | bellard | DEF2(mov_i32, 1, 1, 0, 0) |
44 | c896fe29 | bellard | DEF2(movi_i32, 1, 0, 1, 0) |
45 | be210acb | Richard Henderson | DEF2(setcond_i32, 1, 2, 1, 0) |
46 | c896fe29 | bellard | /* load/store */
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47 | c896fe29 | bellard | DEF2(ld8u_i32, 1, 1, 1, 0) |
48 | c896fe29 | bellard | DEF2(ld8s_i32, 1, 1, 1, 0) |
49 | c896fe29 | bellard | DEF2(ld16u_i32, 1, 1, 1, 0) |
50 | c896fe29 | bellard | DEF2(ld16s_i32, 1, 1, 1, 0) |
51 | c896fe29 | bellard | DEF2(ld_i32, 1, 1, 1, 0) |
52 | 5ff9d6a4 | bellard | DEF2(st8_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) |
53 | 5ff9d6a4 | bellard | DEF2(st16_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) |
54 | 5ff9d6a4 | bellard | DEF2(st_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) |
55 | c896fe29 | bellard | /* arith */
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56 | c896fe29 | bellard | DEF2(add_i32, 1, 2, 0, 0) |
57 | c896fe29 | bellard | DEF2(sub_i32, 1, 2, 0, 0) |
58 | c896fe29 | bellard | DEF2(mul_i32, 1, 2, 0, 0) |
59 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_div_i32
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60 | c896fe29 | bellard | DEF2(div_i32, 1, 2, 0, 0) |
61 | c896fe29 | bellard | DEF2(divu_i32, 1, 2, 0, 0) |
62 | c896fe29 | bellard | DEF2(rem_i32, 1, 2, 0, 0) |
63 | c896fe29 | bellard | DEF2(remu_i32, 1, 2, 0, 0) |
64 | 30138f28 | Aurelien Jarno | #endif
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65 | 30138f28 | Aurelien Jarno | #ifdef TCG_TARGET_HAS_div2_i32
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66 | c896fe29 | bellard | DEF2(div2_i32, 2, 3, 0, 0) |
67 | c896fe29 | bellard | DEF2(divu2_i32, 2, 3, 0, 0) |
68 | c896fe29 | bellard | #endif
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69 | c896fe29 | bellard | DEF2(and_i32, 1, 2, 0, 0) |
70 | c896fe29 | bellard | DEF2(or_i32, 1, 2, 0, 0) |
71 | c896fe29 | bellard | DEF2(xor_i32, 1, 2, 0, 0) |
72 | d42f183c | aurel32 | /* shifts/rotates */
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73 | c896fe29 | bellard | DEF2(shl_i32, 1, 2, 0, 0) |
74 | c896fe29 | bellard | DEF2(shr_i32, 1, 2, 0, 0) |
75 | c896fe29 | bellard | DEF2(sar_i32, 1, 2, 0, 0) |
76 | f31e9370 | aurel32 | #ifdef TCG_TARGET_HAS_rot_i32
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77 | d42f183c | aurel32 | DEF2(rotl_i32, 1, 2, 0, 0) |
78 | d42f183c | aurel32 | DEF2(rotr_i32, 1, 2, 0, 0) |
79 | f31e9370 | aurel32 | #endif
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80 | c896fe29 | bellard | |
81 | 5ff9d6a4 | bellard | DEF2(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
82 | c896fe29 | bellard | #if TCG_TARGET_REG_BITS == 32 |
83 | c896fe29 | bellard | DEF2(add2_i32, 2, 4, 0, 0) |
84 | c896fe29 | bellard | DEF2(sub2_i32, 2, 4, 0, 0) |
85 | 5ff9d6a4 | bellard | DEF2(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
86 | c896fe29 | bellard | DEF2(mulu2_i32, 2, 2, 0, 0) |
87 | be210acb | Richard Henderson | DEF2(setcond2_i32, 1, 4, 1, 0) |
88 | c896fe29 | bellard | #endif
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89 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_ext8s_i32
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90 | c896fe29 | bellard | DEF2(ext8s_i32, 1, 1, 0, 0) |
91 | c896fe29 | bellard | #endif
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92 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_ext16s_i32
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93 | c896fe29 | bellard | DEF2(ext16s_i32, 1, 1, 0, 0) |
94 | c896fe29 | bellard | #endif
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95 | cfc86988 | Aurelien Jarno | #ifdef TCG_TARGET_HAS_ext8u_i32
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96 | cfc86988 | Aurelien Jarno | DEF2(ext8u_i32, 1, 1, 0, 0) |
97 | cfc86988 | Aurelien Jarno | #endif
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98 | cfc86988 | Aurelien Jarno | #ifdef TCG_TARGET_HAS_ext16u_i32
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99 | cfc86988 | Aurelien Jarno | DEF2(ext16u_i32, 1, 1, 0, 0) |
100 | cfc86988 | Aurelien Jarno | #endif
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101 | 84aafb06 | aurel32 | #ifdef TCG_TARGET_HAS_bswap16_i32
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102 | 84aafb06 | aurel32 | DEF2(bswap16_i32, 1, 1, 0, 0) |
103 | 84aafb06 | aurel32 | #endif
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104 | 66896cb8 | aurel32 | #ifdef TCG_TARGET_HAS_bswap32_i32
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105 | 66896cb8 | aurel32 | DEF2(bswap32_i32, 1, 1, 0, 0) |
106 | c896fe29 | bellard | #endif
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107 | 0dd0dd55 | aurel32 | #ifdef TCG_TARGET_HAS_not_i32
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108 | 0dd0dd55 | aurel32 | DEF2(not_i32, 1, 1, 0, 0) |
109 | 0dd0dd55 | aurel32 | #endif
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110 | 0dd0dd55 | aurel32 | #ifdef TCG_TARGET_HAS_neg_i32
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111 | 0dd0dd55 | aurel32 | DEF2(neg_i32, 1, 1, 0, 0) |
112 | 0dd0dd55 | aurel32 | #endif
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113 | 241cbed4 | Richard Henderson | #ifdef TCG_TARGET_HAS_andc_i32
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114 | 241cbed4 | Richard Henderson | DEF2(andc_i32, 1, 2, 0, 0) |
115 | 241cbed4 | Richard Henderson | #endif
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116 | 791d1262 | Richard Henderson | #ifdef TCG_TARGET_HAS_orc_i32
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117 | 791d1262 | Richard Henderson | DEF2(orc_i32, 1, 2, 0, 0) |
118 | 791d1262 | Richard Henderson | #endif
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119 | 8d625cf1 | Richard Henderson | #ifdef TCG_TARGET_HAS_eqv_i32
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120 | 8d625cf1 | Richard Henderson | DEF2(eqv_i32, 1, 2, 0, 0) |
121 | 8d625cf1 | Richard Henderson | #endif
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122 | 9940a96b | Richard Henderson | #ifdef TCG_TARGET_HAS_nand_i32
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123 | 9940a96b | Richard Henderson | DEF2(nand_i32, 1, 2, 0, 0) |
124 | 9940a96b | Richard Henderson | #endif
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125 | 32d98fbd | Richard Henderson | #ifdef TCG_TARGET_HAS_nor_i32
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126 | 32d98fbd | Richard Henderson | DEF2(nor_i32, 1, 2, 0, 0) |
127 | 32d98fbd | Richard Henderson | #endif
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128 | c896fe29 | bellard | |
129 | c896fe29 | bellard | #if TCG_TARGET_REG_BITS == 64 |
130 | c896fe29 | bellard | DEF2(mov_i64, 1, 1, 0, 0) |
131 | c896fe29 | bellard | DEF2(movi_i64, 1, 0, 1, 0) |
132 | be210acb | Richard Henderson | DEF2(setcond_i64, 1, 2, 1, 0) |
133 | c896fe29 | bellard | /* load/store */
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134 | c896fe29 | bellard | DEF2(ld8u_i64, 1, 1, 1, 0) |
135 | c896fe29 | bellard | DEF2(ld8s_i64, 1, 1, 1, 0) |
136 | c896fe29 | bellard | DEF2(ld16u_i64, 1, 1, 1, 0) |
137 | c896fe29 | bellard | DEF2(ld16s_i64, 1, 1, 1, 0) |
138 | c896fe29 | bellard | DEF2(ld32u_i64, 1, 1, 1, 0) |
139 | c896fe29 | bellard | DEF2(ld32s_i64, 1, 1, 1, 0) |
140 | c896fe29 | bellard | DEF2(ld_i64, 1, 1, 1, 0) |
141 | 5ff9d6a4 | bellard | DEF2(st8_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) |
142 | 5ff9d6a4 | bellard | DEF2(st16_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) |
143 | 5ff9d6a4 | bellard | DEF2(st32_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) |
144 | 5ff9d6a4 | bellard | DEF2(st_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) |
145 | c896fe29 | bellard | /* arith */
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146 | c896fe29 | bellard | DEF2(add_i64, 1, 2, 0, 0) |
147 | c896fe29 | bellard | DEF2(sub_i64, 1, 2, 0, 0) |
148 | c896fe29 | bellard | DEF2(mul_i64, 1, 2, 0, 0) |
149 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_div_i64
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150 | c896fe29 | bellard | DEF2(div_i64, 1, 2, 0, 0) |
151 | c896fe29 | bellard | DEF2(divu_i64, 1, 2, 0, 0) |
152 | c896fe29 | bellard | DEF2(rem_i64, 1, 2, 0, 0) |
153 | c896fe29 | bellard | DEF2(remu_i64, 1, 2, 0, 0) |
154 | 30138f28 | Aurelien Jarno | #endif
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155 | 30138f28 | Aurelien Jarno | #ifdef TCG_TARGET_HAS_div2_i64
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156 | c896fe29 | bellard | DEF2(div2_i64, 2, 3, 0, 0) |
157 | c896fe29 | bellard | DEF2(divu2_i64, 2, 3, 0, 0) |
158 | c896fe29 | bellard | #endif
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159 | c896fe29 | bellard | DEF2(and_i64, 1, 2, 0, 0) |
160 | c896fe29 | bellard | DEF2(or_i64, 1, 2, 0, 0) |
161 | c896fe29 | bellard | DEF2(xor_i64, 1, 2, 0, 0) |
162 | d42f183c | aurel32 | /* shifts/rotates */
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163 | c896fe29 | bellard | DEF2(shl_i64, 1, 2, 0, 0) |
164 | c896fe29 | bellard | DEF2(shr_i64, 1, 2, 0, 0) |
165 | c896fe29 | bellard | DEF2(sar_i64, 1, 2, 0, 0) |
166 | f31e9370 | aurel32 | #ifdef TCG_TARGET_HAS_rot_i64
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167 | d42f183c | aurel32 | DEF2(rotl_i64, 1, 2, 0, 0) |
168 | d42f183c | aurel32 | DEF2(rotr_i64, 1, 2, 0, 0) |
169 | f31e9370 | aurel32 | #endif
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170 | c896fe29 | bellard | |
171 | 5ff9d6a4 | bellard | DEF2(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
172 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_ext8s_i64
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173 | c896fe29 | bellard | DEF2(ext8s_i64, 1, 1, 0, 0) |
174 | c896fe29 | bellard | #endif
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175 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_ext16s_i64
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176 | c896fe29 | bellard | DEF2(ext16s_i64, 1, 1, 0, 0) |
177 | c896fe29 | bellard | #endif
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178 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_ext32s_i64
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179 | c896fe29 | bellard | DEF2(ext32s_i64, 1, 1, 0, 0) |
180 | c896fe29 | bellard | #endif
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181 | cfc86988 | Aurelien Jarno | #ifdef TCG_TARGET_HAS_ext8u_i64
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182 | cfc86988 | Aurelien Jarno | DEF2(ext8u_i64, 1, 1, 0, 0) |
183 | cfc86988 | Aurelien Jarno | #endif
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184 | cfc86988 | Aurelien Jarno | #ifdef TCG_TARGET_HAS_ext16u_i64
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185 | cfc86988 | Aurelien Jarno | DEF2(ext16u_i64, 1, 1, 0, 0) |
186 | cfc86988 | Aurelien Jarno | #endif
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187 | cfc86988 | Aurelien Jarno | #ifdef TCG_TARGET_HAS_ext32u_i64
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188 | cfc86988 | Aurelien Jarno | DEF2(ext32u_i64, 1, 1, 0, 0) |
189 | cfc86988 | Aurelien Jarno | #endif
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190 | 9a5c57fd | aurel32 | #ifdef TCG_TARGET_HAS_bswap16_i64
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191 | 9a5c57fd | aurel32 | DEF2(bswap16_i64, 1, 1, 0, 0) |
192 | 9a5c57fd | aurel32 | #endif
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193 | 9a5c57fd | aurel32 | #ifdef TCG_TARGET_HAS_bswap32_i64
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194 | 9a5c57fd | aurel32 | DEF2(bswap32_i64, 1, 1, 0, 0) |
195 | 9a5c57fd | aurel32 | #endif
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196 | 66896cb8 | aurel32 | #ifdef TCG_TARGET_HAS_bswap64_i64
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197 | 66896cb8 | aurel32 | DEF2(bswap64_i64, 1, 1, 0, 0) |
198 | c896fe29 | bellard | #endif
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199 | d2604285 | aurel32 | #ifdef TCG_TARGET_HAS_not_i64
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200 | d2604285 | aurel32 | DEF2(not_i64, 1, 1, 0, 0) |
201 | d2604285 | aurel32 | #endif
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202 | 390efc54 | pbrook | #ifdef TCG_TARGET_HAS_neg_i64
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203 | 390efc54 | pbrook | DEF2(neg_i64, 1, 1, 0, 0) |
204 | 390efc54 | pbrook | #endif
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205 | 241cbed4 | Richard Henderson | #ifdef TCG_TARGET_HAS_andc_i64
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206 | 241cbed4 | Richard Henderson | DEF2(andc_i64, 1, 2, 0, 0) |
207 | 241cbed4 | Richard Henderson | #endif
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208 | 791d1262 | Richard Henderson | #ifdef TCG_TARGET_HAS_orc_i64
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209 | 791d1262 | Richard Henderson | DEF2(orc_i64, 1, 2, 0, 0) |
210 | 791d1262 | Richard Henderson | #endif
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211 | 8d625cf1 | Richard Henderson | #ifdef TCG_TARGET_HAS_eqv_i64
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212 | 8d625cf1 | Richard Henderson | DEF2(eqv_i64, 1, 2, 0, 0) |
213 | 8d625cf1 | Richard Henderson | #endif
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214 | 9940a96b | Richard Henderson | #ifdef TCG_TARGET_HAS_nand_i64
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215 | 9940a96b | Richard Henderson | DEF2(nand_i64, 1, 2, 0, 0) |
216 | 9940a96b | Richard Henderson | #endif
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217 | 32d98fbd | Richard Henderson | #ifdef TCG_TARGET_HAS_nor_i64
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218 | 32d98fbd | Richard Henderson | DEF2(nor_i64, 1, 2, 0, 0) |
219 | 32d98fbd | Richard Henderson | #endif
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220 | 0dd0dd55 | aurel32 | #endif
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221 | c896fe29 | bellard | |
222 | c896fe29 | bellard | /* QEMU specific */
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223 | 7e4597d7 | bellard | #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
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224 | 7e4597d7 | bellard | DEF2(debug_insn_start, 0, 0, 2, 0) |
225 | 7e4597d7 | bellard | #else
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226 | 7e4597d7 | bellard | DEF2(debug_insn_start, 0, 0, 1, 0) |
227 | 7e4597d7 | bellard | #endif
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228 | 5ff9d6a4 | bellard | DEF2(exit_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
229 | 5ff9d6a4 | bellard | DEF2(goto_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
230 | c896fe29 | bellard | /* Note: even if TARGET_LONG_BITS is not defined, the INDEX_op
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231 | c896fe29 | bellard | constants must be defined */
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232 | c896fe29 | bellard | #if TCG_TARGET_REG_BITS == 32 |
233 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
234 | 5ff9d6a4 | bellard | DEF2(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
235 | c896fe29 | bellard | #else
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236 | 5ff9d6a4 | bellard | DEF2(qemu_ld8u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
237 | c896fe29 | bellard | #endif
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238 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
239 | 5ff9d6a4 | bellard | DEF2(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
240 | c896fe29 | bellard | #else
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241 | 5ff9d6a4 | bellard | DEF2(qemu_ld8s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
242 | c896fe29 | bellard | #endif
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243 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
244 | 5ff9d6a4 | bellard | DEF2(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
245 | c896fe29 | bellard | #else
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246 | 5ff9d6a4 | bellard | DEF2(qemu_ld16u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
247 | c896fe29 | bellard | #endif
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248 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
249 | 5ff9d6a4 | bellard | DEF2(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
250 | c896fe29 | bellard | #else
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251 | 5ff9d6a4 | bellard | DEF2(qemu_ld16s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
252 | c896fe29 | bellard | #endif
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253 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
254 | 86feb1c8 | Richard Henderson | DEF2(qemu_ld32, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
255 | c896fe29 | bellard | #else
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256 | 86feb1c8 | Richard Henderson | DEF2(qemu_ld32, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
257 | c896fe29 | bellard | #endif
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258 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
259 | 5ff9d6a4 | bellard | DEF2(qemu_ld64, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
260 | c896fe29 | bellard | #else
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261 | 5ff9d6a4 | bellard | DEF2(qemu_ld64, 2, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
262 | c896fe29 | bellard | #endif
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263 | c896fe29 | bellard | |
264 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
265 | 5ff9d6a4 | bellard | DEF2(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
266 | c896fe29 | bellard | #else
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267 | 5ff9d6a4 | bellard | DEF2(qemu_st8, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
268 | c896fe29 | bellard | #endif
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269 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
270 | 5ff9d6a4 | bellard | DEF2(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
271 | c896fe29 | bellard | #else
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272 | 5ff9d6a4 | bellard | DEF2(qemu_st16, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
273 | c896fe29 | bellard | #endif
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274 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
275 | 5ff9d6a4 | bellard | DEF2(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
276 | c896fe29 | bellard | #else
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277 | 5ff9d6a4 | bellard | DEF2(qemu_st32, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
278 | c896fe29 | bellard | #endif
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279 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
280 | 5ff9d6a4 | bellard | DEF2(qemu_st64, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
281 | c896fe29 | bellard | #else
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282 | 5ff9d6a4 | bellard | DEF2(qemu_st64, 0, 4, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
283 | c896fe29 | bellard | #endif
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284 | c896fe29 | bellard | |
285 | c896fe29 | bellard | #else /* TCG_TARGET_REG_BITS == 32 */ |
286 | c896fe29 | bellard | |
287 | 5ff9d6a4 | bellard | DEF2(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
288 | 5ff9d6a4 | bellard | DEF2(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
289 | 5ff9d6a4 | bellard | DEF2(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
290 | 5ff9d6a4 | bellard | DEF2(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
291 | 86feb1c8 | Richard Henderson | DEF2(qemu_ld32, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
292 | 5ff9d6a4 | bellard | DEF2(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
293 | 5ff9d6a4 | bellard | DEF2(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
294 | 5ff9d6a4 | bellard | DEF2(qemu_ld64, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
295 | c896fe29 | bellard | |
296 | 5ff9d6a4 | bellard | DEF2(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
297 | 5ff9d6a4 | bellard | DEF2(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
298 | 5ff9d6a4 | bellard | DEF2(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
299 | 5ff9d6a4 | bellard | DEF2(qemu_st64, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
300 | c896fe29 | bellard | |
301 | c896fe29 | bellard | #endif /* TCG_TARGET_REG_BITS != 32 */ |
302 | c896fe29 | bellard | |
303 | c896fe29 | bellard | #undef DEF2 |