Archipelago » qemu

/*

 *  ARM translation

 *

 *  Copyright (c) 2003 Fabrice Bellard

 *  Copyright (c) 2005-2007 CodeSourcery

 *  Copyright (c) 2007 OpenedHand, Ltd.

 *

 * This library is free software; you can redistribute it and/or

 * modify it under the terms of the GNU Lesser General Public

 * License as published by the Free Software Foundation; either

 * version 2 of the License, or (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public

 * License along with this library; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

 */

#include <stdarg.h>

#include <stdlib.h>

#include <stdio.h>

#include <string.h>

#include <inttypes.h>

#include "cpu.h"

#include "exec-all.h"

#include "disas.h"

#include "tcg-op.h"

#define GEN_HELPER 1

#include "helpers.h"

#define ENABLE_ARCH_5J    0

#define ENABLE_ARCH_6     arm_feature(env, ARM_FEATURE_V6)

#define ENABLE_ARCH_6K   arm_feature(env, ARM_FEATURE_V6K)

#define ENABLE_ARCH_6T2   arm_feature(env, ARM_FEATURE_THUMB2)

#define ENABLE_ARCH_7     arm_feature(env, ARM_FEATURE_V7)

#define ARCH(x) if (!ENABLE_ARCH_##x) goto illegal_op;

/* internal defines */

typedef struct DisasContext {

    target_ulong pc;

    int is_jmp;

    /* Nonzero if this instruction has been conditionally skipped.  */

    int condjmp;

    /* The label that will be jumped to when the instruction is skipped.  */

    int condlabel;

    /* Thumb-2 condtional execution bits.  */

    int condexec_mask;

    int condexec_cond;

    struct TranslationBlock *tb;

    int singlestep_enabled;

    int thumb;

    int is_mem;

#if !defined(CONFIG_USER_ONLY)

    int user;

#endif

} DisasContext;

#if defined(CONFIG_USER_ONLY)

#define IS_USER(s) 1

#else

#define IS_USER(s) (s->user)

#endif

/* These instructions trap after executing, so defer them until after the

   conditional executions state has been updated.  */

#define DISAS_WFI 4

#define DISAS_SWI 5

/* XXX: move that elsewhere */

extern FILE *logfile;

extern int loglevel;

static TCGv cpu_env;

/* FIXME:  These should be removed.  */

static TCGv cpu_T[3];

/* initialize TCG globals.  */

void arm_translate_init(void)

{

    cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");

    cpu_T[0] = tcg_global_reg_new(TCG_TYPE_I32, TCG_AREG1, "T0");

    cpu_T[1] = tcg_global_reg_new(TCG_TYPE_I32, TCG_AREG2, "T1");

    cpu_T[2] = tcg_global_reg_new(TCG_TYPE_I32, TCG_AREG3, "T2");

}

/* The code generator doesn't like lots of temporaries, so maintain our own

   cache for reuse within a function.  */

#define MAX_TEMPS 8

static int num_temps;

static TCGv temps[MAX_TEMPS];

/* Allocate a temporary variable.  */

static TCGv new_tmp(void)

{

    TCGv tmp;

    if (num_temps == MAX_TEMPS)

        abort();

    if (GET_TCGV(temps[num_temps]))

      return temps[num_temps++];

    tmp = tcg_temp_new(TCG_TYPE_I32);

    temps[num_temps++] = tmp;

    return tmp;

}

/* Release a temporary variable.  */

static void dead_tmp(TCGv tmp)

{

    int i;

    num_temps--;

    i = num_temps;

    if (GET_TCGV(temps[i]) == GET_TCGV(tmp))

        return;

    /* Shuffle this temp to the last slot.  */

    while (GET_TCGV(temps[i]) != GET_TCGV(tmp))

        i--;

    while (i < num_temps) {

        temps[i] = temps[i + 1];

        i++;

    }

    temps[i] = tmp;

}

/* Set a variable to the value of a CPU register.  */

static void load_reg_var(DisasContext *s, TCGv var, int reg)

{

    if (reg == 15) {

        uint32_t addr;

        /* normaly, since we updated PC, we need only to add one insn */

        if (s->thumb)

            addr = (long)s->pc + 2;

        else

            addr = (long)s->pc + 4;

        tcg_gen_movi_i32(var, addr);

    } else {

        tcg_gen_ld_i32(var, cpu_env, offsetof(CPUState, regs[reg]));

    }

}

/* Create a new temporary and set it to the value of a CPU register.  */

static inline TCGv load_reg(DisasContext *s, int reg)

{

    TCGv tmp = new_tmp();

    load_reg_var(s, tmp, reg);

    return tmp;

}

/* Set a CPU register.  The source must be a temporary and will be

   marked as dead.  */

static void store_reg(DisasContext *s, int reg, TCGv var)

{

    if (reg == 15) {

        tcg_gen_andi_i32(var, var, ~1);

        s->is_jmp = DISAS_JUMP;

    }

    tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, regs[reg]));

    dead_tmp(var);

}

/* Basic operations.  */

#define gen_op_movl_T0_T1() tcg_gen_mov_i32(cpu_T[0], cpu_T[1])

#define gen_op_movl_T0_T2() tcg_gen_mov_i32(cpu_T[0], cpu_T[2])

#define gen_op_movl_T1_T0() tcg_gen_mov_i32(cpu_T[1], cpu_T[0])

#define gen_op_movl_T1_T2() tcg_gen_mov_i32(cpu_T[1], cpu_T[2])

#define gen_op_movl_T2_T0() tcg_gen_mov_i32(cpu_T[2], cpu_T[0])

#define gen_op_movl_T0_im(im) tcg_gen_movi_i32(cpu_T[0], im)

#define gen_op_movl_T1_im(im) tcg_gen_movi_i32(cpu_T[1], im)

#define gen_op_movl_T2_im(im) tcg_gen_movi_i32(cpu_T[2], im)

#define gen_op_addl_T1_im(im) tcg_gen_addi_i32(cpu_T[1], cpu_T[1], im)

#define gen_op_addl_T0_T1() tcg_gen_add_i32(cpu_T[0], cpu_T[0], cpu_T[1])

#define gen_op_subl_T0_T1() tcg_gen_sub_i32(cpu_T[0], cpu_T[0], cpu_T[1])

#define gen_op_rsbl_T0_T1() tcg_gen_sub_i32(cpu_T[0], cpu_T[1], cpu_T[0])

#define gen_op_andl_T0_T1() tcg_gen_and_i32(cpu_T[0], cpu_T[0], cpu_T[1])

#define gen_op_xorl_T0_T1() tcg_gen_xor_i32(cpu_T[0], cpu_T[0], cpu_T[1])

#define gen_op_orl_T0_T1() tcg_gen_or_i32(cpu_T[0], cpu_T[0], cpu_T[1])

#define gen_op_notl_T0() tcg_gen_not_i32(cpu_T[0], cpu_T[0])

#define gen_op_notl_T1() tcg_gen_not_i32(cpu_T[1], cpu_T[1])

#define gen_op_logic_T0_cc() gen_logic_CC(cpu_T[0]);

#define gen_op_logic_T1_cc() gen_logic_CC(cpu_T[1]);

#define gen_op_shll_T0_im(im) tcg_gen_shli_i32(cpu_T[0], cpu_T[0], im)

#define gen_op_shll_T1_im(im) tcg_gen_shli_i32(cpu_T[1], cpu_T[1], im)

#define gen_op_shrl_T1_im(im) tcg_gen_shri_i32(cpu_T[1], cpu_T[1], im)

#define gen_op_sarl_T1_im(im) tcg_gen_sari_i32(cpu_T[1], cpu_T[1], im)

#define gen_op_rorl_T1_im(im) tcg_gen_rori_i32(cpu_T[1], cpu_T[1], im)

/* Value extensions.  */

#define gen_uxtb(var) tcg_gen_andi_i32(var, var, 0xff)

#define gen_uxth(var) tcg_gen_andi_i32(var, var, 0xffff)

#define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)

#define gen_sxth(var) tcg_gen_ext16s_i32(var, var)

#define gen_sxtb16(var) gen_helper_sxtb16(var, var)

#define gen_uxtb16(var) gen_helper_uxtb16(var, var)

#define gen_op_rev_T0() tcg_gen_bswap_i32(cpu_T[0], cpu_T[0])

#define gen_op_mul_T0_T1() tcg_gen_mul_i32(cpu_T[0], cpu_T[0], cpu_T[1])

#define gen_op_addl_T0_T1_setq() \

    gen_helper_add_setq(cpu_T[0], cpu_T[0], cpu_T[1])

#define gen_op_addl_T0_T1_saturate() \

    gen_helper_add_saturate(cpu_T[0], cpu_T[0], cpu_T[1])

#define gen_op_subl_T0_T1_saturate() \

    gen_helper_sub_saturate(cpu_T[0], cpu_T[0], cpu_T[1])

#define gen_op_addl_T0_T1_usaturate() \

    gen_helper_add_usaturate(cpu_T[0], cpu_T[0], cpu_T[1])

#define gen_op_subl_T0_T1_usaturate() \

    gen_helper_sub_usaturate(cpu_T[0], cpu_T[0], cpu_T[1])

/* Copy the most significant bit of T0 to all bits of T1.  */

#define gen_op_signbit_T1_T0() tcg_gen_sari_i32(cpu_T[1], cpu_T[0], 31)

static void gen_smul_dual(TCGv a, TCGv b)

{

    TCGv tmp1 = new_tmp();

    TCGv tmp2 = new_tmp();

    tcg_gen_ext8s_i32(tmp1, a);

    tcg_gen_ext8s_i32(tmp2, b);

    tcg_gen_mul_i32(tmp1, tmp1, tmp2);

    dead_tmp(tmp2);

    tcg_gen_sari_i32(a, a, 16);

    tcg_gen_sari_i32(b, b, 16);

    tcg_gen_mul_i32(b, b, a);

    tcg_gen_mov_i32(a, tmp1);

    dead_tmp(tmp1);

}

/* Byteswap each halfword.  */

static void gen_rev16(TCGv var)

{

    TCGv tmp = new_tmp();

    tcg_gen_shri_i32(tmp, var, 8);

    tcg_gen_andi_i32(tmp, tmp, 0x00ff00ff);

    tcg_gen_shli_i32(var, var, 8);

    tcg_gen_andi_i32(var, var, 0xff00ff00);

    tcg_gen_or_i32(var, var, tmp);

    dead_tmp(tmp);

}

/* Byteswap low halfword and sign extend.  */

static void gen_revsh(TCGv var)

{

    TCGv tmp = new_tmp();

    tcg_gen_shri_i32(tmp, var, 8);

    tcg_gen_andi_i32(tmp, tmp, 0x00ff);

    tcg_gen_shli_i32(var, var, 8);

    tcg_gen_ext8s_i32(var, var);

    tcg_gen_or_i32(var, var, tmp);

    dead_tmp(tmp);

}

/* Unsigned bitfield extract.  */

static void gen_ubfx(TCGv var, int shift, uint32_t mask)

{

    if (shift)

        tcg_gen_shri_i32(var, var, shift);

    tcg_gen_andi_i32(var, var, mask);

}

/* Signed bitfield extract.  */

static void gen_sbfx(TCGv var, int shift, int width)

{

    uint32_t signbit;

    if (shift)

        tcg_gen_sari_i32(var, var, shift);

    if (shift + width < 32) {

        signbit = 1u << (width - 1);

        tcg_gen_andi_i32(var, var, (1u << width) - 1);

        tcg_gen_xori_i32(var, var, signbit);

        tcg_gen_subi_i32(var, var, signbit);

    }

}

/* Bitfield insertion.  Insert val into base.  Clobbers base and val.  */

static void gen_bfi(TCGv dest, TCGv base, TCGv val, int shift, uint32_t mask)

{

    tcg_gen_shli_i32(val, val, shift);

    tcg_gen_andi_i32(val, val, mask);

    tcg_gen_andi_i32(base, base, ~mask);

    tcg_gen_or_i32(dest, base, val);

}

static void gen_op_roundqd_T0_T1(void)

{

    tcg_gen_shri_i32(cpu_T[0], cpu_T[0], 31);

    tcg_gen_add_i32(cpu_T[0], cpu_T[0], cpu_T[1]);

}

/* FIXME: Most targets have native widening multiplication.

   It would be good to use that instead of a full wide multiply.  */

/* Unsigned 32x32->64 multiply.  */

static void gen_op_mull_T0_T1(void)

{

    TCGv tmp1 = tcg_temp_new(TCG_TYPE_I64);

    TCGv tmp2 = tcg_temp_new(TCG_TYPE_I64);

    tcg_gen_extu_i32_i64(tmp1, cpu_T[0]);

    tcg_gen_extu_i32_i64(tmp2, cpu_T[1]);

    tcg_gen_mul_i64(tmp1, tmp1, tmp2);

    tcg_gen_trunc_i64_i32(cpu_T[0], tmp1);

    tcg_gen_shri_i64(tmp1, tmp1, 32);

    tcg_gen_trunc_i64_i32(cpu_T[1], tmp1);

}

/* Signed 32x32->64 multiply.  */

static void gen_op_imull_T0_T1(void)

{

    TCGv tmp1 = tcg_temp_new(TCG_TYPE_I64);

    TCGv tmp2 = tcg_temp_new(TCG_TYPE_I64);

    tcg_gen_ext_i32_i64(tmp1, cpu_T[0]);

    tcg_gen_ext_i32_i64(tmp2, cpu_T[1]);

    tcg_gen_mul_i64(tmp1, tmp1, tmp2);

    tcg_gen_trunc_i64_i32(cpu_T[0], tmp1);

    tcg_gen_shri_i64(tmp1, tmp1, 32);

    tcg_gen_trunc_i64_i32(cpu_T[1], tmp1);

}

/* Swap low and high halfwords.  */

static void gen_swap_half(TCGv var)

{

    TCGv tmp = new_tmp();

    tcg_gen_shri_i32(tmp, var, 16);

    tcg_gen_shli_i32(var, var, 16);

    tcg_gen_or_i32(var, var, tmp);

    dead_tmp(tmp);

}

/* Dual 16-bit add.  Result placed in t0 and t1 is marked as dead.

    tmp = (t0 ^ t1) & 0x8000;

    t0 &= ~0x8000;

    t1 &= ~0x8000;

    t0 = (t0 + t1) ^ tmp;

 */

static void gen_add16(TCGv t0, TCGv t1)

{

    TCGv tmp = new_tmp();

    tcg_gen_xor_i32(tmp, t0, t1);

    tcg_gen_andi_i32(tmp, tmp, 0x8000);

    tcg_gen_andi_i32(t0, t0, ~0x8000);

    tcg_gen_andi_i32(t1, t1, ~0x8000);

    tcg_gen_add_i32(t0, t0, t1);

    tcg_gen_xor_i32(t0, t0, tmp);

    dead_tmp(tmp);

    dead_tmp(t1);

}

#define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF))

/* Set CF to the top bit of var.  */

static void gen_set_CF_bit31(TCGv var)

{

    TCGv tmp = new_tmp();

    tcg_gen_shri_i32(tmp, var, 31);

    gen_set_CF(var);

    dead_tmp(tmp);

}

/* Set N and Z flags from var.  */

static inline void gen_logic_CC(TCGv var)

{

    tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, NZF));

}

/* T0 += T1 + CF.  */

static void gen_adc_T0_T1(void)

{

    TCGv tmp = new_tmp();

    gen_op_addl_T0_T1();

    tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUState, CF));

    tcg_gen_add_i32(cpu_T[0], cpu_T[0], tmp);

    dead_tmp(tmp);

}

/* dest = T0 - T1 + CF - 1.  */

static void gen_sub_carry(TCGv dest, TCGv t0, TCGv t1)

{

    TCGv tmp = new_tmp();

    tcg_gen_sub_i32(dest, t0, t1);

    tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUState, CF));

    tcg_gen_add_i32(dest, dest, tmp);

    tcg_gen_subi_i32(dest, dest, 1);

    dead_tmp(tmp);

}

#define gen_sbc_T0_T1() gen_sub_carry(cpu_T[0], cpu_T[0], cpu_T[1])

#define gen_rsc_T0_T1() gen_sub_carry(cpu_T[0], cpu_T[1], cpu_T[0])

/* FIXME:  Implement this natively.  */

static inline void tcg_gen_not_i32(TCGv t0, TCGv t1)

{

    tcg_gen_xori_i32(t0, t1, ~0);

}

/* T0 &= ~T1.  Clobbers T1.  */

/* FIXME: Implement bic natively.  */

static inline void gen_op_bicl_T0_T1(void)

{

    gen_op_notl_T1();

    gen_op_andl_T0_T1();

}

/* FIXME:  Implement this natively.  */

static void tcg_gen_rori_i32(TCGv t0, TCGv t1, int i)

{

    TCGv tmp;

    if (i == 0)

        return;

    tmp = new_tmp();

    tcg_gen_shri_i32(tmp, t1, i);

    tcg_gen_shli_i32(t1, t1, 32 - i);

    tcg_gen_or_i32(t0, t1, tmp);

    dead_tmp(tmp);

}

static void shifter_out_im(TCGv var, int shift)

{

    TCGv tmp = new_tmp();

    if (shift == 0) {

        tcg_gen_andi_i32(tmp, var, 1);

    } else {

        tcg_gen_shri_i32(tmp, var, shift);

        if (shift != 31);

            tcg_gen_andi_i32(tmp, tmp, 1);

    }

    gen_set_CF(tmp);

    dead_tmp(tmp);

}

/* Shift by immediate.  Includes special handling for shift == 0.  */

static inline void gen_arm_shift_im(TCGv var, int shiftop, int shift, int flags)

{

    switch (shiftop) {

    case 0: /* LSL */

        if (shift != 0) {

            if (flags)

                shifter_out_im(var, 32 - shift);

            tcg_gen_shli_i32(var, var, shift);

        }

        break;

    case 1: /* LSR */

        if (shift == 0) {

            if (flags) {

                tcg_gen_shri_i32(var, var, 31);

                gen_set_CF(var);

            }

            tcg_gen_movi_i32(var, 0);

        } else {

            if (flags)

                shifter_out_im(var, shift - 1);

            tcg_gen_shri_i32(var, var, shift);

        }

        break;

    case 2: /* ASR */

        if (shift == 0)

            shift = 32;

        if (flags)

            shifter_out_im(var, shift - 1);

        if (shift == 32)

          shift = 31;

        tcg_gen_sari_i32(var, var, shift);

        break;

    case 3: /* ROR/RRX */

        if (shift != 0) {

            if (flags)

                shifter_out_im(var, shift - 1);

            tcg_gen_rori_i32(var, var, shift); break;

        } else {

            TCGv tmp = new_tmp();

            tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUState, CF));

            if (flags)

                shifter_out_im(var, 0);

            tcg_gen_shri_i32(var, var, 1);

            tcg_gen_shli_i32(tmp, tmp, 31);

            tcg_gen_or_i32(var, var, tmp);

            dead_tmp(tmp);

        }

    }

};

#define PAS_OP(pfx) \

    switch (op2) {  \

    case 0: gen_pas_helper(glue(pfx,add16)); break; \

    case 1: gen_pas_helper(glue(pfx,addsubx)); break; \

    case 2: gen_pas_helper(glue(pfx,subaddx)); break; \

    case 3: gen_pas_helper(glue(pfx,sub16)); break; \

    case 4: gen_pas_helper(glue(pfx,add8)); break; \

    case 7: gen_pas_helper(glue(pfx,sub8)); break; \

    }

void gen_arm_parallel_addsub(int op1, int op2, TCGv a, TCGv b)

{

    TCGv tmp;

    switch (op1) {

#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)

    case 1:

        tmp = tcg_temp_new(TCG_TYPE_PTR);

        tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));

        PAS_OP(s)

        break;

    case 5:

        tmp = tcg_temp_new(TCG_TYPE_PTR);

        tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));

        PAS_OP(u)

        break;

#undef gen_pas_helper

#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)

    case 2:

        PAS_OP(q);

        break;

    case 3:

        PAS_OP(sh);

        break;

    case 6:

        PAS_OP(uq);

        break;

    case 7:

        PAS_OP(uh);

        break;

#undef gen_pas_helper

    }

}

#undef PAS_OP

/* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings.  */

#define PAS_OP(pfx) \

    switch (op2) {  \

    case 0: gen_pas_helper(glue(pfx,add8)); break; \

    case 1: gen_pas_helper(glue(pfx,add16)); break; \

    case 2: gen_pas_helper(glue(pfx,addsubx)); break; \

    case 4: gen_pas_helper(glue(pfx,sub8)); break; \

    case 5: gen_pas_helper(glue(pfx,sub16)); break; \

    case 6: gen_pas_helper(glue(pfx,subaddx)); break; \

    }

void gen_thumb2_parallel_addsub(int op1, int op2, TCGv a, TCGv b)

{

    TCGv tmp;

    switch (op1) {

#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)

    case 0:

        tmp = tcg_temp_new(TCG_TYPE_PTR);

        tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));

        PAS_OP(s)

        break;

    case 4:

        tmp = tcg_temp_new(TCG_TYPE_PTR);

        tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));

        PAS_OP(u)

        break;

#undef gen_pas_helper

#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)

    case 1:

        PAS_OP(q);

        break;

    case 2:

        PAS_OP(sh);

        break;

    case 5:

        PAS_OP(uq);

        break;

    case 6:

        PAS_OP(uh);

        break;

#undef gen_pas_helper

    }

}

#undef PAS_OP

static GenOpFunc1 *gen_test_cc[14] = {

    gen_op_test_eq,

    gen_op_test_ne,

    gen_op_test_cs,

    gen_op_test_cc,

    gen_op_test_mi,

    gen_op_test_pl,

    gen_op_test_vs,

    gen_op_test_vc,

    gen_op_test_hi,

    gen_op_test_ls,

    gen_op_test_ge,

    gen_op_test_lt,

    gen_op_test_gt,

    gen_op_test_le,

};

const uint8_t table_logic_cc[16] = {

    1, /* and */

    1, /* xor */

    0, /* sub */

    0, /* rsb */

    0, /* add */

    0, /* adc */

    0, /* sbc */

    0, /* rsc */

    1, /* andl */

    1, /* xorl */

    0, /* cmp */

    0, /* cmn */

    1, /* orr */

    1, /* mov */

    1, /* bic */

    1, /* mvn */

};

static GenOpFunc *gen_shift_T1_T0[4] = {

    gen_op_shll_T1_T0,

    gen_op_shrl_T1_T0,

    gen_op_sarl_T1_T0,

    gen_op_rorl_T1_T0,

};

static GenOpFunc *gen_shift_T1_T0_cc[4] = {

    gen_op_shll_T1_T0_cc,

    gen_op_shrl_T1_T0_cc,

    gen_op_sarl_T1_T0_cc,

    gen_op_rorl_T1_T0_cc,

};

/* Set PC and thumb state from T0.  Clobbers T0.  */

static inline void gen_bx(DisasContext *s)

{

    TCGv tmp;

    s->is_jmp = DISAS_UPDATE;

    tmp = new_tmp();

    tcg_gen_andi_i32(tmp, cpu_T[0], 1);

    tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, thumb));

    dead_tmp(tmp);

    tcg_gen_andi_i32(cpu_T[0], cpu_T[0], ~1);

    tcg_gen_st_i32(cpu_T[0], cpu_env, offsetof(CPUState, regs[15]));

}

#if defined(CONFIG_USER_ONLY)

#define gen_ldst(name, s) gen_op_##name##_raw()

#else

#define gen_ldst(name, s) do { \

    s->is_mem = 1; \

    if (IS_USER(s)) \

        gen_op_##name##_user(); \

    else \

        gen_op_##name##_kernel(); \

    } while (0)

#endif

static inline void gen_movl_T0_reg(DisasContext *s, int reg)

{

    load_reg_var(s, cpu_T[0], reg);

}

static inline void gen_movl_T1_reg(DisasContext *s, int reg)

{

    load_reg_var(s, cpu_T[1], reg);

}

static inline void gen_movl_T2_reg(DisasContext *s, int reg)

{

    load_reg_var(s, cpu_T[2], reg);

}

static inline void gen_set_pc_T0(void)

{

    tcg_gen_st_i32(cpu_T[0], cpu_env, offsetof(CPUState, regs[15]));

}

static inline void gen_movl_reg_TN(DisasContext *s, int reg, int t)

{

    TCGv tmp;

    if (reg == 15) {

        tmp = new_tmp();

        tcg_gen_andi_i32(tmp, cpu_T[t], ~1);

    } else {

        tmp = cpu_T[t];

    }

    tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, regs[reg]));

    if (reg == 15) {

        dead_tmp(tmp);

        s->is_jmp = DISAS_JUMP;

    }

}

static inline void gen_movl_reg_T0(DisasContext *s, int reg)

{

    gen_movl_reg_TN(s, reg, 0);

}

static inline void gen_movl_reg_T1(DisasContext *s, int reg)

{

    gen_movl_reg_TN(s, reg, 1);

}

/* Force a TB lookup after an instruction that changes the CPU state.  */

static inline void gen_lookup_tb(DisasContext *s)

{

    gen_op_movl_T0_im(s->pc);

    gen_movl_reg_T0(s, 15);

    s->is_jmp = DISAS_UPDATE;

}

static inline void gen_add_data_offset(DisasContext *s, unsigned int insn)

{

    int val, rm, shift, shiftop;

    TCGv offset;

    if (!(insn & (1 << 25))) {

        /* immediate */

        val = insn & 0xfff;

        if (!(insn & (1 << 23)))

            val = -val;

        if (val != 0)

            gen_op_addl_T1_im(val);

    } else {

        /* shift/register */

        rm = (insn) & 0xf;

        shift = (insn >> 7) & 0x1f;

        shiftop = (insn >> 5) & 3;

        offset = load_reg(s, rm);

        gen_arm_shift_im(offset, shiftop, shift, 0);

        if (!(insn & (1 << 23)))

            tcg_gen_sub_i32(cpu_T[1], cpu_T[1], offset);

        else

            tcg_gen_add_i32(cpu_T[1], cpu_T[1], offset);

        dead_tmp(offset);

    }

}

static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn,

                                        int extra)

{

    int val, rm;

    TCGv offset;

    if (insn & (1 << 22)) {

        /* immediate */

        val = (insn & 0xf) | ((insn >> 4) & 0xf0);

        if (!(insn & (1 << 23)))

            val = -val;

        val += extra;

        if (val != 0)

            gen_op_addl_T1_im(val);

    } else {

        /* register */

        if (extra)

            gen_op_addl_T1_im(extra);

        rm = (insn) & 0xf;

        offset = load_reg(s, rm);

        if (!(insn & (1 << 23)))

            tcg_gen_sub_i32(cpu_T[1], cpu_T[1], offset);

        else

            tcg_gen_add_i32(cpu_T[1], cpu_T[1], offset);

        dead_tmp(offset);

    }

}

#define VFP_OP(name)                      \

static inline void gen_vfp_##name(int dp) \

{                                         \

    if (dp)                               \

        gen_op_vfp_##name##d();           \

    else                                  \

        gen_op_vfp_##name##s();           \

}

#define VFP_OP1(name)                               \

static inline void gen_vfp_##name(int dp, int arg)  \

{                                                   \

    if (dp)                                         \

        gen_op_vfp_##name##d(arg);                  \

    else                                            \

        gen_op_vfp_##name##s(arg);                  \

}

VFP_OP(add)

VFP_OP(sub)

VFP_OP(mul)

VFP_OP(div)

VFP_OP(neg)

VFP_OP(abs)

VFP_OP(sqrt)

VFP_OP(cmp)

VFP_OP(cmpe)

VFP_OP(F1_ld0)

VFP_OP(uito)

VFP_OP(sito)

VFP_OP(toui)

VFP_OP(touiz)

VFP_OP(tosi)

VFP_OP(tosiz)

VFP_OP1(tosh)

VFP_OP1(tosl)

VFP_OP1(touh)

VFP_OP1(toul)

VFP_OP1(shto)

VFP_OP1(slto)

VFP_OP1(uhto)

VFP_OP1(ulto)

#undef VFP_OP

static inline void gen_vfp_fconst(int dp, uint32_t val)

{

    if (dp)

        gen_op_vfp_fconstd(val);

    else

        gen_op_vfp_fconsts(val);

}

static inline void gen_vfp_ld(DisasContext *s, int dp)

{

    if (dp)

        gen_ldst(vfp_ldd, s);

    else

        gen_ldst(vfp_lds, s);

}

static inline void gen_vfp_st(DisasContext *s, int dp)

{

    if (dp)

        gen_ldst(vfp_std, s);

    else

        gen_ldst(vfp_sts, s);

}

static inline long

vfp_reg_offset (int dp, int reg)

{

    if (dp)

        return offsetof(CPUARMState, vfp.regs[reg]);

    else if (reg & 1) {

        return offsetof(CPUARMState, vfp.regs[reg >> 1])

          + offsetof(CPU_DoubleU, l.upper);

    } else {

        return offsetof(CPUARMState, vfp.regs[reg >> 1])

          + offsetof(CPU_DoubleU, l.lower);

    }

}

/* Return the offset of a 32-bit piece of a NEON register.

   zero is the least significant end of the register.  */

static inline long

neon_reg_offset (int reg, int n)

{

    int sreg;

    sreg = reg * 2 + n;

    return vfp_reg_offset(0, sreg);

}

#define NEON_GET_REG(T, reg, n) gen_op_neon_getreg_##T(neon_reg_offset(reg, n))

#define NEON_SET_REG(T, reg, n) gen_op_neon_setreg_##T(neon_reg_offset(reg, n))

static inline void gen_mov_F0_vreg(int dp, int reg)

{

    if (dp)

        gen_op_vfp_getreg_F0d(vfp_reg_offset(dp, reg));

    else

        gen_op_vfp_getreg_F0s(vfp_reg_offset(dp, reg));

}

static inline void gen_mov_F1_vreg(int dp, int reg)

{

    if (dp)

        gen_op_vfp_getreg_F1d(vfp_reg_offset(dp, reg));

    else

        gen_op_vfp_getreg_F1s(vfp_reg_offset(dp, reg));

}

static inline void gen_mov_vreg_F0(int dp, int reg)

{