root / target-ppc / op_helper.c @ 6de673d4
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/*
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* PowerPC emulation helpers for QEMU.
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <string.h> |
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#include "cpu.h" |
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#include "dyngen-exec.h" |
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#include "host-utils.h" |
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#include "helper.h" |
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#include "helper_regs.h" |
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#if !defined(CONFIG_USER_ONLY)
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#include "softmmu_exec.h" |
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#endif /* !defined(CONFIG_USER_ONLY) */ |
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//#define DEBUG_OP
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/*****************************************************************************/
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/* SPR accesses */
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void helper_load_dump_spr(uint32_t sprn)
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{
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qemu_log("Read SPR %d %03x => " TARGET_FMT_lx "\n", sprn, sprn, |
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env->spr[sprn]); |
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} |
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void helper_store_dump_spr(uint32_t sprn)
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{
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qemu_log("Write SPR %d %03x <= " TARGET_FMT_lx "\n", sprn, sprn, |
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env->spr[sprn]); |
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} |
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#if !defined(CONFIG_USER_ONLY)
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#if defined(TARGET_PPC64)
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void helper_store_asr(target_ulong val)
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{
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ppc_store_asr(env, val); |
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} |
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#endif
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void helper_store_sdr1(target_ulong val)
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{
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ppc_store_sdr1(env, val); |
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} |
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void helper_store_hid0_601(target_ulong val)
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{
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target_ulong hid0; |
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hid0 = env->spr[SPR_HID0]; |
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if ((val ^ hid0) & 0x00000008) { |
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/* Change current endianness */
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env->hflags &= ~(1 << MSR_LE);
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env->hflags_nmsr &= ~(1 << MSR_LE);
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env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE); |
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env->hflags |= env->hflags_nmsr; |
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qemu_log("%s: set endianness to %c => " TARGET_FMT_lx "\n", __func__, |
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val & 0x8 ? 'l' : 'b', env->hflags); |
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} |
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env->spr[SPR_HID0] = (uint32_t)val; |
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} |
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void helper_store_403_pbr(uint32_t num, target_ulong value)
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{
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if (likely(env->pb[num] != value)) {
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env->pb[num] = value; |
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/* Should be optimized */
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tlb_flush(env, 1);
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} |
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} |
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void helper_store_40x_dbcr0(target_ulong val)
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{
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store_40x_dbcr0(env, val); |
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} |
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void helper_store_40x_sler(target_ulong val)
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{
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store_40x_sler(env, val); |
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} |
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#endif
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/*****************************************************************************/
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/* Memory load and stores */
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static inline target_ulong addr_add(target_ulong addr, target_long arg) |
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{
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#if defined(TARGET_PPC64)
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if (!msr_sf) {
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return (uint32_t)(addr + arg);
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} else
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#endif
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{
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return addr + arg;
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} |
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} |
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void helper_lmw(target_ulong addr, uint32_t reg)
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{
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for (; reg < 32; reg++) { |
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if (msr_le) {
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env->gpr[reg] = bswap32(ldl(addr)); |
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} else {
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env->gpr[reg] = ldl(addr); |
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} |
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addr = addr_add(addr, 4);
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} |
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} |
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void helper_stmw(target_ulong addr, uint32_t reg)
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{
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for (; reg < 32; reg++) { |
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if (msr_le) {
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stl(addr, bswap32((uint32_t)env->gpr[reg])); |
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} else {
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stl(addr, (uint32_t)env->gpr[reg]); |
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} |
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addr = addr_add(addr, 4);
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} |
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} |
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void helper_lsw(target_ulong addr, uint32_t nb, uint32_t reg)
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{
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int sh;
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for (; nb > 3; nb -= 4) { |
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env->gpr[reg] = ldl(addr); |
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reg = (reg + 1) % 32; |
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addr = addr_add(addr, 4);
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} |
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if (unlikely(nb > 0)) { |
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env->gpr[reg] = 0;
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for (sh = 24; nb > 0; nb--, sh -= 8) { |
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env->gpr[reg] |= ldub(addr) << sh; |
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addr = addr_add(addr, 1);
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} |
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} |
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} |
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/* PPC32 specification says we must generate an exception if
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* rA is in the range of registers to be loaded.
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* In an other hand, IBM says this is valid, but rA won't be loaded.
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* For now, I'll follow the spec...
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*/
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void helper_lswx(target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
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{
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if (likely(xer_bc != 0)) { |
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if (unlikely((ra != 0 && reg < ra && (reg + xer_bc) > ra) || |
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(reg < rb && (reg + xer_bc) > rb))) {
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helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM, |
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POWERPC_EXCP_INVAL | |
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POWERPC_EXCP_INVAL_LSWX); |
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} else {
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helper_lsw(addr, xer_bc, reg); |
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} |
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} |
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} |
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void helper_stsw(target_ulong addr, uint32_t nb, uint32_t reg)
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{
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int sh;
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for (; nb > 3; nb -= 4) { |
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stl(addr, env->gpr[reg]); |
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reg = (reg + 1) % 32; |
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addr = addr_add(addr, 4);
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} |
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if (unlikely(nb > 0)) { |
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for (sh = 24; nb > 0; nb--, sh -= 8) { |
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stb(addr, (env->gpr[reg] >> sh) & 0xFF);
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addr = addr_add(addr, 1);
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} |
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} |
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} |
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static void do_dcbz(target_ulong addr, int dcache_line_size) |
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{
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int i;
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addr &= ~(dcache_line_size - 1);
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for (i = 0; i < dcache_line_size; i += 4) { |
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stl(addr + i, 0);
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} |
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if (env->reserve_addr == addr) {
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env->reserve_addr = (target_ulong)-1ULL;
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} |
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} |
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void helper_dcbz(target_ulong addr)
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{
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do_dcbz(addr, env->dcache_line_size); |
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} |
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void helper_dcbz_970(target_ulong addr)
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{
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if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1) { |
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do_dcbz(addr, 32);
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} else {
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do_dcbz(addr, env->dcache_line_size); |
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} |
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} |
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void helper_icbi(target_ulong addr)
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{
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addr &= ~(env->dcache_line_size - 1);
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/* Invalidate one cache line :
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* PowerPC specification says this is to be treated like a load
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* (not a fetch) by the MMU. To be sure it will be so,
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* do the load "by hand".
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*/
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ldl(addr); |
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} |
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/* XXX: to be tested */
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target_ulong helper_lscbx(target_ulong addr, uint32_t reg, uint32_t ra, |
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uint32_t rb) |
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{
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int i, c, d;
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d = 24;
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for (i = 0; i < xer_bc; i++) { |
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c = ldub(addr); |
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addr = addr_add(addr, 1);
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/* ra (if not 0) and rb are never modified */
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if (likely(reg != rb && (ra == 0 || reg != ra))) { |
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env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d);
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} |
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if (unlikely(c == xer_cmp)) {
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break;
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} |
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if (likely(d != 0)) { |
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d -= 8;
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} else {
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d = 24;
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reg++; |
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reg = reg & 0x1F;
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} |
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} |
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return i;
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} |
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/*****************************************************************************/
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/* PowerPC 601 specific instructions (POWER bridge) */
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target_ulong helper_clcs(uint32_t arg) |
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{
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switch (arg) {
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case 0x0CUL: |
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/* Instruction cache line size */
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return env->icache_line_size;
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break;
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case 0x0DUL: |
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/* Data cache line size */
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return env->dcache_line_size;
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break;
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case 0x0EUL: |
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/* Minimum cache line size */
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return (env->icache_line_size < env->dcache_line_size) ?
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env->icache_line_size : env->dcache_line_size; |
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break;
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case 0x0FUL: |
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/* Maximum cache line size */
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return (env->icache_line_size > env->dcache_line_size) ?
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env->icache_line_size : env->dcache_line_size; |
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break;
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default:
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/* Undefined */
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return 0; |
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break;
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} |
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} |
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/*****************************************************************************/
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/* Altivec extension helpers */
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#if defined(HOST_WORDS_BIGENDIAN)
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#define HI_IDX 0 |
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#define LO_IDX 1 |
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#else
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#define HI_IDX 1 |
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#define LO_IDX 0 |
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#endif
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#define LVE(name, access, swap, element) \
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void helper_##name(ppc_avr_t *r, target_ulong addr) \ |
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{ \
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size_t n_elems = ARRAY_SIZE(r->element); \ |
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int adjust = HI_IDX*(n_elems - 1); \ |
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int sh = sizeof(r->element[0]) >> 1; \ |
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int index = (addr & 0xf) >> sh; \ |
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\ |
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if (msr_le) { \
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r->element[LO_IDX ? index : (adjust - index)] = \ |
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swap(access(addr)); \ |
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} else { \
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r->element[LO_IDX ? index : (adjust - index)] = \ |
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access(addr); \ |
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} \ |
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} |
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#define I(x) (x)
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LVE(lvebx, ldub, I, u8) |
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LVE(lvehx, lduw, bswap16, u16) |
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LVE(lvewx, ldl, bswap32, u32) |
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#undef I
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#undef LVE
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#define STVE(name, access, swap, element) \
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void helper_##name(ppc_avr_t *r, target_ulong addr) \ |
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{ \
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size_t n_elems = ARRAY_SIZE(r->element); \ |
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int adjust = HI_IDX * (n_elems - 1); \ |
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int sh = sizeof(r->element[0]) >> 1; \ |
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int index = (addr & 0xf) >> sh; \ |
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\ |
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if (msr_le) { \
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access(addr, swap(r->element[LO_IDX ? index : (adjust - index)])); \ |
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} else { \
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access(addr, r->element[LO_IDX ? index : (adjust - index)]); \ |
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} \ |
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} |
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#define I(x) (x)
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STVE(stvebx, stb, I, u8) |
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STVE(stvehx, stw, bswap16, u16) |
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STVE(stvewx, stl, bswap32, u32) |
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#undef I
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#undef LVE
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#undef HI_IDX
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#undef LO_IDX
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/*****************************************************************************/
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/* Softmmu support */
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#if !defined(CONFIG_USER_ONLY)
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#define MMUSUFFIX _mmu
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#define SHIFT 0 |
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#include "softmmu_template.h" |
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#define SHIFT 1 |
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#include "softmmu_template.h" |
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#define SHIFT 2 |
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#include "softmmu_template.h" |
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#define SHIFT 3 |
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#include "softmmu_template.h" |
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/* try to fill the TLB and return an exception if error. If retaddr is
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NULL, it means that the function was called in C code (i.e. not
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from generated code or from helper.c) */
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/* XXX: fix it to restore all registers */
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void tlb_fill(CPUPPCState *env1, target_ulong addr, int is_write, int mmu_idx, |
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uintptr_t retaddr) |
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{
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TranslationBlock *tb; |
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CPUPPCState *saved_env; |
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int ret;
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saved_env = env; |
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env = env1; |
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ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx); |
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if (unlikely(ret != 0)) { |
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if (likely(retaddr)) {
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/* now we have a real cpu fault */
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tb = tb_find_pc(retaddr); |
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if (likely(tb)) {
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/* the PC is inside the translated code. It means that we have
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a virtual CPU fault */
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cpu_restore_state(tb, env, retaddr); |
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} |
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} |
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helper_raise_exception_err(env, env->exception_index, env->error_code); |
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} |
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env = saved_env; |
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} |
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#endif /* !CONFIG_USER_ONLY */ |