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/*
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 * QEMU Floppy disk emulator (Intel 82078)
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 *
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 * Copyright (c) 2003, 2007 Jocelyn Mayer
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 * Copyright (c) 2008 Herv? Poussineau
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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/*
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 * The controller is used in Sun4m systems in a slightly different
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 * way. There are changes in DOR register and DMA is not available.
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 */
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#include "hw.h"
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#include "fdc.h"
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#include "qemu-error.h"
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#include "qemu-timer.h"
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#include "isa.h"
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#include "sysbus.h"
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#include "qdev-addr.h"
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#include "blockdev.h"
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#include "sysemu.h"
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#include "block_int.h"
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/********************************************************/
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/* debug Floppy devices */
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//#define DEBUG_FLOPPY
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#ifdef DEBUG_FLOPPY
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#define FLOPPY_DPRINTF(fmt, ...)                                \
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    do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define FLOPPY_DPRINTF(fmt, ...)
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#endif
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#define FLOPPY_ERROR(fmt, ...)                                          \
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    do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
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/********************************************************/
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/* Floppy drive emulation                               */
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#define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
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#define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
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/* Will always be a fixed parameter for us */
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#define FD_SECTOR_LEN          512
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#define FD_SECTOR_SC           2   /* Sector size code */
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#define FD_RESET_SENSEI_COUNT  4   /* Number of sense interrupts on RESET */
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/* Floppy disk drive emulation */
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typedef enum FDiskFlags {
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    FDISK_DBL_SIDES  = 0x01,
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} FDiskFlags;
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typedef struct FDrive {
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    BlockDriverState *bs;
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    /* Drive status */
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    FDriveType drive;
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    uint8_t perpendicular;    /* 2.88 MB access mode    */
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    /* Position */
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    uint8_t head;
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    uint8_t track;
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    uint8_t sect;
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    /* Media */
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    FDiskFlags flags;
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    uint8_t last_sect;        /* Nb sector per track    */
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    uint8_t max_track;        /* Nb of tracks           */
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    uint16_t bps;             /* Bytes per sector       */
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    uint8_t ro;               /* Is read-only           */
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    uint8_t media_changed;    /* Is media changed       */
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} FDrive;
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static void fd_init(FDrive *drv)
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{
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    /* Drive */
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    drv->drive = FDRIVE_DRV_NONE;
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    drv->perpendicular = 0;
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    /* Disk */
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    drv->last_sect = 0;
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    drv->max_track = 0;
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}
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static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
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                          uint8_t last_sect)
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{
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    return (((track * 2) + head) * last_sect) + sect - 1;
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}
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/* Returns current position, in sectors, for given drive */
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static int fd_sector(FDrive *drv)
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{
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    return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect);
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}
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/* Seek to a new position:
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 * returns 0 if already on right track
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 * returns 1 if track changed
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 * returns 2 if track is invalid
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 * returns 3 if sector is invalid
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 * returns 4 if seek is disabled
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 */
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static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
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                   int enable_seek)
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{
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    uint32_t sector;
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    int ret;
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    if (track > drv->max_track ||
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        (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
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        FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
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                       head, track, sect, 1,
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                       (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
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                       drv->max_track, drv->last_sect);
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        return 2;
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    }
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    if (sect > drv->last_sect) {
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        FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
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                       head, track, sect, 1,
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                       (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
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                       drv->max_track, drv->last_sect);
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        return 3;
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    }
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    sector = fd_sector_calc(head, track, sect, drv->last_sect);
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    ret = 0;
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    if (sector != fd_sector(drv)) {
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#if 0
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        if (!enable_seek) {
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            FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n",
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                         head, track, sect, 1, drv->max_track, drv->last_sect);
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            return 4;
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        }
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#endif
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        drv->head = head;
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        if (drv->track != track)
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            ret = 1;
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        drv->track = track;
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        drv->sect = sect;
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    }
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    return ret;
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}
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/* Set drive back to track 0 */
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static void fd_recalibrate(FDrive *drv)
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{
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    FLOPPY_DPRINTF("recalibrate\n");
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    drv->head = 0;
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    drv->track = 0;
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    drv->sect = 1;
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}
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/* Revalidate a disk drive after a disk change */
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static void fd_revalidate(FDrive *drv)
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{
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    int nb_heads, max_track, last_sect, ro;
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    FDriveType drive;
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    FLOPPY_DPRINTF("revalidate\n");
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    if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) {
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        ro = bdrv_is_read_only(drv->bs);
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        bdrv_get_floppy_geometry_hint(drv->bs, &nb_heads, &max_track,
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                                      &last_sect, drv->drive, &drive);
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        if (nb_heads != 0 && max_track != 0 && last_sect != 0) {
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            FLOPPY_DPRINTF("User defined disk (%d %d %d)",
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                           nb_heads - 1, max_track, last_sect);
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        } else {
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            FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n", nb_heads,
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                           max_track, last_sect, ro ? "ro" : "rw");
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        }
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        if (nb_heads == 1) {
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            drv->flags &= ~FDISK_DBL_SIDES;
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        } else {
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            drv->flags |= FDISK_DBL_SIDES;
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        }
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        drv->max_track = max_track;
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        drv->last_sect = last_sect;
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        drv->ro = ro;
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        drv->drive = drive;
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    } else {
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        FLOPPY_DPRINTF("No disk in drive\n");
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        drv->last_sect = 0;
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        drv->max_track = 0;
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        drv->flags &= ~FDISK_DBL_SIDES;
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    }
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}
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/********************************************************/
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/* Intel 82078 floppy disk controller emulation          */
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typedef struct FDCtrl FDCtrl;
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static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
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static void fdctrl_reset_fifo(FDCtrl *fdctrl);
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static int fdctrl_transfer_handler (void *opaque, int nchan,
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                                    int dma_pos, int dma_len);
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static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0);
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static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
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static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
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static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
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static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
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static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
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static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
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static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
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static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
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static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
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static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
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static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
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enum {
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    FD_DIR_WRITE   = 0,
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    FD_DIR_READ    = 1,
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    FD_DIR_SCANE   = 2,
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    FD_DIR_SCANL   = 3,
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    FD_DIR_SCANH   = 4,
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};
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enum {
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    FD_STATE_MULTI  = 0x01,        /* multi track flag */
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    FD_STATE_FORMAT = 0x02,        /* format flag */
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    FD_STATE_SEEK   = 0x04,        /* seek flag */
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};
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enum {
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    FD_REG_SRA = 0x00,
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    FD_REG_SRB = 0x01,
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    FD_REG_DOR = 0x02,
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    FD_REG_TDR = 0x03,
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    FD_REG_MSR = 0x04,
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    FD_REG_DSR = 0x04,
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    FD_REG_FIFO = 0x05,
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    FD_REG_DIR = 0x07,
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};
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enum {
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    FD_CMD_READ_TRACK = 0x02,
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    FD_CMD_SPECIFY = 0x03,
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    FD_CMD_SENSE_DRIVE_STATUS = 0x04,
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    FD_CMD_WRITE = 0x05,
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    FD_CMD_READ = 0x06,
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    FD_CMD_RECALIBRATE = 0x07,
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    FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
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    FD_CMD_WRITE_DELETED = 0x09,
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    FD_CMD_READ_ID = 0x0a,
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    FD_CMD_READ_DELETED = 0x0c,
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    FD_CMD_FORMAT_TRACK = 0x0d,
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    FD_CMD_DUMPREG = 0x0e,
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    FD_CMD_SEEK = 0x0f,
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    FD_CMD_VERSION = 0x10,
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    FD_CMD_SCAN_EQUAL = 0x11,
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    FD_CMD_PERPENDICULAR_MODE = 0x12,
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    FD_CMD_CONFIGURE = 0x13,
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    FD_CMD_LOCK = 0x14,
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    FD_CMD_VERIFY = 0x16,
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    FD_CMD_POWERDOWN_MODE = 0x17,
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    FD_CMD_PART_ID = 0x18,
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    FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
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    FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
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    FD_CMD_SAVE = 0x2e,
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    FD_CMD_OPTION = 0x33,
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    FD_CMD_RESTORE = 0x4e,
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    FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
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    FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
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    FD_CMD_FORMAT_AND_WRITE = 0xcd,
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    FD_CMD_RELATIVE_SEEK_IN = 0xcf,
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};
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enum {
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    FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
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    FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
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    FD_CONFIG_POLL  = 0x10, /* Poll enabled */
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    FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
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    FD_CONFIG_EIS   = 0x40, /* No implied seeks */
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};
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enum {
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    FD_SR0_EQPMT    = 0x10,
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    FD_SR0_SEEK     = 0x20,
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    FD_SR0_ABNTERM  = 0x40,
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    FD_SR0_INVCMD   = 0x80,
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    FD_SR0_RDYCHG   = 0xc0,
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};
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enum {
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    FD_SR1_EC       = 0x80, /* End of cylinder */
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};
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enum {
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    FD_SR2_SNS      = 0x04, /* Scan not satisfied */
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    FD_SR2_SEH      = 0x08, /* Scan equal hit */
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};
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enum {
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    FD_SRA_DIR      = 0x01,
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    FD_SRA_nWP      = 0x02,
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    FD_SRA_nINDX    = 0x04,
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    FD_SRA_HDSEL    = 0x08,
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    FD_SRA_nTRK0    = 0x10,
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    FD_SRA_STEP     = 0x20,
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    FD_SRA_nDRV2    = 0x40,
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    FD_SRA_INTPEND  = 0x80,
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};
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enum {
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    FD_SRB_MTR0     = 0x01,
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    FD_SRB_MTR1     = 0x02,
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    FD_SRB_WGATE    = 0x04,
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    FD_SRB_RDATA    = 0x08,
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    FD_SRB_WDATA    = 0x10,
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    FD_SRB_DR0      = 0x20,
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};
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enum {
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#if MAX_FD == 4
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    FD_DOR_SELMASK  = 0x03,
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#else
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    FD_DOR_SELMASK  = 0x01,
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#endif
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    FD_DOR_nRESET   = 0x04,
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    FD_DOR_DMAEN    = 0x08,
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    FD_DOR_MOTEN0   = 0x10,
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    FD_DOR_MOTEN1   = 0x20,
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    FD_DOR_MOTEN2   = 0x40,
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    FD_DOR_MOTEN3   = 0x80,
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};
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enum {
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#if MAX_FD == 4
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    FD_TDR_BOOTSEL  = 0x0c,
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#else
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    FD_TDR_BOOTSEL  = 0x04,
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#endif
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};
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351 9fea808a blueswir1
enum {
352 9fea808a blueswir1
    FD_DSR_DRATEMASK= 0x03,
353 9fea808a blueswir1
    FD_DSR_PWRDOWN  = 0x40,
354 9fea808a blueswir1
    FD_DSR_SWRESET  = 0x80,
355 9fea808a blueswir1
};
356 9fea808a blueswir1
357 9fea808a blueswir1
enum {
358 9fea808a blueswir1
    FD_MSR_DRV0BUSY = 0x01,
359 9fea808a blueswir1
    FD_MSR_DRV1BUSY = 0x02,
360 9fea808a blueswir1
    FD_MSR_DRV2BUSY = 0x04,
361 9fea808a blueswir1
    FD_MSR_DRV3BUSY = 0x08,
362 9fea808a blueswir1
    FD_MSR_CMDBUSY  = 0x10,
363 9fea808a blueswir1
    FD_MSR_NONDMA   = 0x20,
364 9fea808a blueswir1
    FD_MSR_DIO      = 0x40,
365 9fea808a blueswir1
    FD_MSR_RQM      = 0x80,
366 9fea808a blueswir1
};
367 9fea808a blueswir1
368 9fea808a blueswir1
enum {
369 9fea808a blueswir1
    FD_DIR_DSKCHG   = 0x80,
370 9fea808a blueswir1
};
371 9fea808a blueswir1
372 8977f3c1 bellard
#define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
373 8977f3c1 bellard
#define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
374 baca51fa bellard
#define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
375 8977f3c1 bellard
376 5c02c033 Blue Swirl
struct FDCtrl {
377 4b19ec0c bellard
    /* Controller's identification */
378 8977f3c1 bellard
    uint8_t version;
379 8977f3c1 bellard
    /* HW */
380 d537cf6c pbrook
    qemu_irq irq;
381 8977f3c1 bellard
    int dma_chann;
382 4b19ec0c bellard
    /* Controller state */
383 ed5fd2cc bellard
    QEMUTimer *result_timer;
384 8c6a4d77 blueswir1
    uint8_t sra;
385 8c6a4d77 blueswir1
    uint8_t srb;
386 368df94d blueswir1
    uint8_t dor;
387 d7a6c270 Juan Quintela
    uint8_t dor_vmstate; /* only used as temp during vmstate */
388 46d3233b blueswir1
    uint8_t tdr;
389 b9b3d225 blueswir1
    uint8_t dsr;
390 368df94d blueswir1
    uint8_t msr;
391 8977f3c1 bellard
    uint8_t cur_drv;
392 77370520 blueswir1
    uint8_t status0;
393 77370520 blueswir1
    uint8_t status1;
394 77370520 blueswir1
    uint8_t status2;
395 8977f3c1 bellard
    /* Command FIFO */
396 33f00271 balrog
    uint8_t *fifo;
397 d7a6c270 Juan Quintela
    int32_t fifo_size;
398 8977f3c1 bellard
    uint32_t data_pos;
399 8977f3c1 bellard
    uint32_t data_len;
400 8977f3c1 bellard
    uint8_t data_state;
401 8977f3c1 bellard
    uint8_t data_dir;
402 890fa6be bellard
    uint8_t eot; /* last wanted sector */
403 8977f3c1 bellard
    /* States kept only to be returned back */
404 8977f3c1 bellard
    /* Timers state */
405 8977f3c1 bellard
    uint8_t timer0;
406 8977f3c1 bellard
    uint8_t timer1;
407 8977f3c1 bellard
    /* precompensation */
408 8977f3c1 bellard
    uint8_t precomp_trk;
409 8977f3c1 bellard
    uint8_t config;
410 8977f3c1 bellard
    uint8_t lock;
411 8977f3c1 bellard
    /* Power down config (also with status regB access mode */
412 8977f3c1 bellard
    uint8_t pwrd;
413 741402f9 blueswir1
    /* Sun4m quirks? */
414 a06e5a3c blueswir1
    int sun4m;
415 8977f3c1 bellard
    /* Floppy drives */
416 d7a6c270 Juan Quintela
    uint8_t num_floppies;
417 5c02c033 Blue Swirl
    FDrive drives[MAX_FD];
418 f2d81b33 blueswir1
    int reset_sensei;
419 baca51fa bellard
};
420 baca51fa bellard
421 5c02c033 Blue Swirl
typedef struct FDCtrlSysBus {
422 8baf73ad Gerd Hoffmann
    SysBusDevice busdev;
423 5c02c033 Blue Swirl
    struct FDCtrl state;
424 5c02c033 Blue Swirl
} FDCtrlSysBus;
425 8baf73ad Gerd Hoffmann
426 5c02c033 Blue Swirl
typedef struct FDCtrlISABus {
427 8baf73ad Gerd Hoffmann
    ISADevice busdev;
428 5c02c033 Blue Swirl
    struct FDCtrl state;
429 1ca4d09a Gleb Natapov
    int32_t bootindexA;
430 1ca4d09a Gleb Natapov
    int32_t bootindexB;
431 5c02c033 Blue Swirl
} FDCtrlISABus;
432 8baf73ad Gerd Hoffmann
433 baca51fa bellard
static uint32_t fdctrl_read (void *opaque, uint32_t reg)
434 baca51fa bellard
{
435 5c02c033 Blue Swirl
    FDCtrl *fdctrl = opaque;
436 baca51fa bellard
    uint32_t retval;
437 baca51fa bellard
438 e64d7d59 blueswir1
    switch (reg) {
439 8c6a4d77 blueswir1
    case FD_REG_SRA:
440 8c6a4d77 blueswir1
        retval = fdctrl_read_statusA(fdctrl);
441 4f431960 j_mayer
        break;
442 8c6a4d77 blueswir1
    case FD_REG_SRB:
443 4f431960 j_mayer
        retval = fdctrl_read_statusB(fdctrl);
444 4f431960 j_mayer
        break;
445 9fea808a blueswir1
    case FD_REG_DOR:
446 4f431960 j_mayer
        retval = fdctrl_read_dor(fdctrl);
447 4f431960 j_mayer
        break;
448 9fea808a blueswir1
    case FD_REG_TDR:
449 baca51fa bellard
        retval = fdctrl_read_tape(fdctrl);
450 4f431960 j_mayer
        break;
451 9fea808a blueswir1
    case FD_REG_MSR:
452 baca51fa bellard
        retval = fdctrl_read_main_status(fdctrl);
453 4f431960 j_mayer
        break;
454 9fea808a blueswir1
    case FD_REG_FIFO:
455 baca51fa bellard
        retval = fdctrl_read_data(fdctrl);
456 4f431960 j_mayer
        break;
457 9fea808a blueswir1
    case FD_REG_DIR:
458 baca51fa bellard
        retval = fdctrl_read_dir(fdctrl);
459 4f431960 j_mayer
        break;
460 a541f297 bellard
    default:
461 4f431960 j_mayer
        retval = (uint32_t)(-1);
462 4f431960 j_mayer
        break;
463 a541f297 bellard
    }
464 ed5fd2cc bellard
    FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
465 baca51fa bellard
466 baca51fa bellard
    return retval;
467 baca51fa bellard
}
468 baca51fa bellard
469 baca51fa bellard
static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
470 baca51fa bellard
{
471 5c02c033 Blue Swirl
    FDCtrl *fdctrl = opaque;
472 baca51fa bellard
473 ed5fd2cc bellard
    FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
474 ed5fd2cc bellard
475 e64d7d59 blueswir1
    switch (reg) {
476 9fea808a blueswir1
    case FD_REG_DOR:
477 4f431960 j_mayer
        fdctrl_write_dor(fdctrl, value);
478 4f431960 j_mayer
        break;
479 9fea808a blueswir1
    case FD_REG_TDR:
480 baca51fa bellard
        fdctrl_write_tape(fdctrl, value);
481 4f431960 j_mayer
        break;
482 9fea808a blueswir1
    case FD_REG_DSR:
483 baca51fa bellard
        fdctrl_write_rate(fdctrl, value);
484 4f431960 j_mayer
        break;
485 9fea808a blueswir1
    case FD_REG_FIFO:
486 baca51fa bellard
        fdctrl_write_data(fdctrl, value);
487 4f431960 j_mayer
        break;
488 a541f297 bellard
    default:
489 4f431960 j_mayer
        break;
490 a541f297 bellard
    }
491 baca51fa bellard
}
492 baca51fa bellard
493 e64d7d59 blueswir1
static uint32_t fdctrl_read_port (void *opaque, uint32_t reg)
494 e64d7d59 blueswir1
{
495 e64d7d59 blueswir1
    return fdctrl_read(opaque, reg & 7);
496 e64d7d59 blueswir1
}
497 e64d7d59 blueswir1
498 e64d7d59 blueswir1
static void fdctrl_write_port (void *opaque, uint32_t reg, uint32_t value)
499 e64d7d59 blueswir1
{
500 e64d7d59 blueswir1
    fdctrl_write(opaque, reg & 7, value);
501 e64d7d59 blueswir1
}
502 e64d7d59 blueswir1
503 c227f099 Anthony Liguori
static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
504 62a46c61 bellard
{
505 5dcb6b91 blueswir1
    return fdctrl_read(opaque, (uint32_t)reg);
506 62a46c61 bellard
}
507 62a46c61 bellard
508 5fafdf24 ths
static void fdctrl_write_mem (void *opaque,
509 c227f099 Anthony Liguori
                              target_phys_addr_t reg, uint32_t value)
510 62a46c61 bellard
{
511 5dcb6b91 blueswir1
    fdctrl_write(opaque, (uint32_t)reg, value);
512 62a46c61 bellard
}
513 62a46c61 bellard
514 d60efc6b Blue Swirl
static CPUReadMemoryFunc * const fdctrl_mem_read[3] = {
515 62a46c61 bellard
    fdctrl_read_mem,
516 62a46c61 bellard
    fdctrl_read_mem,
517 62a46c61 bellard
    fdctrl_read_mem,
518 e80cfcfc bellard
};
519 e80cfcfc bellard
520 d60efc6b Blue Swirl
static CPUWriteMemoryFunc * const fdctrl_mem_write[3] = {
521 62a46c61 bellard
    fdctrl_write_mem,
522 62a46c61 bellard
    fdctrl_write_mem,
523 62a46c61 bellard
    fdctrl_write_mem,
524 e80cfcfc bellard
};
525 e80cfcfc bellard
526 d60efc6b Blue Swirl
static CPUReadMemoryFunc * const fdctrl_mem_read_strict[3] = {
527 7c560456 blueswir1
    fdctrl_read_mem,
528 7c560456 blueswir1
    NULL,
529 7c560456 blueswir1
    NULL,
530 7c560456 blueswir1
};
531 7c560456 blueswir1
532 d60efc6b Blue Swirl
static CPUWriteMemoryFunc * const fdctrl_mem_write_strict[3] = {
533 7c560456 blueswir1
    fdctrl_write_mem,
534 7c560456 blueswir1
    NULL,
535 7c560456 blueswir1
    NULL,
536 7c560456 blueswir1
};
537 7c560456 blueswir1
538 7d905f71 Jason Wang
static void fdrive_media_changed_pre_save(void *opaque)
539 7d905f71 Jason Wang
{
540 7d905f71 Jason Wang
    FDrive *drive = opaque;
541 7d905f71 Jason Wang
542 7d905f71 Jason Wang
    drive->media_changed = drive->bs->media_changed;
543 7d905f71 Jason Wang
}
544 7d905f71 Jason Wang
545 7d905f71 Jason Wang
static int fdrive_media_changed_post_load(void *opaque, int version_id)
546 7d905f71 Jason Wang
{
547 7d905f71 Jason Wang
    FDrive *drive = opaque;
548 7d905f71 Jason Wang
549 7d905f71 Jason Wang
    if (drive->bs != NULL) {
550 7d905f71 Jason Wang
        drive->bs->media_changed = drive->media_changed;
551 7d905f71 Jason Wang
    }
552 7d905f71 Jason Wang
553 7d905f71 Jason Wang
    /* User ejected the floppy when drive->bs == NULL */
554 7d905f71 Jason Wang
    return 0;
555 7d905f71 Jason Wang
}
556 7d905f71 Jason Wang
557 7d905f71 Jason Wang
static bool fdrive_media_changed_needed(void *opaque)
558 7d905f71 Jason Wang
{
559 7d905f71 Jason Wang
    FDrive *drive = opaque;
560 7d905f71 Jason Wang
561 7d905f71 Jason Wang
    return (drive->bs != NULL && drive->bs->media_changed != 1);
562 7d905f71 Jason Wang
}
563 7d905f71 Jason Wang
564 7d905f71 Jason Wang
static const VMStateDescription vmstate_fdrive_media_changed = {
565 7d905f71 Jason Wang
    .name = "fdrive/media_changed",
566 7d905f71 Jason Wang
    .version_id = 1,
567 7d905f71 Jason Wang
    .minimum_version_id = 1,
568 7d905f71 Jason Wang
    .minimum_version_id_old = 1,
569 7d905f71 Jason Wang
    .pre_save = fdrive_media_changed_pre_save,
570 7d905f71 Jason Wang
    .post_load = fdrive_media_changed_post_load,
571 7d905f71 Jason Wang
    .fields      = (VMStateField[]) {
572 7d905f71 Jason Wang
        VMSTATE_UINT8(media_changed, FDrive),
573 7d905f71 Jason Wang
        VMSTATE_END_OF_LIST()
574 7d905f71 Jason Wang
    }
575 7d905f71 Jason Wang
};
576 7d905f71 Jason Wang
577 d7a6c270 Juan Quintela
static const VMStateDescription vmstate_fdrive = {
578 d7a6c270 Juan Quintela
    .name = "fdrive",
579 d7a6c270 Juan Quintela
    .version_id = 1,
580 d7a6c270 Juan Quintela
    .minimum_version_id = 1,
581 d7a6c270 Juan Quintela
    .minimum_version_id_old = 1,
582 7d905f71 Jason Wang
    .fields      = (VMStateField[]) {
583 5c02c033 Blue Swirl
        VMSTATE_UINT8(head, FDrive),
584 5c02c033 Blue Swirl
        VMSTATE_UINT8(track, FDrive),
585 5c02c033 Blue Swirl
        VMSTATE_UINT8(sect, FDrive),
586 d7a6c270 Juan Quintela
        VMSTATE_END_OF_LIST()
587 7d905f71 Jason Wang
    },
588 7d905f71 Jason Wang
    .subsections = (VMStateSubsection[]) {
589 7d905f71 Jason Wang
        {
590 7d905f71 Jason Wang
            .vmsd = &vmstate_fdrive_media_changed,
591 7d905f71 Jason Wang
            .needed = &fdrive_media_changed_needed,
592 7d905f71 Jason Wang
        } , {
593 7d905f71 Jason Wang
            /* empty */
594 7d905f71 Jason Wang
        }
595 d7a6c270 Juan Quintela
    }
596 d7a6c270 Juan Quintela
};
597 3ccacc4a blueswir1
598 d4bfa4d7 Juan Quintela
static void fdc_pre_save(void *opaque)
599 3ccacc4a blueswir1
{
600 5c02c033 Blue Swirl
    FDCtrl *s = opaque;
601 3ccacc4a blueswir1
602 d7a6c270 Juan Quintela
    s->dor_vmstate = s->dor | GET_CUR_DRV(s);
603 3ccacc4a blueswir1
}
604 3ccacc4a blueswir1
605 e59fb374 Juan Quintela
static int fdc_post_load(void *opaque, int version_id)
606 3ccacc4a blueswir1
{
607 5c02c033 Blue Swirl
    FDCtrl *s = opaque;
608 3ccacc4a blueswir1
609 d7a6c270 Juan Quintela
    SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
610 d7a6c270 Juan Quintela
    s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
611 3ccacc4a blueswir1
    return 0;
612 3ccacc4a blueswir1
}
613 3ccacc4a blueswir1
614 d7a6c270 Juan Quintela
static const VMStateDescription vmstate_fdc = {
615 aef30c3c Juan Quintela
    .name = "fdc",
616 d7a6c270 Juan Quintela
    .version_id = 2,
617 d7a6c270 Juan Quintela
    .minimum_version_id = 2,
618 d7a6c270 Juan Quintela
    .minimum_version_id_old = 2,
619 d7a6c270 Juan Quintela
    .pre_save = fdc_pre_save,
620 d7a6c270 Juan Quintela
    .post_load = fdc_post_load,
621 d7a6c270 Juan Quintela
    .fields      = (VMStateField []) {
622 d7a6c270 Juan Quintela
        /* Controller State */
623 5c02c033 Blue Swirl
        VMSTATE_UINT8(sra, FDCtrl),
624 5c02c033 Blue Swirl
        VMSTATE_UINT8(srb, FDCtrl),
625 5c02c033 Blue Swirl
        VMSTATE_UINT8(dor_vmstate, FDCtrl),
626 5c02c033 Blue Swirl
        VMSTATE_UINT8(tdr, FDCtrl),
627 5c02c033 Blue Swirl
        VMSTATE_UINT8(dsr, FDCtrl),
628 5c02c033 Blue Swirl
        VMSTATE_UINT8(msr, FDCtrl),
629 5c02c033 Blue Swirl
        VMSTATE_UINT8(status0, FDCtrl),
630 5c02c033 Blue Swirl
        VMSTATE_UINT8(status1, FDCtrl),
631 5c02c033 Blue Swirl
        VMSTATE_UINT8(status2, FDCtrl),
632 d7a6c270 Juan Quintela
        /* Command FIFO */
633 8ec68b06 Blue Swirl
        VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
634 8ec68b06 Blue Swirl
                             uint8_t),
635 5c02c033 Blue Swirl
        VMSTATE_UINT32(data_pos, FDCtrl),
636 5c02c033 Blue Swirl
        VMSTATE_UINT32(data_len, FDCtrl),
637 5c02c033 Blue Swirl
        VMSTATE_UINT8(data_state, FDCtrl),
638 5c02c033 Blue Swirl
        VMSTATE_UINT8(data_dir, FDCtrl),
639 5c02c033 Blue Swirl
        VMSTATE_UINT8(eot, FDCtrl),
640 d7a6c270 Juan Quintela
        /* States kept only to be returned back */
641 5c02c033 Blue Swirl
        VMSTATE_UINT8(timer0, FDCtrl),
642 5c02c033 Blue Swirl
        VMSTATE_UINT8(timer1, FDCtrl),
643 5c02c033 Blue Swirl
        VMSTATE_UINT8(precomp_trk, FDCtrl),
644 5c02c033 Blue Swirl
        VMSTATE_UINT8(config, FDCtrl),
645 5c02c033 Blue Swirl
        VMSTATE_UINT8(lock, FDCtrl),
646 5c02c033 Blue Swirl
        VMSTATE_UINT8(pwrd, FDCtrl),
647 5c02c033 Blue Swirl
        VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl),
648 5c02c033 Blue Swirl
        VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
649 5c02c033 Blue Swirl
                             vmstate_fdrive, FDrive),
650 d7a6c270 Juan Quintela
        VMSTATE_END_OF_LIST()
651 78ae820c blueswir1
    }
652 d7a6c270 Juan Quintela
};
653 3ccacc4a blueswir1
654 2be37833 Blue Swirl
static void fdctrl_external_reset_sysbus(DeviceState *d)
655 3ccacc4a blueswir1
{
656 5c02c033 Blue Swirl
    FDCtrlSysBus *sys = container_of(d, FDCtrlSysBus, busdev.qdev);
657 5c02c033 Blue Swirl
    FDCtrl *s = &sys->state;
658 2be37833 Blue Swirl
659 2be37833 Blue Swirl
    fdctrl_reset(s, 0);
660 2be37833 Blue Swirl
}
661 2be37833 Blue Swirl
662 2be37833 Blue Swirl
static void fdctrl_external_reset_isa(DeviceState *d)
663 2be37833 Blue Swirl
{
664 5c02c033 Blue Swirl
    FDCtrlISABus *isa = container_of(d, FDCtrlISABus, busdev.qdev);
665 5c02c033 Blue Swirl
    FDCtrl *s = &isa->state;
666 3ccacc4a blueswir1
667 3ccacc4a blueswir1
    fdctrl_reset(s, 0);
668 3ccacc4a blueswir1
}
669 3ccacc4a blueswir1
670 2be17ebd blueswir1
static void fdctrl_handle_tc(void *opaque, int irq, int level)
671 2be17ebd blueswir1
{
672 5c02c033 Blue Swirl
    //FDCtrl *s = opaque;
673 2be17ebd blueswir1
674 2be17ebd blueswir1
    if (level) {
675 2be17ebd blueswir1
        // XXX
676 2be17ebd blueswir1
        FLOPPY_DPRINTF("TC pulsed\n");
677 2be17ebd blueswir1
    }
678 2be17ebd blueswir1
}
679 2be17ebd blueswir1
680 8977f3c1 bellard
/* Change IRQ state */
681 5c02c033 Blue Swirl
static void fdctrl_reset_irq(FDCtrl *fdctrl)
682 8977f3c1 bellard
{
683 8c6a4d77 blueswir1
    if (!(fdctrl->sra & FD_SRA_INTPEND))
684 8c6a4d77 blueswir1
        return;
685 ed5fd2cc bellard
    FLOPPY_DPRINTF("Reset interrupt\n");
686 d537cf6c pbrook
    qemu_set_irq(fdctrl->irq, 0);
687 8c6a4d77 blueswir1
    fdctrl->sra &= ~FD_SRA_INTPEND;
688 8977f3c1 bellard
}
689 8977f3c1 bellard
690 5c02c033 Blue Swirl
static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0)
691 8977f3c1 bellard
{
692 b9b3d225 blueswir1
    /* Sparc mutation */
693 b9b3d225 blueswir1
    if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
694 b9b3d225 blueswir1
        /* XXX: not sure */
695 b9b3d225 blueswir1
        fdctrl->msr &= ~FD_MSR_CMDBUSY;
696 b9b3d225 blueswir1
        fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
697 77370520 blueswir1
        fdctrl->status0 = status0;
698 4f431960 j_mayer
        return;
699 6f7e9aec bellard
    }
700 8c6a4d77 blueswir1
    if (!(fdctrl->sra & FD_SRA_INTPEND)) {
701 d537cf6c pbrook
        qemu_set_irq(fdctrl->irq, 1);
702 8c6a4d77 blueswir1
        fdctrl->sra |= FD_SRA_INTPEND;
703 8977f3c1 bellard
    }
704 f2d81b33 blueswir1
    fdctrl->reset_sensei = 0;
705 77370520 blueswir1
    fdctrl->status0 = status0;
706 77370520 blueswir1
    FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
707 8977f3c1 bellard
}
708 8977f3c1 bellard
709 4b19ec0c bellard
/* Reset controller */
710 5c02c033 Blue Swirl
static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
711 8977f3c1 bellard
{
712 8977f3c1 bellard
    int i;
713 8977f3c1 bellard
714 4b19ec0c bellard
    FLOPPY_DPRINTF("reset controller\n");
715 baca51fa bellard
    fdctrl_reset_irq(fdctrl);
716 4b19ec0c bellard
    /* Initialise controller */
717 8c6a4d77 blueswir1
    fdctrl->sra = 0;
718 8c6a4d77 blueswir1
    fdctrl->srb = 0xc0;
719 8c6a4d77 blueswir1
    if (!fdctrl->drives[1].bs)
720 8c6a4d77 blueswir1
        fdctrl->sra |= FD_SRA_nDRV2;
721 baca51fa bellard
    fdctrl->cur_drv = 0;
722 1c346df2 blueswir1
    fdctrl->dor = FD_DOR_nRESET;
723 368df94d blueswir1
    fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
724 b9b3d225 blueswir1
    fdctrl->msr = FD_MSR_RQM;
725 8977f3c1 bellard
    /* FIFO state */
726 baca51fa bellard
    fdctrl->data_pos = 0;
727 baca51fa bellard
    fdctrl->data_len = 0;
728 b9b3d225 blueswir1
    fdctrl->data_state = 0;
729 baca51fa bellard
    fdctrl->data_dir = FD_DIR_WRITE;
730 8977f3c1 bellard
    for (i = 0; i < MAX_FD; i++)
731 1c346df2 blueswir1
        fd_recalibrate(&fdctrl->drives[i]);
732 baca51fa bellard
    fdctrl_reset_fifo(fdctrl);
733 77370520 blueswir1
    if (do_irq) {
734 9fea808a blueswir1
        fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);
735 f2d81b33 blueswir1
        fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
736 77370520 blueswir1
    }
737 baca51fa bellard
}
738 baca51fa bellard
739 5c02c033 Blue Swirl
static inline FDrive *drv0(FDCtrl *fdctrl)
740 baca51fa bellard
{
741 46d3233b blueswir1
    return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
742 baca51fa bellard
}
743 baca51fa bellard
744 5c02c033 Blue Swirl
static inline FDrive *drv1(FDCtrl *fdctrl)
745 baca51fa bellard
{
746 46d3233b blueswir1
    if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
747 46d3233b blueswir1
        return &fdctrl->drives[1];
748 46d3233b blueswir1
    else
749 46d3233b blueswir1
        return &fdctrl->drives[0];
750 baca51fa bellard
}
751 baca51fa bellard
752 78ae820c blueswir1
#if MAX_FD == 4
753 5c02c033 Blue Swirl
static inline FDrive *drv2(FDCtrl *fdctrl)
754 78ae820c blueswir1
{
755 78ae820c blueswir1
    if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
756 78ae820c blueswir1
        return &fdctrl->drives[2];
757 78ae820c blueswir1
    else
758 78ae820c blueswir1
        return &fdctrl->drives[1];
759 78ae820c blueswir1
}
760 78ae820c blueswir1
761 5c02c033 Blue Swirl
static inline FDrive *drv3(FDCtrl *fdctrl)
762 78ae820c blueswir1
{
763 78ae820c blueswir1
    if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
764 78ae820c blueswir1
        return &fdctrl->drives[3];
765 78ae820c blueswir1
    else
766 78ae820c blueswir1
        return &fdctrl->drives[2];
767 78ae820c blueswir1
}
768 78ae820c blueswir1
#endif
769 78ae820c blueswir1
770 5c02c033 Blue Swirl
static FDrive *get_cur_drv(FDCtrl *fdctrl)
771 baca51fa bellard
{
772 78ae820c blueswir1
    switch (fdctrl->cur_drv) {
773 78ae820c blueswir1
        case 0: return drv0(fdctrl);
774 78ae820c blueswir1
        case 1: return drv1(fdctrl);
775 78ae820c blueswir1
#if MAX_FD == 4
776 78ae820c blueswir1
        case 2: return drv2(fdctrl);
777 78ae820c blueswir1
        case 3: return drv3(fdctrl);
778 78ae820c blueswir1
#endif
779 78ae820c blueswir1
        default: return NULL;
780 78ae820c blueswir1
    }
781 8977f3c1 bellard
}
782 8977f3c1 bellard
783 8c6a4d77 blueswir1
/* Status A register : 0x00 (read-only) */
784 5c02c033 Blue Swirl
static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
785 8c6a4d77 blueswir1
{
786 8c6a4d77 blueswir1
    uint32_t retval = fdctrl->sra;
787 8c6a4d77 blueswir1
788 8c6a4d77 blueswir1
    FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
789 8c6a4d77 blueswir1
790 8c6a4d77 blueswir1
    return retval;
791 8c6a4d77 blueswir1
}
792 8c6a4d77 blueswir1
793 8977f3c1 bellard
/* Status B register : 0x01 (read-only) */
794 5c02c033 Blue Swirl
static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
795 8977f3c1 bellard
{
796 8c6a4d77 blueswir1
    uint32_t retval = fdctrl->srb;
797 8c6a4d77 blueswir1
798 8c6a4d77 blueswir1
    FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
799 8c6a4d77 blueswir1
800 8c6a4d77 blueswir1
    return retval;
801 8977f3c1 bellard
}
802 8977f3c1 bellard
803 8977f3c1 bellard
/* Digital output register : 0x02 */
804 5c02c033 Blue Swirl
static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
805 8977f3c1 bellard
{
806 1c346df2 blueswir1
    uint32_t retval = fdctrl->dor;
807 8977f3c1 bellard
808 8977f3c1 bellard
    /* Selected drive */
809 baca51fa bellard
    retval |= fdctrl->cur_drv;
810 8977f3c1 bellard
    FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
811 8977f3c1 bellard
812 8977f3c1 bellard
    return retval;
813 8977f3c1 bellard
}
814 8977f3c1 bellard
815 5c02c033 Blue Swirl
static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
816 8977f3c1 bellard
{
817 8977f3c1 bellard
    FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
818 8c6a4d77 blueswir1
819 8c6a4d77 blueswir1
    /* Motors */
820 8c6a4d77 blueswir1
    if (value & FD_DOR_MOTEN0)
821 8c6a4d77 blueswir1
        fdctrl->srb |= FD_SRB_MTR0;
822 8c6a4d77 blueswir1
    else
823 8c6a4d77 blueswir1
        fdctrl->srb &= ~FD_SRB_MTR0;
824 8c6a4d77 blueswir1
    if (value & FD_DOR_MOTEN1)
825 8c6a4d77 blueswir1
        fdctrl->srb |= FD_SRB_MTR1;
826 8c6a4d77 blueswir1
    else
827 8c6a4d77 blueswir1
        fdctrl->srb &= ~FD_SRB_MTR1;
828 8c6a4d77 blueswir1
829 8c6a4d77 blueswir1
    /* Drive */
830 8c6a4d77 blueswir1
    if (value & 1)
831 8c6a4d77 blueswir1
        fdctrl->srb |= FD_SRB_DR0;
832 8c6a4d77 blueswir1
    else
833 8c6a4d77 blueswir1
        fdctrl->srb &= ~FD_SRB_DR0;
834 8c6a4d77 blueswir1
835 8977f3c1 bellard
    /* Reset */
836 9fea808a blueswir1
    if (!(value & FD_DOR_nRESET)) {
837 1c346df2 blueswir1
        if (fdctrl->dor & FD_DOR_nRESET) {
838 4b19ec0c bellard
            FLOPPY_DPRINTF("controller enter RESET state\n");
839 8977f3c1 bellard
        }
840 8977f3c1 bellard
    } else {
841 1c346df2 blueswir1
        if (!(fdctrl->dor & FD_DOR_nRESET)) {
842 4b19ec0c bellard
            FLOPPY_DPRINTF("controller out of RESET state\n");
843 fb6cf1d0 bellard
            fdctrl_reset(fdctrl, 1);
844 b9b3d225 blueswir1
            fdctrl->dsr &= ~FD_DSR_PWRDOWN;
845 8977f3c1 bellard
        }
846 8977f3c1 bellard
    }
847 8977f3c1 bellard
    /* Selected drive */
848 9fea808a blueswir1
    fdctrl->cur_drv = value & FD_DOR_SELMASK;
849 368df94d blueswir1
850 368df94d blueswir1
    fdctrl->dor = value;
851 8977f3c1 bellard
}
852 8977f3c1 bellard
853 8977f3c1 bellard
/* Tape drive register : 0x03 */
854 5c02c033 Blue Swirl
static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
855 8977f3c1 bellard
{
856 46d3233b blueswir1
    uint32_t retval = fdctrl->tdr;
857 8977f3c1 bellard
858 8977f3c1 bellard
    FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
859 8977f3c1 bellard
860 8977f3c1 bellard
    return retval;
861 8977f3c1 bellard
}
862 8977f3c1 bellard
863 5c02c033 Blue Swirl
static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
864 8977f3c1 bellard
{
865 8977f3c1 bellard
    /* Reset mode */
866 1c346df2 blueswir1
    if (!(fdctrl->dor & FD_DOR_nRESET)) {
867 4b19ec0c bellard
        FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
868 8977f3c1 bellard
        return;
869 8977f3c1 bellard
    }
870 8977f3c1 bellard
    FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
871 8977f3c1 bellard
    /* Disk boot selection indicator */
872 46d3233b blueswir1
    fdctrl->tdr = value & FD_TDR_BOOTSEL;
873 8977f3c1 bellard
    /* Tape indicators: never allow */
874 8977f3c1 bellard
}
875 8977f3c1 bellard
876 8977f3c1 bellard
/* Main status register : 0x04 (read) */
877 5c02c033 Blue Swirl
static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
878 8977f3c1 bellard
{
879 b9b3d225 blueswir1
    uint32_t retval = fdctrl->msr;
880 8977f3c1 bellard
881 b9b3d225 blueswir1
    fdctrl->dsr &= ~FD_DSR_PWRDOWN;
882 1c346df2 blueswir1
    fdctrl->dor |= FD_DOR_nRESET;
883 b9b3d225 blueswir1
884 82407d1a Artyom Tarasenko
    /* Sparc mutation */
885 82407d1a Artyom Tarasenko
    if (fdctrl->sun4m) {
886 82407d1a Artyom Tarasenko
        retval |= FD_MSR_DIO;
887 82407d1a Artyom Tarasenko
        fdctrl_reset_irq(fdctrl);
888 82407d1a Artyom Tarasenko
    };
889 82407d1a Artyom Tarasenko
890 8977f3c1 bellard
    FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
891 8977f3c1 bellard
892 8977f3c1 bellard
    return retval;
893 8977f3c1 bellard
}
894 8977f3c1 bellard
895 8977f3c1 bellard
/* Data select rate register : 0x04 (write) */
896 5c02c033 Blue Swirl
static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
897 8977f3c1 bellard
{
898 8977f3c1 bellard
    /* Reset mode */
899 1c346df2 blueswir1
    if (!(fdctrl->dor & FD_DOR_nRESET)) {
900 4f431960 j_mayer
        FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
901 4f431960 j_mayer
        return;
902 4f431960 j_mayer
    }
903 8977f3c1 bellard
    FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
904 8977f3c1 bellard
    /* Reset: autoclear */
905 9fea808a blueswir1
    if (value & FD_DSR_SWRESET) {
906 1c346df2 blueswir1
        fdctrl->dor &= ~FD_DOR_nRESET;
907 baca51fa bellard
        fdctrl_reset(fdctrl, 1);
908 1c346df2 blueswir1
        fdctrl->dor |= FD_DOR_nRESET;
909 8977f3c1 bellard
    }
910 9fea808a blueswir1
    if (value & FD_DSR_PWRDOWN) {
911 baca51fa bellard
        fdctrl_reset(fdctrl, 1);
912 8977f3c1 bellard
    }
913 b9b3d225 blueswir1
    fdctrl->dsr = value;
914 8977f3c1 bellard
}
915 8977f3c1 bellard
916 5c02c033 Blue Swirl
static int fdctrl_media_changed(FDrive *drv)
917 ea185bbd bellard
{
918 ea185bbd bellard
    int ret;
919 4f431960 j_mayer
920 5fafdf24 ths
    if (!drv->bs)
921 ea185bbd bellard
        return 0;
922 ea185bbd bellard
    ret = bdrv_media_changed(drv->bs);
923 ea185bbd bellard
    if (ret) {
924 ea185bbd bellard
        fd_revalidate(drv);
925 ea185bbd bellard
    }
926 ea185bbd bellard
    return ret;
927 ea185bbd bellard
}
928 ea185bbd bellard
929 8977f3c1 bellard
/* Digital input register : 0x07 (read-only) */
930 5c02c033 Blue Swirl
static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
931 8977f3c1 bellard
{
932 8977f3c1 bellard
    uint32_t retval = 0;
933 8977f3c1 bellard
934 78ae820c blueswir1
    if (fdctrl_media_changed(drv0(fdctrl))
935 78ae820c blueswir1
     || fdctrl_media_changed(drv1(fdctrl))
936 78ae820c blueswir1
#if MAX_FD == 4
937 78ae820c blueswir1
     || fdctrl_media_changed(drv2(fdctrl))
938 78ae820c blueswir1
     || fdctrl_media_changed(drv3(fdctrl))
939 78ae820c blueswir1
#endif
940 78ae820c blueswir1
        )
941 9fea808a blueswir1
        retval |= FD_DIR_DSKCHG;
942 3c83eb4f Blue Swirl
    if (retval != 0) {
943 baca51fa bellard
        FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
944 3c83eb4f Blue Swirl
    }
945 8977f3c1 bellard
946 8977f3c1 bellard
    return retval;
947 8977f3c1 bellard
}
948 8977f3c1 bellard
949 8977f3c1 bellard
/* FIFO state control */
950 5c02c033 Blue Swirl
static void fdctrl_reset_fifo(FDCtrl *fdctrl)
951 8977f3c1 bellard
{
952 baca51fa bellard
    fdctrl->data_dir = FD_DIR_WRITE;
953 baca51fa bellard
    fdctrl->data_pos = 0;
954 b9b3d225 blueswir1
    fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
955 8977f3c1 bellard
}
956 8977f3c1 bellard
957 8977f3c1 bellard
/* Set FIFO status for the host to read */
958 5c02c033 Blue Swirl
static void fdctrl_set_fifo(FDCtrl *fdctrl, int fifo_len, int do_irq)
959 8977f3c1 bellard
{
960 baca51fa bellard
    fdctrl->data_dir = FD_DIR_READ;
961 baca51fa bellard
    fdctrl->data_len = fifo_len;
962 baca51fa bellard
    fdctrl->data_pos = 0;
963 b9b3d225 blueswir1
    fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
964 8977f3c1 bellard
    if (do_irq)
965 baca51fa bellard
        fdctrl_raise_irq(fdctrl, 0x00);
966 8977f3c1 bellard
}
967 8977f3c1 bellard
968 8977f3c1 bellard
/* Set an error: unimplemented/unknown command */
969 5c02c033 Blue Swirl
static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
970 8977f3c1 bellard
{
971 77370520 blueswir1
    FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]);
972 9fea808a blueswir1
    fdctrl->fifo[0] = FD_SR0_INVCMD;
973 baca51fa bellard
    fdctrl_set_fifo(fdctrl, 1, 0);
974 8977f3c1 bellard
}
975 8977f3c1 bellard
976 746d6de7 blueswir1
/* Seek to next sector */
977 5c02c033 Blue Swirl
static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
978 746d6de7 blueswir1
{
979 746d6de7 blueswir1
    FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
980 746d6de7 blueswir1
                   cur_drv->head, cur_drv->track, cur_drv->sect,
981 746d6de7 blueswir1
                   fd_sector(cur_drv));
982 746d6de7 blueswir1
    /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
983 746d6de7 blueswir1
       error in fact */
984 746d6de7 blueswir1
    if (cur_drv->sect >= cur_drv->last_sect ||
985 746d6de7 blueswir1
        cur_drv->sect == fdctrl->eot) {
986 746d6de7 blueswir1
        cur_drv->sect = 1;
987 746d6de7 blueswir1
        if (FD_MULTI_TRACK(fdctrl->data_state)) {
988 746d6de7 blueswir1
            if (cur_drv->head == 0 &&
989 746d6de7 blueswir1
                (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
990 746d6de7 blueswir1
                cur_drv->head = 1;
991 746d6de7 blueswir1
            } else {
992 746d6de7 blueswir1
                cur_drv->head = 0;
993 746d6de7 blueswir1
                cur_drv->track++;
994 746d6de7 blueswir1
                if ((cur_drv->flags & FDISK_DBL_SIDES) == 0)
995 746d6de7 blueswir1
                    return 0;
996 746d6de7 blueswir1
            }
997 746d6de7 blueswir1
        } else {
998 746d6de7 blueswir1
            cur_drv->track++;
999 746d6de7 blueswir1
            return 0;
1000 746d6de7 blueswir1
        }
1001 746d6de7 blueswir1
        FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1002 746d6de7 blueswir1
                       cur_drv->head, cur_drv->track,
1003 746d6de7 blueswir1
                       cur_drv->sect, fd_sector(cur_drv));
1004 746d6de7 blueswir1
    } else {
1005 746d6de7 blueswir1
        cur_drv->sect++;
1006 746d6de7 blueswir1
    }
1007 746d6de7 blueswir1
    return 1;
1008 746d6de7 blueswir1
}
1009 746d6de7 blueswir1
1010 8977f3c1 bellard
/* Callback for transfer end (stop or abort) */
1011 5c02c033 Blue Swirl
static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
1012 5c02c033 Blue Swirl
                                 uint8_t status1, uint8_t status2)
1013 8977f3c1 bellard
{
1014 5c02c033 Blue Swirl
    FDrive *cur_drv;
1015 8977f3c1 bellard
1016 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1017 8977f3c1 bellard
    FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1018 8977f3c1 bellard
                   status0, status1, status2,
1019 cefec4f5 blueswir1
                   status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl));
1020 cefec4f5 blueswir1
    fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1021 baca51fa bellard
    fdctrl->fifo[1] = status1;
1022 baca51fa bellard
    fdctrl->fifo[2] = status2;
1023 baca51fa bellard
    fdctrl->fifo[3] = cur_drv->track;
1024 baca51fa bellard
    fdctrl->fifo[4] = cur_drv->head;
1025 baca51fa bellard
    fdctrl->fifo[5] = cur_drv->sect;
1026 baca51fa bellard
    fdctrl->fifo[6] = FD_SECTOR_SC;
1027 baca51fa bellard
    fdctrl->data_dir = FD_DIR_READ;
1028 368df94d blueswir1
    if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1029 baca51fa bellard
        DMA_release_DREQ(fdctrl->dma_chann);
1030 ed5fd2cc bellard
    }
1031 b9b3d225 blueswir1
    fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1032 368df94d blueswir1
    fdctrl->msr &= ~FD_MSR_NONDMA;
1033 baca51fa bellard
    fdctrl_set_fifo(fdctrl, 7, 1);
1034 8977f3c1 bellard
}
1035 8977f3c1 bellard
1036 8977f3c1 bellard
/* Prepare a data transfer (either DMA or FIFO) */
1037 5c02c033 Blue Swirl
static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
1038 8977f3c1 bellard
{
1039 5c02c033 Blue Swirl
    FDrive *cur_drv;
1040 8977f3c1 bellard
    uint8_t kh, kt, ks;
1041 77370520 blueswir1
    int did_seek = 0;
1042 8977f3c1 bellard
1043 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1044 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1045 baca51fa bellard
    kt = fdctrl->fifo[2];
1046 baca51fa bellard
    kh = fdctrl->fifo[3];
1047 baca51fa bellard
    ks = fdctrl->fifo[4];
1048 4b19ec0c bellard
    FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1049 cefec4f5 blueswir1
                   GET_CUR_DRV(fdctrl), kh, kt, ks,
1050 7859cb98 Blue Swirl
                   fd_sector_calc(kh, kt, ks, cur_drv->last_sect));
1051 77370520 blueswir1
    switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1052 8977f3c1 bellard
    case 2:
1053 8977f3c1 bellard
        /* sect too big */
1054 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1055 baca51fa bellard
        fdctrl->fifo[3] = kt;
1056 baca51fa bellard
        fdctrl->fifo[4] = kh;
1057 baca51fa bellard
        fdctrl->fifo[5] = ks;
1058 8977f3c1 bellard
        return;
1059 8977f3c1 bellard
    case 3:
1060 8977f3c1 bellard
        /* track too big */
1061 77370520 blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1062 baca51fa bellard
        fdctrl->fifo[3] = kt;
1063 baca51fa bellard
        fdctrl->fifo[4] = kh;
1064 baca51fa bellard
        fdctrl->fifo[5] = ks;
1065 8977f3c1 bellard
        return;
1066 8977f3c1 bellard
    case 4:
1067 8977f3c1 bellard
        /* No seek enabled */
1068 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1069 baca51fa bellard
        fdctrl->fifo[3] = kt;
1070 baca51fa bellard
        fdctrl->fifo[4] = kh;
1071 baca51fa bellard
        fdctrl->fifo[5] = ks;
1072 8977f3c1 bellard
        return;
1073 8977f3c1 bellard
    case 1:
1074 8977f3c1 bellard
        did_seek = 1;
1075 8977f3c1 bellard
        break;
1076 8977f3c1 bellard
    default:
1077 8977f3c1 bellard
        break;
1078 8977f3c1 bellard
    }
1079 b9b3d225 blueswir1
1080 8977f3c1 bellard
    /* Set the FIFO state */
1081 baca51fa bellard
    fdctrl->data_dir = direction;
1082 baca51fa bellard
    fdctrl->data_pos = 0;
1083 b9b3d225 blueswir1
    fdctrl->msr |= FD_MSR_CMDBUSY;
1084 baca51fa bellard
    if (fdctrl->fifo[0] & 0x80)
1085 baca51fa bellard
        fdctrl->data_state |= FD_STATE_MULTI;
1086 baca51fa bellard
    else
1087 baca51fa bellard
        fdctrl->data_state &= ~FD_STATE_MULTI;
1088 8977f3c1 bellard
    if (did_seek)
1089 baca51fa bellard
        fdctrl->data_state |= FD_STATE_SEEK;
1090 baca51fa bellard
    else
1091 baca51fa bellard
        fdctrl->data_state &= ~FD_STATE_SEEK;
1092 baca51fa bellard
    if (fdctrl->fifo[5] == 00) {
1093 baca51fa bellard
        fdctrl->data_len = fdctrl->fifo[8];
1094 baca51fa bellard
    } else {
1095 4f431960 j_mayer
        int tmp;
1096 3bcb80f1 ths
        fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1097 771effeb blueswir1
        tmp = (fdctrl->fifo[6] - ks + 1);
1098 baca51fa bellard
        if (fdctrl->fifo[0] & 0x80)
1099 771effeb blueswir1
            tmp += fdctrl->fifo[6];
1100 4f431960 j_mayer
        fdctrl->data_len *= tmp;
1101 baca51fa bellard
    }
1102 890fa6be bellard
    fdctrl->eot = fdctrl->fifo[6];
1103 368df94d blueswir1
    if (fdctrl->dor & FD_DOR_DMAEN) {
1104 8977f3c1 bellard
        int dma_mode;
1105 8977f3c1 bellard
        /* DMA transfer are enabled. Check if DMA channel is well programmed */
1106 baca51fa bellard
        dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1107 8977f3c1 bellard
        dma_mode = (dma_mode >> 2) & 3;
1108 baca51fa bellard
        FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1109 4f431960 j_mayer
                       dma_mode, direction,
1110 baca51fa bellard
                       (128 << fdctrl->fifo[5]) *
1111 4f431960 j_mayer
                       (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1112 8977f3c1 bellard
        if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1113 8977f3c1 bellard
              direction == FD_DIR_SCANH) && dma_mode == 0) ||
1114 8977f3c1 bellard
            (direction == FD_DIR_WRITE && dma_mode == 2) ||
1115 8977f3c1 bellard
            (direction == FD_DIR_READ && dma_mode == 1)) {
1116 8977f3c1 bellard
            /* No access is allowed until DMA transfer has completed */
1117 b9b3d225 blueswir1
            fdctrl->msr &= ~FD_MSR_RQM;
1118 4b19ec0c bellard
            /* Now, we just have to wait for the DMA controller to
1119 8977f3c1 bellard
             * recall us...
1120 8977f3c1 bellard
             */
1121 baca51fa bellard
            DMA_hold_DREQ(fdctrl->dma_chann);
1122 baca51fa bellard
            DMA_schedule(fdctrl->dma_chann);
1123 8977f3c1 bellard
            return;
1124 baca51fa bellard
        } else {
1125 4f431960 j_mayer
            FLOPPY_ERROR("dma_mode=%d direction=%d\n", dma_mode, direction);
1126 8977f3c1 bellard
        }
1127 8977f3c1 bellard
    }
1128 8977f3c1 bellard
    FLOPPY_DPRINTF("start non-DMA transfer\n");
1129 368df94d blueswir1
    fdctrl->msr |= FD_MSR_NONDMA;
1130 b9b3d225 blueswir1
    if (direction != FD_DIR_WRITE)
1131 b9b3d225 blueswir1
        fdctrl->msr |= FD_MSR_DIO;
1132 8977f3c1 bellard
    /* IO based transfer: calculate len */
1133 baca51fa bellard
    fdctrl_raise_irq(fdctrl, 0x00);
1134 8977f3c1 bellard
1135 8977f3c1 bellard
    return;
1136 8977f3c1 bellard
}
1137 8977f3c1 bellard
1138 8977f3c1 bellard
/* Prepare a transfer of deleted data */
1139 5c02c033 Blue Swirl
static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
1140 8977f3c1 bellard
{
1141 77370520 blueswir1
    FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
1142 77370520 blueswir1
1143 8977f3c1 bellard
    /* We don't handle deleted data,
1144 8977f3c1 bellard
     * so we don't return *ANYTHING*
1145 8977f3c1 bellard
     */
1146 9fea808a blueswir1
    fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1147 8977f3c1 bellard
}
1148 8977f3c1 bellard
1149 8977f3c1 bellard
/* handlers for DMA transfers */
1150 85571bc7 bellard
static int fdctrl_transfer_handler (void *opaque, int nchan,
1151 85571bc7 bellard
                                    int dma_pos, int dma_len)
1152 8977f3c1 bellard
{
1153 5c02c033 Blue Swirl
    FDCtrl *fdctrl;
1154 5c02c033 Blue Swirl
    FDrive *cur_drv;
1155 baca51fa bellard
    int len, start_pos, rel_pos;
1156 8977f3c1 bellard
    uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1157 8977f3c1 bellard
1158 baca51fa bellard
    fdctrl = opaque;
1159 b9b3d225 blueswir1
    if (fdctrl->msr & FD_MSR_RQM) {
1160 8977f3c1 bellard
        FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1161 8977f3c1 bellard
        return 0;
1162 8977f3c1 bellard
    }
1163 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1164 baca51fa bellard
    if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1165 baca51fa bellard
        fdctrl->data_dir == FD_DIR_SCANH)
1166 77370520 blueswir1
        status2 = FD_SR2_SNS;
1167 85571bc7 bellard
    if (dma_len > fdctrl->data_len)
1168 85571bc7 bellard
        dma_len = fdctrl->data_len;
1169 890fa6be bellard
    if (cur_drv->bs == NULL) {
1170 4f431960 j_mayer
        if (fdctrl->data_dir == FD_DIR_WRITE)
1171 9fea808a blueswir1
            fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1172 4f431960 j_mayer
        else
1173 9fea808a blueswir1
            fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1174 4f431960 j_mayer
        len = 0;
1175 890fa6be bellard
        goto transfer_error;
1176 890fa6be bellard
    }
1177 baca51fa bellard
    rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1178 85571bc7 bellard
    for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1179 85571bc7 bellard
        len = dma_len - fdctrl->data_pos;
1180 baca51fa bellard
        if (len + rel_pos > FD_SECTOR_LEN)
1181 baca51fa bellard
            len = FD_SECTOR_LEN - rel_pos;
1182 6f7e9aec bellard
        FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1183 6f7e9aec bellard
                       "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1184 cefec4f5 blueswir1
                       fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1185 baca51fa bellard
                       cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1186 9fea808a blueswir1
                       fd_sector(cur_drv) * FD_SECTOR_LEN);
1187 baca51fa bellard
        if (fdctrl->data_dir != FD_DIR_WRITE ||
1188 4f431960 j_mayer
            len < FD_SECTOR_LEN || rel_pos != 0) {
1189 baca51fa bellard
            /* READ & SCAN commands and realign to a sector for WRITE */
1190 baca51fa bellard
            if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
1191 4f431960 j_mayer
                          fdctrl->fifo, 1) < 0) {
1192 8977f3c1 bellard
                FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1193 8977f3c1 bellard
                               fd_sector(cur_drv));
1194 8977f3c1 bellard
                /* Sure, image size is too small... */
1195 baca51fa bellard
                memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1196 8977f3c1 bellard
            }
1197 890fa6be bellard
        }
1198 4f431960 j_mayer
        switch (fdctrl->data_dir) {
1199 4f431960 j_mayer
        case FD_DIR_READ:
1200 4f431960 j_mayer
            /* READ commands */
1201 85571bc7 bellard
            DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1202 85571bc7 bellard
                              fdctrl->data_pos, len);
1203 4f431960 j_mayer
            break;
1204 4f431960 j_mayer
        case FD_DIR_WRITE:
1205 baca51fa bellard
            /* WRITE commands */
1206 85571bc7 bellard
            DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1207 85571bc7 bellard
                             fdctrl->data_pos, len);
1208 baca51fa bellard
            if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
1209 4f431960 j_mayer
                           fdctrl->fifo, 1) < 0) {
1210 77370520 blueswir1
                FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1211 9fea808a blueswir1
                fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1212 baca51fa bellard
                goto transfer_error;
1213 890fa6be bellard
            }
1214 4f431960 j_mayer
            break;
1215 4f431960 j_mayer
        default:
1216 4f431960 j_mayer
            /* SCAN commands */
1217 baca51fa bellard
            {
1218 4f431960 j_mayer
                uint8_t tmpbuf[FD_SECTOR_LEN];
1219 baca51fa bellard
                int ret;
1220 85571bc7 bellard
                DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1221 baca51fa bellard
                ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1222 8977f3c1 bellard
                if (ret == 0) {
1223 77370520 blueswir1
                    status2 = FD_SR2_SEH;
1224 8977f3c1 bellard
                    goto end_transfer;
1225 8977f3c1 bellard
                }
1226 baca51fa bellard
                if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1227 baca51fa bellard
                    (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1228 8977f3c1 bellard
                    status2 = 0x00;
1229 8977f3c1 bellard
                    goto end_transfer;
1230 8977f3c1 bellard
                }
1231 8977f3c1 bellard
            }
1232 4f431960 j_mayer
            break;
1233 8977f3c1 bellard
        }
1234 4f431960 j_mayer
        fdctrl->data_pos += len;
1235 4f431960 j_mayer
        rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1236 baca51fa bellard
        if (rel_pos == 0) {
1237 8977f3c1 bellard
            /* Seek to next sector */
1238 746d6de7 blueswir1
            if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1239 746d6de7 blueswir1
                break;
1240 8977f3c1 bellard
        }
1241 8977f3c1 bellard
    }
1242 4f431960 j_mayer
 end_transfer:
1243 baca51fa bellard
    len = fdctrl->data_pos - start_pos;
1244 baca51fa bellard
    FLOPPY_DPRINTF("end transfer %d %d %d\n",
1245 4f431960 j_mayer
                   fdctrl->data_pos, len, fdctrl->data_len);
1246 baca51fa bellard
    if (fdctrl->data_dir == FD_DIR_SCANE ||
1247 baca51fa bellard
        fdctrl->data_dir == FD_DIR_SCANL ||
1248 baca51fa bellard
        fdctrl->data_dir == FD_DIR_SCANH)
1249 77370520 blueswir1
        status2 = FD_SR2_SEH;
1250 baca51fa bellard
    if (FD_DID_SEEK(fdctrl->data_state))
1251 9fea808a blueswir1
        status0 |= FD_SR0_SEEK;
1252 baca51fa bellard
    fdctrl->data_len -= len;
1253 890fa6be bellard
    fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1254 4f431960 j_mayer
 transfer_error:
1255 8977f3c1 bellard
1256 baca51fa bellard
    return len;
1257 8977f3c1 bellard
}
1258 8977f3c1 bellard
1259 8977f3c1 bellard
/* Data register : 0x05 */
1260 5c02c033 Blue Swirl
static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
1261 8977f3c1 bellard
{
1262 5c02c033 Blue Swirl
    FDrive *cur_drv;
1263 8977f3c1 bellard
    uint32_t retval = 0;
1264 746d6de7 blueswir1
    int pos;
1265 8977f3c1 bellard
1266 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1267 b9b3d225 blueswir1
    fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1268 b9b3d225 blueswir1
    if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1269 b9b3d225 blueswir1
        FLOPPY_ERROR("controller not ready for reading\n");
1270 8977f3c1 bellard
        return 0;
1271 8977f3c1 bellard
    }
1272 baca51fa bellard
    pos = fdctrl->data_pos;
1273 368df94d blueswir1
    if (fdctrl->msr & FD_MSR_NONDMA) {
1274 8977f3c1 bellard
        pos %= FD_SECTOR_LEN;
1275 8977f3c1 bellard
        if (pos == 0) {
1276 746d6de7 blueswir1
            if (fdctrl->data_pos != 0)
1277 746d6de7 blueswir1
                if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1278 746d6de7 blueswir1
                    FLOPPY_DPRINTF("error seeking to next sector %d\n",
1279 746d6de7 blueswir1
                                   fd_sector(cur_drv));
1280 746d6de7 blueswir1
                    return 0;
1281 746d6de7 blueswir1
                }
1282 77370520 blueswir1
            if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1283 77370520 blueswir1
                FLOPPY_DPRINTF("error getting sector %d\n",
1284 77370520 blueswir1
                               fd_sector(cur_drv));
1285 77370520 blueswir1
                /* Sure, image size is too small... */
1286 77370520 blueswir1
                memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1287 77370520 blueswir1
            }
1288 8977f3c1 bellard
        }
1289 8977f3c1 bellard
    }
1290 baca51fa bellard
    retval = fdctrl->fifo[pos];
1291 baca51fa bellard
    if (++fdctrl->data_pos == fdctrl->data_len) {
1292 baca51fa bellard
        fdctrl->data_pos = 0;
1293 890fa6be bellard
        /* Switch from transfer mode to status mode
1294 8977f3c1 bellard
         * then from status mode to command mode
1295 8977f3c1 bellard
         */
1296 368df94d blueswir1
        if (fdctrl->msr & FD_MSR_NONDMA) {
1297 9fea808a blueswir1
            fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1298 ed5fd2cc bellard
        } else {
1299 baca51fa bellard
            fdctrl_reset_fifo(fdctrl);
1300 ed5fd2cc bellard
            fdctrl_reset_irq(fdctrl);
1301 ed5fd2cc bellard
        }
1302 8977f3c1 bellard
    }
1303 8977f3c1 bellard
    FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1304 8977f3c1 bellard
1305 8977f3c1 bellard
    return retval;
1306 8977f3c1 bellard
}
1307 8977f3c1 bellard
1308 5c02c033 Blue Swirl
static void fdctrl_format_sector(FDCtrl *fdctrl)
1309 8977f3c1 bellard
{
1310 5c02c033 Blue Swirl
    FDrive *cur_drv;
1311 baca51fa bellard
    uint8_t kh, kt, ks;
1312 8977f3c1 bellard
1313 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1314 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1315 baca51fa bellard
    kt = fdctrl->fifo[6];
1316 baca51fa bellard
    kh = fdctrl->fifo[7];
1317 baca51fa bellard
    ks = fdctrl->fifo[8];
1318 baca51fa bellard
    FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1319 cefec4f5 blueswir1
                   GET_CUR_DRV(fdctrl), kh, kt, ks,
1320 7859cb98 Blue Swirl
                   fd_sector_calc(kh, kt, ks, cur_drv->last_sect));
1321 9fea808a blueswir1
    switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1322 baca51fa bellard
    case 2:
1323 baca51fa bellard
        /* sect too big */
1324 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1325 baca51fa bellard
        fdctrl->fifo[3] = kt;
1326 baca51fa bellard
        fdctrl->fifo[4] = kh;
1327 baca51fa bellard
        fdctrl->fifo[5] = ks;
1328 baca51fa bellard
        return;
1329 baca51fa bellard
    case 3:
1330 baca51fa bellard
        /* track too big */
1331 77370520 blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1332 baca51fa bellard
        fdctrl->fifo[3] = kt;
1333 baca51fa bellard
        fdctrl->fifo[4] = kh;
1334 baca51fa bellard
        fdctrl->fifo[5] = ks;
1335 baca51fa bellard
        return;
1336 baca51fa bellard
    case 4:
1337 baca51fa bellard
        /* No seek enabled */
1338 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1339 baca51fa bellard
        fdctrl->fifo[3] = kt;
1340 baca51fa bellard
        fdctrl->fifo[4] = kh;
1341 baca51fa bellard
        fdctrl->fifo[5] = ks;
1342 baca51fa bellard
        return;
1343 baca51fa bellard
    case 1:
1344 baca51fa bellard
        fdctrl->data_state |= FD_STATE_SEEK;
1345 baca51fa bellard
        break;
1346 baca51fa bellard
    default:
1347 baca51fa bellard
        break;
1348 baca51fa bellard
    }
1349 baca51fa bellard
    memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1350 baca51fa bellard
    if (cur_drv->bs == NULL ||
1351 baca51fa bellard
        bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1352 37a4c539 ths
        FLOPPY_ERROR("formatting sector %d\n", fd_sector(cur_drv));
1353 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1354 baca51fa bellard
    } else {
1355 4f431960 j_mayer
        if (cur_drv->sect == cur_drv->last_sect) {
1356 4f431960 j_mayer
            fdctrl->data_state &= ~FD_STATE_FORMAT;
1357 4f431960 j_mayer
            /* Last sector done */
1358 4f431960 j_mayer
            if (FD_DID_SEEK(fdctrl->data_state))
1359 9fea808a blueswir1
                fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1360 4f431960 j_mayer
            else
1361 4f431960 j_mayer
                fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1362 4f431960 j_mayer
        } else {
1363 4f431960 j_mayer
            /* More to do */
1364 4f431960 j_mayer
            fdctrl->data_pos = 0;
1365 4f431960 j_mayer
            fdctrl->data_len = 4;
1366 4f431960 j_mayer
        }
1367 baca51fa bellard
    }
1368 baca51fa bellard
}
1369 baca51fa bellard
1370 5c02c033 Blue Swirl
static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
1371 65cef780 blueswir1
{
1372 65cef780 blueswir1
    fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1373 65cef780 blueswir1
    fdctrl->fifo[0] = fdctrl->lock << 4;
1374 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, fdctrl->lock);
1375 65cef780 blueswir1
}
1376 65cef780 blueswir1
1377 5c02c033 Blue Swirl
static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
1378 65cef780 blueswir1
{
1379 5c02c033 Blue Swirl
    FDrive *cur_drv = get_cur_drv(fdctrl);
1380 65cef780 blueswir1
1381 65cef780 blueswir1
    /* Drives position */
1382 65cef780 blueswir1
    fdctrl->fifo[0] = drv0(fdctrl)->track;
1383 65cef780 blueswir1
    fdctrl->fifo[1] = drv1(fdctrl)->track;
1384 78ae820c blueswir1
#if MAX_FD == 4
1385 78ae820c blueswir1
    fdctrl->fifo[2] = drv2(fdctrl)->track;
1386 78ae820c blueswir1
    fdctrl->fifo[3] = drv3(fdctrl)->track;
1387 78ae820c blueswir1
#else
1388 65cef780 blueswir1
    fdctrl->fifo[2] = 0;
1389 65cef780 blueswir1
    fdctrl->fifo[3] = 0;
1390 78ae820c blueswir1
#endif
1391 65cef780 blueswir1
    /* timers */
1392 65cef780 blueswir1
    fdctrl->fifo[4] = fdctrl->timer0;
1393 368df94d blueswir1
    fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1394 65cef780 blueswir1
    fdctrl->fifo[6] = cur_drv->last_sect;
1395 65cef780 blueswir1
    fdctrl->fifo[7] = (fdctrl->lock << 7) |
1396 65cef780 blueswir1
        (cur_drv->perpendicular << 2);
1397 65cef780 blueswir1
    fdctrl->fifo[8] = fdctrl->config;
1398 65cef780 blueswir1
    fdctrl->fifo[9] = fdctrl->precomp_trk;
1399 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 10, 0);
1400 65cef780 blueswir1
}
1401 65cef780 blueswir1
1402 5c02c033 Blue Swirl
static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
1403 65cef780 blueswir1
{
1404 65cef780 blueswir1
    /* Controller's version */
1405 65cef780 blueswir1
    fdctrl->fifo[0] = fdctrl->version;
1406 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, 1);
1407 65cef780 blueswir1
}
1408 65cef780 blueswir1
1409 5c02c033 Blue Swirl
static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
1410 65cef780 blueswir1
{
1411 65cef780 blueswir1
    fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1412 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, 0);
1413 65cef780 blueswir1
}
1414 65cef780 blueswir1
1415 5c02c033 Blue Swirl
static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
1416 65cef780 blueswir1
{
1417 5c02c033 Blue Swirl
    FDrive *cur_drv = get_cur_drv(fdctrl);
1418 65cef780 blueswir1
1419 65cef780 blueswir1
    /* Drives position */
1420 65cef780 blueswir1
    drv0(fdctrl)->track = fdctrl->fifo[3];
1421 65cef780 blueswir1
    drv1(fdctrl)->track = fdctrl->fifo[4];
1422 78ae820c blueswir1
#if MAX_FD == 4
1423 78ae820c blueswir1
    drv2(fdctrl)->track = fdctrl->fifo[5];
1424 78ae820c blueswir1
    drv3(fdctrl)->track = fdctrl->fifo[6];
1425 78ae820c blueswir1
#endif
1426 65cef780 blueswir1
    /* timers */
1427 65cef780 blueswir1
    fdctrl->timer0 = fdctrl->fifo[7];
1428 65cef780 blueswir1
    fdctrl->timer1 = fdctrl->fifo[8];
1429 65cef780 blueswir1
    cur_drv->last_sect = fdctrl->fifo[9];
1430 65cef780 blueswir1
    fdctrl->lock = fdctrl->fifo[10] >> 7;
1431 65cef780 blueswir1
    cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1432 65cef780 blueswir1
    fdctrl->config = fdctrl->fifo[11];
1433 65cef780 blueswir1
    fdctrl->precomp_trk = fdctrl->fifo[12];
1434 65cef780 blueswir1
    fdctrl->pwrd = fdctrl->fifo[13];
1435 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1436 65cef780 blueswir1
}
1437 65cef780 blueswir1
1438 5c02c033 Blue Swirl
static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
1439 65cef780 blueswir1
{
1440 5c02c033 Blue Swirl
    FDrive *cur_drv = get_cur_drv(fdctrl);
1441 65cef780 blueswir1
1442 65cef780 blueswir1
    fdctrl->fifo[0] = 0;
1443 65cef780 blueswir1
    fdctrl->fifo[1] = 0;
1444 65cef780 blueswir1
    /* Drives position */
1445 65cef780 blueswir1
    fdctrl->fifo[2] = drv0(fdctrl)->track;
1446 65cef780 blueswir1
    fdctrl->fifo[3] = drv1(fdctrl)->track;
1447 78ae820c blueswir1
#if MAX_FD == 4
1448 78ae820c blueswir1
    fdctrl->fifo[4] = drv2(fdctrl)->track;
1449 78ae820c blueswir1
    fdctrl->fifo[5] = drv3(fdctrl)->track;
1450 78ae820c blueswir1
#else
1451 65cef780 blueswir1
    fdctrl->fifo[4] = 0;
1452 65cef780 blueswir1
    fdctrl->fifo[5] = 0;
1453 78ae820c blueswir1
#endif
1454 65cef780 blueswir1
    /* timers */
1455 65cef780 blueswir1
    fdctrl->fifo[6] = fdctrl->timer0;
1456 65cef780 blueswir1
    fdctrl->fifo[7] = fdctrl->timer1;
1457 65cef780 blueswir1
    fdctrl->fifo[8] = cur_drv->last_sect;
1458 65cef780 blueswir1
    fdctrl->fifo[9] = (fdctrl->lock << 7) |
1459 65cef780 blueswir1
        (cur_drv->perpendicular << 2);
1460 65cef780 blueswir1
    fdctrl->fifo[10] = fdctrl->config;
1461 65cef780 blueswir1
    fdctrl->fifo[11] = fdctrl->precomp_trk;
1462 65cef780 blueswir1
    fdctrl->fifo[12] = fdctrl->pwrd;
1463 65cef780 blueswir1
    fdctrl->fifo[13] = 0;
1464 65cef780 blueswir1
    fdctrl->fifo[14] = 0;
1465 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 15, 1);
1466 65cef780 blueswir1
}
1467 65cef780 blueswir1
1468 5c02c033 Blue Swirl
static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
1469 65cef780 blueswir1
{
1470 5c02c033 Blue Swirl
    FDrive *cur_drv = get_cur_drv(fdctrl);
1471 65cef780 blueswir1
1472 65cef780 blueswir1
    /* XXX: should set main status register to busy */
1473 65cef780 blueswir1
    cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1474 65cef780 blueswir1
    qemu_mod_timer(fdctrl->result_timer,
1475 74475455 Paolo Bonzini
                   qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 50));
1476 65cef780 blueswir1
}
1477 65cef780 blueswir1
1478 5c02c033 Blue Swirl
static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
1479 65cef780 blueswir1
{
1480 5c02c033 Blue Swirl
    FDrive *cur_drv;
1481 65cef780 blueswir1
1482 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1483 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1484 65cef780 blueswir1
    fdctrl->data_state |= FD_STATE_FORMAT;
1485 65cef780 blueswir1
    if (fdctrl->fifo[0] & 0x80)
1486 65cef780 blueswir1
        fdctrl->data_state |= FD_STATE_MULTI;
1487 65cef780 blueswir1
    else
1488 65cef780 blueswir1
        fdctrl->data_state &= ~FD_STATE_MULTI;
1489 65cef780 blueswir1
    fdctrl->data_state &= ~FD_STATE_SEEK;
1490 65cef780 blueswir1
    cur_drv->bps =
1491 65cef780 blueswir1
        fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1492 65cef780 blueswir1
#if 0
1493 65cef780 blueswir1
    cur_drv->last_sect =
1494 65cef780 blueswir1
        cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1495 65cef780 blueswir1
        fdctrl->fifo[3] / 2;
1496 65cef780 blueswir1
#else
1497 65cef780 blueswir1
    cur_drv->last_sect = fdctrl->fifo[3];
1498 65cef780 blueswir1
#endif
1499 65cef780 blueswir1
    /* TODO: implement format using DMA expected by the Bochs BIOS
1500 65cef780 blueswir1
     * and Linux fdformat (read 3 bytes per sector via DMA and fill
1501 65cef780 blueswir1
     * the sector with the specified fill byte
1502 65cef780 blueswir1
     */
1503 65cef780 blueswir1
    fdctrl->data_state &= ~FD_STATE_FORMAT;
1504 65cef780 blueswir1
    fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1505 65cef780 blueswir1
}
1506 65cef780 blueswir1
1507 5c02c033 Blue Swirl
static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
1508 65cef780 blueswir1
{
1509 65cef780 blueswir1
    fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1510 65cef780 blueswir1
    fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1511 368df94d blueswir1
    if (fdctrl->fifo[2] & 1)
1512 368df94d blueswir1
        fdctrl->dor &= ~FD_DOR_DMAEN;
1513 368df94d blueswir1
    else
1514 368df94d blueswir1
        fdctrl->dor |= FD_DOR_DMAEN;
1515 65cef780 blueswir1
    /* No result back */
1516 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1517 65cef780 blueswir1
}
1518 65cef780 blueswir1
1519 5c02c033 Blue Swirl
static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
1520 65cef780 blueswir1
{
1521 5c02c033 Blue Swirl
    FDrive *cur_drv;
1522 65cef780 blueswir1
1523 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1524 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1525 65cef780 blueswir1
    cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1526 65cef780 blueswir1
    /* 1 Byte status back */
1527 65cef780 blueswir1
    fdctrl->fifo[0] = (cur_drv->ro << 6) |
1528 65cef780 blueswir1
        (cur_drv->track == 0 ? 0x10 : 0x00) |
1529 65cef780 blueswir1
        (cur_drv->head << 2) |
1530 cefec4f5 blueswir1
        GET_CUR_DRV(fdctrl) |
1531 65cef780 blueswir1
        0x28;
1532 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, 0);
1533 65cef780 blueswir1
}
1534 65cef780 blueswir1
1535 5c02c033 Blue Swirl
static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
1536 65cef780 blueswir1
{
1537 5c02c033 Blue Swirl
    FDrive *cur_drv;
1538 65cef780 blueswir1
1539 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1540 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1541 65cef780 blueswir1
    fd_recalibrate(cur_drv);
1542 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1543 65cef780 blueswir1
    /* Raise Interrupt */
1544 65cef780 blueswir1
    fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1545 65cef780 blueswir1
}
1546 65cef780 blueswir1
1547 5c02c033 Blue Swirl
static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
1548 65cef780 blueswir1
{
1549 5c02c033 Blue Swirl
    FDrive *cur_drv = get_cur_drv(fdctrl);
1550 65cef780 blueswir1
1551 f2d81b33 blueswir1
    if(fdctrl->reset_sensei > 0) {
1552 f2d81b33 blueswir1
        fdctrl->fifo[0] =
1553 f2d81b33 blueswir1
            FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
1554 f2d81b33 blueswir1
        fdctrl->reset_sensei--;
1555 f2d81b33 blueswir1
    } else {
1556 f2d81b33 blueswir1
        /* XXX: status0 handling is broken for read/write
1557 f2d81b33 blueswir1
           commands, so we do this hack. It should be suppressed
1558 f2d81b33 blueswir1
           ASAP */
1559 f2d81b33 blueswir1
        fdctrl->fifo[0] =
1560 f2d81b33 blueswir1
            FD_SR0_SEEK | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1561 f2d81b33 blueswir1
    }
1562 f2d81b33 blueswir1
1563 65cef780 blueswir1
    fdctrl->fifo[1] = cur_drv->track;
1564 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 2, 0);
1565 65cef780 blueswir1
    fdctrl_reset_irq(fdctrl);
1566 77370520 blueswir1
    fdctrl->status0 = FD_SR0_RDYCHG;
1567 65cef780 blueswir1
}
1568 65cef780 blueswir1
1569 5c02c033 Blue Swirl
static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
1570 65cef780 blueswir1
{
1571 5c02c033 Blue Swirl
    FDrive *cur_drv;
1572 65cef780 blueswir1
1573 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1574 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1575 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1576 65cef780 blueswir1
    if (fdctrl->fifo[2] > cur_drv->max_track) {
1577 65cef780 blueswir1
        fdctrl_raise_irq(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK);
1578 65cef780 blueswir1
    } else {
1579 65cef780 blueswir1
        cur_drv->track = fdctrl->fifo[2];
1580 65cef780 blueswir1
        /* Raise Interrupt */
1581 65cef780 blueswir1
        fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1582 65cef780 blueswir1
    }
1583 65cef780 blueswir1
}
1584 65cef780 blueswir1
1585 5c02c033 Blue Swirl
static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
1586 65cef780 blueswir1
{
1587 5c02c033 Blue Swirl
    FDrive *cur_drv = get_cur_drv(fdctrl);
1588 65cef780 blueswir1
1589 65cef780 blueswir1
    if (fdctrl->fifo[1] & 0x80)
1590 65cef780 blueswir1
        cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1591 65cef780 blueswir1
    /* No result back */
1592 1c346df2 blueswir1
    fdctrl_reset_fifo(fdctrl);
1593 65cef780 blueswir1
}
1594 65cef780 blueswir1
1595 5c02c033 Blue Swirl
static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
1596 65cef780 blueswir1
{
1597 65cef780 blueswir1
    fdctrl->config = fdctrl->fifo[2];
1598 65cef780 blueswir1
    fdctrl->precomp_trk =  fdctrl->fifo[3];
1599 65cef780 blueswir1
    /* No result back */
1600 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1601 65cef780 blueswir1
}
1602 65cef780 blueswir1
1603 5c02c033 Blue Swirl
static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
1604 65cef780 blueswir1
{
1605 65cef780 blueswir1
    fdctrl->pwrd = fdctrl->fifo[1];
1606 65cef780 blueswir1
    fdctrl->fifo[0] = fdctrl->fifo[1];
1607 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, 1);
1608 65cef780 blueswir1
}
1609 65cef780 blueswir1
1610 5c02c033 Blue Swirl
static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
1611 65cef780 blueswir1
{
1612 65cef780 blueswir1
    /* No result back */
1613 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1614 65cef780 blueswir1
}
1615 65cef780 blueswir1
1616 5c02c033 Blue Swirl
static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
1617 65cef780 blueswir1
{
1618 5c02c033 Blue Swirl
    FDrive *cur_drv = get_cur_drv(fdctrl);
1619 65cef780 blueswir1
1620 65cef780 blueswir1
    if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1621 65cef780 blueswir1
        /* Command parameters done */
1622 65cef780 blueswir1
        if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1623 65cef780 blueswir1
            fdctrl->fifo[0] = fdctrl->fifo[1];
1624 65cef780 blueswir1
            fdctrl->fifo[2] = 0;
1625 65cef780 blueswir1
            fdctrl->fifo[3] = 0;
1626 65cef780 blueswir1
            fdctrl_set_fifo(fdctrl, 4, 1);
1627 65cef780 blueswir1
        } else {
1628 65cef780 blueswir1
            fdctrl_reset_fifo(fdctrl);
1629 65cef780 blueswir1
        }
1630 65cef780 blueswir1
    } else if (fdctrl->data_len > 7) {
1631 65cef780 blueswir1
        /* ERROR */
1632 65cef780 blueswir1
        fdctrl->fifo[0] = 0x80 |
1633 cefec4f5 blueswir1
            (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1634 65cef780 blueswir1
        fdctrl_set_fifo(fdctrl, 1, 1);
1635 65cef780 blueswir1
    }
1636 65cef780 blueswir1
}
1637 65cef780 blueswir1
1638 5c02c033 Blue Swirl
static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
1639 65cef780 blueswir1
{
1640 5c02c033 Blue Swirl
    FDrive *cur_drv;
1641 65cef780 blueswir1
1642 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1643 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1644 65cef780 blueswir1
    if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1645 65cef780 blueswir1
        cur_drv->track = cur_drv->max_track - 1;
1646 65cef780 blueswir1
    } else {
1647 65cef780 blueswir1
        cur_drv->track += fdctrl->fifo[2];
1648 65cef780 blueswir1
    }
1649 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1650 77370520 blueswir1
    /* Raise Interrupt */
1651 65cef780 blueswir1
    fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1652 65cef780 blueswir1
}
1653 65cef780 blueswir1
1654 5c02c033 Blue Swirl
static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
1655 65cef780 blueswir1
{
1656 5c02c033 Blue Swirl
    FDrive *cur_drv;
1657 65cef780 blueswir1
1658 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1659 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1660 65cef780 blueswir1
    if (fdctrl->fifo[2] > cur_drv->track) {
1661 65cef780 blueswir1
        cur_drv->track = 0;
1662 65cef780 blueswir1
    } else {
1663 65cef780 blueswir1
        cur_drv->track -= fdctrl->fifo[2];
1664 65cef780 blueswir1
    }
1665 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1666 65cef780 blueswir1
    /* Raise Interrupt */
1667 65cef780 blueswir1
    fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1668 65cef780 blueswir1
}
1669 65cef780 blueswir1
1670 678803ab blueswir1
static const struct {
1671 678803ab blueswir1
    uint8_t value;
1672 678803ab blueswir1
    uint8_t mask;
1673 678803ab blueswir1
    const char* name;
1674 678803ab blueswir1
    int parameters;
1675 5c02c033 Blue Swirl
    void (*handler)(FDCtrl *fdctrl, int direction);
1676 678803ab blueswir1
    int direction;
1677 678803ab blueswir1
} handlers[] = {
1678 678803ab blueswir1
    { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
1679 678803ab blueswir1
    { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
1680 678803ab blueswir1
    { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
1681 678803ab blueswir1
    { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
1682 678803ab blueswir1
    { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
1683 678803ab blueswir1
    { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
1684 678803ab blueswir1
    { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
1685 678803ab blueswir1
    { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
1686 678803ab blueswir1
    { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
1687 678803ab blueswir1
    { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
1688 678803ab blueswir1
    { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
1689 678803ab blueswir1
    { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented },
1690 678803ab blueswir1
    { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
1691 678803ab blueswir1
    { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
1692 678803ab blueswir1
    { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
1693 678803ab blueswir1
    { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
1694 678803ab blueswir1
    { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
1695 678803ab blueswir1
    { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
1696 678803ab blueswir1
    { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
1697 678803ab blueswir1
    { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
1698 678803ab blueswir1
    { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
1699 678803ab blueswir1
    { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
1700 678803ab blueswir1
    { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
1701 678803ab blueswir1
    { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
1702 678803ab blueswir1
    { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
1703 678803ab blueswir1
    { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
1704 678803ab blueswir1
    { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
1705 678803ab blueswir1
    { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
1706 678803ab blueswir1
    { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
1707 678803ab blueswir1
    { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
1708 678803ab blueswir1
    { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
1709 678803ab blueswir1
    { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
1710 678803ab blueswir1
};
1711 678803ab blueswir1
/* Associate command to an index in the 'handlers' array */
1712 678803ab blueswir1
static uint8_t command_to_handler[256];
1713 678803ab blueswir1
1714 5c02c033 Blue Swirl
static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
1715 baca51fa bellard
{
1716 5c02c033 Blue Swirl
    FDrive *cur_drv;
1717 65cef780 blueswir1
    int pos;
1718 baca51fa bellard
1719 8977f3c1 bellard
    /* Reset mode */
1720 1c346df2 blueswir1
    if (!(fdctrl->dor & FD_DOR_nRESET)) {
1721 4b19ec0c bellard
        FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1722 8977f3c1 bellard
        return;
1723 8977f3c1 bellard
    }
1724 b9b3d225 blueswir1
    if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
1725 b9b3d225 blueswir1
        FLOPPY_ERROR("controller not ready for writing\n");
1726 8977f3c1 bellard
        return;
1727 8977f3c1 bellard
    }
1728 b9b3d225 blueswir1
    fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1729 8977f3c1 bellard
    /* Is it write command time ? */
1730 368df94d blueswir1
    if (fdctrl->msr & FD_MSR_NONDMA) {
1731 8977f3c1 bellard
        /* FIFO data write */
1732 b3bc1540 blueswir1
        pos = fdctrl->data_pos++;
1733 b3bc1540 blueswir1
        pos %= FD_SECTOR_LEN;
1734 b3bc1540 blueswir1
        fdctrl->fifo[pos] = value;
1735 b3bc1540 blueswir1
        if (pos == FD_SECTOR_LEN - 1 ||
1736 baca51fa bellard
            fdctrl->data_pos == fdctrl->data_len) {
1737 77370520 blueswir1
            cur_drv = get_cur_drv(fdctrl);
1738 77370520 blueswir1
            if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1739 77370520 blueswir1
                FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1740 77370520 blueswir1
                return;
1741 77370520 blueswir1
            }
1742 746d6de7 blueswir1
            if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1743 746d6de7 blueswir1
                FLOPPY_DPRINTF("error seeking to next sector %d\n",
1744 746d6de7 blueswir1
                               fd_sector(cur_drv));
1745 746d6de7 blueswir1
                return;
1746 746d6de7 blueswir1
            }
1747 8977f3c1 bellard
        }
1748 890fa6be bellard
        /* Switch from transfer mode to status mode
1749 8977f3c1 bellard
         * then from status mode to command mode
1750 8977f3c1 bellard
         */
1751 b9b3d225 blueswir1
        if (fdctrl->data_pos == fdctrl->data_len)
1752 9fea808a blueswir1
            fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1753 8977f3c1 bellard
        return;
1754 8977f3c1 bellard
    }
1755 baca51fa bellard
    if (fdctrl->data_pos == 0) {
1756 8977f3c1 bellard
        /* Command */
1757 678803ab blueswir1
        pos = command_to_handler[value & 0xff];
1758 678803ab blueswir1
        FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
1759 678803ab blueswir1
        fdctrl->data_len = handlers[pos].parameters + 1;
1760 8977f3c1 bellard
    }
1761 678803ab blueswir1
1762 baca51fa bellard
    FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
1763 77370520 blueswir1
    fdctrl->fifo[fdctrl->data_pos++] = value;
1764 77370520 blueswir1
    if (fdctrl->data_pos == fdctrl->data_len) {
1765 8977f3c1 bellard
        /* We now have all parameters
1766 8977f3c1 bellard
         * and will be able to treat the command
1767 8977f3c1 bellard
         */
1768 4f431960 j_mayer
        if (fdctrl->data_state & FD_STATE_FORMAT) {
1769 4f431960 j_mayer
            fdctrl_format_sector(fdctrl);
1770 8977f3c1 bellard
            return;
1771 8977f3c1 bellard
        }
1772 65cef780 blueswir1
1773 678803ab blueswir1
        pos = command_to_handler[fdctrl->fifo[0] & 0xff];
1774 678803ab blueswir1
        FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
1775 678803ab blueswir1
        (*handlers[pos].handler)(fdctrl, handlers[pos].direction);
1776 8977f3c1 bellard
    }
1777 8977f3c1 bellard
}
1778 ed5fd2cc bellard
1779 ed5fd2cc bellard
static void fdctrl_result_timer(void *opaque)
1780 ed5fd2cc bellard
{
1781 5c02c033 Blue Swirl
    FDCtrl *fdctrl = opaque;
1782 5c02c033 Blue Swirl
    FDrive *cur_drv = get_cur_drv(fdctrl);
1783 4f431960 j_mayer
1784 b7ffa3b1 ths
    /* Pretend we are spinning.
1785 b7ffa3b1 ths
     * This is needed for Coherent, which uses READ ID to check for
1786 b7ffa3b1 ths
     * sector interleaving.
1787 b7ffa3b1 ths
     */
1788 b7ffa3b1 ths
    if (cur_drv->last_sect != 0) {
1789 b7ffa3b1 ths
        cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
1790 b7ffa3b1 ths
    }
1791 ed5fd2cc bellard
    fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1792 ed5fd2cc bellard
}
1793 678803ab blueswir1
1794 678803ab blueswir1
/* Init functions */
1795 b47b3525 Markus Armbruster
static int fdctrl_connect_drives(FDCtrl *fdctrl)
1796 678803ab blueswir1
{
1797 12a71a02 Blue Swirl
    unsigned int i;
1798 7d0d6950 Markus Armbruster
    FDrive *drive;
1799 678803ab blueswir1
1800 678803ab blueswir1
    for (i = 0; i < MAX_FD; i++) {
1801 7d0d6950 Markus Armbruster
        drive = &fdctrl->drives[i];
1802 7d0d6950 Markus Armbruster
1803 b47b3525 Markus Armbruster
        if (drive->bs) {
1804 b47b3525 Markus Armbruster
            if (bdrv_get_on_error(drive->bs, 0) != BLOCK_ERR_STOP_ENOSPC) {
1805 b47b3525 Markus Armbruster
                error_report("fdc doesn't support drive option werror");
1806 b47b3525 Markus Armbruster
                return -1;
1807 b47b3525 Markus Armbruster
            }
1808 b47b3525 Markus Armbruster
            if (bdrv_get_on_error(drive->bs, 1) != BLOCK_ERR_REPORT) {
1809 b47b3525 Markus Armbruster
                error_report("fdc doesn't support drive option rerror");
1810 b47b3525 Markus Armbruster
                return -1;
1811 b47b3525 Markus Armbruster
            }
1812 b47b3525 Markus Armbruster
        }
1813 b47b3525 Markus Armbruster
1814 7d0d6950 Markus Armbruster
        fd_init(drive);
1815 7d0d6950 Markus Armbruster
        fd_revalidate(drive);
1816 7d0d6950 Markus Armbruster
        if (drive->bs) {
1817 7d0d6950 Markus Armbruster
            bdrv_set_removable(drive->bs, 1);
1818 7d0d6950 Markus Armbruster
        }
1819 678803ab blueswir1
    }
1820 b47b3525 Markus Armbruster
    return 0;
1821 678803ab blueswir1
}
1822 678803ab blueswir1
1823 63ffb564 Blue Swirl
void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
1824 63ffb564 Blue Swirl
                        target_phys_addr_t mmio_base, DriveInfo **fds)
1825 2091ba23 Gerd Hoffmann
{
1826 5c02c033 Blue Swirl
    FDCtrl *fdctrl;
1827 2091ba23 Gerd Hoffmann
    DeviceState *dev;
1828 5c02c033 Blue Swirl
    FDCtrlSysBus *sys;
1829 2091ba23 Gerd Hoffmann
1830 2091ba23 Gerd Hoffmann
    dev = qdev_create(NULL, "sysbus-fdc");
1831 5c02c033 Blue Swirl
    sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
1832 99244fa1 Gerd Hoffmann
    fdctrl = &sys->state;
1833 99244fa1 Gerd Hoffmann
    fdctrl->dma_chann = dma_chann; /* FIXME */
1834 995bf0ca Gerd Hoffmann
    if (fds[0]) {
1835 18846dee Markus Armbruster
        qdev_prop_set_drive_nofail(dev, "driveA", fds[0]->bdrv);
1836 995bf0ca Gerd Hoffmann
    }
1837 995bf0ca Gerd Hoffmann
    if (fds[1]) {
1838 18846dee Markus Armbruster
        qdev_prop_set_drive_nofail(dev, "driveB", fds[1]->bdrv);
1839 995bf0ca Gerd Hoffmann
    }
1840 e23a1b33 Markus Armbruster
    qdev_init_nofail(dev);
1841 2091ba23 Gerd Hoffmann
    sysbus_connect_irq(&sys->busdev, 0, irq);
1842 2091ba23 Gerd Hoffmann
    sysbus_mmio_map(&sys->busdev, 0, mmio_base);
1843 678803ab blueswir1
}
1844 678803ab blueswir1
1845 63ffb564 Blue Swirl
void sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base,
1846 63ffb564 Blue Swirl
                       DriveInfo **fds, qemu_irq *fdc_tc)
1847 678803ab blueswir1
{
1848 f64ab228 Blue Swirl
    DeviceState *dev;
1849 5c02c033 Blue Swirl
    FDCtrlSysBus *sys;
1850 678803ab blueswir1
1851 12a71a02 Blue Swirl
    dev = qdev_create(NULL, "SUNW,fdtwo");
1852 995bf0ca Gerd Hoffmann
    if (fds[0]) {
1853 18846dee Markus Armbruster
        qdev_prop_set_drive_nofail(dev, "drive", fds[0]->bdrv);
1854 995bf0ca Gerd Hoffmann
    }
1855 e23a1b33 Markus Armbruster
    qdev_init_nofail(dev);
1856 5c02c033 Blue Swirl
    sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
1857 8baf73ad Gerd Hoffmann
    sysbus_connect_irq(&sys->busdev, 0, irq);
1858 8baf73ad Gerd Hoffmann
    sysbus_mmio_map(&sys->busdev, 0, io_base);
1859 f64ab228 Blue Swirl
    *fdc_tc = qdev_get_gpio_in(dev, 0);
1860 678803ab blueswir1
}
1861 f64ab228 Blue Swirl
1862 a64405d1 Jan Kiszka
static int fdctrl_init_common(FDCtrl *fdctrl)
1863 f64ab228 Blue Swirl
{
1864 12a71a02 Blue Swirl
    int i, j;
1865 12a71a02 Blue Swirl
    static int command_tables_inited = 0;
1866 f64ab228 Blue Swirl
1867 12a71a02 Blue Swirl
    /* Fill 'command_to_handler' lookup table */
1868 12a71a02 Blue Swirl
    if (!command_tables_inited) {
1869 12a71a02 Blue Swirl
        command_tables_inited = 1;
1870 12a71a02 Blue Swirl
        for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
1871 12a71a02 Blue Swirl
            for (j = 0; j < sizeof(command_to_handler); j++) {
1872 12a71a02 Blue Swirl
                if ((j & handlers[i].mask) == handlers[i].value) {
1873 12a71a02 Blue Swirl
                    command_to_handler[j] = i;
1874 12a71a02 Blue Swirl
                }
1875 12a71a02 Blue Swirl
            }
1876 12a71a02 Blue Swirl
        }
1877 12a71a02 Blue Swirl
    }
1878 12a71a02 Blue Swirl
1879 12a71a02 Blue Swirl
    FLOPPY_DPRINTF("init controller\n");
1880 12a71a02 Blue Swirl
    fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
1881 d7a6c270 Juan Quintela
    fdctrl->fifo_size = 512;
1882 74475455 Paolo Bonzini
    fdctrl->result_timer = qemu_new_timer_ns(vm_clock,
1883 12a71a02 Blue Swirl
                                          fdctrl_result_timer, fdctrl);
1884 12a71a02 Blue Swirl
1885 12a71a02 Blue Swirl
    fdctrl->version = 0x90; /* Intel 82078 controller */
1886 12a71a02 Blue Swirl
    fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
1887 d7a6c270 Juan Quintela
    fdctrl->num_floppies = MAX_FD;
1888 12a71a02 Blue Swirl
1889 99244fa1 Gerd Hoffmann
    if (fdctrl->dma_chann != -1)
1890 99244fa1 Gerd Hoffmann
        DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl);
1891 b47b3525 Markus Armbruster
    return fdctrl_connect_drives(fdctrl);
1892 f64ab228 Blue Swirl
}
1893 f64ab228 Blue Swirl
1894 81a322d4 Gerd Hoffmann
static int isabus_fdc_init1(ISADevice *dev)
1895 8baf73ad Gerd Hoffmann
{
1896 5c02c033 Blue Swirl
    FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev);
1897 5c02c033 Blue Swirl
    FDCtrl *fdctrl = &isa->state;
1898 86c86157 Gerd Hoffmann
    int iobase = 0x3f0;
1899 2e15e23b Gerd Hoffmann
    int isairq = 6;
1900 99244fa1 Gerd Hoffmann
    int dma_chann = 2;
1901 2be37833 Blue Swirl
    int ret;
1902 8baf73ad Gerd Hoffmann
1903 86c86157 Gerd Hoffmann
    register_ioport_read(iobase + 0x01, 5, 1,
1904 8baf73ad Gerd Hoffmann
                         &fdctrl_read_port, fdctrl);
1905 86c86157 Gerd Hoffmann
    register_ioport_read(iobase + 0x07, 1, 1,
1906 8baf73ad Gerd Hoffmann
                         &fdctrl_read_port, fdctrl);
1907 86c86157 Gerd Hoffmann
    register_ioport_write(iobase + 0x01, 5, 1,
1908 8baf73ad Gerd Hoffmann
                          &fdctrl_write_port, fdctrl);
1909 86c86157 Gerd Hoffmann
    register_ioport_write(iobase + 0x07, 1, 1,
1910 8baf73ad Gerd Hoffmann
                          &fdctrl_write_port, fdctrl);
1911 dee41d58 Gleb Natapov
    isa_init_ioport_range(dev, iobase, 6);
1912 dee41d58 Gleb Natapov
    isa_init_ioport(dev, iobase + 7);
1913 dee41d58 Gleb Natapov
1914 2e15e23b Gerd Hoffmann
    isa_init_irq(&isa->busdev, &fdctrl->irq, isairq);
1915 99244fa1 Gerd Hoffmann
    fdctrl->dma_chann = dma_chann;
1916 8baf73ad Gerd Hoffmann
1917 a64405d1 Jan Kiszka
    qdev_set_legacy_instance_id(&dev->qdev, iobase, 2);
1918 a64405d1 Jan Kiszka
    ret = fdctrl_init_common(fdctrl);
1919 2be37833 Blue Swirl
1920 1ca4d09a Gleb Natapov
    add_boot_device_path(isa->bootindexA, &dev->qdev, "/floppy@0");
1921 1ca4d09a Gleb Natapov
    add_boot_device_path(isa->bootindexB, &dev->qdev, "/floppy@1");
1922 1ca4d09a Gleb Natapov
1923 2be37833 Blue Swirl
    return ret;
1924 8baf73ad Gerd Hoffmann
}
1925 8baf73ad Gerd Hoffmann
1926 81a322d4 Gerd Hoffmann
static int sysbus_fdc_init1(SysBusDevice *dev)
1927 12a71a02 Blue Swirl
{
1928 5c02c033 Blue Swirl
    FDCtrlSysBus *sys = DO_UPCAST(FDCtrlSysBus, busdev, dev);
1929 5c02c033 Blue Swirl
    FDCtrl *fdctrl = &sys->state;
1930 12a71a02 Blue Swirl
    int io;
1931 2be37833 Blue Swirl
    int ret;
1932 12a71a02 Blue Swirl
1933 2507c12a Alexander Graf
    io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, fdctrl,
1934 2507c12a Alexander Graf
                                DEVICE_NATIVE_ENDIAN);
1935 8baf73ad Gerd Hoffmann
    sysbus_init_mmio(dev, 0x08, io);
1936 8baf73ad Gerd Hoffmann
    sysbus_init_irq(dev, &fdctrl->irq);
1937 8baf73ad Gerd Hoffmann
    qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
1938 99244fa1 Gerd Hoffmann
    fdctrl->dma_chann = -1;
1939 8baf73ad Gerd Hoffmann
1940 a64405d1 Jan Kiszka
    qdev_set_legacy_instance_id(&dev->qdev, io, 2);
1941 a64405d1 Jan Kiszka
    ret = fdctrl_init_common(fdctrl);
1942 2be37833 Blue Swirl
1943 2be37833 Blue Swirl
    return ret;
1944 12a71a02 Blue Swirl
}
1945 12a71a02 Blue Swirl
1946 81a322d4 Gerd Hoffmann
static int sun4m_fdc_init1(SysBusDevice *dev)
1947 12a71a02 Blue Swirl
{
1948 5c02c033 Blue Swirl
    FDCtrl *fdctrl = &(FROM_SYSBUS(FDCtrlSysBus, dev)->state);
1949 12a71a02 Blue Swirl
    int io;
1950 12a71a02 Blue Swirl
1951 12a71a02 Blue Swirl
    io = cpu_register_io_memory(fdctrl_mem_read_strict,
1952 2507c12a Alexander Graf
                                fdctrl_mem_write_strict, fdctrl,
1953 2507c12a Alexander Graf
                                DEVICE_NATIVE_ENDIAN);
1954 8baf73ad Gerd Hoffmann
    sysbus_init_mmio(dev, 0x08, io);
1955 8baf73ad Gerd Hoffmann
    sysbus_init_irq(dev, &fdctrl->irq);
1956 8baf73ad Gerd Hoffmann
    qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
1957 8baf73ad Gerd Hoffmann
1958 8baf73ad Gerd Hoffmann
    fdctrl->sun4m = 1;
1959 a64405d1 Jan Kiszka
    qdev_set_legacy_instance_id(&dev->qdev, io, 2);
1960 a64405d1 Jan Kiszka
    return fdctrl_init_common(fdctrl);
1961 12a71a02 Blue Swirl
}
1962 f64ab228 Blue Swirl
1963 a64405d1 Jan Kiszka
static const VMStateDescription vmstate_isa_fdc ={
1964 a64405d1 Jan Kiszka
    .name = "fdc",
1965 a64405d1 Jan Kiszka
    .version_id = 2,
1966 a64405d1 Jan Kiszka
    .minimum_version_id = 2,
1967 a64405d1 Jan Kiszka
    .fields = (VMStateField []) {
1968 a64405d1 Jan Kiszka
        VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
1969 a64405d1 Jan Kiszka
        VMSTATE_END_OF_LIST()
1970 a64405d1 Jan Kiszka
    }
1971 a64405d1 Jan Kiszka
};
1972 a64405d1 Jan Kiszka
1973 8baf73ad Gerd Hoffmann
static ISADeviceInfo isa_fdc_info = {
1974 8baf73ad Gerd Hoffmann
    .init = isabus_fdc_init1,
1975 8baf73ad Gerd Hoffmann
    .qdev.name  = "isa-fdc",
1976 779206de Gleb Natapov
    .qdev.fw_name  = "fdc",
1977 5c02c033 Blue Swirl
    .qdev.size  = sizeof(FDCtrlISABus),
1978 39a51dfd Markus Armbruster
    .qdev.no_user = 1,
1979 a64405d1 Jan Kiszka
    .qdev.vmsd  = &vmstate_isa_fdc,
1980 2be37833 Blue Swirl
    .qdev.reset = fdctrl_external_reset_isa,
1981 fd8014e1 Gerd Hoffmann
    .qdev.props = (Property[]) {
1982 f8b6cc00 Markus Armbruster
        DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].bs),
1983 f8b6cc00 Markus Armbruster
        DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].bs),
1984 1ca4d09a Gleb Natapov
        DEFINE_PROP_INT32("bootindexA", FDCtrlISABus, bootindexA, -1),
1985 1ca4d09a Gleb Natapov
        DEFINE_PROP_INT32("bootindexB", FDCtrlISABus, bootindexB, -1),
1986 fd8014e1 Gerd Hoffmann
        DEFINE_PROP_END_OF_LIST(),
1987 fd8014e1 Gerd Hoffmann
    },
1988 8baf73ad Gerd Hoffmann
};
1989 8baf73ad Gerd Hoffmann
1990 a64405d1 Jan Kiszka
static const VMStateDescription vmstate_sysbus_fdc ={
1991 a64405d1 Jan Kiszka
    .name = "fdc",
1992 a64405d1 Jan Kiszka
    .version_id = 2,
1993 a64405d1 Jan Kiszka
    .minimum_version_id = 2,
1994 a64405d1 Jan Kiszka
    .fields = (VMStateField []) {
1995 a64405d1 Jan Kiszka
        VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl),
1996 a64405d1 Jan Kiszka
        VMSTATE_END_OF_LIST()
1997 a64405d1 Jan Kiszka
    }
1998 a64405d1 Jan Kiszka
};
1999 a64405d1 Jan Kiszka
2000 8baf73ad Gerd Hoffmann
static SysBusDeviceInfo sysbus_fdc_info = {
2001 8baf73ad Gerd Hoffmann
    .init = sysbus_fdc_init1,
2002 8baf73ad Gerd Hoffmann
    .qdev.name  = "sysbus-fdc",
2003 5c02c033 Blue Swirl
    .qdev.size  = sizeof(FDCtrlSysBus),
2004 a64405d1 Jan Kiszka
    .qdev.vmsd  = &vmstate_sysbus_fdc,
2005 2be37833 Blue Swirl
    .qdev.reset = fdctrl_external_reset_sysbus,
2006 fd8014e1 Gerd Hoffmann
    .qdev.props = (Property[]) {
2007 f8b6cc00 Markus Armbruster
        DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].bs),
2008 f8b6cc00 Markus Armbruster
        DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].bs),
2009 fd8014e1 Gerd Hoffmann
        DEFINE_PROP_END_OF_LIST(),
2010 fd8014e1 Gerd Hoffmann
    },
2011 12a71a02 Blue Swirl
};
2012 12a71a02 Blue Swirl
2013 12a71a02 Blue Swirl
static SysBusDeviceInfo sun4m_fdc_info = {
2014 12a71a02 Blue Swirl
    .init = sun4m_fdc_init1,
2015 12a71a02 Blue Swirl
    .qdev.name  = "SUNW,fdtwo",
2016 5c02c033 Blue Swirl
    .qdev.size  = sizeof(FDCtrlSysBus),
2017 a64405d1 Jan Kiszka
    .qdev.vmsd  = &vmstate_sysbus_fdc,
2018 2be37833 Blue Swirl
    .qdev.reset = fdctrl_external_reset_sysbus,
2019 fd8014e1 Gerd Hoffmann
    .qdev.props = (Property[]) {
2020 f8b6cc00 Markus Armbruster
        DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].bs),
2021 fd8014e1 Gerd Hoffmann
        DEFINE_PROP_END_OF_LIST(),
2022 fd8014e1 Gerd Hoffmann
    },
2023 f64ab228 Blue Swirl
};
2024 f64ab228 Blue Swirl
2025 f64ab228 Blue Swirl
static void fdc_register_devices(void)
2026 f64ab228 Blue Swirl
{
2027 8baf73ad Gerd Hoffmann
    isa_qdev_register(&isa_fdc_info);
2028 8baf73ad Gerd Hoffmann
    sysbus_register_withprop(&sysbus_fdc_info);
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    sysbus_register_withprop(&sun4m_fdc_info);
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}
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2032 f64ab228 Blue Swirl
device_init(fdc_register_devices)