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1 | 2c0262af | bellard | /*
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2 | 2c0262af | bellard | * i386 micro operations
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3 | 5fafdf24 | ths | *
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4 | 2c0262af | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 2c0262af | bellard | *
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6 | 2c0262af | bellard | * This library is free software; you can redistribute it and/or
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7 | 2c0262af | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 2c0262af | bellard | * License as published by the Free Software Foundation; either
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9 | 2c0262af | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 2c0262af | bellard | *
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11 | 2c0262af | bellard | * This library is distributed in the hope that it will be useful,
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12 | 2c0262af | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 2c0262af | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 2c0262af | bellard | * Lesser General Public License for more details.
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15 | 2c0262af | bellard | *
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16 | 2c0262af | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 2c0262af | bellard | * License along with this library; if not, write to the Free Software
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18 | 2c0262af | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 2c0262af | bellard | */
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20 | f68dd770 | bellard | |
21 | f68dd770 | bellard | #define ASM_SOFTMMU
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22 | 2c0262af | bellard | #include "exec.h" |
23 | 2c0262af | bellard | |
24 | 2c0262af | bellard | /* we define the various pieces of code used by the JIT */
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25 | 2c0262af | bellard | |
26 | 2c0262af | bellard | #define REG EAX
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27 | 2c0262af | bellard | #define REGNAME _EAX
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28 | 2c0262af | bellard | #include "opreg_template.h" |
29 | 2c0262af | bellard | #undef REG
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30 | 2c0262af | bellard | #undef REGNAME
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31 | 2c0262af | bellard | |
32 | 2c0262af | bellard | #define REG ECX
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33 | 2c0262af | bellard | #define REGNAME _ECX
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34 | 2c0262af | bellard | #include "opreg_template.h" |
35 | 2c0262af | bellard | #undef REG
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36 | 2c0262af | bellard | #undef REGNAME
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37 | 2c0262af | bellard | |
38 | 2c0262af | bellard | #define REG EDX
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39 | 2c0262af | bellard | #define REGNAME _EDX
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40 | 2c0262af | bellard | #include "opreg_template.h" |
41 | 2c0262af | bellard | #undef REG
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42 | 2c0262af | bellard | #undef REGNAME
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43 | 2c0262af | bellard | |
44 | 2c0262af | bellard | #define REG EBX
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45 | 2c0262af | bellard | #define REGNAME _EBX
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46 | 2c0262af | bellard | #include "opreg_template.h" |
47 | 2c0262af | bellard | #undef REG
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48 | 2c0262af | bellard | #undef REGNAME
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49 | 2c0262af | bellard | |
50 | 2c0262af | bellard | #define REG ESP
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51 | 2c0262af | bellard | #define REGNAME _ESP
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52 | 2c0262af | bellard | #include "opreg_template.h" |
53 | 2c0262af | bellard | #undef REG
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54 | 2c0262af | bellard | #undef REGNAME
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55 | 2c0262af | bellard | |
56 | 2c0262af | bellard | #define REG EBP
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57 | 2c0262af | bellard | #define REGNAME _EBP
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58 | 2c0262af | bellard | #include "opreg_template.h" |
59 | 2c0262af | bellard | #undef REG
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60 | 2c0262af | bellard | #undef REGNAME
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61 | 2c0262af | bellard | |
62 | 2c0262af | bellard | #define REG ESI
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63 | 2c0262af | bellard | #define REGNAME _ESI
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64 | 2c0262af | bellard | #include "opreg_template.h" |
65 | 2c0262af | bellard | #undef REG
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66 | 2c0262af | bellard | #undef REGNAME
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67 | 2c0262af | bellard | |
68 | 2c0262af | bellard | #define REG EDI
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69 | 2c0262af | bellard | #define REGNAME _EDI
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70 | 2c0262af | bellard | #include "opreg_template.h" |
71 | 2c0262af | bellard | #undef REG
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72 | 2c0262af | bellard | #undef REGNAME
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73 | 2c0262af | bellard | |
74 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
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75 | 14ce26e7 | bellard | |
76 | 14ce26e7 | bellard | #define REG (env->regs[8]) |
77 | 14ce26e7 | bellard | #define REGNAME _R8
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78 | 14ce26e7 | bellard | #include "opreg_template.h" |
79 | 14ce26e7 | bellard | #undef REG
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80 | 14ce26e7 | bellard | #undef REGNAME
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81 | 14ce26e7 | bellard | |
82 | 14ce26e7 | bellard | #define REG (env->regs[9]) |
83 | 14ce26e7 | bellard | #define REGNAME _R9
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84 | 14ce26e7 | bellard | #include "opreg_template.h" |
85 | 14ce26e7 | bellard | #undef REG
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86 | 14ce26e7 | bellard | #undef REGNAME
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87 | 14ce26e7 | bellard | |
88 | 14ce26e7 | bellard | #define REG (env->regs[10]) |
89 | 14ce26e7 | bellard | #define REGNAME _R10
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90 | 14ce26e7 | bellard | #include "opreg_template.h" |
91 | 14ce26e7 | bellard | #undef REG
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92 | 14ce26e7 | bellard | #undef REGNAME
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93 | 14ce26e7 | bellard | |
94 | 14ce26e7 | bellard | #define REG (env->regs[11]) |
95 | 14ce26e7 | bellard | #define REGNAME _R11
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96 | 14ce26e7 | bellard | #include "opreg_template.h" |
97 | 14ce26e7 | bellard | #undef REG
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98 | 14ce26e7 | bellard | #undef REGNAME
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99 | 14ce26e7 | bellard | |
100 | 14ce26e7 | bellard | #define REG (env->regs[12]) |
101 | 14ce26e7 | bellard | #define REGNAME _R12
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102 | 14ce26e7 | bellard | #include "opreg_template.h" |
103 | 14ce26e7 | bellard | #undef REG
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104 | 14ce26e7 | bellard | #undef REGNAME
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105 | 14ce26e7 | bellard | |
106 | 14ce26e7 | bellard | #define REG (env->regs[13]) |
107 | 14ce26e7 | bellard | #define REGNAME _R13
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108 | 14ce26e7 | bellard | #include "opreg_template.h" |
109 | 14ce26e7 | bellard | #undef REG
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110 | 14ce26e7 | bellard | #undef REGNAME
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111 | 14ce26e7 | bellard | |
112 | 14ce26e7 | bellard | #define REG (env->regs[14]) |
113 | 14ce26e7 | bellard | #define REGNAME _R14
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114 | 14ce26e7 | bellard | #include "opreg_template.h" |
115 | 14ce26e7 | bellard | #undef REG
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116 | 14ce26e7 | bellard | #undef REGNAME
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117 | 14ce26e7 | bellard | |
118 | 14ce26e7 | bellard | #define REG (env->regs[15]) |
119 | 14ce26e7 | bellard | #define REGNAME _R15
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120 | 14ce26e7 | bellard | #include "opreg_template.h" |
121 | 14ce26e7 | bellard | #undef REG
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122 | 14ce26e7 | bellard | #undef REGNAME
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123 | 14ce26e7 | bellard | |
124 | 14ce26e7 | bellard | #endif
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125 | 14ce26e7 | bellard | |
126 | 2c0262af | bellard | /* multiply/divide */
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127 | d36cd60e | bellard | |
128 | d36cd60e | bellard | /* XXX: add eflags optimizations */
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129 | d36cd60e | bellard | /* XXX: add non P4 style flags */
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130 | d36cd60e | bellard | |
131 | 2c0262af | bellard | void OPPROTO op_mulb_AL_T0(void) |
132 | 2c0262af | bellard | { |
133 | 2c0262af | bellard | unsigned int res; |
134 | 2c0262af | bellard | res = (uint8_t)EAX * (uint8_t)T0; |
135 | 14ce26e7 | bellard | EAX = (EAX & ~0xffff) | res;
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136 | d36cd60e | bellard | CC_DST = res; |
137 | 2c0262af | bellard | CC_SRC = (res & 0xff00);
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138 | 2c0262af | bellard | } |
139 | 2c0262af | bellard | |
140 | 2c0262af | bellard | void OPPROTO op_imulb_AL_T0(void) |
141 | 2c0262af | bellard | { |
142 | 2c0262af | bellard | int res;
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143 | 2c0262af | bellard | res = (int8_t)EAX * (int8_t)T0; |
144 | 14ce26e7 | bellard | EAX = (EAX & ~0xffff) | (res & 0xffff); |
145 | d36cd60e | bellard | CC_DST = res; |
146 | 2c0262af | bellard | CC_SRC = (res != (int8_t)res); |
147 | 2c0262af | bellard | } |
148 | 2c0262af | bellard | |
149 | 2c0262af | bellard | void OPPROTO op_mulw_AX_T0(void) |
150 | 2c0262af | bellard | { |
151 | 2c0262af | bellard | unsigned int res; |
152 | 2c0262af | bellard | res = (uint16_t)EAX * (uint16_t)T0; |
153 | 14ce26e7 | bellard | EAX = (EAX & ~0xffff) | (res & 0xffff); |
154 | 14ce26e7 | bellard | EDX = (EDX & ~0xffff) | ((res >> 16) & 0xffff); |
155 | d36cd60e | bellard | CC_DST = res; |
156 | 2c0262af | bellard | CC_SRC = res >> 16;
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157 | 2c0262af | bellard | } |
158 | 2c0262af | bellard | |
159 | 2c0262af | bellard | void OPPROTO op_imulw_AX_T0(void) |
160 | 2c0262af | bellard | { |
161 | 2c0262af | bellard | int res;
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162 | 2c0262af | bellard | res = (int16_t)EAX * (int16_t)T0; |
163 | 14ce26e7 | bellard | EAX = (EAX & ~0xffff) | (res & 0xffff); |
164 | 14ce26e7 | bellard | EDX = (EDX & ~0xffff) | ((res >> 16) & 0xffff); |
165 | d36cd60e | bellard | CC_DST = res; |
166 | 2c0262af | bellard | CC_SRC = (res != (int16_t)res); |
167 | 2c0262af | bellard | } |
168 | 2c0262af | bellard | |
169 | 2c0262af | bellard | void OPPROTO op_mull_EAX_T0(void) |
170 | 2c0262af | bellard | { |
171 | 2c0262af | bellard | uint64_t res; |
172 | 2c0262af | bellard | res = (uint64_t)((uint32_t)EAX) * (uint64_t)((uint32_t)T0); |
173 | 14ce26e7 | bellard | EAX = (uint32_t)res; |
174 | 14ce26e7 | bellard | EDX = (uint32_t)(res >> 32);
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175 | 14ce26e7 | bellard | CC_DST = (uint32_t)res; |
176 | 14ce26e7 | bellard | CC_SRC = (uint32_t)(res >> 32);
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177 | 2c0262af | bellard | } |
178 | 2c0262af | bellard | |
179 | 2c0262af | bellard | void OPPROTO op_imull_EAX_T0(void) |
180 | 2c0262af | bellard | { |
181 | 2c0262af | bellard | int64_t res; |
182 | 2c0262af | bellard | res = (int64_t)((int32_t)EAX) * (int64_t)((int32_t)T0); |
183 | 31313213 | bellard | EAX = (uint32_t)(res); |
184 | 31313213 | bellard | EDX = (uint32_t)(res >> 32);
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185 | d36cd60e | bellard | CC_DST = res; |
186 | 2c0262af | bellard | CC_SRC = (res != (int32_t)res); |
187 | 2c0262af | bellard | } |
188 | 2c0262af | bellard | |
189 | 2c0262af | bellard | void OPPROTO op_imulw_T0_T1(void) |
190 | 2c0262af | bellard | { |
191 | 2c0262af | bellard | int res;
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192 | 2c0262af | bellard | res = (int16_t)T0 * (int16_t)T1; |
193 | 2c0262af | bellard | T0 = res; |
194 | d36cd60e | bellard | CC_DST = res; |
195 | 2c0262af | bellard | CC_SRC = (res != (int16_t)res); |
196 | 2c0262af | bellard | } |
197 | 2c0262af | bellard | |
198 | 2c0262af | bellard | void OPPROTO op_imull_T0_T1(void) |
199 | 2c0262af | bellard | { |
200 | 2c0262af | bellard | int64_t res; |
201 | 2c0262af | bellard | res = (int64_t)((int32_t)T0) * (int64_t)((int32_t)T1); |
202 | 2c0262af | bellard | T0 = res; |
203 | d36cd60e | bellard | CC_DST = res; |
204 | 2c0262af | bellard | CC_SRC = (res != (int32_t)res); |
205 | 2c0262af | bellard | } |
206 | 2c0262af | bellard | |
207 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
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208 | 14ce26e7 | bellard | void OPPROTO op_mulq_EAX_T0(void) |
209 | 14ce26e7 | bellard | { |
210 | b8b6a50b | bellard | helper_mulq_EAX_T0(T0); |
211 | 14ce26e7 | bellard | } |
212 | 14ce26e7 | bellard | |
213 | 14ce26e7 | bellard | void OPPROTO op_imulq_EAX_T0(void) |
214 | 14ce26e7 | bellard | { |
215 | b8b6a50b | bellard | helper_imulq_EAX_T0(T0); |
216 | 14ce26e7 | bellard | } |
217 | 14ce26e7 | bellard | |
218 | 14ce26e7 | bellard | void OPPROTO op_imulq_T0_T1(void) |
219 | 14ce26e7 | bellard | { |
220 | b8b6a50b | bellard | T0 = helper_imulq_T0_T1(T0, T1); |
221 | 14ce26e7 | bellard | } |
222 | 14ce26e7 | bellard | #endif
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223 | 14ce26e7 | bellard | |
224 | 2c0262af | bellard | /* constant load & misc op */
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225 | 2c0262af | bellard | |
226 | 14ce26e7 | bellard | /* XXX: consistent names */
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227 | 2c0262af | bellard | void OPPROTO op_into(void) |
228 | 2c0262af | bellard | { |
229 | 2c0262af | bellard | int eflags;
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230 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
231 | 2c0262af | bellard | if (eflags & CC_O) {
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232 | 2c0262af | bellard | raise_interrupt(EXCP04_INTO, 1, 0, PARAM1); |
233 | 2c0262af | bellard | } |
234 | 2c0262af | bellard | FORCE_RET(); |
235 | 2c0262af | bellard | } |
236 | 2c0262af | bellard | |
237 | 2c0262af | bellard | void OPPROTO op_cmpxchg8b(void) |
238 | 2c0262af | bellard | { |
239 | b8b6a50b | bellard | helper_cmpxchg8b(A0); |
240 | 2c0262af | bellard | } |
241 | 2c0262af | bellard | |
242 | 2c0262af | bellard | /* multiple size ops */
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243 | 2c0262af | bellard | |
244 | 2c0262af | bellard | #define ldul ldl
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245 | 2c0262af | bellard | |
246 | 2c0262af | bellard | #define SHIFT 0 |
247 | 2c0262af | bellard | #include "ops_template.h" |
248 | 2c0262af | bellard | #undef SHIFT
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249 | 2c0262af | bellard | |
250 | 2c0262af | bellard | #define SHIFT 1 |
251 | 2c0262af | bellard | #include "ops_template.h" |
252 | 2c0262af | bellard | #undef SHIFT
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253 | 2c0262af | bellard | |
254 | 2c0262af | bellard | #define SHIFT 2 |
255 | 2c0262af | bellard | #include "ops_template.h" |
256 | 2c0262af | bellard | #undef SHIFT
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257 | 2c0262af | bellard | |
258 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
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259 | 14ce26e7 | bellard | |
260 | 14ce26e7 | bellard | #define SHIFT 3 |
261 | 14ce26e7 | bellard | #include "ops_template.h" |
262 | 14ce26e7 | bellard | #undef SHIFT
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263 | 14ce26e7 | bellard | |
264 | 14ce26e7 | bellard | #endif
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265 | 14ce26e7 | bellard | |
266 | 2c0262af | bellard | /* bcd */
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267 | 2c0262af | bellard | |
268 | 2c0262af | bellard | void OPPROTO op_aam(void) |
269 | 2c0262af | bellard | { |
270 | b5b38f61 | bellard | helper_aam(PARAM1); |
271 | 2c0262af | bellard | } |
272 | 2c0262af | bellard | |
273 | 2c0262af | bellard | void OPPROTO op_aad(void) |
274 | 2c0262af | bellard | { |
275 | b5b38f61 | bellard | helper_aad(PARAM1); |
276 | 2c0262af | bellard | } |
277 | 2c0262af | bellard | |
278 | 2c0262af | bellard | void OPPROTO op_aaa(void) |
279 | 2c0262af | bellard | { |
280 | b5b38f61 | bellard | helper_aaa(); |
281 | 2c0262af | bellard | } |
282 | 2c0262af | bellard | |
283 | 2c0262af | bellard | void OPPROTO op_aas(void) |
284 | 2c0262af | bellard | { |
285 | b5b38f61 | bellard | helper_aas(); |
286 | 2c0262af | bellard | } |
287 | 2c0262af | bellard | |
288 | 2c0262af | bellard | void OPPROTO op_daa(void) |
289 | 2c0262af | bellard | { |
290 | b5b38f61 | bellard | helper_daa(); |
291 | 2c0262af | bellard | } |
292 | 2c0262af | bellard | |
293 | 2c0262af | bellard | void OPPROTO op_das(void) |
294 | 2c0262af | bellard | { |
295 | b5b38f61 | bellard | helper_das(); |
296 | 2c0262af | bellard | } |
297 | 2c0262af | bellard | |
298 | 2c0262af | bellard | /* segment handling */
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299 | 2c0262af | bellard | |
300 | 2c0262af | bellard | /* faster VM86 version */
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301 | 2c0262af | bellard | void OPPROTO op_movl_seg_T0_vm(void) |
302 | 2c0262af | bellard | { |
303 | 2c0262af | bellard | int selector;
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304 | 2c0262af | bellard | SegmentCache *sc; |
305 | 3b46e624 | ths | |
306 | 2c0262af | bellard | selector = T0 & 0xffff;
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307 | 2c0262af | bellard | /* env->segs[] access */
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308 | 2c0262af | bellard | sc = (SegmentCache *)((char *)env + PARAM1);
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309 | 2c0262af | bellard | sc->selector = selector; |
310 | 14ce26e7 | bellard | sc->base = (selector << 4);
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311 | 2c0262af | bellard | } |
312 | 2c0262af | bellard | |
313 | 2c0262af | bellard | void OPPROTO op_movl_T0_seg(void) |
314 | 2c0262af | bellard | { |
315 | 2c0262af | bellard | T0 = env->segs[PARAM1].selector; |
316 | 2c0262af | bellard | } |
317 | 2c0262af | bellard | |
318 | 2c0262af | bellard | void OPPROTO op_lsl(void) |
319 | 2c0262af | bellard | { |
320 | b8b6a50b | bellard | uint32_t val; |
321 | b8b6a50b | bellard | val = helper_lsl(T0); |
322 | b8b6a50b | bellard | if (CC_SRC & CC_Z)
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323 | b8b6a50b | bellard | T1 = val; |
324 | b8b6a50b | bellard | FORCE_RET(); |
325 | 2c0262af | bellard | } |
326 | 2c0262af | bellard | |
327 | 2c0262af | bellard | void OPPROTO op_lar(void) |
328 | 2c0262af | bellard | { |
329 | b8b6a50b | bellard | uint32_t val; |
330 | b8b6a50b | bellard | val = helper_lar(T0); |
331 | b8b6a50b | bellard | if (CC_SRC & CC_Z)
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332 | b8b6a50b | bellard | T1 = val; |
333 | b8b6a50b | bellard | FORCE_RET(); |
334 | 2c0262af | bellard | } |
335 | 2c0262af | bellard | |
336 | 3ab493de | bellard | void OPPROTO op_verr(void) |
337 | 3ab493de | bellard | { |
338 | b5b38f61 | bellard | helper_verr(T0); |
339 | 3ab493de | bellard | } |
340 | 3ab493de | bellard | |
341 | 3ab493de | bellard | void OPPROTO op_verw(void) |
342 | 3ab493de | bellard | { |
343 | b5b38f61 | bellard | helper_verw(T0); |
344 | 3ab493de | bellard | } |
345 | 3ab493de | bellard | |
346 | 3ab493de | bellard | void OPPROTO op_arpl(void) |
347 | 3ab493de | bellard | { |
348 | 3ab493de | bellard | if ((T0 & 3) < (T1 & 3)) { |
349 | 3ab493de | bellard | /* XXX: emulate bug or 0xff3f0000 oring as in bochs ? */
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350 | 3ab493de | bellard | T0 = (T0 & ~3) | (T1 & 3); |
351 | 3ab493de | bellard | T1 = CC_Z; |
352 | 3ab493de | bellard | } else {
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353 | 3ab493de | bellard | T1 = 0;
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354 | 3ab493de | bellard | } |
355 | 3ab493de | bellard | FORCE_RET(); |
356 | 3ab493de | bellard | } |
357 | 3b46e624 | ths | |
358 | 3ab493de | bellard | void OPPROTO op_arpl_update(void) |
359 | 3ab493de | bellard | { |
360 | 3ab493de | bellard | int eflags;
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361 | 3ab493de | bellard | eflags = cc_table[CC_OP].compute_all(); |
362 | 3ab493de | bellard | CC_SRC = (eflags & ~CC_Z) | T1; |
363 | 3ab493de | bellard | } |
364 | 3b46e624 | ths | |
365 | 2c0262af | bellard | void OPPROTO op_movl_T0_env(void) |
366 | 2c0262af | bellard | { |
367 | 2c0262af | bellard | T0 = *(uint32_t *)((char *)env + PARAM1);
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368 | 2c0262af | bellard | } |
369 | 2c0262af | bellard | |
370 | 2c0262af | bellard | void OPPROTO op_movl_env_T0(void) |
371 | 2c0262af | bellard | { |
372 | 2c0262af | bellard | *(uint32_t *)((char *)env + PARAM1) = T0;
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373 | 2c0262af | bellard | } |
374 | 2c0262af | bellard | |
375 | 2c0262af | bellard | void OPPROTO op_movl_env_T1(void) |
376 | 2c0262af | bellard | { |
377 | 2c0262af | bellard | *(uint32_t *)((char *)env + PARAM1) = T1;
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378 | 2c0262af | bellard | } |
379 | 2c0262af | bellard | |
380 | 14ce26e7 | bellard | void OPPROTO op_movtl_T0_env(void) |
381 | 14ce26e7 | bellard | { |
382 | 14ce26e7 | bellard | T0 = *(target_ulong *)((char *)env + PARAM1);
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383 | 14ce26e7 | bellard | } |
384 | 14ce26e7 | bellard | |
385 | 14ce26e7 | bellard | void OPPROTO op_movtl_env_T0(void) |
386 | 14ce26e7 | bellard | { |
387 | 14ce26e7 | bellard | *(target_ulong *)((char *)env + PARAM1) = T0;
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388 | 14ce26e7 | bellard | } |
389 | 14ce26e7 | bellard | |
390 | 14ce26e7 | bellard | void OPPROTO op_movtl_T1_env(void) |
391 | 14ce26e7 | bellard | { |
392 | 14ce26e7 | bellard | T1 = *(target_ulong *)((char *)env + PARAM1);
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393 | 14ce26e7 | bellard | } |
394 | 14ce26e7 | bellard | |
395 | 14ce26e7 | bellard | void OPPROTO op_movtl_env_T1(void) |
396 | 14ce26e7 | bellard | { |
397 | 14ce26e7 | bellard | *(target_ulong *)((char *)env + PARAM1) = T1;
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398 | 14ce26e7 | bellard | } |
399 | 14ce26e7 | bellard | |
400 | 2c0262af | bellard | /* flags handling */
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401 | 2c0262af | bellard | |
402 | 14ce26e7 | bellard | void OPPROTO op_jmp_label(void) |
403 | 14ce26e7 | bellard | { |
404 | 14ce26e7 | bellard | GOTO_LABEL_PARAM(1);
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405 | 2c0262af | bellard | } |
406 | 2c0262af | bellard | |
407 | 14ce26e7 | bellard | void OPPROTO op_jnz_T0_label(void) |
408 | 2c0262af | bellard | { |
409 | 2c0262af | bellard | if (T0)
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410 | 14ce26e7 | bellard | GOTO_LABEL_PARAM(1);
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411 | 39c61f49 | bellard | FORCE_RET(); |
412 | 14ce26e7 | bellard | } |
413 | 14ce26e7 | bellard | |
414 | 2c0262af | bellard | /* slow set cases (compute x86 flags) */
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415 | 2c0262af | bellard | void OPPROTO op_seto_T0_cc(void) |
416 | 2c0262af | bellard | { |
417 | 2c0262af | bellard | int eflags;
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418 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
419 | 2c0262af | bellard | T0 = (eflags >> 11) & 1; |
420 | 2c0262af | bellard | } |
421 | 2c0262af | bellard | |
422 | 2c0262af | bellard | void OPPROTO op_setb_T0_cc(void) |
423 | 2c0262af | bellard | { |
424 | 2c0262af | bellard | T0 = cc_table[CC_OP].compute_c(); |
425 | 2c0262af | bellard | } |
426 | 2c0262af | bellard | |
427 | 2c0262af | bellard | void OPPROTO op_setz_T0_cc(void) |
428 | 2c0262af | bellard | { |
429 | 2c0262af | bellard | int eflags;
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430 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
431 | 2c0262af | bellard | T0 = (eflags >> 6) & 1; |
432 | 2c0262af | bellard | } |
433 | 2c0262af | bellard | |
434 | 2c0262af | bellard | void OPPROTO op_setbe_T0_cc(void) |
435 | 2c0262af | bellard | { |
436 | 2c0262af | bellard | int eflags;
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437 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
438 | 2c0262af | bellard | T0 = (eflags & (CC_Z | CC_C)) != 0;
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439 | 2c0262af | bellard | } |
440 | 2c0262af | bellard | |
441 | 2c0262af | bellard | void OPPROTO op_sets_T0_cc(void) |
442 | 2c0262af | bellard | { |
443 | 2c0262af | bellard | int eflags;
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444 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
445 | 2c0262af | bellard | T0 = (eflags >> 7) & 1; |
446 | 2c0262af | bellard | } |
447 | 2c0262af | bellard | |
448 | 2c0262af | bellard | void OPPROTO op_setp_T0_cc(void) |
449 | 2c0262af | bellard | { |
450 | 2c0262af | bellard | int eflags;
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451 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
452 | 2c0262af | bellard | T0 = (eflags >> 2) & 1; |
453 | 2c0262af | bellard | } |
454 | 2c0262af | bellard | |
455 | 2c0262af | bellard | void OPPROTO op_setl_T0_cc(void) |
456 | 2c0262af | bellard | { |
457 | 2c0262af | bellard | int eflags;
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458 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
459 | 2c0262af | bellard | T0 = ((eflags ^ (eflags >> 4)) >> 7) & 1; |
460 | 2c0262af | bellard | } |
461 | 2c0262af | bellard | |
462 | 2c0262af | bellard | void OPPROTO op_setle_T0_cc(void) |
463 | 2c0262af | bellard | { |
464 | 2c0262af | bellard | int eflags;
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465 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
466 | 2c0262af | bellard | T0 = (((eflags ^ (eflags >> 4)) & 0x80) || (eflags & CC_Z)) != 0; |
467 | 2c0262af | bellard | } |
468 | 2c0262af | bellard | |
469 | 2c0262af | bellard | void OPPROTO op_xor_T0_1(void) |
470 | 2c0262af | bellard | { |
471 | 2c0262af | bellard | T0 ^= 1;
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472 | 2c0262af | bellard | } |
473 | 2c0262af | bellard | |
474 | 4136f33c | bellard | /* XXX: clear VIF/VIP in all ops ? */
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475 | 2c0262af | bellard | |
476 | 2c0262af | bellard | void OPPROTO op_movl_eflags_T0(void) |
477 | 2c0262af | bellard | { |
478 | 4b7aba51 | bellard | load_eflags(T0, (TF_MASK | AC_MASK | ID_MASK | NT_MASK)); |
479 | 2c0262af | bellard | } |
480 | 2c0262af | bellard | |
481 | 2c0262af | bellard | void OPPROTO op_movw_eflags_T0(void) |
482 | 2c0262af | bellard | { |
483 | 4b7aba51 | bellard | load_eflags(T0, (TF_MASK | AC_MASK | ID_MASK | NT_MASK) & 0xffff);
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484 | 4136f33c | bellard | } |
485 | 4136f33c | bellard | |
486 | 4136f33c | bellard | void OPPROTO op_movl_eflags_T0_io(void) |
487 | 4136f33c | bellard | { |
488 | 4b7aba51 | bellard | load_eflags(T0, (TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK)); |
489 | 4136f33c | bellard | } |
490 | 4136f33c | bellard | |
491 | 4136f33c | bellard | void OPPROTO op_movw_eflags_T0_io(void) |
492 | 4136f33c | bellard | { |
493 | 4b7aba51 | bellard | load_eflags(T0, (TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK) & 0xffff);
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494 | 2c0262af | bellard | } |
495 | 2c0262af | bellard | |
496 | 2c0262af | bellard | void OPPROTO op_movl_eflags_T0_cpl0(void) |
497 | 2c0262af | bellard | { |
498 | 4b7aba51 | bellard | load_eflags(T0, (TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK)); |
499 | 2c0262af | bellard | } |
500 | 2c0262af | bellard | |
501 | 2c0262af | bellard | void OPPROTO op_movw_eflags_T0_cpl0(void) |
502 | 2c0262af | bellard | { |
503 | 4b7aba51 | bellard | load_eflags(T0, (TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK) & 0xffff);
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504 | 2c0262af | bellard | } |
505 | 2c0262af | bellard | |
506 | 2c0262af | bellard | #if 0
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507 | 2c0262af | bellard | /* vm86plus version */
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508 | 2c0262af | bellard | void OPPROTO op_movw_eflags_T0_vm(void)
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509 | 2c0262af | bellard | {
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510 | 2c0262af | bellard | int eflags;
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511 | 2c0262af | bellard | eflags = T0;
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512 | 2c0262af | bellard | CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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513 | 2c0262af | bellard | DF = 1 - (2 * ((eflags >> 10) & 1));
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514 | 2c0262af | bellard | /* we also update some system flags as in user mode */
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515 | 2c0262af | bellard | env->eflags = (env->eflags & ~(FL_UPDATE_MASK16 | VIF_MASK)) |
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516 | 2c0262af | bellard | (eflags & FL_UPDATE_MASK16);
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517 | 2c0262af | bellard | if (eflags & IF_MASK) {
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518 | 2c0262af | bellard | env->eflags |= VIF_MASK;
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519 | 2c0262af | bellard | if (env->eflags & VIP_MASK) {
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520 | 2c0262af | bellard | EIP = PARAM1;
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521 | 2c0262af | bellard | raise_exception(EXCP0D_GPF);
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522 | 2c0262af | bellard | }
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523 | 2c0262af | bellard | }
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524 | 2c0262af | bellard | FORCE_RET();
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525 | 2c0262af | bellard | }
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526 | 2c0262af | bellard | |
527 | 2c0262af | bellard | void OPPROTO op_movl_eflags_T0_vm(void)
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528 | 2c0262af | bellard | {
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529 | 2c0262af | bellard | int eflags;
|
530 | 2c0262af | bellard | eflags = T0;
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531 | 2c0262af | bellard | CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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532 | 2c0262af | bellard | DF = 1 - (2 * ((eflags >> 10) & 1));
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533 | 2c0262af | bellard | /* we also update some system flags as in user mode */
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534 | 2c0262af | bellard | env->eflags = (env->eflags & ~(FL_UPDATE_MASK32 | VIF_MASK)) |
|
535 | 2c0262af | bellard | (eflags & FL_UPDATE_MASK32);
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536 | 2c0262af | bellard | if (eflags & IF_MASK) {
|
537 | 2c0262af | bellard | env->eflags |= VIF_MASK;
|
538 | 2c0262af | bellard | if (env->eflags & VIP_MASK) {
|
539 | 2c0262af | bellard | EIP = PARAM1;
|
540 | 2c0262af | bellard | raise_exception(EXCP0D_GPF);
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541 | 2c0262af | bellard | }
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542 | 2c0262af | bellard | }
|
543 | 2c0262af | bellard | FORCE_RET();
|
544 | 2c0262af | bellard | }
|
545 | 2c0262af | bellard | #endif
|
546 | 2c0262af | bellard | |
547 | 2c0262af | bellard | /* XXX: compute only O flag */
|
548 | 2c0262af | bellard | void OPPROTO op_movb_eflags_T0(void) |
549 | 2c0262af | bellard | { |
550 | 2c0262af | bellard | int of;
|
551 | 2c0262af | bellard | of = cc_table[CC_OP].compute_all() & CC_O; |
552 | 2c0262af | bellard | CC_SRC = (T0 & (CC_S | CC_Z | CC_A | CC_P | CC_C)) | of; |
553 | 2c0262af | bellard | } |
554 | 2c0262af | bellard | |
555 | 2c0262af | bellard | void OPPROTO op_movl_T0_eflags(void) |
556 | 2c0262af | bellard | { |
557 | 2c0262af | bellard | int eflags;
|
558 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
559 | 2c0262af | bellard | eflags |= (DF & DF_MASK); |
560 | 2c0262af | bellard | eflags |= env->eflags & ~(VM_MASK | RF_MASK); |
561 | 2c0262af | bellard | T0 = eflags; |
562 | 2c0262af | bellard | } |
563 | 2c0262af | bellard | |
564 | 2c0262af | bellard | /* vm86plus version */
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565 | 2c0262af | bellard | #if 0
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566 | 2c0262af | bellard | void OPPROTO op_movl_T0_eflags_vm(void)
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567 | 2c0262af | bellard | {
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568 | 2c0262af | bellard | int eflags;
|
569 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all();
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570 | 2c0262af | bellard | eflags |= (DF & DF_MASK);
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571 | 2c0262af | bellard | eflags |= env->eflags & ~(VM_MASK | RF_MASK | IF_MASK);
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572 | 2c0262af | bellard | if (env->eflags & VIF_MASK)
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573 | 2c0262af | bellard | eflags |= IF_MASK;
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574 | 2c0262af | bellard | T0 = eflags;
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575 | 2c0262af | bellard | }
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576 | 2c0262af | bellard | #endif
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577 | 2c0262af | bellard | |
578 | 2c0262af | bellard | void OPPROTO op_clc(void) |
579 | 2c0262af | bellard | { |
580 | 2c0262af | bellard | int eflags;
|
581 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
582 | 2c0262af | bellard | eflags &= ~CC_C; |
583 | 2c0262af | bellard | CC_SRC = eflags; |
584 | 2c0262af | bellard | } |
585 | 2c0262af | bellard | |
586 | 2c0262af | bellard | void OPPROTO op_stc(void) |
587 | 2c0262af | bellard | { |
588 | 2c0262af | bellard | int eflags;
|
589 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
590 | 2c0262af | bellard | eflags |= CC_C; |
591 | 2c0262af | bellard | CC_SRC = eflags; |
592 | 2c0262af | bellard | } |
593 | 2c0262af | bellard | |
594 | 2c0262af | bellard | void OPPROTO op_cmc(void) |
595 | 2c0262af | bellard | { |
596 | 2c0262af | bellard | int eflags;
|
597 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
598 | 2c0262af | bellard | eflags ^= CC_C; |
599 | 2c0262af | bellard | CC_SRC = eflags; |
600 | 2c0262af | bellard | } |
601 | 2c0262af | bellard | |
602 | 2c0262af | bellard | void OPPROTO op_salc(void) |
603 | 2c0262af | bellard | { |
604 | 2c0262af | bellard | int cf;
|
605 | 2c0262af | bellard | cf = cc_table[CC_OP].compute_c(); |
606 | 2c0262af | bellard | EAX = (EAX & ~0xff) | ((-cf) & 0xff); |
607 | 2c0262af | bellard | } |
608 | 2c0262af | bellard | |
609 | 19e6c4b8 | bellard | void OPPROTO op_fcomi_dummy(void) |
610 | 2c0262af | bellard | { |
611 | 19e6c4b8 | bellard | T0 = 0;
|
612 | 2c0262af | bellard | } |
613 | 2c0262af | bellard | |
614 | 14ce26e7 | bellard | /* SSE support */
|
615 | 5af45186 | bellard | void OPPROTO op_com_dummy(void) |
616 | 14ce26e7 | bellard | { |
617 | 5af45186 | bellard | T0 = 0;
|
618 | 664e0f19 | bellard | } |