root / tcg / hppa / tcg-target.h @ 6e0d8677
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1 | f54b3f92 | aurel32 | /*
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2 | f54b3f92 | aurel32 | * Tiny Code Generator for QEMU
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3 | f54b3f92 | aurel32 | *
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4 | f54b3f92 | aurel32 | * Copyright (c) 2008 Fabrice Bellard
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5 | f54b3f92 | aurel32 | *
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6 | f54b3f92 | aurel32 | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | f54b3f92 | aurel32 | * of this software and associated documentation files (the "Software"), to deal
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8 | f54b3f92 | aurel32 | * in the Software without restriction, including without limitation the rights
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9 | f54b3f92 | aurel32 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | f54b3f92 | aurel32 | * copies of the Software, and to permit persons to whom the Software is
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11 | f54b3f92 | aurel32 | * furnished to do so, subject to the following conditions:
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12 | f54b3f92 | aurel32 | *
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13 | f54b3f92 | aurel32 | * The above copyright notice and this permission notice shall be included in
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14 | f54b3f92 | aurel32 | * all copies or substantial portions of the Software.
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15 | f54b3f92 | aurel32 | *
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16 | f54b3f92 | aurel32 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | f54b3f92 | aurel32 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | f54b3f92 | aurel32 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | f54b3f92 | aurel32 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | f54b3f92 | aurel32 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | f54b3f92 | aurel32 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | f54b3f92 | aurel32 | * THE SOFTWARE.
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23 | f54b3f92 | aurel32 | */
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24 | f54b3f92 | aurel32 | |
25 | f54b3f92 | aurel32 | #define TCG_TARGET_HPPA 1 |
26 | f54b3f92 | aurel32 | |
27 | f54b3f92 | aurel32 | #if defined(_PA_RISC1_1)
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28 | f54b3f92 | aurel32 | #define TCG_TARGET_REG_BITS 32 |
29 | f54b3f92 | aurel32 | #else
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30 | f54b3f92 | aurel32 | #error unsupported
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31 | f54b3f92 | aurel32 | #endif
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32 | f54b3f92 | aurel32 | |
33 | f54b3f92 | aurel32 | #define TCG_TARGET_WORDS_BIGENDIAN
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34 | f54b3f92 | aurel32 | |
35 | f54b3f92 | aurel32 | #define TCG_TARGET_NB_REGS 32 |
36 | f54b3f92 | aurel32 | |
37 | f54b3f92 | aurel32 | enum {
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38 | f54b3f92 | aurel32 | TCG_REG_R0 = 0,
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39 | f54b3f92 | aurel32 | TCG_REG_R1, |
40 | f54b3f92 | aurel32 | TCG_REG_RP, |
41 | f54b3f92 | aurel32 | TCG_REG_R3, |
42 | f54b3f92 | aurel32 | TCG_REG_R4, |
43 | f54b3f92 | aurel32 | TCG_REG_R5, |
44 | f54b3f92 | aurel32 | TCG_REG_R6, |
45 | f54b3f92 | aurel32 | TCG_REG_R7, |
46 | f54b3f92 | aurel32 | TCG_REG_R8, |
47 | f54b3f92 | aurel32 | TCG_REG_R9, |
48 | f54b3f92 | aurel32 | TCG_REG_R10, |
49 | f54b3f92 | aurel32 | TCG_REG_R11, |
50 | f54b3f92 | aurel32 | TCG_REG_R12, |
51 | f54b3f92 | aurel32 | TCG_REG_R13, |
52 | f54b3f92 | aurel32 | TCG_REG_R14, |
53 | f54b3f92 | aurel32 | TCG_REG_R15, |
54 | f54b3f92 | aurel32 | TCG_REG_R16, |
55 | f54b3f92 | aurel32 | TCG_REG_R17, |
56 | f54b3f92 | aurel32 | TCG_REG_R18, |
57 | f54b3f92 | aurel32 | TCG_REG_R19, |
58 | f54b3f92 | aurel32 | TCG_REG_R20, |
59 | f54b3f92 | aurel32 | TCG_REG_R21, |
60 | f54b3f92 | aurel32 | TCG_REG_R22, |
61 | f54b3f92 | aurel32 | TCG_REG_R23, |
62 | f54b3f92 | aurel32 | TCG_REG_R24, |
63 | f54b3f92 | aurel32 | TCG_REG_R25, |
64 | f54b3f92 | aurel32 | TCG_REG_R26, |
65 | f54b3f92 | aurel32 | TCG_REG_DP, |
66 | f54b3f92 | aurel32 | TCG_REG_RET0, |
67 | f54b3f92 | aurel32 | TCG_REG_RET1, |
68 | f54b3f92 | aurel32 | TCG_REG_SP, |
69 | f54b3f92 | aurel32 | TCG_REG_R31, |
70 | f54b3f92 | aurel32 | }; |
71 | f54b3f92 | aurel32 | |
72 | f54b3f92 | aurel32 | /* used for function call generation */
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73 | f54b3f92 | aurel32 | #define TCG_REG_CALL_STACK TCG_REG_SP
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74 | f54b3f92 | aurel32 | #define TCG_TARGET_STACK_ALIGN 16 |
75 | f54b3f92 | aurel32 | #define TCG_TARGET_STACK_GROWSUP
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76 | f54b3f92 | aurel32 | |
77 | f54b3f92 | aurel32 | /* optional instructions */
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78 | f54b3f92 | aurel32 | //#define TCG_TARGET_HAS_ext8s_i32
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79 | f54b3f92 | aurel32 | //#define TCG_TARGET_HAS_ext16s_i32
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80 | f54b3f92 | aurel32 | //#define TCG_TARGET_HAS_bswap16_i32
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81 | f54b3f92 | aurel32 | //#define TCG_TARGET_HAS_bswap_i32
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82 | f54b3f92 | aurel32 | |
83 | f54b3f92 | aurel32 | /* Note: must be synced with dyngen-exec.h */
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84 | f54b3f92 | aurel32 | #define TCG_AREG0 TCG_REG_R17
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85 | f54b3f92 | aurel32 | #define TCG_AREG1 TCG_REG_R14
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86 | f54b3f92 | aurel32 | #define TCG_AREG2 TCG_REG_R15
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87 | f54b3f92 | aurel32 | #define TCG_AREG3 TCG_REG_R16
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88 | f54b3f92 | aurel32 | |
89 | f54b3f92 | aurel32 | static inline void flush_icache_range(unsigned long start, unsigned long stop) |
90 | f54b3f92 | aurel32 | { |
91 | f54b3f92 | aurel32 | start &= ~31;
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92 | f54b3f92 | aurel32 | while (start <= stop)
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93 | f54b3f92 | aurel32 | { |
94 | f54b3f92 | aurel32 | asm volatile ("fdc 0(%0)\n" |
95 | f54b3f92 | aurel32 | "sync\n"
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96 | f54b3f92 | aurel32 | "fic 0(%%sr4, %0)\n"
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97 | f54b3f92 | aurel32 | "sync\n"
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98 | f54b3f92 | aurel32 | : : "r"(start) : "memory"); |
99 | f54b3f92 | aurel32 | start += 32;
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100 | f54b3f92 | aurel32 | } |
101 | f54b3f92 | aurel32 | } |
102 | f54b3f92 | aurel32 | |
103 | f54b3f92 | aurel32 | /* supplied by libgcc */
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104 | f54b3f92 | aurel32 | extern void *__canonicalize_funcptr_for_compare(void *); |
105 | f54b3f92 | aurel32 | |
106 | f54b3f92 | aurel32 | /* Field selection types defined by hppa */
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107 | f54b3f92 | aurel32 | #define rnd(x) (((x)+0x1000)&~0x1fff) |
108 | f54b3f92 | aurel32 | /* lsel: select left 21 bits */
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109 | f54b3f92 | aurel32 | #define lsel(v,a) (((v)+(a))>>11) |
110 | f54b3f92 | aurel32 | /* rsel: select right 11 bits */
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111 | f54b3f92 | aurel32 | #define rsel(v,a) (((v)+(a))&0x7ff) |
112 | f54b3f92 | aurel32 | /* lrsel with rounding of addend to nearest 8k */
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113 | f54b3f92 | aurel32 | #define lrsel(v,a) (((v)+rnd(a))>>11) |
114 | f54b3f92 | aurel32 | /* rrsel with rounding of addend to nearest 8k */
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115 | f54b3f92 | aurel32 | #define rrsel(v,a) ((((v)+rnd(a))&0x7ff)+((a)-rnd(a))) |
116 | f54b3f92 | aurel32 | |
117 | f54b3f92 | aurel32 | #define mask(x,sz) ((x) & ~((1<<(sz))-1)) |
118 | f54b3f92 | aurel32 | |
119 | f54b3f92 | aurel32 | static inline int reassemble_12(int as12) |
120 | f54b3f92 | aurel32 | { |
121 | f54b3f92 | aurel32 | return (((as12 & 0x800) >> 11) | |
122 | f54b3f92 | aurel32 | ((as12 & 0x400) >> 8) | |
123 | f54b3f92 | aurel32 | ((as12 & 0x3ff) << 3)); |
124 | f54b3f92 | aurel32 | } |
125 | f54b3f92 | aurel32 | |
126 | f54b3f92 | aurel32 | static inline int reassemble_14(int as14) |
127 | f54b3f92 | aurel32 | { |
128 | f54b3f92 | aurel32 | return (((as14 & 0x1fff) << 1) | |
129 | f54b3f92 | aurel32 | ((as14 & 0x2000) >> 13)); |
130 | f54b3f92 | aurel32 | } |
131 | f54b3f92 | aurel32 | |
132 | f54b3f92 | aurel32 | static inline int reassemble_17(int as17) |
133 | f54b3f92 | aurel32 | { |
134 | f54b3f92 | aurel32 | return (((as17 & 0x10000) >> 16) | |
135 | f54b3f92 | aurel32 | ((as17 & 0x0f800) << 5) | |
136 | f54b3f92 | aurel32 | ((as17 & 0x00400) >> 8) | |
137 | f54b3f92 | aurel32 | ((as17 & 0x003ff) << 3)); |
138 | f54b3f92 | aurel32 | } |
139 | f54b3f92 | aurel32 | |
140 | f54b3f92 | aurel32 | static inline int reassemble_21(int as21) |
141 | f54b3f92 | aurel32 | { |
142 | f54b3f92 | aurel32 | return (((as21 & 0x100000) >> 20) | |
143 | f54b3f92 | aurel32 | ((as21 & 0x0ffe00) >> 8) | |
144 | f54b3f92 | aurel32 | ((as21 & 0x000180) << 7) | |
145 | f54b3f92 | aurel32 | ((as21 & 0x00007c) << 14) | |
146 | f54b3f92 | aurel32 | ((as21 & 0x000003) << 12)); |
147 | f54b3f92 | aurel32 | } |
148 | f54b3f92 | aurel32 | |
149 | f54b3f92 | aurel32 | static inline void hppa_patch21l(uint32_t *insn, int val, int addend) |
150 | f54b3f92 | aurel32 | { |
151 | f54b3f92 | aurel32 | val = lrsel(val, addend); |
152 | f54b3f92 | aurel32 | *insn = mask(*insn, 21) | reassemble_21(val);
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153 | f54b3f92 | aurel32 | } |
154 | f54b3f92 | aurel32 | |
155 | f54b3f92 | aurel32 | static inline void hppa_patch14r(uint32_t *insn, int val, int addend) |
156 | f54b3f92 | aurel32 | { |
157 | f54b3f92 | aurel32 | val = rrsel(val, addend); |
158 | f54b3f92 | aurel32 | *insn = mask(*insn, 14) | reassemble_14(val);
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159 | f54b3f92 | aurel32 | } |
160 | f54b3f92 | aurel32 | |
161 | f54b3f92 | aurel32 | static inline void hppa_patch17r(uint32_t *insn, int val, int addend) |
162 | f54b3f92 | aurel32 | { |
163 | f54b3f92 | aurel32 | val = rrsel(val, addend); |
164 | f54b3f92 | aurel32 | *insn = (*insn & ~0x1f1ffd) | reassemble_17(val);
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165 | f54b3f92 | aurel32 | } |
166 | f54b3f92 | aurel32 | |
167 | f54b3f92 | aurel32 | |
168 | f54b3f92 | aurel32 | static inline void hppa_patch21l_dprel(uint32_t *insn, int val, int addend) |
169 | f54b3f92 | aurel32 | { |
170 | f54b3f92 | aurel32 | register unsigned int dp asm("r27"); |
171 | f54b3f92 | aurel32 | hppa_patch21l(insn, val - dp, addend); |
172 | f54b3f92 | aurel32 | } |
173 | f54b3f92 | aurel32 | |
174 | f54b3f92 | aurel32 | static inline void hppa_patch14r_dprel(uint32_t *insn, int val, int addend) |
175 | f54b3f92 | aurel32 | { |
176 | f54b3f92 | aurel32 | register unsigned int dp asm("r27"); |
177 | f54b3f92 | aurel32 | hppa_patch14r(insn, val - dp, addend); |
178 | f54b3f92 | aurel32 | } |
179 | f54b3f92 | aurel32 | |
180 | f54b3f92 | aurel32 | static inline void hppa_patch17f(uint32_t *insn, int val, int addend) |
181 | f54b3f92 | aurel32 | { |
182 | f54b3f92 | aurel32 | int dot = (int)insn & ~0x3; |
183 | f54b3f92 | aurel32 | int v = ((val + addend) - dot - 8) / 4; |
184 | f54b3f92 | aurel32 | if (v > (1 << 16) || v < -(1 << 16)) { |
185 | f54b3f92 | aurel32 | printf("cannot fit branch to offset %d [%08x->%08x]\n", v, dot, val);
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186 | f54b3f92 | aurel32 | abort(); |
187 | f54b3f92 | aurel32 | } |
188 | f54b3f92 | aurel32 | *insn = (*insn & ~0x1f1ffd) | reassemble_17(v);
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189 | f54b3f92 | aurel32 | } |
190 | f54b3f92 | aurel32 | |
191 | f54b3f92 | aurel32 | static inline void hppa_load_imm21l(uint32_t *insn, int val, int addend) |
192 | f54b3f92 | aurel32 | { |
193 | f54b3f92 | aurel32 | /* Transform addil L'sym(%dp) to ldil L'val, %r1 */
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194 | f54b3f92 | aurel32 | *insn = 0x20200000 | reassemble_21(lrsel(val, 0)); |
195 | f54b3f92 | aurel32 | } |
196 | f54b3f92 | aurel32 | |
197 | f54b3f92 | aurel32 | static inline void hppa_load_imm14r(uint32_t *insn, int val, int addend) |
198 | f54b3f92 | aurel32 | { |
199 | f54b3f92 | aurel32 | /* Transform ldw R'sym(%r1), %rN to ldo R'sym(%r1), %rN */
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200 | f54b3f92 | aurel32 | hppa_patch14r(insn, val, addend); |
201 | f54b3f92 | aurel32 | /* HACK */
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202 | f54b3f92 | aurel32 | if (addend == 0) |
203 | f54b3f92 | aurel32 | *insn = (*insn & ~0xfc000000) | (0x0d << 26); |
204 | f54b3f92 | aurel32 | } |