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/*
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* i386 emulator main execution loop
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "config.h" |
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#include "exec.h" |
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#include "disas.h" |
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#if !defined(CONFIG_SOFTMMU)
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#undef EAX
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#undef ECX
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#undef EDX
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#undef EBX
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#undef ESP
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#undef EBP
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#undef ESI
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#undef EDI
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#undef EIP
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#include <signal.h> |
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#include <sys/ucontext.h> |
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#endif
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int tb_invalidated_flag;
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//#define DEBUG_EXEC
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//#define DEBUG_SIGNAL
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#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_M68K) || \
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defined(TARGET_ALPHA) |
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/* XXX: unify with i386 target */
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void cpu_loop_exit(void) |
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{ |
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longjmp(env->jmp_env, 1);
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} |
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#endif
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#if !(defined(TARGET_SPARC) || defined(TARGET_SH4) || defined(TARGET_M68K))
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#define reg_T2
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#endif
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/* exit the current TB from a signal handler. The host registers are
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restored in a state compatible with the CPU emulator
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*/
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void cpu_resume_from_signal(CPUState *env1, void *puc) |
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{ |
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#if !defined(CONFIG_SOFTMMU)
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struct ucontext *uc = puc;
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#endif
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env = env1; |
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/* XXX: restore cpu registers saved in host registers */
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#if !defined(CONFIG_SOFTMMU)
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if (puc) {
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/* XXX: use siglongjmp ? */
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sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
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} |
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#endif
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longjmp(env->jmp_env, 1);
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} |
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static TranslationBlock *tb_find_slow(target_ulong pc,
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target_ulong cs_base, |
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unsigned int flags) |
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{ |
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TranslationBlock *tb, **ptb1; |
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int code_gen_size;
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unsigned int h; |
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target_ulong phys_pc, phys_page1, phys_page2, virt_page2; |
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uint8_t *tc_ptr; |
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spin_lock(&tb_lock); |
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tb_invalidated_flag = 0;
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regs_to_env(); /* XXX: do it just before cpu_gen_code() */
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/* find translated block using physical mappings */
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phys_pc = get_phys_addr_code(env, pc); |
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phys_page1 = phys_pc & TARGET_PAGE_MASK; |
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phys_page2 = -1;
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h = tb_phys_hash_func(phys_pc); |
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ptb1 = &tb_phys_hash[h]; |
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for(;;) {
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tb = *ptb1; |
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if (!tb)
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goto not_found;
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if (tb->pc == pc &&
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tb->page_addr[0] == phys_page1 &&
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tb->cs_base == cs_base && |
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tb->flags == flags) { |
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/* check next page if needed */
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if (tb->page_addr[1] != -1) { |
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virt_page2 = (pc & TARGET_PAGE_MASK) + |
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TARGET_PAGE_SIZE; |
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phys_page2 = get_phys_addr_code(env, virt_page2); |
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if (tb->page_addr[1] == phys_page2) |
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goto found;
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} else {
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goto found;
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} |
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} |
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ptb1 = &tb->phys_hash_next; |
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} |
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not_found:
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/* if no translated code available, then translate it now */
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tb = tb_alloc(pc); |
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if (!tb) {
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/* flush must be done */
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tb_flush(env); |
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/* cannot fail at this point */
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tb = tb_alloc(pc); |
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/* don't forget to invalidate previous TB info */
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tb_invalidated_flag = 1;
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} |
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tc_ptr = code_gen_ptr; |
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tb->tc_ptr = tc_ptr; |
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tb->cs_base = cs_base; |
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tb->flags = flags; |
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cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size); |
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code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
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/* check next page if needed */
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virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
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phys_page2 = -1;
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if ((pc & TARGET_PAGE_MASK) != virt_page2) {
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phys_page2 = get_phys_addr_code(env, virt_page2); |
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} |
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tb_link_phys(tb, phys_pc, phys_page2); |
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found:
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/* we add the TB in the virtual pc hash table */
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env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb; |
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spin_unlock(&tb_lock); |
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return tb;
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} |
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static inline TranslationBlock *tb_find_fast(void) |
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{ |
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TranslationBlock *tb; |
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target_ulong cs_base, pc; |
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unsigned int flags; |
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/* we record a subset of the CPU state. It will
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always be the same before a given translated block
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is executed. */
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#if defined(TARGET_I386)
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flags = env->hflags; |
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flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK)); |
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cs_base = env->segs[R_CS].base; |
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pc = cs_base + env->eip; |
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#elif defined(TARGET_ARM)
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flags = env->thumb | (env->vfp.vec_len << 1)
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| (env->vfp.vec_stride << 4);
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if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
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flags |= (1 << 6); |
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if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) |
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flags |= (1 << 7); |
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cs_base = 0;
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pc = env->regs[15];
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#elif defined(TARGET_SPARC)
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#ifdef TARGET_SPARC64
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// Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
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flags = (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2)) |
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| (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
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#else
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// FPU enable . MMU enabled . MMU no-fault . Supervisor
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flags = (env->psref << 3) | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1) |
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| env->psrs; |
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#endif
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cs_base = env->npc; |
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pc = env->pc; |
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#elif defined(TARGET_PPC)
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flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) | |
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(msr_se << MSR_SE) | (msr_le << MSR_LE); |
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cs_base = 0;
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pc = env->nip; |
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#elif defined(TARGET_MIPS)
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flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK); |
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cs_base = 0;
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pc = env->PC; |
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#elif defined(TARGET_M68K)
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flags = (env->fpcr & M68K_FPCR_PREC) | (env->sr & SR_S); |
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cs_base = 0;
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pc = env->pc; |
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#elif defined(TARGET_SH4)
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flags = env->sr & (SR_MD | SR_RB); |
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cs_base = 0; /* XXXXX */ |
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pc = env->pc; |
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#elif defined(TARGET_ALPHA)
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flags = env->ps; |
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cs_base = 0;
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pc = env->pc; |
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#else
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#error unsupported CPU
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#endif
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tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)]; |
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if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
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tb->flags != flags, 0)) {
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tb = tb_find_slow(pc, cs_base, flags); |
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/* Note: we do it here to avoid a gcc bug on Mac OS X when
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doing it in tb_find_slow */
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if (tb_invalidated_flag) {
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/* as some TB could have been invalidated because
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of memory exceptions while generating the code, we
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must recompute the hash index here */
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T0 = 0;
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} |
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} |
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return tb;
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} |
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/* main execution loop */
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int cpu_exec(CPUState *env1)
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{ |
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#define DECLARE_HOST_REGS 1 |
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#include "hostregs_helper.h" |
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#if defined(TARGET_SPARC)
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#if defined(reg_REGWPTR)
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uint32_t *saved_regwptr; |
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#endif
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#endif
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#if defined(__sparc__) && !defined(HOST_SOLARIS)
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int saved_i7;
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target_ulong tmp_T0; |
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#endif
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int ret, interrupt_request;
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void (*gen_func)(void); |
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TranslationBlock *tb; |
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uint8_t *tc_ptr; |
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#if defined(TARGET_I386)
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/* handle exit of HALTED state */
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if (env1->hflags & HF_HALTED_MASK) {
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/* disable halt condition */
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if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
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(env1->eflags & IF_MASK)) { |
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env1->hflags &= ~HF_HALTED_MASK; |
257 |
} else {
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return EXCP_HALTED;
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} |
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} |
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#elif defined(TARGET_PPC)
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if (env1->halted) {
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if (env1->msr[MSR_EE] &&
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(env1->interrupt_request & CPU_INTERRUPT_HARD)) { |
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env1->halted = 0;
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} else {
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return EXCP_HALTED;
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} |
269 |
} |
270 |
#elif defined(TARGET_SPARC)
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if (env1->halted) {
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if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
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(env1->psret != 0)) {
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env1->halted = 0;
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} else {
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return EXCP_HALTED;
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} |
278 |
} |
279 |
#elif defined(TARGET_ARM)
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if (env1->halted) {
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/* An interrupt wakes the CPU even if the I and F CPSR bits are
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set. We use EXITTB to silently wake CPU without causing an
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actual interrupt. */
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if (env1->interrupt_request &
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(CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB)) { |
286 |
env1->halted = 0;
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} else {
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return EXCP_HALTED;
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} |
290 |
} |
291 |
#elif defined(TARGET_MIPS)
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if (env1->halted) {
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if (env1->interrupt_request &
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(CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) { |
295 |
env1->halted = 0;
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} else {
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297 |
return EXCP_HALTED;
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298 |
} |
299 |
} |
300 |
#elif defined(TARGET_ALPHA) || defined(TARGET_M68K)
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if (env1->halted) {
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302 |
if (env1->interrupt_request & CPU_INTERRUPT_HARD) {
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303 |
env1->halted = 0;
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} else {
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return EXCP_HALTED;
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} |
307 |
} |
308 |
#endif
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309 |
|
310 |
cpu_single_env = env1; |
311 |
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312 |
/* first we save global registers */
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#define SAVE_HOST_REGS 1 |
314 |
#include "hostregs_helper.h" |
315 |
env = env1; |
316 |
#if defined(__sparc__) && !defined(HOST_SOLARIS)
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317 |
/* we also save i7 because longjmp may not restore it */
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asm volatile ("mov %%i7, %0" : "=r" (saved_i7)); |
319 |
#endif
|
320 |
|
321 |
#if defined(TARGET_I386)
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env_to_regs(); |
323 |
/* put eflags in CPU temporary format */
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324 |
CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
325 |
DF = 1 - (2 * ((env->eflags >> 10) & 1)); |
326 |
CC_OP = CC_OP_EFLAGS; |
327 |
env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
328 |
#elif defined(TARGET_ARM)
|
329 |
#elif defined(TARGET_SPARC)
|
330 |
#if defined(reg_REGWPTR)
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331 |
saved_regwptr = REGWPTR; |
332 |
#endif
|
333 |
#elif defined(TARGET_PPC)
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334 |
#elif defined(TARGET_M68K)
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335 |
env->cc_op = CC_OP_FLAGS; |
336 |
env->cc_dest = env->sr & 0xf;
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337 |
env->cc_x = (env->sr >> 4) & 1; |
338 |
#elif defined(TARGET_MIPS)
|
339 |
#elif defined(TARGET_SH4)
|
340 |
/* XXXXX */
|
341 |
#elif defined(TARGET_ALPHA)
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342 |
env_to_regs(); |
343 |
#else
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344 |
#error unsupported target CPU
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345 |
#endif
|
346 |
env->exception_index = -1;
|
347 |
|
348 |
/* prepare setjmp context for exception handling */
|
349 |
for(;;) {
|
350 |
if (setjmp(env->jmp_env) == 0) { |
351 |
env->current_tb = NULL;
|
352 |
/* if an exception is pending, we execute it here */
|
353 |
if (env->exception_index >= 0) { |
354 |
if (env->exception_index >= EXCP_INTERRUPT) {
|
355 |
/* exit request from the cpu execution loop */
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356 |
ret = env->exception_index; |
357 |
break;
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358 |
} else if (env->user_mode_only) { |
359 |
/* if user mode only, we simulate a fake exception
|
360 |
which will be handled outside the cpu execution
|
361 |
loop */
|
362 |
#if defined(TARGET_I386)
|
363 |
do_interrupt_user(env->exception_index, |
364 |
env->exception_is_int, |
365 |
env->error_code, |
366 |
env->exception_next_eip); |
367 |
#endif
|
368 |
ret = env->exception_index; |
369 |
break;
|
370 |
} else {
|
371 |
#if defined(TARGET_I386)
|
372 |
/* simulate a real cpu exception. On i386, it can
|
373 |
trigger new exceptions, but we do not handle
|
374 |
double or triple faults yet. */
|
375 |
do_interrupt(env->exception_index, |
376 |
env->exception_is_int, |
377 |
env->error_code, |
378 |
env->exception_next_eip, 0);
|
379 |
/* successfully delivered */
|
380 |
env->old_exception = -1;
|
381 |
#elif defined(TARGET_PPC)
|
382 |
do_interrupt(env); |
383 |
#elif defined(TARGET_MIPS)
|
384 |
do_interrupt(env); |
385 |
#elif defined(TARGET_SPARC)
|
386 |
do_interrupt(env->exception_index); |
387 |
#elif defined(TARGET_ARM)
|
388 |
do_interrupt(env); |
389 |
#elif defined(TARGET_SH4)
|
390 |
do_interrupt(env); |
391 |
#elif defined(TARGET_ALPHA)
|
392 |
do_interrupt(env); |
393 |
#elif defined(TARGET_M68K)
|
394 |
do_interrupt(0);
|
395 |
#endif
|
396 |
} |
397 |
env->exception_index = -1;
|
398 |
} |
399 |
#ifdef USE_KQEMU
|
400 |
if (kqemu_is_ok(env) && env->interrupt_request == 0) { |
401 |
int ret;
|
402 |
env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
403 |
ret = kqemu_cpu_exec(env); |
404 |
/* put eflags in CPU temporary format */
|
405 |
CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
406 |
DF = 1 - (2 * ((env->eflags >> 10) & 1)); |
407 |
CC_OP = CC_OP_EFLAGS; |
408 |
env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
409 |
if (ret == 1) { |
410 |
/* exception */
|
411 |
longjmp(env->jmp_env, 1);
|
412 |
} else if (ret == 2) { |
413 |
/* softmmu execution needed */
|
414 |
} else {
|
415 |
if (env->interrupt_request != 0) { |
416 |
/* hardware interrupt will be executed just after */
|
417 |
} else {
|
418 |
/* otherwise, we restart */
|
419 |
longjmp(env->jmp_env, 1);
|
420 |
} |
421 |
} |
422 |
} |
423 |
#endif
|
424 |
|
425 |
T0 = 0; /* force lookup of first TB */ |
426 |
for(;;) {
|
427 |
#if defined(__sparc__) && !defined(HOST_SOLARIS)
|
428 |
/* g1 can be modified by some libc? functions */
|
429 |
tmp_T0 = T0; |
430 |
#endif
|
431 |
interrupt_request = env->interrupt_request; |
432 |
if (__builtin_expect(interrupt_request, 0)) { |
433 |
if (interrupt_request & CPU_INTERRUPT_DEBUG) {
|
434 |
env->interrupt_request &= ~CPU_INTERRUPT_DEBUG; |
435 |
env->exception_index = EXCP_DEBUG; |
436 |
cpu_loop_exit(); |
437 |
} |
438 |
#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
|
439 |
defined(TARGET_PPC) || defined(TARGET_ALPHA) |
440 |
if (interrupt_request & CPU_INTERRUPT_HALT) {
|
441 |
env->interrupt_request &= ~CPU_INTERRUPT_HALT; |
442 |
env->halted = 1;
|
443 |
env->exception_index = EXCP_HLT; |
444 |
cpu_loop_exit(); |
445 |
} |
446 |
#endif
|
447 |
#if defined(TARGET_I386)
|
448 |
if ((interrupt_request & CPU_INTERRUPT_SMI) &&
|
449 |
!(env->hflags & HF_SMM_MASK)) { |
450 |
env->interrupt_request &= ~CPU_INTERRUPT_SMI; |
451 |
do_smm_enter(); |
452 |
#if defined(__sparc__) && !defined(HOST_SOLARIS)
|
453 |
tmp_T0 = 0;
|
454 |
#else
|
455 |
T0 = 0;
|
456 |
#endif
|
457 |
} else if ((interrupt_request & CPU_INTERRUPT_HARD) && |
458 |
(env->eflags & IF_MASK) && |
459 |
!(env->hflags & HF_INHIBIT_IRQ_MASK)) { |
460 |
int intno;
|
461 |
env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
462 |
intno = cpu_get_pic_interrupt(env); |
463 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
464 |
fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
|
465 |
} |
466 |
do_interrupt(intno, 0, 0, 0, 1); |
467 |
/* ensure that no TB jump will be modified as
|
468 |
the program flow was changed */
|
469 |
#if defined(__sparc__) && !defined(HOST_SOLARIS)
|
470 |
tmp_T0 = 0;
|
471 |
#else
|
472 |
T0 = 0;
|
473 |
#endif
|
474 |
} |
475 |
#elif defined(TARGET_PPC)
|
476 |
#if 0
|
477 |
if ((interrupt_request & CPU_INTERRUPT_RESET)) {
|
478 |
cpu_ppc_reset(env);
|
479 |
}
|
480 |
#endif
|
481 |
if (interrupt_request & CPU_INTERRUPT_HARD) {
|
482 |
ppc_hw_interrupt(env); |
483 |
if (env->pending_interrupts == 0) |
484 |
env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
485 |
#if defined(__sparc__) && !defined(HOST_SOLARIS)
|
486 |
tmp_T0 = 0;
|
487 |
#else
|
488 |
T0 = 0;
|
489 |
#endif
|
490 |
} |
491 |
#elif defined(TARGET_MIPS)
|
492 |
if ((interrupt_request & CPU_INTERRUPT_HARD) &&
|
493 |
(env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) && |
494 |
(env->CP0_Status & (1 << CP0St_IE)) &&
|
495 |
!(env->CP0_Status & (1 << CP0St_EXL)) &&
|
496 |
!(env->CP0_Status & (1 << CP0St_ERL)) &&
|
497 |
!(env->hflags & MIPS_HFLAG_DM)) { |
498 |
/* Raise it */
|
499 |
env->exception_index = EXCP_EXT_INTERRUPT; |
500 |
env->error_code = 0;
|
501 |
do_interrupt(env); |
502 |
#if defined(__sparc__) && !defined(HOST_SOLARIS)
|
503 |
tmp_T0 = 0;
|
504 |
#else
|
505 |
T0 = 0;
|
506 |
#endif
|
507 |
} |
508 |
#elif defined(TARGET_SPARC)
|
509 |
if ((interrupt_request & CPU_INTERRUPT_HARD) &&
|
510 |
(env->psret != 0)) {
|
511 |
int pil = env->interrupt_index & 15; |
512 |
int type = env->interrupt_index & 0xf0; |
513 |
|
514 |
if (((type == TT_EXTINT) &&
|
515 |
(pil == 15 || pil > env->psrpil)) ||
|
516 |
type != TT_EXTINT) { |
517 |
env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
518 |
do_interrupt(env->interrupt_index); |
519 |
env->interrupt_index = 0;
|
520 |
#if defined(__sparc__) && !defined(HOST_SOLARIS)
|
521 |
tmp_T0 = 0;
|
522 |
#else
|
523 |
T0 = 0;
|
524 |
#endif
|
525 |
} |
526 |
} else if (interrupt_request & CPU_INTERRUPT_TIMER) { |
527 |
//do_interrupt(0, 0, 0, 0, 0);
|
528 |
env->interrupt_request &= ~CPU_INTERRUPT_TIMER; |
529 |
} |
530 |
#elif defined(TARGET_ARM)
|
531 |
if (interrupt_request & CPU_INTERRUPT_FIQ
|
532 |
&& !(env->uncached_cpsr & CPSR_F)) { |
533 |
env->exception_index = EXCP_FIQ; |
534 |
do_interrupt(env); |
535 |
} |
536 |
if (interrupt_request & CPU_INTERRUPT_HARD
|
537 |
&& !(env->uncached_cpsr & CPSR_I)) { |
538 |
env->exception_index = EXCP_IRQ; |
539 |
do_interrupt(env); |
540 |
} |
541 |
#elif defined(TARGET_SH4)
|
542 |
/* XXXXX */
|
543 |
#elif defined(TARGET_ALPHA)
|
544 |
if (interrupt_request & CPU_INTERRUPT_HARD) {
|
545 |
do_interrupt(env); |
546 |
} |
547 |
#elif defined(TARGET_M68K)
|
548 |
if (interrupt_request & CPU_INTERRUPT_HARD
|
549 |
&& ((env->sr & SR_I) >> SR_I_SHIFT) |
550 |
< env->pending_level) { |
551 |
/* Real hardware gets the interrupt vector via an
|
552 |
IACK cycle at this point. Current emulated
|
553 |
hardware doesn't rely on this, so we
|
554 |
provide/save the vector when the interrupt is
|
555 |
first signalled. */
|
556 |
env->exception_index = env->pending_vector; |
557 |
do_interrupt(1);
|
558 |
} |
559 |
#endif
|
560 |
/* Don't use the cached interupt_request value,
|
561 |
do_interrupt may have updated the EXITTB flag. */
|
562 |
if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
|
563 |
env->interrupt_request &= ~CPU_INTERRUPT_EXITTB; |
564 |
/* ensure that no TB jump will be modified as
|
565 |
the program flow was changed */
|
566 |
#if defined(__sparc__) && !defined(HOST_SOLARIS)
|
567 |
tmp_T0 = 0;
|
568 |
#else
|
569 |
T0 = 0;
|
570 |
#endif
|
571 |
} |
572 |
if (interrupt_request & CPU_INTERRUPT_EXIT) {
|
573 |
env->interrupt_request &= ~CPU_INTERRUPT_EXIT; |
574 |
env->exception_index = EXCP_INTERRUPT; |
575 |
cpu_loop_exit(); |
576 |
} |
577 |
} |
578 |
#ifdef DEBUG_EXEC
|
579 |
if ((loglevel & CPU_LOG_TB_CPU)) {
|
580 |
#if defined(TARGET_I386)
|
581 |
/* restore flags in standard format */
|
582 |
#ifdef reg_EAX
|
583 |
env->regs[R_EAX] = EAX; |
584 |
#endif
|
585 |
#ifdef reg_EBX
|
586 |
env->regs[R_EBX] = EBX; |
587 |
#endif
|
588 |
#ifdef reg_ECX
|
589 |
env->regs[R_ECX] = ECX; |
590 |
#endif
|
591 |
#ifdef reg_EDX
|
592 |
env->regs[R_EDX] = EDX; |
593 |
#endif
|
594 |
#ifdef reg_ESI
|
595 |
env->regs[R_ESI] = ESI; |
596 |
#endif
|
597 |
#ifdef reg_EDI
|
598 |
env->regs[R_EDI] = EDI; |
599 |
#endif
|
600 |
#ifdef reg_EBP
|
601 |
env->regs[R_EBP] = EBP; |
602 |
#endif
|
603 |
#ifdef reg_ESP
|
604 |
env->regs[R_ESP] = ESP; |
605 |
#endif
|
606 |
env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
607 |
cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP); |
608 |
env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
609 |
#elif defined(TARGET_ARM)
|
610 |
cpu_dump_state(env, logfile, fprintf, 0);
|
611 |
#elif defined(TARGET_SPARC)
|
612 |
REGWPTR = env->regbase + (env->cwp * 16);
|
613 |
env->regwptr = REGWPTR; |
614 |
cpu_dump_state(env, logfile, fprintf, 0);
|
615 |
#elif defined(TARGET_PPC)
|
616 |
cpu_dump_state(env, logfile, fprintf, 0);
|
617 |
#elif defined(TARGET_M68K)
|
618 |
cpu_m68k_flush_flags(env, env->cc_op); |
619 |
env->cc_op = CC_OP_FLAGS; |
620 |
env->sr = (env->sr & 0xffe0)
|
621 |
| env->cc_dest | (env->cc_x << 4);
|
622 |
cpu_dump_state(env, logfile, fprintf, 0);
|
623 |
#elif defined(TARGET_MIPS)
|
624 |
cpu_dump_state(env, logfile, fprintf, 0);
|
625 |
#elif defined(TARGET_SH4)
|
626 |
cpu_dump_state(env, logfile, fprintf, 0);
|
627 |
#elif defined(TARGET_ALPHA)
|
628 |
cpu_dump_state(env, logfile, fprintf, 0);
|
629 |
#else
|
630 |
#error unsupported target CPU
|
631 |
#endif
|
632 |
} |
633 |
#endif
|
634 |
tb = tb_find_fast(); |
635 |
#ifdef DEBUG_EXEC
|
636 |
if ((loglevel & CPU_LOG_EXEC)) {
|
637 |
fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n", |
638 |
(long)tb->tc_ptr, tb->pc,
|
639 |
lookup_symbol(tb->pc)); |
640 |
} |
641 |
#endif
|
642 |
#if defined(__sparc__) && !defined(HOST_SOLARIS)
|
643 |
T0 = tmp_T0; |
644 |
#endif
|
645 |
/* see if we can patch the calling TB. When the TB
|
646 |
spans two pages, we cannot safely do a direct
|
647 |
jump. */
|
648 |
{ |
649 |
if (T0 != 0 && |
650 |
#if USE_KQEMU
|
651 |
(env->kqemu_enabled != 2) &&
|
652 |
#endif
|
653 |
tb->page_addr[1] == -1 |
654 |
#if defined(TARGET_I386) && defined(USE_CODE_COPY)
|
655 |
&& (tb->cflags & CF_CODE_COPY) == |
656 |
(((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
|
657 |
#endif
|
658 |
) { |
659 |
spin_lock(&tb_lock); |
660 |
tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb); |
661 |
#if defined(USE_CODE_COPY)
|
662 |
/* propagates the FP use info */
|
663 |
((TranslationBlock *)(T0 & ~3))->cflags |=
|
664 |
(tb->cflags & CF_FP_USED); |
665 |
#endif
|
666 |
spin_unlock(&tb_lock); |
667 |
} |
668 |
} |
669 |
tc_ptr = tb->tc_ptr; |
670 |
env->current_tb = tb; |
671 |
/* execute the generated code */
|
672 |
gen_func = (void *)tc_ptr;
|
673 |
#if defined(__sparc__)
|
674 |
__asm__ __volatile__("call %0\n\t"
|
675 |
"mov %%o7,%%i0"
|
676 |
: /* no outputs */
|
677 |
: "r" (gen_func)
|
678 |
: "i0", "i1", "i2", "i3", "i4", "i5", |
679 |
"o0", "o1", "o2", "o3", "o4", "o5", |
680 |
"l0", "l1", "l2", "l3", "l4", "l5", |
681 |
"l6", "l7"); |
682 |
#elif defined(__arm__)
|
683 |
asm volatile ("mov pc, %0\n\t" |
684 |
".global exec_loop\n\t"
|
685 |
"exec_loop:\n\t"
|
686 |
: /* no outputs */
|
687 |
: "r" (gen_func)
|
688 |
: "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14"); |
689 |
#elif defined(TARGET_I386) && defined(USE_CODE_COPY)
|
690 |
{ |
691 |
if (!(tb->cflags & CF_CODE_COPY)) {
|
692 |
if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
|
693 |
save_native_fp_state(env); |
694 |
} |
695 |
gen_func(); |
696 |
} else {
|
697 |
if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
|
698 |
restore_native_fp_state(env); |
699 |
} |
700 |
/* we work with native eflags */
|
701 |
CC_SRC = cc_table[CC_OP].compute_all(); |
702 |
CC_OP = CC_OP_EFLAGS; |
703 |
asm(".globl exec_loop\n" |
704 |
"\n"
|
705 |
"debug1:\n"
|
706 |
" pushl %%ebp\n"
|
707 |
" fs movl %10, %9\n"
|
708 |
" fs movl %11, %%eax\n"
|
709 |
" andl $0x400, %%eax\n"
|
710 |
" fs orl %8, %%eax\n"
|
711 |
" pushl %%eax\n"
|
712 |
" popf\n"
|
713 |
" fs movl %%esp, %12\n"
|
714 |
" fs movl %0, %%eax\n"
|
715 |
" fs movl %1, %%ecx\n"
|
716 |
" fs movl %2, %%edx\n"
|
717 |
" fs movl %3, %%ebx\n"
|
718 |
" fs movl %4, %%esp\n"
|
719 |
" fs movl %5, %%ebp\n"
|
720 |
" fs movl %6, %%esi\n"
|
721 |
" fs movl %7, %%edi\n"
|
722 |
" fs jmp *%9\n"
|
723 |
"exec_loop:\n"
|
724 |
" fs movl %%esp, %4\n"
|
725 |
" fs movl %12, %%esp\n"
|
726 |
" fs movl %%eax, %0\n"
|
727 |
" fs movl %%ecx, %1\n"
|
728 |
" fs movl %%edx, %2\n"
|
729 |
" fs movl %%ebx, %3\n"
|
730 |
" fs movl %%ebp, %5\n"
|
731 |
" fs movl %%esi, %6\n"
|
732 |
" fs movl %%edi, %7\n"
|
733 |
" pushf\n"
|
734 |
" popl %%eax\n"
|
735 |
" movl %%eax, %%ecx\n"
|
736 |
" andl $0x400, %%ecx\n"
|
737 |
" shrl $9, %%ecx\n"
|
738 |
" andl $0x8d5, %%eax\n"
|
739 |
" fs movl %%eax, %8\n"
|
740 |
" movl $1, %%eax\n"
|
741 |
" subl %%ecx, %%eax\n"
|
742 |
" fs movl %%eax, %11\n"
|
743 |
" fs movl %9, %%ebx\n" /* get T0 value */ |
744 |
" popl %%ebp\n"
|
745 |
: |
746 |
: "m" (*(uint8_t *)offsetof(CPUState, regs[0])), |
747 |
"m" (*(uint8_t *)offsetof(CPUState, regs[1])), |
748 |
"m" (*(uint8_t *)offsetof(CPUState, regs[2])), |
749 |
"m" (*(uint8_t *)offsetof(CPUState, regs[3])), |
750 |
"m" (*(uint8_t *)offsetof(CPUState, regs[4])), |
751 |
"m" (*(uint8_t *)offsetof(CPUState, regs[5])), |
752 |
"m" (*(uint8_t *)offsetof(CPUState, regs[6])), |
753 |
"m" (*(uint8_t *)offsetof(CPUState, regs[7])), |
754 |
"m" (*(uint8_t *)offsetof(CPUState, cc_src)),
|
755 |
"m" (*(uint8_t *)offsetof(CPUState, tmp0)),
|
756 |
"a" (gen_func),
|
757 |
"m" (*(uint8_t *)offsetof(CPUState, df)),
|
758 |
"m" (*(uint8_t *)offsetof(CPUState, saved_esp))
|
759 |
: "%ecx", "%edx" |
760 |
); |
761 |
} |
762 |
} |
763 |
#elif defined(__ia64)
|
764 |
struct fptr {
|
765 |
void *ip;
|
766 |
void *gp;
|
767 |
} fp; |
768 |
|
769 |
fp.ip = tc_ptr; |
770 |
fp.gp = code_gen_buffer + 2 * (1 << 20); |
771 |
(*(void (*)(void)) &fp)(); |
772 |
#else
|
773 |
gen_func(); |
774 |
#endif
|
775 |
env->current_tb = NULL;
|
776 |
/* reset soft MMU for next block (it can currently
|
777 |
only be set by a memory fault) */
|
778 |
#if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
|
779 |
if (env->hflags & HF_SOFTMMU_MASK) {
|
780 |
env->hflags &= ~HF_SOFTMMU_MASK; |
781 |
/* do not allow linking to another block */
|
782 |
T0 = 0;
|
783 |
} |
784 |
#endif
|
785 |
#if defined(USE_KQEMU)
|
786 |
#define MIN_CYCLE_BEFORE_SWITCH (100 * 1000) |
787 |
if (kqemu_is_ok(env) &&
|
788 |
(cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) { |
789 |
cpu_loop_exit(); |
790 |
} |
791 |
#endif
|
792 |
} |
793 |
} else {
|
794 |
env_to_regs(); |
795 |
} |
796 |
} /* for(;;) */
|
797 |
|
798 |
|
799 |
#if defined(TARGET_I386)
|
800 |
#if defined(USE_CODE_COPY)
|
801 |
if (env->native_fp_regs) {
|
802 |
save_native_fp_state(env); |
803 |
} |
804 |
#endif
|
805 |
/* restore flags in standard format */
|
806 |
env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
807 |
#elif defined(TARGET_ARM)
|
808 |
/* XXX: Save/restore host fpu exception state?. */
|
809 |
#elif defined(TARGET_SPARC)
|
810 |
#if defined(reg_REGWPTR)
|
811 |
REGWPTR = saved_regwptr; |
812 |
#endif
|
813 |
#elif defined(TARGET_PPC)
|
814 |
#elif defined(TARGET_M68K)
|
815 |
cpu_m68k_flush_flags(env, env->cc_op); |
816 |
env->cc_op = CC_OP_FLAGS; |
817 |
env->sr = (env->sr & 0xffe0)
|
818 |
| env->cc_dest | (env->cc_x << 4);
|
819 |
#elif defined(TARGET_MIPS)
|
820 |
#elif defined(TARGET_SH4)
|
821 |
#elif defined(TARGET_ALPHA)
|
822 |
/* XXXXX */
|
823 |
#else
|
824 |
#error unsupported target CPU
|
825 |
#endif
|
826 |
|
827 |
/* restore global registers */
|
828 |
#if defined(__sparc__) && !defined(HOST_SOLARIS)
|
829 |
asm volatile ("mov %0, %%i7" : : "r" (saved_i7)); |
830 |
#endif
|
831 |
#include "hostregs_helper.h" |
832 |
|
833 |
/* fail safe : never use cpu_single_env outside cpu_exec() */
|
834 |
cpu_single_env = NULL;
|
835 |
return ret;
|
836 |
} |
837 |
|
838 |
/* must only be called from the generated code as an exception can be
|
839 |
generated */
|
840 |
void tb_invalidate_page_range(target_ulong start, target_ulong end)
|
841 |
{ |
842 |
/* XXX: cannot enable it yet because it yields to MMU exception
|
843 |
where NIP != read address on PowerPC */
|
844 |
#if 0
|
845 |
target_ulong phys_addr;
|
846 |
phys_addr = get_phys_addr_code(env, start);
|
847 |
tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
|
848 |
#endif
|
849 |
} |
850 |
|
851 |
#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
|
852 |
|
853 |
void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector) |
854 |
{ |
855 |
CPUX86State *saved_env; |
856 |
|
857 |
saved_env = env; |
858 |
env = s; |
859 |
if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { |
860 |
selector &= 0xffff;
|
861 |
cpu_x86_load_seg_cache(env, seg_reg, selector, |
862 |
(selector << 4), 0xffff, 0); |
863 |
} else {
|
864 |
load_seg(seg_reg, selector); |
865 |
} |
866 |
env = saved_env; |
867 |
} |
868 |
|
869 |
void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32) |
870 |
{ |
871 |
CPUX86State *saved_env; |
872 |
|
873 |
saved_env = env; |
874 |
env = s; |
875 |
|
876 |
helper_fsave((target_ulong)ptr, data32); |
877 |
|
878 |
env = saved_env; |
879 |
} |
880 |
|
881 |
void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32) |
882 |
{ |
883 |
CPUX86State *saved_env; |
884 |
|
885 |
saved_env = env; |
886 |
env = s; |
887 |
|
888 |
helper_frstor((target_ulong)ptr, data32); |
889 |
|
890 |
env = saved_env; |
891 |
} |
892 |
|
893 |
#endif /* TARGET_I386 */ |
894 |
|
895 |
#if !defined(CONFIG_SOFTMMU)
|
896 |
|
897 |
#if defined(TARGET_I386)
|
898 |
|
899 |
/* 'pc' is the host PC at which the exception was raised. 'address' is
|
900 |
the effective address of the memory exception. 'is_write' is 1 if a
|
901 |
write caused the exception and otherwise 0'. 'old_set' is the
|
902 |
signal set which should be restored */
|
903 |
static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
904 |
int is_write, sigset_t *old_set,
|
905 |
void *puc)
|
906 |
{ |
907 |
TranslationBlock *tb; |
908 |
int ret;
|
909 |
|
910 |
if (cpu_single_env)
|
911 |
env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
912 |
#if defined(DEBUG_SIGNAL)
|
913 |
qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
914 |
pc, address, is_write, *(unsigned long *)old_set); |
915 |
#endif
|
916 |
/* XXX: locking issue */
|
917 |
if (is_write && page_unprotect(h2g(address), pc, puc)) {
|
918 |
return 1; |
919 |
} |
920 |
|
921 |
/* see if it is an MMU fault */
|
922 |
ret = cpu_x86_handle_mmu_fault(env, address, is_write, |
923 |
((env->hflags & HF_CPL_MASK) == 3), 0); |
924 |
if (ret < 0) |
925 |
return 0; /* not an MMU fault */ |
926 |
if (ret == 0) |
927 |
return 1; /* the MMU fault was handled without causing real CPU fault */ |
928 |
/* now we have a real cpu fault */
|
929 |
tb = tb_find_pc(pc); |
930 |
if (tb) {
|
931 |
/* the PC is inside the translated code. It means that we have
|
932 |
a virtual CPU fault */
|
933 |
cpu_restore_state(tb, env, pc, puc); |
934 |
} |
935 |
if (ret == 1) { |
936 |
#if 0
|
937 |
printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
|
938 |
env->eip, env->cr[2], env->error_code);
|
939 |
#endif
|
940 |
/* we restore the process signal mask as the sigreturn should
|
941 |
do it (XXX: use sigsetjmp) */
|
942 |
sigprocmask(SIG_SETMASK, old_set, NULL);
|
943 |
raise_exception_err(env->exception_index, env->error_code); |
944 |
} else {
|
945 |
/* activate soft MMU for this block */
|
946 |
env->hflags |= HF_SOFTMMU_MASK; |
947 |
cpu_resume_from_signal(env, puc); |
948 |
} |
949 |
/* never comes here */
|
950 |
return 1; |
951 |
} |
952 |
|
953 |
#elif defined(TARGET_ARM)
|
954 |
static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
955 |
int is_write, sigset_t *old_set,
|
956 |
void *puc)
|
957 |
{ |
958 |
TranslationBlock *tb; |
959 |
int ret;
|
960 |
|
961 |
if (cpu_single_env)
|
962 |
env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
963 |
#if defined(DEBUG_SIGNAL)
|
964 |
printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
965 |
pc, address, is_write, *(unsigned long *)old_set); |
966 |
#endif
|
967 |
/* XXX: locking issue */
|
968 |
if (is_write && page_unprotect(h2g(address), pc, puc)) {
|
969 |
return 1; |
970 |
} |
971 |
/* see if it is an MMU fault */
|
972 |
ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0); |
973 |
if (ret < 0) |
974 |
return 0; /* not an MMU fault */ |
975 |
if (ret == 0) |
976 |
return 1; /* the MMU fault was handled without causing real CPU fault */ |
977 |
/* now we have a real cpu fault */
|
978 |
tb = tb_find_pc(pc); |
979 |
if (tb) {
|
980 |
/* the PC is inside the translated code. It means that we have
|
981 |
a virtual CPU fault */
|
982 |
cpu_restore_state(tb, env, pc, puc); |
983 |
} |
984 |
/* we restore the process signal mask as the sigreturn should
|
985 |
do it (XXX: use sigsetjmp) */
|
986 |
sigprocmask(SIG_SETMASK, old_set, NULL);
|
987 |
cpu_loop_exit(); |
988 |
} |
989 |
#elif defined(TARGET_SPARC)
|
990 |
static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
991 |
int is_write, sigset_t *old_set,
|
992 |
void *puc)
|
993 |
{ |
994 |
TranslationBlock *tb; |
995 |
int ret;
|
996 |
|
997 |
if (cpu_single_env)
|
998 |
env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
999 |
#if defined(DEBUG_SIGNAL)
|
1000 |
printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
1001 |
pc, address, is_write, *(unsigned long *)old_set); |
1002 |
#endif
|
1003 |
/* XXX: locking issue */
|
1004 |
if (is_write && page_unprotect(h2g(address), pc, puc)) {
|
1005 |
return 1; |
1006 |
} |
1007 |
/* see if it is an MMU fault */
|
1008 |
ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0); |
1009 |
if (ret < 0) |
1010 |
return 0; /* not an MMU fault */ |
1011 |
if (ret == 0) |
1012 |
return 1; /* the MMU fault was handled without causing real CPU fault */ |
1013 |
/* now we have a real cpu fault */
|
1014 |
tb = tb_find_pc(pc); |
1015 |
if (tb) {
|
1016 |
/* the PC is inside the translated code. It means that we have
|
1017 |
a virtual CPU fault */
|
1018 |
cpu_restore_state(tb, env, pc, puc); |
1019 |
} |
1020 |
/* we restore the process signal mask as the sigreturn should
|
1021 |
do it (XXX: use sigsetjmp) */
|
1022 |
sigprocmask(SIG_SETMASK, old_set, NULL);
|
1023 |
cpu_loop_exit(); |
1024 |
} |
1025 |
#elif defined (TARGET_PPC)
|
1026 |
static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
1027 |
int is_write, sigset_t *old_set,
|
1028 |
void *puc)
|
1029 |
{ |
1030 |
TranslationBlock *tb; |
1031 |
int ret;
|
1032 |
|
1033 |
if (cpu_single_env)
|
1034 |
env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
1035 |
#if defined(DEBUG_SIGNAL)
|
1036 |
printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
1037 |
pc, address, is_write, *(unsigned long *)old_set); |
1038 |
#endif
|
1039 |
/* XXX: locking issue */
|
1040 |
if (is_write && page_unprotect(h2g(address), pc, puc)) {
|
1041 |
return 1; |
1042 |
} |
1043 |
|
1044 |
/* see if it is an MMU fault */
|
1045 |
ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
|
1046 |
if (ret < 0) |
1047 |
return 0; /* not an MMU fault */ |
1048 |
if (ret == 0) |
1049 |
return 1; /* the MMU fault was handled without causing real CPU fault */ |
1050 |
|
1051 |
/* now we have a real cpu fault */
|
1052 |
tb = tb_find_pc(pc); |
1053 |
if (tb) {
|
1054 |
/* the PC is inside the translated code. It means that we have
|
1055 |
a virtual CPU fault */
|
1056 |
cpu_restore_state(tb, env, pc, puc); |
1057 |
} |
1058 |
if (ret == 1) { |
1059 |
#if 0
|
1060 |
printf("PF exception: NIP=0x%08x error=0x%x %p\n",
|
1061 |
env->nip, env->error_code, tb);
|
1062 |
#endif
|
1063 |
/* we restore the process signal mask as the sigreturn should
|
1064 |
do it (XXX: use sigsetjmp) */
|
1065 |
sigprocmask(SIG_SETMASK, old_set, NULL);
|
1066 |
do_raise_exception_err(env->exception_index, env->error_code); |
1067 |
} else {
|
1068 |
/* activate soft MMU for this block */
|
1069 |
cpu_resume_from_signal(env, puc); |
1070 |
} |
1071 |
/* never comes here */
|
1072 |
return 1; |
1073 |
} |
1074 |
|
1075 |
#elif defined(TARGET_M68K)
|
1076 |
static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
1077 |
int is_write, sigset_t *old_set,
|
1078 |
void *puc)
|
1079 |
{ |
1080 |
TranslationBlock *tb; |
1081 |
int ret;
|
1082 |
|
1083 |
if (cpu_single_env)
|
1084 |
env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
1085 |
#if defined(DEBUG_SIGNAL)
|
1086 |
printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
1087 |
pc, address, is_write, *(unsigned long *)old_set); |
1088 |
#endif
|
1089 |
/* XXX: locking issue */
|
1090 |
if (is_write && page_unprotect(address, pc, puc)) {
|
1091 |
return 1; |
1092 |
} |
1093 |
/* see if it is an MMU fault */
|
1094 |
ret = cpu_m68k_handle_mmu_fault(env, address, is_write, 1, 0); |
1095 |
if (ret < 0) |
1096 |
return 0; /* not an MMU fault */ |
1097 |
if (ret == 0) |
1098 |
return 1; /* the MMU fault was handled without causing real CPU fault */ |
1099 |
/* now we have a real cpu fault */
|
1100 |
tb = tb_find_pc(pc); |
1101 |
if (tb) {
|
1102 |
/* the PC is inside the translated code. It means that we have
|
1103 |
a virtual CPU fault */
|
1104 |
cpu_restore_state(tb, env, pc, puc); |
1105 |
} |
1106 |
/* we restore the process signal mask as the sigreturn should
|
1107 |
do it (XXX: use sigsetjmp) */
|
1108 |
sigprocmask(SIG_SETMASK, old_set, NULL);
|
1109 |
cpu_loop_exit(); |
1110 |
/* never comes here */
|
1111 |
return 1; |
1112 |
} |
1113 |
|
1114 |
#elif defined (TARGET_MIPS)
|
1115 |
static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
1116 |
int is_write, sigset_t *old_set,
|
1117 |
void *puc)
|
1118 |
{ |
1119 |
TranslationBlock *tb; |
1120 |
int ret;
|
1121 |
|
1122 |
if (cpu_single_env)
|
1123 |
env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
1124 |
#if defined(DEBUG_SIGNAL)
|
1125 |
printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
1126 |
pc, address, is_write, *(unsigned long *)old_set); |
1127 |
#endif
|
1128 |
/* XXX: locking issue */
|
1129 |
if (is_write && page_unprotect(h2g(address), pc, puc)) {
|
1130 |
return 1; |
1131 |
} |
1132 |
|
1133 |
/* see if it is an MMU fault */
|
1134 |
ret = cpu_mips_handle_mmu_fault(env, address, is_write, 1, 0); |
1135 |
if (ret < 0) |
1136 |
return 0; /* not an MMU fault */ |
1137 |
if (ret == 0) |
1138 |
return 1; /* the MMU fault was handled without causing real CPU fault */ |
1139 |
|
1140 |
/* now we have a real cpu fault */
|
1141 |
tb = tb_find_pc(pc); |
1142 |
if (tb) {
|
1143 |
/* the PC is inside the translated code. It means that we have
|
1144 |
a virtual CPU fault */
|
1145 |
cpu_restore_state(tb, env, pc, puc); |
1146 |
} |
1147 |
if (ret == 1) { |
1148 |
#if 0
|
1149 |
printf("PF exception: PC=0x" TARGET_FMT_lx " error=0x%x %p\n",
|
1150 |
env->PC, env->error_code, tb);
|
1151 |
#endif
|
1152 |
/* we restore the process signal mask as the sigreturn should
|
1153 |
do it (XXX: use sigsetjmp) */
|
1154 |
sigprocmask(SIG_SETMASK, old_set, NULL);
|
1155 |
do_raise_exception_err(env->exception_index, env->error_code); |
1156 |
} else {
|
1157 |
/* activate soft MMU for this block */
|
1158 |
cpu_resume_from_signal(env, puc); |
1159 |
} |
1160 |
/* never comes here */
|
1161 |
return 1; |
1162 |
} |
1163 |
|
1164 |
#elif defined (TARGET_SH4)
|
1165 |
static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
1166 |
int is_write, sigset_t *old_set,
|
1167 |
void *puc)
|
1168 |
{ |
1169 |
TranslationBlock *tb; |
1170 |
int ret;
|
1171 |
|
1172 |
if (cpu_single_env)
|
1173 |
env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
1174 |
#if defined(DEBUG_SIGNAL)
|
1175 |
printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
1176 |
pc, address, is_write, *(unsigned long *)old_set); |
1177 |
#endif
|
1178 |
/* XXX: locking issue */
|
1179 |
if (is_write && page_unprotect(h2g(address), pc, puc)) {
|
1180 |
return 1; |
1181 |
} |
1182 |
|
1183 |
/* see if it is an MMU fault */
|
1184 |
ret = cpu_sh4_handle_mmu_fault(env, address, is_write, 1, 0); |
1185 |
if (ret < 0) |
1186 |
return 0; /* not an MMU fault */ |
1187 |
if (ret == 0) |
1188 |
return 1; /* the MMU fault was handled without causing real CPU fault */ |
1189 |
|
1190 |
/* now we have a real cpu fault */
|
1191 |
tb = tb_find_pc(pc); |
1192 |
if (tb) {
|
1193 |
/* the PC is inside the translated code. It means that we have
|
1194 |
a virtual CPU fault */
|
1195 |
cpu_restore_state(tb, env, pc, puc); |
1196 |
} |
1197 |
#if 0
|
1198 |
printf("PF exception: NIP=0x%08x error=0x%x %p\n",
|
1199 |
env->nip, env->error_code, tb);
|
1200 |
#endif
|
1201 |
/* we restore the process signal mask as the sigreturn should
|
1202 |
do it (XXX: use sigsetjmp) */
|
1203 |
sigprocmask(SIG_SETMASK, old_set, NULL);
|
1204 |
cpu_loop_exit(); |
1205 |
/* never comes here */
|
1206 |
return 1; |
1207 |
} |
1208 |
|
1209 |
#elif defined (TARGET_ALPHA)
|
1210 |
static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
1211 |
int is_write, sigset_t *old_set,
|
1212 |
void *puc)
|
1213 |
{ |
1214 |
TranslationBlock *tb; |
1215 |
int ret;
|
1216 |
|
1217 |
if (cpu_single_env)
|
1218 |
env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
1219 |
#if defined(DEBUG_SIGNAL)
|
1220 |
printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
1221 |
pc, address, is_write, *(unsigned long *)old_set); |
1222 |
#endif
|
1223 |
/* XXX: locking issue */
|
1224 |
if (is_write && page_unprotect(h2g(address), pc, puc)) {
|
1225 |
return 1; |
1226 |
} |
1227 |
|
1228 |
/* see if it is an MMU fault */
|
1229 |
ret = cpu_alpha_handle_mmu_fault(env, address, is_write, 1, 0); |
1230 |
if (ret < 0) |
1231 |
return 0; /* not an MMU fault */ |
1232 |
if (ret == 0) |
1233 |
return 1; /* the MMU fault was handled without causing real CPU fault */ |
1234 |
|
1235 |
/* now we have a real cpu fault */
|
1236 |
tb = tb_find_pc(pc); |
1237 |
if (tb) {
|
1238 |
/* the PC is inside the translated code. It means that we have
|
1239 |
a virtual CPU fault */
|
1240 |
cpu_restore_state(tb, env, pc, puc); |
1241 |
} |
1242 |
#if 0
|
1243 |
printf("PF exception: NIP=0x%08x error=0x%x %p\n",
|
1244 |
env->nip, env->error_code, tb);
|
1245 |
#endif
|
1246 |
/* we restore the process signal mask as the sigreturn should
|
1247 |
do it (XXX: use sigsetjmp) */
|
1248 |
sigprocmask(SIG_SETMASK, old_set, NULL);
|
1249 |
cpu_loop_exit(); |
1250 |
/* never comes here */
|
1251 |
return 1; |
1252 |
} |
1253 |
#else
|
1254 |
#error unsupported target CPU
|
1255 |
#endif
|
1256 |
|
1257 |
#if defined(__i386__)
|
1258 |
|
1259 |
#if defined(__APPLE__)
|
1260 |
# include <sys/ucontext.h> |
1261 |
|
1262 |
# define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip)) |
1263 |
# define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
|
1264 |
# define ERROR_sig(context) ((context)->uc_mcontext->es.err)
|
1265 |
#else
|
1266 |
# define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
|
1267 |
# define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
|
1268 |
# define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
|
1269 |
#endif
|
1270 |
|
1271 |
#if defined(USE_CODE_COPY)
|
1272 |
static void cpu_send_trap(unsigned long pc, int trap, |
1273 |
struct ucontext *uc)
|
1274 |
{ |
1275 |
TranslationBlock *tb; |
1276 |
|
1277 |
if (cpu_single_env)
|
1278 |
env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
1279 |
/* now we have a real cpu fault */
|
1280 |
tb = tb_find_pc(pc); |
1281 |
if (tb) {
|
1282 |
/* the PC is inside the translated code. It means that we have
|
1283 |
a virtual CPU fault */
|
1284 |
cpu_restore_state(tb, env, pc, uc); |
1285 |
} |
1286 |
sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
|
1287 |
raise_exception_err(trap, env->error_code); |
1288 |
} |
1289 |
#endif
|
1290 |
|
1291 |
int cpu_signal_handler(int host_signum, void *pinfo, |
1292 |
void *puc)
|
1293 |
{ |
1294 |
siginfo_t *info = pinfo; |
1295 |
struct ucontext *uc = puc;
|
1296 |
unsigned long pc; |
1297 |
int trapno;
|
1298 |
|
1299 |
#ifndef REG_EIP
|
1300 |
/* for glibc 2.1 */
|
1301 |
#define REG_EIP EIP
|
1302 |
#define REG_ERR ERR
|
1303 |
#define REG_TRAPNO TRAPNO
|
1304 |
#endif
|
1305 |
pc = EIP_sig(uc); |
1306 |
trapno = TRAP_sig(uc); |
1307 |
#if defined(TARGET_I386) && defined(USE_CODE_COPY)
|
1308 |
if (trapno == 0x00 || trapno == 0x05) { |
1309 |
/* send division by zero or bound exception */
|
1310 |
cpu_send_trap(pc, trapno, uc); |
1311 |
return 1; |
1312 |
} else
|
1313 |
#endif
|
1314 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1315 |
trapno == 0xe ?
|
1316 |
(ERROR_sig(uc) >> 1) & 1 : 0, |
1317 |
&uc->uc_sigmask, puc); |
1318 |
} |
1319 |
|
1320 |
#elif defined(__x86_64__)
|
1321 |
|
1322 |
int cpu_signal_handler(int host_signum, void *pinfo, |
1323 |
void *puc)
|
1324 |
{ |
1325 |
siginfo_t *info = pinfo; |
1326 |
struct ucontext *uc = puc;
|
1327 |
unsigned long pc; |
1328 |
|
1329 |
pc = uc->uc_mcontext.gregs[REG_RIP]; |
1330 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1331 |
uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
|
1332 |
(uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, |
1333 |
&uc->uc_sigmask, puc); |
1334 |
} |
1335 |
|
1336 |
#elif defined(__powerpc__)
|
1337 |
|
1338 |
/***********************************************************************
|
1339 |
* signal context platform-specific definitions
|
1340 |
* From Wine
|
1341 |
*/
|
1342 |
#ifdef linux
|
1343 |
/* All Registers access - only for local access */
|
1344 |
# define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
|
1345 |
/* Gpr Registers access */
|
1346 |
# define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
|
1347 |
# define IAR_sig(context) REG_sig(nip, context) /* Program counter */ |
1348 |
# define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */ |
1349 |
# define CTR_sig(context) REG_sig(ctr, context) /* Count register */ |
1350 |
# define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */ |
1351 |
# define LR_sig(context) REG_sig(link, context) /* Link register */ |
1352 |
# define CR_sig(context) REG_sig(ccr, context) /* Condition register */ |
1353 |
/* Float Registers access */
|
1354 |
# define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num]) |
1355 |
# define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4))) |
1356 |
/* Exception Registers access */
|
1357 |
# define DAR_sig(context) REG_sig(dar, context)
|
1358 |
# define DSISR_sig(context) REG_sig(dsisr, context)
|
1359 |
# define TRAP_sig(context) REG_sig(trap, context)
|
1360 |
#endif /* linux */ |
1361 |
|
1362 |
#ifdef __APPLE__
|
1363 |
# include <sys/ucontext.h> |
1364 |
typedef struct ucontext SIGCONTEXT; |
1365 |
/* All Registers access - only for local access */
|
1366 |
# define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
|
1367 |
# define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
|
1368 |
# define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
|
1369 |
# define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
|
1370 |
/* Gpr Registers access */
|
1371 |
# define GPR_sig(reg_num, context) REG_sig(r##reg_num, context) |
1372 |
# define IAR_sig(context) REG_sig(srr0, context) /* Program counter */ |
1373 |
# define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */ |
1374 |
# define CTR_sig(context) REG_sig(ctr, context)
|
1375 |
# define XER_sig(context) REG_sig(xer, context) /* Link register */ |
1376 |
# define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */ |
1377 |
# define CR_sig(context) REG_sig(cr, context) /* Condition register */ |
1378 |
/* Float Registers access */
|
1379 |
# define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
|
1380 |
# define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context)) |
1381 |
/* Exception Registers access */
|
1382 |
# define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */ |
1383 |
# define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
|
1384 |
# define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */ |
1385 |
#endif /* __APPLE__ */ |
1386 |
|
1387 |
int cpu_signal_handler(int host_signum, void *pinfo, |
1388 |
void *puc)
|
1389 |
{ |
1390 |
siginfo_t *info = pinfo; |
1391 |
struct ucontext *uc = puc;
|
1392 |
unsigned long pc; |
1393 |
int is_write;
|
1394 |
|
1395 |
pc = IAR_sig(uc); |
1396 |
is_write = 0;
|
1397 |
#if 0
|
1398 |
/* ppc 4xx case */
|
1399 |
if (DSISR_sig(uc) & 0x00800000)
|
1400 |
is_write = 1;
|
1401 |
#else
|
1402 |
if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) |
1403 |
is_write = 1;
|
1404 |
#endif
|
1405 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1406 |
is_write, &uc->uc_sigmask, puc); |
1407 |
} |
1408 |
|
1409 |
#elif defined(__alpha__)
|
1410 |
|
1411 |
int cpu_signal_handler(int host_signum, void *pinfo, |
1412 |
void *puc)
|
1413 |
{ |
1414 |
siginfo_t *info = pinfo; |
1415 |
struct ucontext *uc = puc;
|
1416 |
uint32_t *pc = uc->uc_mcontext.sc_pc; |
1417 |
uint32_t insn = *pc; |
1418 |
int is_write = 0; |
1419 |
|
1420 |
/* XXX: need kernel patch to get write flag faster */
|
1421 |
switch (insn >> 26) { |
1422 |
case 0x0d: // stw |
1423 |
case 0x0e: // stb |
1424 |
case 0x0f: // stq_u |
1425 |
case 0x24: // stf |
1426 |
case 0x25: // stg |
1427 |
case 0x26: // sts |
1428 |
case 0x27: // stt |
1429 |
case 0x2c: // stl |
1430 |
case 0x2d: // stq |
1431 |
case 0x2e: // stl_c |
1432 |
case 0x2f: // stq_c |
1433 |
is_write = 1;
|
1434 |
} |
1435 |
|
1436 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1437 |
is_write, &uc->uc_sigmask, puc); |
1438 |
} |
1439 |
#elif defined(__sparc__)
|
1440 |
|
1441 |
int cpu_signal_handler(int host_signum, void *pinfo, |
1442 |
void *puc)
|
1443 |
{ |
1444 |
siginfo_t *info = pinfo; |
1445 |
uint32_t *regs = (uint32_t *)(info + 1);
|
1446 |
void *sigmask = (regs + 20); |
1447 |
unsigned long pc; |
1448 |
int is_write;
|
1449 |
uint32_t insn; |
1450 |
|
1451 |
/* XXX: is there a standard glibc define ? */
|
1452 |
pc = regs[1];
|
1453 |
/* XXX: need kernel patch to get write flag faster */
|
1454 |
is_write = 0;
|
1455 |
insn = *(uint32_t *)pc; |
1456 |
if ((insn >> 30) == 3) { |
1457 |
switch((insn >> 19) & 0x3f) { |
1458 |
case 0x05: // stb |
1459 |
case 0x06: // sth |
1460 |
case 0x04: // st |
1461 |
case 0x07: // std |
1462 |
case 0x24: // stf |
1463 |
case 0x27: // stdf |
1464 |
case 0x25: // stfsr |
1465 |
is_write = 1;
|
1466 |
break;
|
1467 |
} |
1468 |
} |
1469 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1470 |
is_write, sigmask, NULL);
|
1471 |
} |
1472 |
|
1473 |
#elif defined(__arm__)
|
1474 |
|
1475 |
int cpu_signal_handler(int host_signum, void *pinfo, |
1476 |
void *puc)
|
1477 |
{ |
1478 |
siginfo_t *info = pinfo; |
1479 |
struct ucontext *uc = puc;
|
1480 |
unsigned long pc; |
1481 |
int is_write;
|
1482 |
|
1483 |
pc = uc->uc_mcontext.gregs[R15]; |
1484 |
/* XXX: compute is_write */
|
1485 |
is_write = 0;
|
1486 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1487 |
is_write, |
1488 |
&uc->uc_sigmask, puc); |
1489 |
} |
1490 |
|
1491 |
#elif defined(__mc68000)
|
1492 |
|
1493 |
int cpu_signal_handler(int host_signum, void *pinfo, |
1494 |
void *puc)
|
1495 |
{ |
1496 |
siginfo_t *info = pinfo; |
1497 |
struct ucontext *uc = puc;
|
1498 |
unsigned long pc; |
1499 |
int is_write;
|
1500 |
|
1501 |
pc = uc->uc_mcontext.gregs[16];
|
1502 |
/* XXX: compute is_write */
|
1503 |
is_write = 0;
|
1504 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1505 |
is_write, |
1506 |
&uc->uc_sigmask, puc); |
1507 |
} |
1508 |
|
1509 |
#elif defined(__ia64)
|
1510 |
|
1511 |
#ifndef __ISR_VALID
|
1512 |
/* This ought to be in <bits/siginfo.h>... */
|
1513 |
# define __ISR_VALID 1 |
1514 |
#endif
|
1515 |
|
1516 |
int cpu_signal_handler(int host_signum, void *pinfo, void *puc) |
1517 |
{ |
1518 |
siginfo_t *info = pinfo; |
1519 |
struct ucontext *uc = puc;
|
1520 |
unsigned long ip; |
1521 |
int is_write = 0; |
1522 |
|
1523 |
ip = uc->uc_mcontext.sc_ip; |
1524 |
switch (host_signum) {
|
1525 |
case SIGILL:
|
1526 |
case SIGFPE:
|
1527 |
case SIGSEGV:
|
1528 |
case SIGBUS:
|
1529 |
case SIGTRAP:
|
1530 |
if (info->si_code && (info->si_segvflags & __ISR_VALID))
|
1531 |
/* ISR.W (write-access) is bit 33: */
|
1532 |
is_write = (info->si_isr >> 33) & 1; |
1533 |
break;
|
1534 |
|
1535 |
default:
|
1536 |
break;
|
1537 |
} |
1538 |
return handle_cpu_signal(ip, (unsigned long)info->si_addr, |
1539 |
is_write, |
1540 |
&uc->uc_sigmask, puc); |
1541 |
} |
1542 |
|
1543 |
#elif defined(__s390__)
|
1544 |
|
1545 |
int cpu_signal_handler(int host_signum, void *pinfo, |
1546 |
void *puc)
|
1547 |
{ |
1548 |
siginfo_t *info = pinfo; |
1549 |
struct ucontext *uc = puc;
|
1550 |
unsigned long pc; |
1551 |
int is_write;
|
1552 |
|
1553 |
pc = uc->uc_mcontext.psw.addr; |
1554 |
/* XXX: compute is_write */
|
1555 |
is_write = 0;
|
1556 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1557 |
is_write, &uc->uc_sigmask, puc); |
1558 |
} |
1559 |
|
1560 |
#elif defined(__mips__)
|
1561 |
|
1562 |
int cpu_signal_handler(int host_signum, void *pinfo, |
1563 |
void *puc)
|
1564 |
{ |
1565 |
siginfo_t *info = pinfo; |
1566 |
struct ucontext *uc = puc;
|
1567 |
greg_t pc = uc->uc_mcontext.pc; |
1568 |
int is_write;
|
1569 |
|
1570 |
/* XXX: compute is_write */
|
1571 |
is_write = 0;
|
1572 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1573 |
is_write, &uc->uc_sigmask, puc); |
1574 |
} |
1575 |
|
1576 |
#else
|
1577 |
|
1578 |
#error host CPU specific signal handler needed
|
1579 |
|
1580 |
#endif
|
1581 |
|
1582 |
#endif /* !defined(CONFIG_SOFTMMU) */ |