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/*
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* QEMU System Emulator header
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef VL_H
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#define VL_H
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/* we put basic includes here to avoid repeating them in device drivers */
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#include <stdlib.h> |
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#include <stdio.h> |
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#include <stdarg.h> |
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#include <string.h> |
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#include <inttypes.h> |
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#include <limits.h> |
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#include <time.h> |
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#include <ctype.h> |
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#include <errno.h> |
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#include <unistd.h> |
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#include <fcntl.h> |
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#include <sys/stat.h> |
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#ifndef O_LARGEFILE
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#define O_LARGEFILE 0 |
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#endif
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#ifndef O_BINARY
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#define O_BINARY 0 |
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#endif
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#ifndef ENOMEDIUM
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#define ENOMEDIUM ENODEV
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#endif
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#ifdef _WIN32
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#include <windows.h> |
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#define fsync _commit
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#define lseek _lseeki64
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#define ENOTSUP 4096 |
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extern int qemu_ftruncate64(int, int64_t); |
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#define ftruncate qemu_ftruncate64
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static inline char *realpath(const char *path, char *resolved_path) |
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{ |
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_fullpath(resolved_path, path, _MAX_PATH); |
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return resolved_path;
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} |
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#define PRId64 "I64d" |
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#define PRIx64 "I64x" |
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#define PRIu64 "I64u" |
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#define PRIo64 "I64o" |
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#endif
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#ifdef QEMU_TOOL
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/* we use QEMU_TOOL in the command line tools which do not depend on
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the target CPU type */
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#include "config-host.h" |
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#include <setjmp.h> |
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#include "osdep.h" |
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#include "bswap.h" |
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#else
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#include "audio/audio.h" |
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#include "cpu.h" |
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#endif /* !defined(QEMU_TOOL) */ |
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#ifndef glue
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#define xglue(x, y) x ## y |
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#define glue(x, y) xglue(x, y)
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#define stringify(s) tostring(s)
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#define tostring(s) #s |
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#endif
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#ifndef MIN
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#define MIN(a, b) (((a) < (b)) ? (a) : (b))
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#endif
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#ifndef MAX
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#define MAX(a, b) (((a) > (b)) ? (a) : (b))
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#endif
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/* cutils.c */
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void pstrcpy(char *buf, int buf_size, const char *str); |
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char *pstrcat(char *buf, int buf_size, const char *s); |
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int strstart(const char *str, const char *val, const char **ptr); |
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int stristart(const char *str, const char *val, const char **ptr); |
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/* vl.c */
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uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c); |
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void hw_error(const char *fmt, ...); |
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extern const char *bios_dir; |
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extern int vm_running; |
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extern const char *qemu_name; |
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typedef struct vm_change_state_entry VMChangeStateEntry; |
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typedef void VMChangeStateHandler(void *opaque, int running); |
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typedef void VMStopHandler(void *opaque, int reason); |
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VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb, |
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void *opaque);
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void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
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int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque); |
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void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque); |
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void vm_start(void); |
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void vm_stop(int reason); |
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typedef void QEMUResetHandler(void *opaque); |
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void qemu_register_reset(QEMUResetHandler *func, void *opaque); |
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void qemu_system_reset_request(void); |
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void qemu_system_shutdown_request(void); |
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void qemu_system_powerdown_request(void); |
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#if !defined(TARGET_SPARC)
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// Please implement a power failure function to signal the OS
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#define qemu_system_powerdown() do{}while(0) |
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#else
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void qemu_system_powerdown(void); |
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#endif
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void main_loop_wait(int timeout); |
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extern int ram_size; |
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extern int bios_size; |
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extern int rtc_utc; |
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extern int cirrus_vga_enabled; |
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extern int vmsvga_enabled; |
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extern int graphic_width; |
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extern int graphic_height; |
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extern int graphic_depth; |
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extern const char *keyboard_layout; |
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extern int kqemu_allowed; |
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extern int win2k_install_hack; |
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extern int usb_enabled; |
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extern int smp_cpus; |
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extern int cursor_hide; |
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extern int graphic_rotate; |
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extern int no_quit; |
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extern int semihosting_enabled; |
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extern int autostart; |
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extern const char *bootp_filename; |
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#define MAX_OPTION_ROMS 16 |
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extern const char *option_rom[MAX_OPTION_ROMS]; |
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extern int nb_option_roms; |
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#ifdef TARGET_SPARC
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#define MAX_PROM_ENVS 128 |
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extern const char *prom_envs[MAX_PROM_ENVS]; |
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extern unsigned int nb_prom_envs; |
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#endif
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/* XXX: make it dynamic */
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#define MAX_BIOS_SIZE (4 * 1024 * 1024) |
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#if defined (TARGET_PPC) || defined (TARGET_SPARC64)
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#define BIOS_SIZE ((512 + 32) * 1024) |
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#elif defined(TARGET_MIPS)
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#define BIOS_SIZE (4 * 1024 * 1024) |
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#endif
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/* keyboard/mouse support */
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#define MOUSE_EVENT_LBUTTON 0x01 |
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#define MOUSE_EVENT_RBUTTON 0x02 |
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#define MOUSE_EVENT_MBUTTON 0x04 |
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typedef void QEMUPutKBDEvent(void *opaque, int keycode); |
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typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state); |
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typedef struct QEMUPutMouseEntry { |
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QEMUPutMouseEvent *qemu_put_mouse_event; |
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void *qemu_put_mouse_event_opaque;
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int qemu_put_mouse_event_absolute;
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char *qemu_put_mouse_event_name;
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/* used internally by qemu for handling mice */
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struct QEMUPutMouseEntry *next;
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} QEMUPutMouseEntry; |
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void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque); |
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QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func, |
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void *opaque, int absolute, |
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const char *name); |
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void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry);
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void kbd_put_keycode(int keycode); |
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void kbd_mouse_event(int dx, int dy, int dz, int buttons_state); |
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int kbd_mouse_is_absolute(void); |
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void do_info_mice(void); |
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void do_mouse_set(int index); |
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/* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
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constants) */
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#define QEMU_KEY_ESC1(c) ((c) | 0xe100) |
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#define QEMU_KEY_BACKSPACE 0x007f |
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#define QEMU_KEY_UP QEMU_KEY_ESC1('A') |
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#define QEMU_KEY_DOWN QEMU_KEY_ESC1('B') |
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#define QEMU_KEY_RIGHT QEMU_KEY_ESC1('C') |
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#define QEMU_KEY_LEFT QEMU_KEY_ESC1('D') |
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#define QEMU_KEY_HOME QEMU_KEY_ESC1(1) |
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#define QEMU_KEY_END QEMU_KEY_ESC1(4) |
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#define QEMU_KEY_PAGEUP QEMU_KEY_ESC1(5) |
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#define QEMU_KEY_PAGEDOWN QEMU_KEY_ESC1(6) |
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#define QEMU_KEY_DELETE QEMU_KEY_ESC1(3) |
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#define QEMU_KEY_CTRL_UP 0xe400 |
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#define QEMU_KEY_CTRL_DOWN 0xe401 |
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#define QEMU_KEY_CTRL_LEFT 0xe402 |
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#define QEMU_KEY_CTRL_RIGHT 0xe403 |
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#define QEMU_KEY_CTRL_HOME 0xe404 |
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#define QEMU_KEY_CTRL_END 0xe405 |
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#define QEMU_KEY_CTRL_PAGEUP 0xe406 |
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#define QEMU_KEY_CTRL_PAGEDOWN 0xe407 |
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void kbd_put_keysym(int keysym); |
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/* async I/O support */
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typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size); |
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typedef int IOCanRWHandler(void *opaque); |
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typedef void IOHandler(void *opaque); |
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int qemu_set_fd_handler2(int fd, |
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IOCanRWHandler *fd_read_poll, |
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IOHandler *fd_read, |
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IOHandler *fd_write, |
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void *opaque);
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int qemu_set_fd_handler(int fd, |
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IOHandler *fd_read, |
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IOHandler *fd_write, |
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void *opaque);
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/* Polling handling */
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/* return TRUE if no sleep should be done afterwards */
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typedef int PollingFunc(void *opaque); |
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int qemu_add_polling_cb(PollingFunc *func, void *opaque); |
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void qemu_del_polling_cb(PollingFunc *func, void *opaque); |
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#ifdef _WIN32
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/* Wait objects handling */
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typedef void WaitObjectFunc(void *opaque); |
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int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque); |
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void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque); |
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#endif
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typedef struct QEMUBH QEMUBH; |
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/* character device */
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#define CHR_EVENT_BREAK 0 /* serial break char */ |
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#define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */ |
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#define CHR_EVENT_RESET 2 /* new connection established */ |
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#define CHR_IOCTL_SERIAL_SET_PARAMS 1 |
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typedef struct { |
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int speed;
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int parity;
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int data_bits;
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int stop_bits;
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} QEMUSerialSetParams; |
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#define CHR_IOCTL_SERIAL_SET_BREAK 2 |
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#define CHR_IOCTL_PP_READ_DATA 3 |
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#define CHR_IOCTL_PP_WRITE_DATA 4 |
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#define CHR_IOCTL_PP_READ_CONTROL 5 |
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#define CHR_IOCTL_PP_WRITE_CONTROL 6 |
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#define CHR_IOCTL_PP_READ_STATUS 7 |
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#define CHR_IOCTL_PP_EPP_READ_ADDR 8 |
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#define CHR_IOCTL_PP_EPP_READ 9 |
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#define CHR_IOCTL_PP_EPP_WRITE_ADDR 10 |
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#define CHR_IOCTL_PP_EPP_WRITE 11 |
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typedef void IOEventHandler(void *opaque, int event); |
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typedef struct CharDriverState { |
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int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len); |
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void (*chr_update_read_handler)(struct CharDriverState *s); |
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int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg); |
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IOEventHandler *chr_event; |
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IOCanRWHandler *chr_can_read; |
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IOReadHandler *chr_read; |
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void *handler_opaque;
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void (*chr_send_event)(struct CharDriverState *chr, int event); |
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void (*chr_close)(struct CharDriverState *chr); |
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void *opaque;
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int focus;
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QEMUBH *bh; |
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} CharDriverState; |
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CharDriverState *qemu_chr_open(const char *filename); |
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void qemu_chr_printf(CharDriverState *s, const char *fmt, ...); |
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int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len); |
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void qemu_chr_send_event(CharDriverState *s, int event); |
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void qemu_chr_add_handlers(CharDriverState *s,
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IOCanRWHandler *fd_can_read, |
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IOReadHandler *fd_read, |
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IOEventHandler *fd_event, |
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void *opaque);
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int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg); |
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void qemu_chr_reset(CharDriverState *s);
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int qemu_chr_can_read(CharDriverState *s);
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void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len); |
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/* consoles */
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typedef struct DisplayState DisplayState; |
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typedef struct TextConsole TextConsole; |
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typedef void (*vga_hw_update_ptr)(void *); |
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typedef void (*vga_hw_invalidate_ptr)(void *); |
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typedef void (*vga_hw_screen_dump_ptr)(void *, const char *); |
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TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update, |
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vga_hw_invalidate_ptr invalidate, |
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vga_hw_screen_dump_ptr screen_dump, |
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void *opaque);
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void vga_hw_update(void); |
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void vga_hw_invalidate(void); |
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void vga_hw_screen_dump(const char *filename); |
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int is_graphic_console(void); |
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CharDriverState *text_console_init(DisplayState *ds); |
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void console_select(unsigned int index); |
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/* serial ports */
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#define MAX_SERIAL_PORTS 4 |
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extern CharDriverState *serial_hds[MAX_SERIAL_PORTS];
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/* parallel ports */
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#define MAX_PARALLEL_PORTS 3 |
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extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS];
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struct ParallelIOArg {
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void *buffer;
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int count;
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}; |
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/* VLANs support */
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typedef struct VLANClientState VLANClientState; |
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struct VLANClientState {
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IOReadHandler *fd_read; |
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/* Packets may still be sent if this returns zero. It's used to
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rate-limit the slirp code. */
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IOCanRWHandler *fd_can_read; |
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void *opaque;
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struct VLANClientState *next;
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struct VLANState *vlan;
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char info_str[256]; |
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}; |
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typedef struct VLANState { |
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int id;
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VLANClientState *first_client; |
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struct VLANState *next;
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unsigned int nb_guest_devs, nb_host_devs; |
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} VLANState; |
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VLANState *qemu_find_vlan(int id);
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VLANClientState *qemu_new_vlan_client(VLANState *vlan, |
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IOReadHandler *fd_read, |
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IOCanRWHandler *fd_can_read, |
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void *opaque);
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int qemu_can_send_packet(VLANClientState *vc);
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void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size); |
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void qemu_handler_true(void *opaque); |
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void do_info_network(void); |
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/* TAP win32 */
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int tap_win32_init(VLANState *vlan, const char *ifname); |
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/* NIC info */
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#define MAX_NICS 8 |
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typedef struct NICInfo { |
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uint8_t macaddr[6];
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const char *model; |
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VLANState *vlan; |
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} NICInfo; |
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extern int nb_nics; |
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extern NICInfo nd_table[MAX_NICS];
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|
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/* timers */
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typedef struct QEMUClock QEMUClock; |
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typedef struct QEMUTimer QEMUTimer; |
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typedef void QEMUTimerCB(void *opaque); |
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/* The real time clock should be used only for stuff which does not
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change the virtual machine state, as it is run even if the virtual
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machine is stopped. The real time clock has a frequency of 1000
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Hz. */
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extern QEMUClock *rt_clock;
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/* The virtual clock is only run during the emulation. It is stopped
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when the virtual machine is stopped. Virtual timers use a high
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precision clock, usually cpu cycles (use ticks_per_sec). */
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extern QEMUClock *vm_clock;
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int64_t qemu_get_clock(QEMUClock *clock); |
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QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
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void qemu_free_timer(QEMUTimer *ts);
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void qemu_del_timer(QEMUTimer *ts);
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void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
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int qemu_timer_pending(QEMUTimer *ts);
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extern int64_t ticks_per_sec;
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extern int pit_min_timer_count; |
449 |
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int64_t cpu_get_ticks(void);
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void cpu_enable_ticks(void); |
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void cpu_disable_ticks(void); |
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/* VM Load/Save */
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typedef struct QEMUFile QEMUFile; |
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QEMUFile *qemu_fopen(const char *filename, const char *mode); |
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void qemu_fflush(QEMUFile *f);
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void qemu_fclose(QEMUFile *f);
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void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size); |
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void qemu_put_byte(QEMUFile *f, int v); |
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void qemu_put_be16(QEMUFile *f, unsigned int v); |
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void qemu_put_be32(QEMUFile *f, unsigned int v); |
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void qemu_put_be64(QEMUFile *f, uint64_t v);
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int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size); |
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int qemu_get_byte(QEMUFile *f);
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unsigned int qemu_get_be16(QEMUFile *f); |
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unsigned int qemu_get_be32(QEMUFile *f); |
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uint64_t qemu_get_be64(QEMUFile *f); |
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|
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static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv) |
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{ |
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qemu_put_be64(f, *pv); |
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} |
476 |
|
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static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv) |
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{ |
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qemu_put_be32(f, *pv); |
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} |
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|
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static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv) |
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{ |
484 |
qemu_put_be16(f, *pv); |
485 |
} |
486 |
|
487 |
static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv) |
488 |
{ |
489 |
qemu_put_byte(f, *pv); |
490 |
} |
491 |
|
492 |
static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv) |
493 |
{ |
494 |
*pv = qemu_get_be64(f); |
495 |
} |
496 |
|
497 |
static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv) |
498 |
{ |
499 |
*pv = qemu_get_be32(f); |
500 |
} |
501 |
|
502 |
static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv) |
503 |
{ |
504 |
*pv = qemu_get_be16(f); |
505 |
} |
506 |
|
507 |
static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv) |
508 |
{ |
509 |
*pv = qemu_get_byte(f); |
510 |
} |
511 |
|
512 |
#if TARGET_LONG_BITS == 64 |
513 |
#define qemu_put_betl qemu_put_be64
|
514 |
#define qemu_get_betl qemu_get_be64
|
515 |
#define qemu_put_betls qemu_put_be64s
|
516 |
#define qemu_get_betls qemu_get_be64s
|
517 |
#else
|
518 |
#define qemu_put_betl qemu_put_be32
|
519 |
#define qemu_get_betl qemu_get_be32
|
520 |
#define qemu_put_betls qemu_put_be32s
|
521 |
#define qemu_get_betls qemu_get_be32s
|
522 |
#endif
|
523 |
|
524 |
int64_t qemu_ftell(QEMUFile *f); |
525 |
int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
|
526 |
|
527 |
typedef void SaveStateHandler(QEMUFile *f, void *opaque); |
528 |
typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id); |
529 |
|
530 |
int register_savevm(const char *idstr, |
531 |
int instance_id,
|
532 |
int version_id,
|
533 |
SaveStateHandler *save_state, |
534 |
LoadStateHandler *load_state, |
535 |
void *opaque);
|
536 |
void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
|
537 |
void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
|
538 |
|
539 |
void cpu_save(QEMUFile *f, void *opaque); |
540 |
int cpu_load(QEMUFile *f, void *opaque, int version_id); |
541 |
|
542 |
void do_savevm(const char *name); |
543 |
void do_loadvm(const char *name); |
544 |
void do_delvm(const char *name); |
545 |
void do_info_snapshots(void); |
546 |
|
547 |
/* bottom halves */
|
548 |
typedef void QEMUBHFunc(void *opaque); |
549 |
|
550 |
QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque);
|
551 |
void qemu_bh_schedule(QEMUBH *bh);
|
552 |
void qemu_bh_cancel(QEMUBH *bh);
|
553 |
void qemu_bh_delete(QEMUBH *bh);
|
554 |
int qemu_bh_poll(void); |
555 |
|
556 |
/* block.c */
|
557 |
typedef struct BlockDriverState BlockDriverState; |
558 |
typedef struct BlockDriver BlockDriver; |
559 |
|
560 |
extern BlockDriver bdrv_raw;
|
561 |
extern BlockDriver bdrv_host_device;
|
562 |
extern BlockDriver bdrv_cow;
|
563 |
extern BlockDriver bdrv_qcow;
|
564 |
extern BlockDriver bdrv_vmdk;
|
565 |
extern BlockDriver bdrv_cloop;
|
566 |
extern BlockDriver bdrv_dmg;
|
567 |
extern BlockDriver bdrv_bochs;
|
568 |
extern BlockDriver bdrv_vpc;
|
569 |
extern BlockDriver bdrv_vvfat;
|
570 |
extern BlockDriver bdrv_qcow2;
|
571 |
|
572 |
typedef struct BlockDriverInfo { |
573 |
/* in bytes, 0 if irrelevant */
|
574 |
int cluster_size;
|
575 |
/* offset at which the VM state can be saved (0 if not possible) */
|
576 |
int64_t vm_state_offset; |
577 |
} BlockDriverInfo; |
578 |
|
579 |
typedef struct QEMUSnapshotInfo { |
580 |
char id_str[128]; /* unique snapshot id */ |
581 |
/* the following fields are informative. They are not needed for
|
582 |
the consistency of the snapshot */
|
583 |
char name[256]; /* user choosen name */ |
584 |
uint32_t vm_state_size; /* VM state info size */
|
585 |
uint32_t date_sec; /* UTC date of the snapshot */
|
586 |
uint32_t date_nsec; |
587 |
uint64_t vm_clock_nsec; /* VM clock relative to boot */
|
588 |
} QEMUSnapshotInfo; |
589 |
|
590 |
#define BDRV_O_RDONLY 0x0000 |
591 |
#define BDRV_O_RDWR 0x0002 |
592 |
#define BDRV_O_ACCESS 0x0003 |
593 |
#define BDRV_O_CREAT 0x0004 /* create an empty file */ |
594 |
#define BDRV_O_SNAPSHOT 0x0008 /* open the file read only and save writes in a snapshot */ |
595 |
#define BDRV_O_FILE 0x0010 /* open as a raw file (do not try to |
596 |
use a disk image format on top of
|
597 |
it (default for
|
598 |
bdrv_file_open()) */
|
599 |
|
600 |
void bdrv_init(void); |
601 |
BlockDriver *bdrv_find_format(const char *format_name); |
602 |
int bdrv_create(BlockDriver *drv,
|
603 |
const char *filename, int64_t size_in_sectors, |
604 |
const char *backing_file, int flags); |
605 |
BlockDriverState *bdrv_new(const char *device_name); |
606 |
void bdrv_delete(BlockDriverState *bs);
|
607 |
int bdrv_file_open(BlockDriverState **pbs, const char *filename, int flags); |
608 |
int bdrv_open(BlockDriverState *bs, const char *filename, int flags); |
609 |
int bdrv_open2(BlockDriverState *bs, const char *filename, int flags, |
610 |
BlockDriver *drv); |
611 |
void bdrv_close(BlockDriverState *bs);
|
612 |
int bdrv_read(BlockDriverState *bs, int64_t sector_num,
|
613 |
uint8_t *buf, int nb_sectors);
|
614 |
int bdrv_write(BlockDriverState *bs, int64_t sector_num,
|
615 |
const uint8_t *buf, int nb_sectors); |
616 |
int bdrv_pread(BlockDriverState *bs, int64_t offset,
|
617 |
void *buf, int count); |
618 |
int bdrv_pwrite(BlockDriverState *bs, int64_t offset,
|
619 |
const void *buf, int count); |
620 |
int bdrv_truncate(BlockDriverState *bs, int64_t offset);
|
621 |
int64_t bdrv_getlength(BlockDriverState *bs); |
622 |
void bdrv_get_geometry(BlockDriverState *bs, int64_t *nb_sectors_ptr);
|
623 |
int bdrv_commit(BlockDriverState *bs);
|
624 |
void bdrv_set_boot_sector(BlockDriverState *bs, const uint8_t *data, int size); |
625 |
/* async block I/O */
|
626 |
typedef struct BlockDriverAIOCB BlockDriverAIOCB; |
627 |
typedef void BlockDriverCompletionFunc(void *opaque, int ret); |
628 |
|
629 |
BlockDriverAIOCB *bdrv_aio_read(BlockDriverState *bs, int64_t sector_num, |
630 |
uint8_t *buf, int nb_sectors,
|
631 |
BlockDriverCompletionFunc *cb, void *opaque);
|
632 |
BlockDriverAIOCB *bdrv_aio_write(BlockDriverState *bs, int64_t sector_num, |
633 |
const uint8_t *buf, int nb_sectors, |
634 |
BlockDriverCompletionFunc *cb, void *opaque);
|
635 |
void bdrv_aio_cancel(BlockDriverAIOCB *acb);
|
636 |
|
637 |
void qemu_aio_init(void); |
638 |
void qemu_aio_poll(void); |
639 |
void qemu_aio_flush(void); |
640 |
void qemu_aio_wait_start(void); |
641 |
void qemu_aio_wait(void); |
642 |
void qemu_aio_wait_end(void); |
643 |
|
644 |
int qemu_key_check(BlockDriverState *bs, const char *name); |
645 |
|
646 |
/* Ensure contents are flushed to disk. */
|
647 |
void bdrv_flush(BlockDriverState *bs);
|
648 |
|
649 |
#define BDRV_TYPE_HD 0 |
650 |
#define BDRV_TYPE_CDROM 1 |
651 |
#define BDRV_TYPE_FLOPPY 2 |
652 |
#define BIOS_ATA_TRANSLATION_AUTO 0 |
653 |
#define BIOS_ATA_TRANSLATION_NONE 1 |
654 |
#define BIOS_ATA_TRANSLATION_LBA 2 |
655 |
#define BIOS_ATA_TRANSLATION_LARGE 3 |
656 |
#define BIOS_ATA_TRANSLATION_RECHS 4 |
657 |
|
658 |
void bdrv_set_geometry_hint(BlockDriverState *bs,
|
659 |
int cyls, int heads, int secs); |
660 |
void bdrv_set_type_hint(BlockDriverState *bs, int type); |
661 |
void bdrv_set_translation_hint(BlockDriverState *bs, int translation); |
662 |
void bdrv_get_geometry_hint(BlockDriverState *bs,
|
663 |
int *pcyls, int *pheads, int *psecs); |
664 |
int bdrv_get_type_hint(BlockDriverState *bs);
|
665 |
int bdrv_get_translation_hint(BlockDriverState *bs);
|
666 |
int bdrv_is_removable(BlockDriverState *bs);
|
667 |
int bdrv_is_read_only(BlockDriverState *bs);
|
668 |
int bdrv_is_inserted(BlockDriverState *bs);
|
669 |
int bdrv_media_changed(BlockDriverState *bs);
|
670 |
int bdrv_is_locked(BlockDriverState *bs);
|
671 |
void bdrv_set_locked(BlockDriverState *bs, int locked); |
672 |
void bdrv_eject(BlockDriverState *bs, int eject_flag); |
673 |
void bdrv_set_change_cb(BlockDriverState *bs,
|
674 |
void (*change_cb)(void *opaque), void *opaque); |
675 |
void bdrv_get_format(BlockDriverState *bs, char *buf, int buf_size); |
676 |
void bdrv_info(void); |
677 |
BlockDriverState *bdrv_find(const char *name); |
678 |
void bdrv_iterate(void (*it)(void *opaque, const char *name), void *opaque); |
679 |
int bdrv_is_encrypted(BlockDriverState *bs);
|
680 |
int bdrv_set_key(BlockDriverState *bs, const char *key); |
681 |
void bdrv_iterate_format(void (*it)(void *opaque, const char *name), |
682 |
void *opaque);
|
683 |
const char *bdrv_get_device_name(BlockDriverState *bs); |
684 |
int bdrv_write_compressed(BlockDriverState *bs, int64_t sector_num,
|
685 |
const uint8_t *buf, int nb_sectors); |
686 |
int bdrv_get_info(BlockDriverState *bs, BlockDriverInfo *bdi);
|
687 |
|
688 |
void bdrv_get_backing_filename(BlockDriverState *bs,
|
689 |
char *filename, int filename_size); |
690 |
int bdrv_snapshot_create(BlockDriverState *bs,
|
691 |
QEMUSnapshotInfo *sn_info); |
692 |
int bdrv_snapshot_goto(BlockDriverState *bs,
|
693 |
const char *snapshot_id); |
694 |
int bdrv_snapshot_delete(BlockDriverState *bs, const char *snapshot_id); |
695 |
int bdrv_snapshot_list(BlockDriverState *bs,
|
696 |
QEMUSnapshotInfo **psn_info); |
697 |
char *bdrv_snapshot_dump(char *buf, int buf_size, QEMUSnapshotInfo *sn); |
698 |
|
699 |
char *get_human_readable_size(char *buf, int buf_size, int64_t size); |
700 |
int path_is_absolute(const char *path); |
701 |
void path_combine(char *dest, int dest_size, |
702 |
const char *base_path, |
703 |
const char *filename); |
704 |
|
705 |
#ifndef QEMU_TOOL
|
706 |
|
707 |
typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size, |
708 |
int boot_device,
|
709 |
DisplayState *ds, const char **fd_filename, int snapshot, |
710 |
const char *kernel_filename, const char *kernel_cmdline, |
711 |
const char *initrd_filename, const char *cpu_model); |
712 |
|
713 |
typedef struct QEMUMachine { |
714 |
const char *name; |
715 |
const char *desc; |
716 |
QEMUMachineInitFunc *init; |
717 |
struct QEMUMachine *next;
|
718 |
} QEMUMachine; |
719 |
|
720 |
int qemu_register_machine(QEMUMachine *m);
|
721 |
|
722 |
typedef void SetIRQFunc(void *opaque, int irq_num, int level); |
723 |
|
724 |
#if defined(TARGET_PPC)
|
725 |
void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
726 |
#endif
|
727 |
|
728 |
#if defined(TARGET_MIPS)
|
729 |
void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
730 |
#endif
|
731 |
|
732 |
#include "hw/irq.h" |
733 |
|
734 |
/* ISA bus */
|
735 |
|
736 |
extern target_phys_addr_t isa_mem_base;
|
737 |
|
738 |
typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data); |
739 |
typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address); |
740 |
|
741 |
int register_ioport_read(int start, int length, int size, |
742 |
IOPortReadFunc *func, void *opaque);
|
743 |
int register_ioport_write(int start, int length, int size, |
744 |
IOPortWriteFunc *func, void *opaque);
|
745 |
void isa_unassign_ioport(int start, int length); |
746 |
|
747 |
void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
|
748 |
|
749 |
/* PCI bus */
|
750 |
|
751 |
extern target_phys_addr_t pci_mem_base;
|
752 |
|
753 |
typedef struct PCIBus PCIBus; |
754 |
typedef struct PCIDevice PCIDevice; |
755 |
|
756 |
typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, |
757 |
uint32_t address, uint32_t data, int len);
|
758 |
typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
|
759 |
uint32_t address, int len);
|
760 |
typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, |
761 |
uint32_t addr, uint32_t size, int type);
|
762 |
|
763 |
#define PCI_ADDRESS_SPACE_MEM 0x00 |
764 |
#define PCI_ADDRESS_SPACE_IO 0x01 |
765 |
#define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08 |
766 |
|
767 |
typedef struct PCIIORegion { |
768 |
uint32_t addr; /* current PCI mapping address. -1 means not mapped */
|
769 |
uint32_t size; |
770 |
uint8_t type; |
771 |
PCIMapIORegionFunc *map_func; |
772 |
} PCIIORegion; |
773 |
|
774 |
#define PCI_ROM_SLOT 6 |
775 |
#define PCI_NUM_REGIONS 7 |
776 |
|
777 |
#define PCI_DEVICES_MAX 64 |
778 |
|
779 |
#define PCI_VENDOR_ID 0x00 /* 16 bits */ |
780 |
#define PCI_DEVICE_ID 0x02 /* 16 bits */ |
781 |
#define PCI_COMMAND 0x04 /* 16 bits */ |
782 |
#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ |
783 |
#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ |
784 |
#define PCI_CLASS_DEVICE 0x0a /* Device class */ |
785 |
#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ |
786 |
#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ |
787 |
#define PCI_MIN_GNT 0x3e /* 8 bits */ |
788 |
#define PCI_MAX_LAT 0x3f /* 8 bits */ |
789 |
|
790 |
struct PCIDevice {
|
791 |
/* PCI config space */
|
792 |
uint8_t config[256];
|
793 |
|
794 |
/* the following fields are read only */
|
795 |
PCIBus *bus; |
796 |
int devfn;
|
797 |
char name[64]; |
798 |
PCIIORegion io_regions[PCI_NUM_REGIONS]; |
799 |
|
800 |
/* do not access the following fields */
|
801 |
PCIConfigReadFunc *config_read; |
802 |
PCIConfigWriteFunc *config_write; |
803 |
/* ??? This is a PC-specific hack, and should be removed. */
|
804 |
int irq_index;
|
805 |
|
806 |
/* IRQ objects for the INTA-INTD pins. */
|
807 |
qemu_irq *irq; |
808 |
|
809 |
/* Current IRQ levels. Used internally by the generic PCI code. */
|
810 |
int irq_state[4]; |
811 |
}; |
812 |
|
813 |
PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
814 |
int instance_size, int devfn, |
815 |
PCIConfigReadFunc *config_read, |
816 |
PCIConfigWriteFunc *config_write); |
817 |
|
818 |
void pci_register_io_region(PCIDevice *pci_dev, int region_num, |
819 |
uint32_t size, int type,
|
820 |
PCIMapIORegionFunc *map_func); |
821 |
|
822 |
uint32_t pci_default_read_config(PCIDevice *d, |
823 |
uint32_t address, int len);
|
824 |
void pci_default_write_config(PCIDevice *d,
|
825 |
uint32_t address, uint32_t val, int len);
|
826 |
void pci_device_save(PCIDevice *s, QEMUFile *f);
|
827 |
int pci_device_load(PCIDevice *s, QEMUFile *f);
|
828 |
|
829 |
typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level); |
830 |
typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); |
831 |
PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
832 |
qemu_irq *pic, int devfn_min, int nirq); |
833 |
|
834 |
void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn); |
835 |
void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len); |
836 |
uint32_t pci_data_read(void *opaque, uint32_t addr, int len); |
837 |
int pci_bus_num(PCIBus *s);
|
838 |
void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d)); |
839 |
|
840 |
void pci_info(void); |
841 |
PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
|
842 |
pci_map_irq_fn map_irq, const char *name); |
843 |
|
844 |
/* prep_pci.c */
|
845 |
PCIBus *pci_prep_init(qemu_irq *pic); |
846 |
|
847 |
/* grackle_pci.c */
|
848 |
PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic); |
849 |
|
850 |
/* unin_pci.c */
|
851 |
PCIBus *pci_pmac_init(qemu_irq *pic); |
852 |
|
853 |
/* apb_pci.c */
|
854 |
PCIBus *pci_apb_init(target_ulong special_base, target_ulong mem_base, |
855 |
qemu_irq *pic); |
856 |
|
857 |
PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview); |
858 |
|
859 |
/* piix_pci.c */
|
860 |
PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic); |
861 |
void i440fx_set_smm(PCIDevice *d, int val); |
862 |
int piix3_init(PCIBus *bus, int devfn); |
863 |
void i440fx_init_memory_mappings(PCIDevice *d);
|
864 |
|
865 |
int piix4_init(PCIBus *bus, int devfn); |
866 |
|
867 |
/* openpic.c */
|
868 |
/* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
|
869 |
enum {
|
870 |
OPENPIC_OUTPUT_INT = 0, /* IRQ */ |
871 |
OPENPIC_OUTPUT_CINT, /* critical IRQ */
|
872 |
OPENPIC_OUTPUT_MCK, /* Machine check event */
|
873 |
OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */
|
874 |
OPENPIC_OUTPUT_RESET, /* Core reset event */
|
875 |
OPENPIC_OUTPUT_NB, |
876 |
}; |
877 |
qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus, |
878 |
qemu_irq **irqs, qemu_irq irq_out); |
879 |
|
880 |
/* heathrow_pic.c */
|
881 |
qemu_irq *heathrow_pic_init(int *pmem_index);
|
882 |
|
883 |
/* gt64xxx.c */
|
884 |
PCIBus *pci_gt64120_init(qemu_irq *pic); |
885 |
|
886 |
#ifdef HAS_AUDIO
|
887 |
struct soundhw {
|
888 |
const char *name; |
889 |
const char *descr; |
890 |
int enabled;
|
891 |
int isa;
|
892 |
union {
|
893 |
int (*init_isa) (AudioState *s, qemu_irq *pic);
|
894 |
int (*init_pci) (PCIBus *bus, AudioState *s);
|
895 |
} init; |
896 |
}; |
897 |
|
898 |
extern struct soundhw soundhw[]; |
899 |
#endif
|
900 |
|
901 |
/* vga.c */
|
902 |
|
903 |
#ifndef TARGET_SPARC
|
904 |
#define VGA_RAM_SIZE (8192 * 1024) |
905 |
#else
|
906 |
#define VGA_RAM_SIZE (9 * 1024 * 1024) |
907 |
#endif
|
908 |
|
909 |
struct DisplayState {
|
910 |
uint8_t *data; |
911 |
int linesize;
|
912 |
int depth;
|
913 |
int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */ |
914 |
int width;
|
915 |
int height;
|
916 |
void *opaque;
|
917 |
|
918 |
void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h); |
919 |
void (*dpy_resize)(struct DisplayState *s, int w, int h); |
920 |
void (*dpy_refresh)(struct DisplayState *s); |
921 |
void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y, |
922 |
int dst_x, int dst_y, int w, int h); |
923 |
void (*dpy_fill)(struct DisplayState *s, int x, int y, |
924 |
int w, int h, uint32_t c); |
925 |
void (*mouse_set)(int x, int y, int on); |
926 |
void (*cursor_define)(int width, int height, int bpp, int hot_x, int hot_y, |
927 |
uint8_t *image, uint8_t *mask); |
928 |
}; |
929 |
|
930 |
static inline void dpy_update(DisplayState *s, int x, int y, int w, int h) |
931 |
{ |
932 |
s->dpy_update(s, x, y, w, h); |
933 |
} |
934 |
|
935 |
static inline void dpy_resize(DisplayState *s, int w, int h) |
936 |
{ |
937 |
s->dpy_resize(s, w, h); |
938 |
} |
939 |
|
940 |
int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
|
941 |
unsigned long vga_ram_offset, int vga_ram_size); |
942 |
int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
|
943 |
unsigned long vga_ram_offset, int vga_ram_size, |
944 |
unsigned long vga_bios_offset, int vga_bios_size); |
945 |
int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
|
946 |
unsigned long vga_ram_offset, int vga_ram_size, |
947 |
target_phys_addr_t vram_base, target_phys_addr_t ctrl_base, |
948 |
int it_shift);
|
949 |
|
950 |
/* cirrus_vga.c */
|
951 |
void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
|
952 |
unsigned long vga_ram_offset, int vga_ram_size); |
953 |
void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
|
954 |
unsigned long vga_ram_offset, int vga_ram_size); |
955 |
|
956 |
/* vmware_vga.c */
|
957 |
void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
|
958 |
unsigned long vga_ram_offset, int vga_ram_size); |
959 |
|
960 |
/* sdl.c */
|
961 |
void sdl_display_init(DisplayState *ds, int full_screen, int no_frame); |
962 |
|
963 |
/* cocoa.m */
|
964 |
void cocoa_display_init(DisplayState *ds, int full_screen); |
965 |
|
966 |
/* vnc.c */
|
967 |
void vnc_display_init(DisplayState *ds, const char *display); |
968 |
void do_info_vnc(void); |
969 |
|
970 |
/* x_keymap.c */
|
971 |
extern uint8_t _translate_keycode(const int key); |
972 |
|
973 |
/* ide.c */
|
974 |
#define MAX_DISKS 4 |
975 |
|
976 |
extern BlockDriverState *bs_table[MAX_DISKS + 1]; |
977 |
extern BlockDriverState *sd_bdrv;
|
978 |
extern BlockDriverState *mtd_bdrv;
|
979 |
|
980 |
void isa_ide_init(int iobase, int iobase2, qemu_irq irq, |
981 |
BlockDriverState *hd0, BlockDriverState *hd1); |
982 |
void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
|
983 |
int secondary_ide_enabled);
|
984 |
void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn, |
985 |
qemu_irq *pic); |
986 |
int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq);
|
987 |
|
988 |
/* cdrom.c */
|
989 |
int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track); |
990 |
int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num); |
991 |
|
992 |
/* ds1225y.c */
|
993 |
typedef struct ds1225y_t ds1225y_t; |
994 |
ds1225y_t *ds1225y_init(target_ulong mem_base, const char *filename); |
995 |
|
996 |
/* es1370.c */
|
997 |
int es1370_init (PCIBus *bus, AudioState *s);
|
998 |
|
999 |
/* sb16.c */
|
1000 |
int SB16_init (AudioState *s, qemu_irq *pic);
|
1001 |
|
1002 |
/* adlib.c */
|
1003 |
int Adlib_init (AudioState *s, qemu_irq *pic);
|
1004 |
|
1005 |
/* gus.c */
|
1006 |
int GUS_init (AudioState *s, qemu_irq *pic);
|
1007 |
|
1008 |
/* dma.c */
|
1009 |
typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size); |
1010 |
int DMA_get_channel_mode (int nchan); |
1011 |
int DMA_read_memory (int nchan, void *buf, int pos, int size); |
1012 |
int DMA_write_memory (int nchan, void *buf, int pos, int size); |
1013 |
void DMA_hold_DREQ (int nchan); |
1014 |
void DMA_release_DREQ (int nchan); |
1015 |
void DMA_schedule(int nchan); |
1016 |
void DMA_run (void); |
1017 |
void DMA_init (int high_page_enable); |
1018 |
void DMA_register_channel (int nchan, |
1019 |
DMA_transfer_handler transfer_handler, |
1020 |
void *opaque);
|
1021 |
/* fdc.c */
|
1022 |
#define MAX_FD 2 |
1023 |
extern BlockDriverState *fd_table[MAX_FD];
|
1024 |
|
1025 |
typedef struct fdctrl_t fdctrl_t; |
1026 |
|
1027 |
fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped, |
1028 |
target_phys_addr_t io_base, |
1029 |
BlockDriverState **fds); |
1030 |
int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num); |
1031 |
|
1032 |
/* eepro100.c */
|
1033 |
|
1034 |
void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn); |
1035 |
void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn); |
1036 |
void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn); |
1037 |
|
1038 |
/* ne2000.c */
|
1039 |
|
1040 |
void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd); |
1041 |
void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn); |
1042 |
|
1043 |
/* rtl8139.c */
|
1044 |
|
1045 |
void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn); |
1046 |
|
1047 |
/* pcnet.c */
|
1048 |
|
1049 |
void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn); |
1050 |
void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque, |
1051 |
qemu_irq irq); |
1052 |
|
1053 |
/* vmmouse.c */
|
1054 |
void *vmmouse_init(void *m); |
1055 |
|
1056 |
/* pckbd.c */
|
1057 |
|
1058 |
void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
|
1059 |
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, target_ulong base, int it_shift); |
1060 |
|
1061 |
/* mc146818rtc.c */
|
1062 |
|
1063 |
typedef struct RTCState RTCState; |
1064 |
|
1065 |
RTCState *rtc_init(int base, qemu_irq irq);
|
1066 |
RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
|
1067 |
void rtc_set_memory(RTCState *s, int addr, int val); |
1068 |
void rtc_set_date(RTCState *s, const struct tm *tm); |
1069 |
|
1070 |
/* serial.c */
|
1071 |
|
1072 |
typedef struct SerialState SerialState; |
1073 |
SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr);
|
1074 |
SerialState *serial_mm_init (target_ulong base, int it_shift,
|
1075 |
qemu_irq irq, CharDriverState *chr, |
1076 |
int ioregister);
|
1077 |
uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
|
1078 |
void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value); |
1079 |
uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
|
1080 |
void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value); |
1081 |
uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
|
1082 |
void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value); |
1083 |
|
1084 |
/* parallel.c */
|
1085 |
|
1086 |
typedef struct ParallelState ParallelState; |
1087 |
ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
|
1088 |
|
1089 |
/* i8259.c */
|
1090 |
|
1091 |
typedef struct PicState2 PicState2; |
1092 |
extern PicState2 *isa_pic;
|
1093 |
void pic_set_irq(int irq, int level); |
1094 |
void pic_set_irq_new(void *opaque, int irq, int level); |
1095 |
qemu_irq *i8259_init(qemu_irq parent_irq); |
1096 |
void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
|
1097 |
void *alt_irq_opaque);
|
1098 |
int pic_read_irq(PicState2 *s);
|
1099 |
void pic_update_irq(PicState2 *s);
|
1100 |
uint32_t pic_intack_read(PicState2 *s); |
1101 |
void pic_info(void); |
1102 |
void irq_info(void); |
1103 |
|
1104 |
/* APIC */
|
1105 |
typedef struct IOAPICState IOAPICState; |
1106 |
|
1107 |
int apic_init(CPUState *env);
|
1108 |
int apic_get_interrupt(CPUState *env);
|
1109 |
IOAPICState *ioapic_init(void);
|
1110 |
void ioapic_set_irq(void *opaque, int vector, int level); |
1111 |
|
1112 |
/* i8254.c */
|
1113 |
|
1114 |
#define PIT_FREQ 1193182 |
1115 |
|
1116 |
typedef struct PITState PITState; |
1117 |
|
1118 |
PITState *pit_init(int base, qemu_irq irq);
|
1119 |
void pit_set_gate(PITState *pit, int channel, int val); |
1120 |
int pit_get_gate(PITState *pit, int channel); |
1121 |
int pit_get_initial_count(PITState *pit, int channel); |
1122 |
int pit_get_mode(PITState *pit, int channel); |
1123 |
int pit_get_out(PITState *pit, int channel, int64_t current_time); |
1124 |
|
1125 |
/* pcspk.c */
|
1126 |
void pcspk_init(PITState *);
|
1127 |
int pcspk_audio_init(AudioState *, qemu_irq *pic);
|
1128 |
|
1129 |
#include "hw/i2c.h" |
1130 |
|
1131 |
#include "hw/smbus.h" |
1132 |
|
1133 |
/* acpi.c */
|
1134 |
extern int acpi_enabled; |
1135 |
i2c_bus *piix4_pm_init(PCIBus *bus, int devfn);
|
1136 |
void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
|
1137 |
void acpi_bios_init(void); |
1138 |
|
1139 |
/* pc.c */
|
1140 |
extern QEMUMachine pc_machine;
|
1141 |
extern QEMUMachine isapc_machine;
|
1142 |
extern int fd_bootchk; |
1143 |
|
1144 |
void ioport_set_a20(int enable); |
1145 |
int ioport_get_a20(void); |
1146 |
|
1147 |
/* ppc.c */
|
1148 |
extern QEMUMachine prep_machine;
|
1149 |
extern QEMUMachine core99_machine;
|
1150 |
extern QEMUMachine heathrow_machine;
|
1151 |
extern QEMUMachine ref405ep_machine;
|
1152 |
extern QEMUMachine taihu_machine;
|
1153 |
|
1154 |
/* mips_r4k.c */
|
1155 |
extern QEMUMachine mips_machine;
|
1156 |
|
1157 |
/* mips_malta.c */
|
1158 |
extern QEMUMachine mips_malta_machine;
|
1159 |
|
1160 |
/* mips_int.c */
|
1161 |
extern void cpu_mips_irq_init_cpu(CPUState *env); |
1162 |
|
1163 |
/* mips_pica61.c */
|
1164 |
extern QEMUMachine mips_pica61_machine;
|
1165 |
|
1166 |
/* mips_timer.c */
|
1167 |
extern void cpu_mips_clock_init(CPUState *); |
1168 |
extern void cpu_mips_irqctrl_init (void); |
1169 |
|
1170 |
/* shix.c */
|
1171 |
extern QEMUMachine shix_machine;
|
1172 |
|
1173 |
#ifdef TARGET_PPC
|
1174 |
/* PowerPC hardware exceptions management helpers */
|
1175 |
typedef void (*clk_setup_cb)(void *opaque, uint32_t freq); |
1176 |
typedef struct clk_setup_t clk_setup_t; |
1177 |
struct clk_setup_t {
|
1178 |
clk_setup_cb cb; |
1179 |
void *opaque;
|
1180 |
}; |
1181 |
static inline void clk_setup (clk_setup_t *clk, uint32_t freq) |
1182 |
{ |
1183 |
if (clk->cb != NULL) |
1184 |
(*clk->cb)(clk->opaque, freq); |
1185 |
} |
1186 |
|
1187 |
clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq); |
1188 |
/* Embedded PowerPC DCR management */
|
1189 |
typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn); |
1190 |
typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val); |
1191 |
int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn), |
1192 |
int (*dcr_write_error)(int dcrn)); |
1193 |
int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, |
1194 |
dcr_read_cb drc_read, dcr_write_cb dcr_write); |
1195 |
clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq); |
1196 |
/* Embedded PowerPC reset */
|
1197 |
void ppc40x_core_reset (CPUState *env);
|
1198 |
void ppc40x_chip_reset (CPUState *env);
|
1199 |
void ppc40x_system_reset (CPUState *env);
|
1200 |
#endif
|
1201 |
void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val); |
1202 |
|
1203 |
extern CPUWriteMemoryFunc *PPC_io_write[];
|
1204 |
extern CPUReadMemoryFunc *PPC_io_read[];
|
1205 |
void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val); |
1206 |
|
1207 |
/* sun4m.c */
|
1208 |
extern QEMUMachine ss5_machine, ss10_machine;
|
1209 |
|
1210 |
/* iommu.c */
|
1211 |
void *iommu_init(target_phys_addr_t addr);
|
1212 |
void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr, |
1213 |
uint8_t *buf, int len, int is_write); |
1214 |
static inline void sparc_iommu_memory_read(void *opaque, |
1215 |
target_phys_addr_t addr, |
1216 |
uint8_t *buf, int len)
|
1217 |
{ |
1218 |
sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
|
1219 |
} |
1220 |
|
1221 |
static inline void sparc_iommu_memory_write(void *opaque, |
1222 |
target_phys_addr_t addr, |
1223 |
uint8_t *buf, int len)
|
1224 |
{ |
1225 |
sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
|
1226 |
} |
1227 |
|
1228 |
/* tcx.c */
|
1229 |
void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
|
1230 |
unsigned long vram_offset, int vram_size, int width, int height, |
1231 |
int depth);
|
1232 |
|
1233 |
/* slavio_intctl.c */
|
1234 |
void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
|
1235 |
const uint32_t *intbit_to_level,
|
1236 |
qemu_irq **irq, qemu_irq **cpu_irq, |
1237 |
qemu_irq **parent_irq, unsigned int cputimer); |
1238 |
void slavio_pic_info(void *opaque); |
1239 |
void slavio_irq_info(void *opaque); |
1240 |
|
1241 |
/* loader.c */
|
1242 |
int get_image_size(const char *filename); |
1243 |
int load_image(const char *filename, uint8_t *addr); |
1244 |
int load_elf(const char *filename, int64_t virt_to_phys_addend, |
1245 |
uint64_t *pentry, uint64_t *lowaddr, uint64_t *highaddr); |
1246 |
int load_aout(const char *filename, uint8_t *addr); |
1247 |
int load_uboot(const char *filename, target_ulong *ep, int *is_linux); |
1248 |
|
1249 |
/* slavio_timer.c */
|
1250 |
void slavio_timer_init(target_phys_addr_t addr, qemu_irq irq, int mode); |
1251 |
|
1252 |
/* slavio_serial.c */
|
1253 |
SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq, |
1254 |
CharDriverState *chr1, CharDriverState *chr2); |
1255 |
void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq);
|
1256 |
|
1257 |
/* slavio_misc.c */
|
1258 |
void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
|
1259 |
qemu_irq irq); |
1260 |
void slavio_set_power_fail(void *opaque, int power_failing); |
1261 |
|
1262 |
/* esp.c */
|
1263 |
void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id); |
1264 |
void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
|
1265 |
void *dma_opaque, qemu_irq irq);
|
1266 |
|
1267 |
/* sparc32_dma.c */
|
1268 |
void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
|
1269 |
void *iommu, qemu_irq **dev_irq);
|
1270 |
void ledma_memory_read(void *opaque, target_phys_addr_t addr, |
1271 |
uint8_t *buf, int len, int do_bswap); |
1272 |
void ledma_memory_write(void *opaque, target_phys_addr_t addr, |
1273 |
uint8_t *buf, int len, int do_bswap); |
1274 |
void espdma_memory_read(void *opaque, uint8_t *buf, int len); |
1275 |
void espdma_memory_write(void *opaque, uint8_t *buf, int len); |
1276 |
void sparc32_dma_set_reset_data(void *opaque, void (*dev_reset)(void *opaque), |
1277 |
void *dev_opaque);
|
1278 |
|
1279 |
/* cs4231.c */
|
1280 |
void cs_init(target_phys_addr_t base, int irq, void *intctl); |
1281 |
|
1282 |
/* sun4u.c */
|
1283 |
extern QEMUMachine sun4u_machine;
|
1284 |
|
1285 |
/* NVRAM helpers */
|
1286 |
#include "hw/m48t59.h" |
1287 |
|
1288 |
void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value);
|
1289 |
uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr); |
1290 |
void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value);
|
1291 |
uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr); |
1292 |
void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value);
|
1293 |
uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr); |
1294 |
void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
|
1295 |
const unsigned char *str, uint32_t max); |
1296 |
int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max); |
1297 |
void NVRAM_set_crc (m48t59_t *nvram, uint32_t addr,
|
1298 |
uint32_t start, uint32_t count); |
1299 |
int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
|
1300 |
const unsigned char *arch, |
1301 |
uint32_t RAM_size, int boot_device,
|
1302 |
uint32_t kernel_image, uint32_t kernel_size, |
1303 |
const char *cmdline, |
1304 |
uint32_t initrd_image, uint32_t initrd_size, |
1305 |
uint32_t NVRAM_image, |
1306 |
int width, int height, int depth); |
1307 |
|
1308 |
/* adb.c */
|
1309 |
|
1310 |
#define MAX_ADB_DEVICES 16 |
1311 |
|
1312 |
#define ADB_MAX_OUT_LEN 16 |
1313 |
|
1314 |
typedef struct ADBDevice ADBDevice; |
1315 |
|
1316 |
/* buf = NULL means polling */
|
1317 |
typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out, |
1318 |
const uint8_t *buf, int len); |
1319 |
typedef int ADBDeviceReset(ADBDevice *d); |
1320 |
|
1321 |
struct ADBDevice {
|
1322 |
struct ADBBusState *bus;
|
1323 |
int devaddr;
|
1324 |
int handler;
|
1325 |
ADBDeviceRequest *devreq; |
1326 |
ADBDeviceReset *devreset; |
1327 |
void *opaque;
|
1328 |
}; |
1329 |
|
1330 |
typedef struct ADBBusState { |
1331 |
ADBDevice devices[MAX_ADB_DEVICES]; |
1332 |
int nb_devices;
|
1333 |
int poll_index;
|
1334 |
} ADBBusState; |
1335 |
|
1336 |
int adb_request(ADBBusState *s, uint8_t *buf_out,
|
1337 |
const uint8_t *buf, int len); |
1338 |
int adb_poll(ADBBusState *s, uint8_t *buf_out);
|
1339 |
|
1340 |
ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
|
1341 |
ADBDeviceRequest *devreq, |
1342 |
ADBDeviceReset *devreset, |
1343 |
void *opaque);
|
1344 |
void adb_kbd_init(ADBBusState *bus);
|
1345 |
void adb_mouse_init(ADBBusState *bus);
|
1346 |
|
1347 |
/* cuda.c */
|
1348 |
|
1349 |
extern ADBBusState adb_bus;
|
1350 |
int cuda_init(qemu_irq irq);
|
1351 |
|
1352 |
#include "hw/usb.h" |
1353 |
|
1354 |
/* usb ports of the VM */
|
1355 |
|
1356 |
void qemu_register_usb_port(USBPort *port, void *opaque, int index, |
1357 |
usb_attachfn attach); |
1358 |
|
1359 |
#define VM_USB_HUB_SIZE 8 |
1360 |
|
1361 |
void do_usb_add(const char *devname); |
1362 |
void do_usb_del(const char *devname); |
1363 |
void usb_info(void); |
1364 |
|
1365 |
/* scsi-disk.c */
|
1366 |
enum scsi_reason {
|
1367 |
SCSI_REASON_DONE, /* Command complete. */
|
1368 |
SCSI_REASON_DATA /* Transfer complete, more data required. */
|
1369 |
}; |
1370 |
|
1371 |
typedef struct SCSIDevice SCSIDevice; |
1372 |
typedef void (*scsi_completionfn)(void *opaque, int reason, uint32_t tag, |
1373 |
uint32_t arg); |
1374 |
|
1375 |
SCSIDevice *scsi_disk_init(BlockDriverState *bdrv, |
1376 |
int tcq,
|
1377 |
scsi_completionfn completion, |
1378 |
void *opaque);
|
1379 |
void scsi_disk_destroy(SCSIDevice *s);
|
1380 |
|
1381 |
int32_t scsi_send_command(SCSIDevice *s, uint32_t tag, uint8_t *buf, int lun);
|
1382 |
/* SCSI data transfers are asynchrnonous. However, unlike the block IO
|
1383 |
layer the completion routine may be called directly by
|
1384 |
scsi_{read,write}_data. */
|
1385 |
void scsi_read_data(SCSIDevice *s, uint32_t tag);
|
1386 |
int scsi_write_data(SCSIDevice *s, uint32_t tag);
|
1387 |
void scsi_cancel_io(SCSIDevice *s, uint32_t tag);
|
1388 |
uint8_t *scsi_get_buf(SCSIDevice *s, uint32_t tag); |
1389 |
|
1390 |
/* lsi53c895a.c */
|
1391 |
void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id); |
1392 |
void *lsi_scsi_init(PCIBus *bus, int devfn); |
1393 |
|
1394 |
/* integratorcp.c */
|
1395 |
extern QEMUMachine integratorcp_machine;
|
1396 |
|
1397 |
/* versatilepb.c */
|
1398 |
extern QEMUMachine versatilepb_machine;
|
1399 |
extern QEMUMachine versatileab_machine;
|
1400 |
|
1401 |
/* realview.c */
|
1402 |
extern QEMUMachine realview_machine;
|
1403 |
|
1404 |
/* spitz.c */
|
1405 |
extern QEMUMachine akitapda_machine;
|
1406 |
extern QEMUMachine spitzpda_machine;
|
1407 |
extern QEMUMachine borzoipda_machine;
|
1408 |
extern QEMUMachine terrierpda_machine;
|
1409 |
|
1410 |
/* ps2.c */
|
1411 |
void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg); |
1412 |
void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg); |
1413 |
void ps2_write_mouse(void *, int val); |
1414 |
void ps2_write_keyboard(void *, int val); |
1415 |
uint32_t ps2_read_data(void *);
|
1416 |
void ps2_queue(void *, int b); |
1417 |
void ps2_keyboard_set_translation(void *opaque, int mode); |
1418 |
void ps2_mouse_fake_event(void *opaque); |
1419 |
|
1420 |
/* smc91c111.c */
|
1421 |
void smc91c111_init(NICInfo *, uint32_t, qemu_irq);
|
1422 |
|
1423 |
/* pl110.c */
|
1424 |
void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq, int); |
1425 |
|
1426 |
/* pl011.c */
|
1427 |
void pl011_init(uint32_t base, qemu_irq irq, CharDriverState *chr);
|
1428 |
|
1429 |
/* pl050.c */
|
1430 |
void pl050_init(uint32_t base, qemu_irq irq, int is_mouse); |
1431 |
|
1432 |
/* pl080.c */
|
1433 |
void *pl080_init(uint32_t base, qemu_irq irq, int nchannels); |
1434 |
|
1435 |
/* pl181.c */
|
1436 |
void pl181_init(uint32_t base, BlockDriverState *bd,
|
1437 |
qemu_irq irq0, qemu_irq irq1); |
1438 |
|
1439 |
/* pl190.c */
|
1440 |
qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq); |
1441 |
|
1442 |
/* arm-timer.c */
|
1443 |
void sp804_init(uint32_t base, qemu_irq irq);
|
1444 |
void icp_pit_init(uint32_t base, qemu_irq *pic, int irq); |
1445 |
|
1446 |
/* arm_sysctl.c */
|
1447 |
void arm_sysctl_init(uint32_t base, uint32_t sys_id);
|
1448 |
|
1449 |
/* arm_gic.c */
|
1450 |
qemu_irq *arm_gic_init(uint32_t base, qemu_irq parent_irq); |
1451 |
|
1452 |
/* arm_boot.c */
|
1453 |
|
1454 |
void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename, |
1455 |
const char *kernel_cmdline, const char *initrd_filename, |
1456 |
int board_id, target_phys_addr_t loader_start);
|
1457 |
|
1458 |
/* sh7750.c */
|
1459 |
struct SH7750State;
|
1460 |
|
1461 |
struct SH7750State *sh7750_init(CPUState * cpu);
|
1462 |
|
1463 |
typedef struct { |
1464 |
/* The callback will be triggered if any of the designated lines change */
|
1465 |
uint16_t portamask_trigger; |
1466 |
uint16_t portbmask_trigger; |
1467 |
/* Return 0 if no action was taken */
|
1468 |
int (*port_change_cb) (uint16_t porta, uint16_t portb,
|
1469 |
uint16_t * periph_pdtra, |
1470 |
uint16_t * periph_portdira, |
1471 |
uint16_t * periph_pdtrb, |
1472 |
uint16_t * periph_portdirb); |
1473 |
} sh7750_io_device; |
1474 |
|
1475 |
int sh7750_register_io_device(struct SH7750State *s, |
1476 |
sh7750_io_device * device); |
1477 |
/* tc58128.c */
|
1478 |
int tc58128_init(struct SH7750State *s, char *zone1, char *zone2); |
1479 |
|
1480 |
/* NOR flash devices */
|
1481 |
#define MAX_PFLASH 4 |
1482 |
extern BlockDriverState *pflash_table[MAX_PFLASH];
|
1483 |
typedef struct pflash_t pflash_t; |
1484 |
|
1485 |
pflash_t *pflash_register (target_ulong base, ram_addr_t off, |
1486 |
BlockDriverState *bs, |
1487 |
target_ulong sector_len, int nb_blocs, int width, |
1488 |
uint16_t id0, uint16_t id1, |
1489 |
uint16_t id2, uint16_t id3); |
1490 |
|
1491 |
/* nand.c */
|
1492 |
struct nand_flash_s;
|
1493 |
struct nand_flash_s *nand_init(int manf_id, int chip_id); |
1494 |
void nand_done(struct nand_flash_s *s); |
1495 |
void nand_setpins(struct nand_flash_s *s, |
1496 |
int cle, int ale, int ce, int wp, int gnd); |
1497 |
void nand_getpins(struct nand_flash_s *s, int *rb); |
1498 |
void nand_setio(struct nand_flash_s *s, uint8_t value); |
1499 |
uint8_t nand_getio(struct nand_flash_s *s);
|
1500 |
|
1501 |
#define NAND_MFR_TOSHIBA 0x98 |
1502 |
#define NAND_MFR_SAMSUNG 0xec |
1503 |
#define NAND_MFR_FUJITSU 0x04 |
1504 |
#define NAND_MFR_NATIONAL 0x8f |
1505 |
#define NAND_MFR_RENESAS 0x07 |
1506 |
#define NAND_MFR_STMICRO 0x20 |
1507 |
#define NAND_MFR_HYNIX 0xad |
1508 |
#define NAND_MFR_MICRON 0x2c |
1509 |
|
1510 |
#include "ecc.h" |
1511 |
|
1512 |
/* GPIO */
|
1513 |
typedef void (*gpio_handler_t)(int line, int level, void *opaque); |
1514 |
|
1515 |
/* ads7846.c */
|
1516 |
struct ads7846_state_s;
|
1517 |
uint32_t ads7846_read(void *opaque);
|
1518 |
void ads7846_write(void *opaque, uint32_t value); |
1519 |
struct ads7846_state_s *ads7846_init(qemu_irq penirq);
|
1520 |
|
1521 |
/* max111x.c */
|
1522 |
struct max111x_s;
|
1523 |
uint32_t max111x_read(void *opaque);
|
1524 |
void max111x_write(void *opaque, uint32_t value); |
1525 |
struct max111x_s *max1110_init(qemu_irq cb);
|
1526 |
struct max111x_s *max1111_init(qemu_irq cb);
|
1527 |
void max111x_set_input(struct max111x_s *s, int line, uint8_t value); |
1528 |
|
1529 |
/* PCMCIA/Cardbus */
|
1530 |
|
1531 |
struct pcmcia_socket_s {
|
1532 |
qemu_irq irq; |
1533 |
int attached;
|
1534 |
const char *slot_string; |
1535 |
const char *card_string; |
1536 |
}; |
1537 |
|
1538 |
void pcmcia_socket_register(struct pcmcia_socket_s *socket); |
1539 |
void pcmcia_socket_unregister(struct pcmcia_socket_s *socket); |
1540 |
void pcmcia_info(void); |
1541 |
|
1542 |
struct pcmcia_card_s {
|
1543 |
void *state;
|
1544 |
struct pcmcia_socket_s *slot;
|
1545 |
int (*attach)(void *state); |
1546 |
int (*detach)(void *state); |
1547 |
const uint8_t *cis;
|
1548 |
int cis_len;
|
1549 |
|
1550 |
/* Only valid if attached */
|
1551 |
uint8_t (*attr_read)(void *state, uint32_t address);
|
1552 |
void (*attr_write)(void *state, uint32_t address, uint8_t value); |
1553 |
uint16_t (*common_read)(void *state, uint32_t address);
|
1554 |
void (*common_write)(void *state, uint32_t address, uint16_t value); |
1555 |
uint16_t (*io_read)(void *state, uint32_t address);
|
1556 |
void (*io_write)(void *state, uint32_t address, uint16_t value); |
1557 |
}; |
1558 |
|
1559 |
#define CISTPL_DEVICE 0x01 /* 5V Device Information Tuple */ |
1560 |
#define CISTPL_NO_LINK 0x14 /* No Link Tuple */ |
1561 |
#define CISTPL_VERS_1 0x15 /* Level 1 Version Tuple */ |
1562 |
#define CISTPL_JEDEC_C 0x18 /* JEDEC ID Tuple */ |
1563 |
#define CISTPL_JEDEC_A 0x19 /* JEDEC ID Tuple */ |
1564 |
#define CISTPL_CONFIG 0x1a /* Configuration Tuple */ |
1565 |
#define CISTPL_CFTABLE_ENTRY 0x1b /* 16-bit PCCard Configuration */ |
1566 |
#define CISTPL_DEVICE_OC 0x1c /* Additional Device Information */ |
1567 |
#define CISTPL_DEVICE_OA 0x1d /* Additional Device Information */ |
1568 |
#define CISTPL_DEVICE_GEO 0x1e /* Additional Device Information */ |
1569 |
#define CISTPL_DEVICE_GEO_A 0x1f /* Additional Device Information */ |
1570 |
#define CISTPL_MANFID 0x20 /* Manufacture ID Tuple */ |
1571 |
#define CISTPL_FUNCID 0x21 /* Function ID Tuple */ |
1572 |
#define CISTPL_FUNCE 0x22 /* Function Extension Tuple */ |
1573 |
#define CISTPL_END 0xff /* Tuple End */ |
1574 |
#define CISTPL_ENDMARK 0xff |
1575 |
|
1576 |
/* dscm1xxxx.c */
|
1577 |
struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv);
|
1578 |
|
1579 |
/* ptimer.c */
|
1580 |
typedef struct ptimer_state ptimer_state; |
1581 |
typedef void (*ptimer_cb)(void *opaque); |
1582 |
|
1583 |
ptimer_state *ptimer_init(QEMUBH *bh); |
1584 |
void ptimer_set_period(ptimer_state *s, int64_t period);
|
1585 |
void ptimer_set_freq(ptimer_state *s, uint32_t freq);
|
1586 |
void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload); |
1587 |
uint64_t ptimer_get_count(ptimer_state *s); |
1588 |
void ptimer_set_count(ptimer_state *s, uint64_t count);
|
1589 |
void ptimer_run(ptimer_state *s, int oneshot); |
1590 |
void ptimer_stop(ptimer_state *s);
|
1591 |
void qemu_put_ptimer(QEMUFile *f, ptimer_state *s);
|
1592 |
void qemu_get_ptimer(QEMUFile *f, ptimer_state *s);
|
1593 |
|
1594 |
#include "hw/pxa.h" |
1595 |
|
1596 |
/* mcf5206.c */
|
1597 |
qemu_irq *mcf5206_init(uint32_t base, CPUState *env); |
1598 |
|
1599 |
/* an5206.c */
|
1600 |
extern QEMUMachine an5206_machine;
|
1601 |
|
1602 |
#include "gdbstub.h" |
1603 |
|
1604 |
#endif /* defined(QEMU_TOOL) */ |
1605 |
|
1606 |
/* monitor.c */
|
1607 |
void monitor_init(CharDriverState *hd, int show_banner); |
1608 |
void term_puts(const char *str); |
1609 |
void term_vprintf(const char *fmt, va_list ap); |
1610 |
void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2))); |
1611 |
void term_print_filename(const char *filename); |
1612 |
void term_flush(void); |
1613 |
void term_print_help(void); |
1614 |
void monitor_readline(const char *prompt, int is_password, |
1615 |
char *buf, int buf_size); |
1616 |
|
1617 |
/* readline.c */
|
1618 |
typedef void ReadLineFunc(void *opaque, const char *str); |
1619 |
|
1620 |
extern int completion_index; |
1621 |
void add_completion(const char *str); |
1622 |
void readline_handle_byte(int ch); |
1623 |
void readline_find_completion(const char *cmdline); |
1624 |
const char *readline_get_history(unsigned int index); |
1625 |
void readline_start(const char *prompt, int is_password, |
1626 |
ReadLineFunc *readline_func, void *opaque);
|
1627 |
|
1628 |
void kqemu_record_dump(void); |
1629 |
|
1630 |
#endif /* VL_H */ |