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/*
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 * Toshiba TC6393XB I/O Controller.
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 * Found in Sharp Zaurus SL-6000 (tosa) or some
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 * Toshiba e-Series PDAs.
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 *
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 * Most features are currently unsupported!!!
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 *
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 * This code is licensed under the GNU GPL v2.
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 */
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#include "hw.h"
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#include "devices.h"
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#include "flash.h"
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#include "console.h"
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#include "pixel_ops.h"
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#define IRQ_TC6393_NAND                0
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#define IRQ_TC6393_MMC                1
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#define IRQ_TC6393_OHCI                2
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#define IRQ_TC6393_SERIAL        3
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#define IRQ_TC6393_FB                4
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#define        TC6393XB_NR_IRQS        8
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#define TC6393XB_GPIOS  16
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#define SCR_REVID        0x08                /* b Revision ID        */
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#define SCR_ISR                0x50                /* b Interrupt Status        */
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#define SCR_IMR                0x52                /* b Interrupt Mask        */
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#define SCR_IRR                0x54                /* b Interrupt Routing        */
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#define SCR_GPER        0x60                /* w GP Enable                */
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#define SCR_GPI_SR(i)        (0x64 + (i))        /* b3 GPI Status        */
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#define SCR_GPI_IMR(i)        (0x68 + (i))        /* b3 GPI INT Mask        */
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#define SCR_GPI_EDER(i)        (0x6c + (i))        /* b3 GPI Edge Detect Enable */
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#define SCR_GPI_LIR(i)        (0x70 + (i))        /* b3 GPI Level Invert        */
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#define SCR_GPO_DSR(i)        (0x78 + (i))        /* b3 GPO Data Set        */
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#define SCR_GPO_DOECR(i) (0x7c + (i))        /* b3 GPO Data OE Control */
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#define SCR_GP_IARCR(i)        (0x80 + (i))        /* b3 GP Internal Active Register Control */
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#define SCR_GP_IARLCR(i) (0x84 + (i))        /* b3 GP INTERNAL Active Register Level Control */
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#define SCR_GPI_BCR(i)        (0x88 + (i))        /* b3 GPI Buffer Control */
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#define SCR_GPA_IARCR        0x8c                /* w GPa Internal Active Register Control */
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#define SCR_GPA_IARLCR        0x90                /* w GPa Internal Active Register Level Control */
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#define SCR_GPA_BCR        0x94                /* w GPa Buffer Control */
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#define SCR_CCR                0x98                /* w Clock Control        */
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#define SCR_PLL2CR        0x9a                /* w PLL2 Control        */
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#define SCR_PLL1CR        0x9c                /* l PLL1 Control        */
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#define SCR_DIARCR        0xa0                /* b Device Internal Active Register Control */
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#define SCR_DBOCR        0xa1                /* b Device Buffer Off Control */
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#define SCR_FER                0xe0                /* b Function Enable        */
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#define SCR_MCR                0xe4                /* w Mode Control        */
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#define SCR_CONFIG        0xfc                /* b Configuration Control */
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#define SCR_DEBUG        0xff                /* b Debug                */
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#define NAND_CFG_COMMAND    0x04    /* w Command        */
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#define NAND_CFG_BASE       0x10    /* l Control Base Address */
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#define NAND_CFG_INTP       0x3d    /* b Interrupt Pin  */
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#define NAND_CFG_INTE       0x48    /* b Int Enable     */
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#define NAND_CFG_EC         0x4a    /* b Event Control  */
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#define NAND_CFG_ICC        0x4c    /* b Internal Clock Control */
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#define NAND_CFG_ECCC       0x5b    /* b ECC Control    */
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#define NAND_CFG_NFTC       0x60    /* b NAND Flash Transaction Control */
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#define NAND_CFG_NFM        0x61    /* b NAND Flash Monitor */
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#define NAND_CFG_NFPSC      0x62    /* b NAND Flash Power Supply Control */
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#define NAND_CFG_NFDC       0x63    /* b NAND Flash Detect Control */
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#define NAND_DATA   0x00        /* l Data       */
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#define NAND_MODE   0x04        /* b Mode       */
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#define NAND_STATUS 0x05        /* b Status     */
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#define NAND_ISR    0x06        /* b Interrupt Status */
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#define NAND_IMR    0x07        /* b Interrupt Mask */
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#define NAND_MODE_WP        0x80
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#define NAND_MODE_CE        0x10
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#define NAND_MODE_ALE       0x02
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#define NAND_MODE_CLE       0x01
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#define NAND_MODE_ECC_MASK  0x60
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#define NAND_MODE_ECC_EN    0x20
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#define NAND_MODE_ECC_READ  0x40
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#define NAND_MODE_ECC_RST   0x60
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struct TC6393xbState {
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    qemu_irq irq;
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    qemu_irq *sub_irqs;
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    struct {
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        uint8_t ISR;
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        uint8_t IMR;
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        uint8_t IRR;
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        uint16_t GPER;
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        uint8_t GPI_SR[3];
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        uint8_t GPI_IMR[3];
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        uint8_t GPI_EDER[3];
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        uint8_t GPI_LIR[3];
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        uint8_t GP_IARCR[3];
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        uint8_t GP_IARLCR[3];
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        uint8_t GPI_BCR[3];
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        uint16_t GPA_IARCR;
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        uint16_t GPA_IARLCR;
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        uint16_t CCR;
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        uint16_t PLL2CR;
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        uint32_t PLL1CR;
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        uint8_t DIARCR;
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        uint8_t DBOCR;
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        uint8_t FER;
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        uint16_t MCR;
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        uint8_t CONFIG;
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        uint8_t DEBUG;
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    } scr;
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    uint32_t gpio_dir;
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    uint32_t gpio_level;
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    uint32_t prev_level;
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    qemu_irq handler[TC6393XB_GPIOS];
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    qemu_irq *gpio_in;
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    struct {
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        uint8_t mode;
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        uint8_t isr;
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        uint8_t imr;
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    } nand;
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    int nand_enable;
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    uint32_t nand_phys;
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    NANDFlashState *flash;
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    ECCState ecc;
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    DisplayState *ds;
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    ram_addr_t vram_addr;
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    uint16_t *vram_ptr;
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    uint32_t scr_width, scr_height; /* in pixels */
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    qemu_irq l3v;
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    unsigned blank : 1,
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             blanked : 1;
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};
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qemu_irq *tc6393xb_gpio_in_get(TC6393xbState *s)
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{
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    return s->gpio_in;
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}
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static void tc6393xb_gpio_set(void *opaque, int line, int level)
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{
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//    TC6393xbState *s = opaque;
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    if (line > TC6393XB_GPIOS) {
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        printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
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        return;
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    }
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    // FIXME: how does the chip reflect the GPIO input level change?
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}
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void tc6393xb_gpio_out_set(TC6393xbState *s, int line,
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                    qemu_irq handler)
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{
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    if (line >= TC6393XB_GPIOS) {
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        fprintf(stderr, "TC6393xb: no GPIO pin %d\n", line);
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        return;
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    }
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    s->handler[line] = handler;
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}
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static void tc6393xb_gpio_handler_update(TC6393xbState *s)
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{
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    uint32_t level, diff;
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    int bit;
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    level = s->gpio_level & s->gpio_dir;
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    for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
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        bit = ffs(diff) - 1;
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        qemu_set_irq(s->handler[bit], (level >> bit) & 1);
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    }
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    s->prev_level = level;
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}
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qemu_irq tc6393xb_l3v_get(TC6393xbState *s)
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{
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    return s->l3v;
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}
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static void tc6393xb_l3v(void *opaque, int line, int level)
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{
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    TC6393xbState *s = opaque;
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    s->blank = !level;
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    fprintf(stderr, "L3V: %d\n", level);
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}
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static void tc6393xb_sub_irq(void *opaque, int line, int level) {
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    TC6393xbState *s = opaque;
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    uint8_t isr = s->scr.ISR;
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    if (level)
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        isr |= 1 << line;
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    else
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        isr &= ~(1 << line);
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    s->scr.ISR = isr;
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    qemu_set_irq(s->irq, isr & s->scr.IMR);
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}
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#define SCR_REG_B(N)                            \
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    case SCR_ ##N: return s->scr.N
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#define SCR_REG_W(N)                            \
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    case SCR_ ##N: return s->scr.N;             \
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    case SCR_ ##N + 1: return s->scr.N >> 8;
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#define SCR_REG_L(N)                            \
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    case SCR_ ##N: return s->scr.N;             \
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    case SCR_ ##N + 1: return s->scr.N >> 8;    \
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    case SCR_ ##N + 2: return s->scr.N >> 16;   \
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    case SCR_ ##N + 3: return s->scr.N >> 24;
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#define SCR_REG_A(N)                            \
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    case SCR_ ##N(0): return s->scr.N[0];       \
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    case SCR_ ##N(1): return s->scr.N[1];       \
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    case SCR_ ##N(2): return s->scr.N[2]
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static uint32_t tc6393xb_scr_readb(TC6393xbState *s, target_phys_addr_t addr)
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{
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    switch (addr) {
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        case SCR_REVID:
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            return 3;
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        case SCR_REVID+1:
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            return 0;
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        SCR_REG_B(ISR);
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        SCR_REG_B(IMR);
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        SCR_REG_B(IRR);
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        SCR_REG_W(GPER);
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        SCR_REG_A(GPI_SR);
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        SCR_REG_A(GPI_IMR);
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        SCR_REG_A(GPI_EDER);
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        SCR_REG_A(GPI_LIR);
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        case SCR_GPO_DSR(0):
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        case SCR_GPO_DSR(1):
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        case SCR_GPO_DSR(2):
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            return (s->gpio_level >> ((addr - SCR_GPO_DSR(0)) * 8)) & 0xff;
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        case SCR_GPO_DOECR(0):
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        case SCR_GPO_DOECR(1):
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        case SCR_GPO_DOECR(2):
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            return (s->gpio_dir >> ((addr - SCR_GPO_DOECR(0)) * 8)) & 0xff;
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        SCR_REG_A(GP_IARCR);
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        SCR_REG_A(GP_IARLCR);
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        SCR_REG_A(GPI_BCR);
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        SCR_REG_W(GPA_IARCR);
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        SCR_REG_W(GPA_IARLCR);
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        SCR_REG_W(CCR);
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        SCR_REG_W(PLL2CR);
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        SCR_REG_L(PLL1CR);
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        SCR_REG_B(DIARCR);
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        SCR_REG_B(DBOCR);
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        SCR_REG_B(FER);
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        SCR_REG_W(MCR);
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        SCR_REG_B(CONFIG);
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        SCR_REG_B(DEBUG);
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    }
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    fprintf(stderr, "tc6393xb_scr: unhandled read at %08x\n", (uint32_t) addr);
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    return 0;
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}
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#undef SCR_REG_B
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#undef SCR_REG_W
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#undef SCR_REG_L
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#undef SCR_REG_A
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#define SCR_REG_B(N)                                \
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    case SCR_ ##N: s->scr.N = value; return;
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#define SCR_REG_W(N)                                \
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    case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); return; \
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    case SCR_ ##N + 1: s->scr.N = (s->scr.N & 0xff) | (value << 8); return
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#define SCR_REG_L(N)                                \
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    case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); return;   \
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    case SCR_ ##N + 1: s->scr.N = (s->scr.N & ~(0xff << 8)) | (value & (0xff << 8)); return;     \
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    case SCR_ ##N + 2: s->scr.N = (s->scr.N & ~(0xff << 16)) | (value & (0xff << 16)); return;   \
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    case SCR_ ##N + 3: s->scr.N = (s->scr.N & ~(0xff << 24)) | (value & (0xff << 24)); return;
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#define SCR_REG_A(N)                                \
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    case SCR_ ##N(0): s->scr.N[0] = value; return;   \
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    case SCR_ ##N(1): s->scr.N[1] = value; return;   \
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    case SCR_ ##N(2): s->scr.N[2] = value; return
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static void tc6393xb_scr_writeb(TC6393xbState *s, target_phys_addr_t addr, uint32_t value)
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{
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    switch (addr) {
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        SCR_REG_B(ISR);
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        SCR_REG_B(IMR);
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        SCR_REG_B(IRR);
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        SCR_REG_W(GPER);
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        SCR_REG_A(GPI_SR);
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        SCR_REG_A(GPI_IMR);
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        SCR_REG_A(GPI_EDER);
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        SCR_REG_A(GPI_LIR);
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        case SCR_GPO_DSR(0):
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        case SCR_GPO_DSR(1):
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        case SCR_GPO_DSR(2):
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            s->gpio_level = (s->gpio_level & ~(0xff << ((addr - SCR_GPO_DSR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DSR(0))*8));
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            tc6393xb_gpio_handler_update(s);
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            return;
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        case SCR_GPO_DOECR(0):
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        case SCR_GPO_DOECR(1):
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        case SCR_GPO_DOECR(2):
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            s->gpio_dir = (s->gpio_dir & ~(0xff << ((addr - SCR_GPO_DOECR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DOECR(0))*8));
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            tc6393xb_gpio_handler_update(s);
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            return;
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        SCR_REG_A(GP_IARCR);
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        SCR_REG_A(GP_IARLCR);
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        SCR_REG_A(GPI_BCR);
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        SCR_REG_W(GPA_IARCR);
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        SCR_REG_W(GPA_IARLCR);
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        SCR_REG_W(CCR);
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        SCR_REG_W(PLL2CR);
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        SCR_REG_L(PLL1CR);
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        SCR_REG_B(DIARCR);
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        SCR_REG_B(DBOCR);
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        SCR_REG_B(FER);
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        SCR_REG_W(MCR);
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        SCR_REG_B(CONFIG);
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        SCR_REG_B(DEBUG);
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    }
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    fprintf(stderr, "tc6393xb_scr: unhandled write at %08x: %02x\n",
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                                        (uint32_t) addr, value & 0xff);
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}
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#undef SCR_REG_B
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#undef SCR_REG_W
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#undef SCR_REG_L
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#undef SCR_REG_A
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static void tc6393xb_nand_irq(TC6393xbState *s) {
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    qemu_set_irq(s->sub_irqs[IRQ_TC6393_NAND],
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            (s->nand.imr & 0x80) && (s->nand.imr & s->nand.isr));
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}
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static uint32_t tc6393xb_nand_cfg_readb(TC6393xbState *s, target_phys_addr_t addr) {
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    switch (addr) {
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        case NAND_CFG_COMMAND:
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            return s->nand_enable ? 2 : 0;
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        case NAND_CFG_BASE:
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        case NAND_CFG_BASE + 1:
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        case NAND_CFG_BASE + 2:
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        case NAND_CFG_BASE + 3:
333 a6569fc5 balrog
            return s->nand_phys >> (addr - NAND_CFG_BASE);
334 a6569fc5 balrog
    }
335 a6569fc5 balrog
    fprintf(stderr, "tc6393xb_nand_cfg: unhandled read at %08x\n", (uint32_t) addr);
336 a6569fc5 balrog
    return 0;
337 a6569fc5 balrog
}
338 c227f099 Anthony Liguori
static void tc6393xb_nand_cfg_writeb(TC6393xbState *s, target_phys_addr_t addr, uint32_t value) {
339 a6569fc5 balrog
    switch (addr) {
340 a6569fc5 balrog
        case NAND_CFG_COMMAND:
341 a6569fc5 balrog
            s->nand_enable = (value & 0x2);
342 a6569fc5 balrog
            return;
343 a6569fc5 balrog
        case NAND_CFG_BASE:
344 a6569fc5 balrog
        case NAND_CFG_BASE + 1:
345 a6569fc5 balrog
        case NAND_CFG_BASE + 2:
346 a6569fc5 balrog
        case NAND_CFG_BASE + 3:
347 a6569fc5 balrog
            s->nand_phys &= ~(0xff << ((addr - NAND_CFG_BASE) * 8));
348 a6569fc5 balrog
            s->nand_phys |= (value & 0xff) << ((addr - NAND_CFG_BASE) * 8);
349 a6569fc5 balrog
            return;
350 a6569fc5 balrog
    }
351 a6569fc5 balrog
    fprintf(stderr, "tc6393xb_nand_cfg: unhandled write at %08x: %02x\n",
352 a6569fc5 balrog
                                        (uint32_t) addr, value & 0xff);
353 a6569fc5 balrog
}
354 a6569fc5 balrog
355 c227f099 Anthony Liguori
static uint32_t tc6393xb_nand_readb(TC6393xbState *s, target_phys_addr_t addr) {
356 a6569fc5 balrog
    switch (addr) {
357 a6569fc5 balrog
        case NAND_DATA + 0:
358 a6569fc5 balrog
        case NAND_DATA + 1:
359 a6569fc5 balrog
        case NAND_DATA + 2:
360 a6569fc5 balrog
        case NAND_DATA + 3:
361 a6569fc5 balrog
            return nand_getio(s->flash);
362 a6569fc5 balrog
        case NAND_MODE:
363 a6569fc5 balrog
            return s->nand.mode;
364 a6569fc5 balrog
        case NAND_STATUS:
365 a6569fc5 balrog
            return 0x14;
366 a6569fc5 balrog
        case NAND_ISR:
367 a6569fc5 balrog
            return s->nand.isr;
368 a6569fc5 balrog
        case NAND_IMR:
369 a6569fc5 balrog
            return s->nand.imr;
370 a6569fc5 balrog
    }
371 a6569fc5 balrog
    fprintf(stderr, "tc6393xb_nand: unhandled read at %08x\n", (uint32_t) addr);
372 a6569fc5 balrog
    return 0;
373 a6569fc5 balrog
}
374 c227f099 Anthony Liguori
static void tc6393xb_nand_writeb(TC6393xbState *s, target_phys_addr_t addr, uint32_t value) {
375 a6569fc5 balrog
//    fprintf(stderr, "tc6393xb_nand: write at %08x: %02x\n",
376 a6569fc5 balrog
//                                        (uint32_t) addr, value & 0xff);
377 a6569fc5 balrog
    switch (addr) {
378 a6569fc5 balrog
        case NAND_DATA + 0:
379 a6569fc5 balrog
        case NAND_DATA + 1:
380 a6569fc5 balrog
        case NAND_DATA + 2:
381 a6569fc5 balrog
        case NAND_DATA + 3:
382 a6569fc5 balrog
            nand_setio(s->flash, value);
383 f23c1b2a Dmitry Eremin-Solenikov
            s->nand.isr |= 1;
384 a6569fc5 balrog
            tc6393xb_nand_irq(s);
385 a6569fc5 balrog
            return;
386 a6569fc5 balrog
        case NAND_MODE:
387 a6569fc5 balrog
            s->nand.mode = value;
388 a6569fc5 balrog
            nand_setpins(s->flash,
389 a6569fc5 balrog
                    value & NAND_MODE_CLE,
390 a6569fc5 balrog
                    value & NAND_MODE_ALE,
391 a6569fc5 balrog
                    !(value & NAND_MODE_CE),
392 a6569fc5 balrog
                    value & NAND_MODE_WP,
393 a6569fc5 balrog
                    0); // FIXME: gnd
394 a6569fc5 balrog
            switch (value & NAND_MODE_ECC_MASK) {
395 a6569fc5 balrog
                case NAND_MODE_ECC_RST:
396 a6569fc5 balrog
                    ecc_reset(&s->ecc);
397 a6569fc5 balrog
                    break;
398 a6569fc5 balrog
                case NAND_MODE_ECC_READ:
399 a6569fc5 balrog
                    // FIXME
400 a6569fc5 balrog
                    break;
401 a6569fc5 balrog
                case NAND_MODE_ECC_EN:
402 a6569fc5 balrog
                    ecc_reset(&s->ecc);
403 a6569fc5 balrog
            }
404 a6569fc5 balrog
            return;
405 a6569fc5 balrog
        case NAND_ISR:
406 a6569fc5 balrog
            s->nand.isr = value;
407 a6569fc5 balrog
            tc6393xb_nand_irq(s);
408 a6569fc5 balrog
            return;
409 a6569fc5 balrog
        case NAND_IMR:
410 a6569fc5 balrog
            s->nand.imr = value;
411 a6569fc5 balrog
            tc6393xb_nand_irq(s);
412 a6569fc5 balrog
            return;
413 a6569fc5 balrog
    }
414 a6569fc5 balrog
    fprintf(stderr, "tc6393xb_nand: unhandled write at %08x: %02x\n",
415 a6569fc5 balrog
                                        (uint32_t) addr, value & 0xff);
416 a6569fc5 balrog
}
417 a6569fc5 balrog
418 64b40bc5 balrog
#define BITS 8
419 64b40bc5 balrog
#include "tc6393xb_template.h"
420 64b40bc5 balrog
#define BITS 15
421 64b40bc5 balrog
#include "tc6393xb_template.h"
422 64b40bc5 balrog
#define BITS 16
423 64b40bc5 balrog
#include "tc6393xb_template.h"
424 64b40bc5 balrog
#define BITS 24
425 64b40bc5 balrog
#include "tc6393xb_template.h"
426 64b40bc5 balrog
#define BITS 32
427 64b40bc5 balrog
#include "tc6393xb_template.h"
428 64b40bc5 balrog
429 bc24a225 Paul Brook
static void tc6393xb_draw_graphic(TC6393xbState *s, int full_update)
430 64b40bc5 balrog
{
431 0e1f5a0c aliguori
    switch (ds_get_bits_per_pixel(s->ds)) {
432 64b40bc5 balrog
        case 8:
433 64b40bc5 balrog
            tc6393xb_draw_graphic8(s);
434 64b40bc5 balrog
            break;
435 64b40bc5 balrog
        case 15:
436 64b40bc5 balrog
            tc6393xb_draw_graphic15(s);
437 64b40bc5 balrog
            break;
438 64b40bc5 balrog
        case 16:
439 64b40bc5 balrog
            tc6393xb_draw_graphic16(s);
440 64b40bc5 balrog
            break;
441 64b40bc5 balrog
        case 24:
442 64b40bc5 balrog
            tc6393xb_draw_graphic24(s);
443 64b40bc5 balrog
            break;
444 64b40bc5 balrog
        case 32:
445 64b40bc5 balrog
            tc6393xb_draw_graphic32(s);
446 64b40bc5 balrog
            break;
447 64b40bc5 balrog
        default:
448 0e1f5a0c aliguori
            printf("tc6393xb: unknown depth %d\n", ds_get_bits_per_pixel(s->ds));
449 64b40bc5 balrog
            return;
450 64b40bc5 balrog
    }
451 64b40bc5 balrog
452 64b40bc5 balrog
    dpy_update(s->ds, 0, 0, s->scr_width, s->scr_height);
453 64b40bc5 balrog
}
454 64b40bc5 balrog
455 bc24a225 Paul Brook
static void tc6393xb_draw_blank(TC6393xbState *s, int full_update)
456 64b40bc5 balrog
{
457 64b40bc5 balrog
    int i, w;
458 64b40bc5 balrog
    uint8_t *d;
459 64b40bc5 balrog
460 64b40bc5 balrog
    if (!full_update)
461 64b40bc5 balrog
        return;
462 64b40bc5 balrog
463 0e1f5a0c aliguori
    w = s->scr_width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
464 0e1f5a0c aliguori
    d = ds_get_data(s->ds);
465 64b40bc5 balrog
    for(i = 0; i < s->scr_height; i++) {
466 64b40bc5 balrog
        memset(d, 0, w);
467 0e1f5a0c aliguori
        d += ds_get_linesize(s->ds);
468 64b40bc5 balrog
    }
469 64b40bc5 balrog
470 64b40bc5 balrog
    dpy_update(s->ds, 0, 0, s->scr_width, s->scr_height);
471 64b40bc5 balrog
}
472 64b40bc5 balrog
473 64b40bc5 balrog
static void tc6393xb_update_display(void *opaque)
474 64b40bc5 balrog
{
475 bc24a225 Paul Brook
    TC6393xbState *s = opaque;
476 64b40bc5 balrog
    int full_update;
477 64b40bc5 balrog
478 64b40bc5 balrog
    if (s->scr_width == 0 || s->scr_height == 0)
479 64b40bc5 balrog
        return;
480 64b40bc5 balrog
481 64b40bc5 balrog
    full_update = 0;
482 64b40bc5 balrog
    if (s->blanked != s->blank) {
483 64b40bc5 balrog
        s->blanked = s->blank;
484 64b40bc5 balrog
        full_update = 1;
485 64b40bc5 balrog
    }
486 0e1f5a0c aliguori
    if (s->scr_width != ds_get_width(s->ds) || s->scr_height != ds_get_height(s->ds)) {
487 3023f332 aliguori
        qemu_console_resize(s->ds, s->scr_width, s->scr_height);
488 64b40bc5 balrog
        full_update = 1;
489 64b40bc5 balrog
    }
490 64b40bc5 balrog
    if (s->blanked)
491 64b40bc5 balrog
        tc6393xb_draw_blank(s, full_update);
492 64b40bc5 balrog
    else
493 64b40bc5 balrog
        tc6393xb_draw_graphic(s, full_update);
494 64b40bc5 balrog
}
495 64b40bc5 balrog
496 64b40bc5 balrog
497 c227f099 Anthony Liguori
static uint32_t tc6393xb_readb(void *opaque, target_phys_addr_t addr) {
498 bc24a225 Paul Brook
    TC6393xbState *s = opaque;
499 a6569fc5 balrog
500 a6569fc5 balrog
    switch (addr >> 8) {
501 a6569fc5 balrog
        case 0:
502 a6569fc5 balrog
            return tc6393xb_scr_readb(s, addr & 0xff);
503 a6569fc5 balrog
        case 1:
504 a6569fc5 balrog
            return tc6393xb_nand_cfg_readb(s, addr & 0xff);
505 a6569fc5 balrog
    };
506 a6569fc5 balrog
507 a6569fc5 balrog
    if ((addr &~0xff) == s->nand_phys && s->nand_enable) {
508 a6569fc5 balrog
//        return tc6393xb_nand_readb(s, addr & 0xff);
509 a6569fc5 balrog
        uint8_t d = tc6393xb_nand_readb(s, addr & 0xff);
510 a6569fc5 balrog
//        fprintf(stderr, "tc6393xb_nand: read at %08x: %02hhx\n", (uint32_t) addr, d);
511 a6569fc5 balrog
        return d;
512 a6569fc5 balrog
    }
513 a6569fc5 balrog
514 a6569fc5 balrog
//    fprintf(stderr, "tc6393xb: unhandled read at %08x\n", (uint32_t) addr);
515 a6569fc5 balrog
    return 0;
516 a6569fc5 balrog
}
517 a6569fc5 balrog
518 c227f099 Anthony Liguori
static void tc6393xb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) {
519 bc24a225 Paul Brook
    TC6393xbState *s = opaque;
520 a6569fc5 balrog
521 a6569fc5 balrog
    switch (addr >> 8) {
522 a6569fc5 balrog
        case 0:
523 a6569fc5 balrog
            tc6393xb_scr_writeb(s, addr & 0xff, value);
524 a6569fc5 balrog
            return;
525 a6569fc5 balrog
        case 1:
526 a6569fc5 balrog
            tc6393xb_nand_cfg_writeb(s, addr & 0xff, value);
527 a6569fc5 balrog
            return;
528 a6569fc5 balrog
    };
529 a6569fc5 balrog
530 a6569fc5 balrog
    if ((addr &~0xff) == s->nand_phys && s->nand_enable)
531 a6569fc5 balrog
        tc6393xb_nand_writeb(s, addr & 0xff, value);
532 a6569fc5 balrog
    else
533 a6569fc5 balrog
        fprintf(stderr, "tc6393xb: unhandled write at %08x: %02x\n",
534 a6569fc5 balrog
                                        (uint32_t) addr, value & 0xff);
535 a6569fc5 balrog
}
536 a6569fc5 balrog
537 c227f099 Anthony Liguori
static uint32_t tc6393xb_readw(void *opaque, target_phys_addr_t addr)
538 88d2c950 balrog
{
539 88d2c950 balrog
    return (tc6393xb_readb(opaque, addr) & 0xff) |
540 88d2c950 balrog
        (tc6393xb_readb(opaque, addr + 1) << 8);
541 88d2c950 balrog
}
542 88d2c950 balrog
543 c227f099 Anthony Liguori
static uint32_t tc6393xb_readl(void *opaque, target_phys_addr_t addr)
544 88d2c950 balrog
{
545 88d2c950 balrog
    return (tc6393xb_readb(opaque, addr) & 0xff) |
546 88d2c950 balrog
        ((tc6393xb_readb(opaque, addr + 1) & 0xff) << 8) |
547 88d2c950 balrog
        ((tc6393xb_readb(opaque, addr + 2) & 0xff) << 16) |
548 88d2c950 balrog
        ((tc6393xb_readb(opaque, addr + 3) & 0xff) << 24);
549 88d2c950 balrog
}
550 88d2c950 balrog
551 c227f099 Anthony Liguori
static void tc6393xb_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
552 88d2c950 balrog
{
553 88d2c950 balrog
    tc6393xb_writeb(opaque, addr, value);
554 88d2c950 balrog
    tc6393xb_writeb(opaque, addr + 1, value >> 8);
555 88d2c950 balrog
}
556 88d2c950 balrog
557 c227f099 Anthony Liguori
static void tc6393xb_writel(void *opaque, target_phys_addr_t addr, uint32_t value)
558 88d2c950 balrog
{
559 88d2c950 balrog
    tc6393xb_writeb(opaque, addr, value);
560 88d2c950 balrog
    tc6393xb_writeb(opaque, addr + 1, value >> 8);
561 88d2c950 balrog
    tc6393xb_writeb(opaque, addr + 2, value >> 16);
562 88d2c950 balrog
    tc6393xb_writeb(opaque, addr + 3, value >> 24);
563 88d2c950 balrog
}
564 88d2c950 balrog
565 bc24a225 Paul Brook
TC6393xbState *tc6393xb_init(uint32_t base, qemu_irq irq)
566 88d2c950 balrog
{
567 88d2c950 balrog
    int iomemtype;
568 bc24a225 Paul Brook
    TC6393xbState *s;
569 d60efc6b Blue Swirl
    CPUReadMemoryFunc * const tc6393xb_readfn[] = {
570 88d2c950 balrog
        tc6393xb_readb,
571 88d2c950 balrog
        tc6393xb_readw,
572 88d2c950 balrog
        tc6393xb_readl,
573 88d2c950 balrog
    };
574 d60efc6b Blue Swirl
    CPUWriteMemoryFunc * const tc6393xb_writefn[] = {
575 88d2c950 balrog
        tc6393xb_writeb,
576 88d2c950 balrog
        tc6393xb_writew,
577 88d2c950 balrog
        tc6393xb_writel,
578 88d2c950 balrog
    };
579 88d2c950 balrog
580 bc24a225 Paul Brook
    s = (TC6393xbState *) qemu_mallocz(sizeof(TC6393xbState));
581 a6569fc5 balrog
    s->irq = irq;
582 88d2c950 balrog
    s->gpio_in = qemu_allocate_irqs(tc6393xb_gpio_set, s, TC6393XB_GPIOS);
583 88d2c950 balrog
584 64b40bc5 balrog
    s->l3v = *qemu_allocate_irqs(tc6393xb_l3v, s, 1);
585 64b40bc5 balrog
    s->blanked = 1;
586 64b40bc5 balrog
587 a6569fc5 balrog
    s->sub_irqs = qemu_allocate_irqs(tc6393xb_sub_irq, s, TC6393XB_NR_IRQS);
588 a6569fc5 balrog
589 a6569fc5 balrog
    s->flash = nand_init(NAND_MFR_TOSHIBA, 0x76);
590 a6569fc5 balrog
591 1eed09cb Avi Kivity
    iomemtype = cpu_register_io_memory(tc6393xb_readfn,
592 2507c12a Alexander Graf
                    tc6393xb_writefn, s, DEVICE_NATIVE_ENDIAN);
593 8da3ff18 pbrook
    cpu_register_physical_memory(base, 0x10000, iomemtype);
594 64b40bc5 balrog
595 1724f049 Alex Williamson
    s->vram_addr = qemu_ram_alloc(NULL, "tc6393xb.vram", 0x100000);
596 44654490 pbrook
    s->vram_ptr = qemu_get_ram_ptr(s->vram_addr);
597 3023f332 aliguori
    cpu_register_physical_memory(base + 0x100000, 0x100000, s->vram_addr);
598 3023f332 aliguori
    s->scr_width = 480;
599 3023f332 aliguori
    s->scr_height = 640;
600 3023f332 aliguori
    s->ds = graphic_console_init(tc6393xb_update_display,
601 3023f332 aliguori
            NULL, /* invalidate */
602 3023f332 aliguori
            NULL, /* screen_dump */
603 3023f332 aliguori
            NULL, /* text_update */
604 3023f332 aliguori
            s);
605 88d2c950 balrog
606 88d2c950 balrog
    return s;
607 88d2c950 balrog
}