Revision 6eab3de1
b/hw/apb_pci.c | ||
---|---|---|
312 | 312 |
PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ | |
313 | 313 |
PCI_STATUS_DEVSEL_MEDIUM); |
314 | 314 |
pci_set_byte(dev->config + PCI_REVISION_ID, 0x11); |
315 |
pci_set_byte(dev->config + PCI_HEADER_TYPE, |
|
316 |
pci_get_byte(dev->config + PCI_HEADER_TYPE) | |
|
317 |
PCI_HEADER_TYPE_MULTI_FUNCTION); |
|
318 | 315 |
} |
319 | 316 |
|
320 | 317 |
PCIBus *pci_apb_init(target_phys_addr_t special_base, |
b/hw/pci.c | ||
---|---|---|
584 | 584 |
pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff); |
585 | 585 |
} |
586 | 586 |
|
587 |
static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev) |
|
588 |
{ |
|
589 |
uint8_t slot = PCI_SLOT(dev->devfn); |
|
590 |
uint8_t func; |
|
591 |
|
|
592 |
if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { |
|
593 |
dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; |
|
594 |
} |
|
595 |
|
|
596 |
/* |
|
597 |
* multifuction bit is interpreted in two ways as follows. |
|
598 |
* - all functions must set the bit to 1. |
|
599 |
* Example: Intel X53 |
|
600 |
* - function 0 must set the bit, but the rest function (> 0) |
|
601 |
* is allowed to leave the bit to 0. |
|
602 |
* Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10, |
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603 |
* |
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604 |
* So OS (at least Linux) checks the bit of only function 0, |
|
605 |
* and doesn't see the bit of function > 0. |
|
606 |
* |
|
607 |
* The below check allows both interpretation. |
|
608 |
*/ |
|
609 |
if (PCI_FUNC(dev->devfn)) { |
|
610 |
PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)]; |
|
611 |
if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) { |
|
612 |
/* function 0 should set multifunction bit */ |
|
613 |
error_report("PCI: single function device can't be populated " |
|
614 |
"in function %x.%x", slot, PCI_FUNC(dev->devfn)); |
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615 |
return -1; |
|
616 |
} |
|
617 |
return 0; |
|
618 |
} |
|
619 |
|
|
620 |
if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { |
|
621 |
return 0; |
|
622 |
} |
|
623 |
/* function 0 indicates single function, so function > 0 must be NULL */ |
|
624 |
for (func = 1; func < PCI_FUNC_MAX; ++func) { |
|
625 |
if (bus->devices[PCI_DEVFN(slot, func)]) { |
|
626 |
error_report("PCI: %x.0 indicates single function, " |
|
627 |
"but %x.%x is already populated.", |
|
628 |
slot, slot, func); |
|
629 |
return -1; |
|
630 |
} |
|
631 |
} |
|
632 |
return 0; |
|
633 |
} |
|
634 |
|
|
587 | 635 |
static void pci_config_alloc(PCIDevice *pci_dev) |
588 | 636 |
{ |
589 | 637 |
int config_size = pci_config_size(pci_dev); |
... | ... | |
637 | 685 |
if (is_bridge) { |
638 | 686 |
pci_init_wmask_bridge(pci_dev); |
639 | 687 |
} |
688 |
if (pci_init_multifunction(bus, pci_dev)) { |
|
689 |
pci_config_free(pci_dev); |
|
690 |
return NULL; |
|
691 |
} |
|
640 | 692 |
|
641 | 693 |
if (!config_read) |
642 | 694 |
config_read = pci_default_read_config; |
b/hw/piix4.c | ||
---|---|---|
93 | 93 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
94 | 94 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_0); // 82371AB/EB/MB PIIX4 PCI-to-ISA bridge |
95 | 95 |
pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA); |
96 |
pci_conf[PCI_HEADER_TYPE] = |
|
97 |
PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic |
|
98 | 96 |
|
99 | 97 |
piix4_dev = d; |
100 | 98 |
qemu_register_reset(piix4_reset, d); |
b/hw/piix_pci.c | ||
---|---|---|
335 | 335 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
336 | 336 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1) |
337 | 337 |
pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA); |
338 |
pci_conf[PCI_HEADER_TYPE] = |
|
339 |
PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic |
|
340 | 338 |
|
341 | 339 |
qemu_register_reset(piix3_reset, d); |
342 | 340 |
return 0; |
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