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1 | 6f7e9aec | bellard | /*
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2 | 67e999be | bellard | * QEMU ESP/NCR53C9x emulation
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3 | 6f7e9aec | bellard | *
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4 | 4e9aec74 | pbrook | * Copyright (c) 2005-2006 Fabrice Bellard
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5 | 6f7e9aec | bellard | *
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6 | 6f7e9aec | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 6f7e9aec | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 6f7e9aec | bellard | * in the Software without restriction, including without limitation the rights
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9 | 6f7e9aec | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 6f7e9aec | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 6f7e9aec | bellard | * furnished to do so, subject to the following conditions:
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12 | 6f7e9aec | bellard | *
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13 | 6f7e9aec | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 6f7e9aec | bellard | * all copies or substantial portions of the Software.
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15 | 6f7e9aec | bellard | *
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16 | 6f7e9aec | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 6f7e9aec | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 6f7e9aec | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 6f7e9aec | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 6f7e9aec | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 6f7e9aec | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 6f7e9aec | bellard | * THE SOFTWARE.
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23 | 6f7e9aec | bellard | */
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24 | 6f7e9aec | bellard | #include "vl.h" |
25 | 6f7e9aec | bellard | |
26 | 6f7e9aec | bellard | /* debug ESP card */
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27 | 2f275b8f | bellard | //#define DEBUG_ESP
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28 | 6f7e9aec | bellard | |
29 | 67e999be | bellard | /*
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30 | 67e999be | bellard | * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), also
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31 | 67e999be | bellard | * produced as NCR89C100. See
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32 | 67e999be | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
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33 | 67e999be | bellard | * and
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34 | 67e999be | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
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35 | 67e999be | bellard | */
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36 | 67e999be | bellard | |
37 | 6f7e9aec | bellard | #ifdef DEBUG_ESP
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38 | 6f7e9aec | bellard | #define DPRINTF(fmt, args...) \
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39 | 6f7e9aec | bellard | do { printf("ESP: " fmt , ##args); } while (0) |
40 | 6f7e9aec | bellard | #else
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41 | 6f7e9aec | bellard | #define DPRINTF(fmt, args...)
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42 | 6f7e9aec | bellard | #endif
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43 | 6f7e9aec | bellard | |
44 | 6f7e9aec | bellard | #define ESP_MAXREG 0x3f |
45 | 2e5d83bb | pbrook | #define TI_BUFSZ 32 |
46 | 67e999be | bellard | |
47 | 4e9aec74 | pbrook | typedef struct ESPState ESPState; |
48 | 6f7e9aec | bellard | |
49 | 4e9aec74 | pbrook | struct ESPState {
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50 | 6f7e9aec | bellard | BlockDriverState **bd; |
51 | 2f275b8f | bellard | uint8_t rregs[ESP_MAXREG]; |
52 | 2f275b8f | bellard | uint8_t wregs[ESP_MAXREG]; |
53 | 67e999be | bellard | int32_t ti_size; |
54 | 4f6200f0 | bellard | uint32_t ti_rptr, ti_wptr; |
55 | 4f6200f0 | bellard | uint8_t ti_buf[TI_BUFSZ]; |
56 | 0fc5c15a | pbrook | int sense;
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57 | 4f6200f0 | bellard | int dma;
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58 | 2e5d83bb | pbrook | SCSIDevice *scsi_dev[MAX_DISKS]; |
59 | 2e5d83bb | pbrook | SCSIDevice *current_dev; |
60 | 9f149aa9 | pbrook | uint8_t cmdbuf[TI_BUFSZ]; |
61 | 9f149aa9 | pbrook | int cmdlen;
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62 | 9f149aa9 | pbrook | int do_cmd;
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63 | 4d611c9a | pbrook | |
64 | 6787f5fa | pbrook | /* The amount of data left in the current DMA transfer. */
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65 | 4d611c9a | pbrook | uint32_t dma_left; |
66 | 6787f5fa | pbrook | /* The size of the current DMA transfer. Zero if no transfer is in
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67 | 6787f5fa | pbrook | progress. */
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68 | 6787f5fa | pbrook | uint32_t dma_counter; |
69 | a917d384 | pbrook | uint8_t *async_buf; |
70 | 4d611c9a | pbrook | uint32_t async_len; |
71 | 67e999be | bellard | void *dma_opaque;
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72 | 4e9aec74 | pbrook | }; |
73 | 6f7e9aec | bellard | |
74 | 2f275b8f | bellard | #define STAT_DO 0x00 |
75 | 2f275b8f | bellard | #define STAT_DI 0x01 |
76 | 2f275b8f | bellard | #define STAT_CD 0x02 |
77 | 2f275b8f | bellard | #define STAT_ST 0x03 |
78 | 2f275b8f | bellard | #define STAT_MI 0x06 |
79 | 2f275b8f | bellard | #define STAT_MO 0x07 |
80 | 2f275b8f | bellard | |
81 | 2f275b8f | bellard | #define STAT_TC 0x10 |
82 | 4d611c9a | pbrook | #define STAT_PE 0x20 |
83 | 4d611c9a | pbrook | #define STAT_GE 0x40 |
84 | 2f275b8f | bellard | #define STAT_IN 0x80 |
85 | 2f275b8f | bellard | |
86 | 2f275b8f | bellard | #define INTR_FC 0x08 |
87 | 2f275b8f | bellard | #define INTR_BS 0x10 |
88 | 2f275b8f | bellard | #define INTR_DC 0x20 |
89 | 9e61bde5 | bellard | #define INTR_RST 0x80 |
90 | 2f275b8f | bellard | |
91 | 2f275b8f | bellard | #define SEQ_0 0x0 |
92 | 2f275b8f | bellard | #define SEQ_CD 0x4 |
93 | 2f275b8f | bellard | |
94 | 9f149aa9 | pbrook | static int get_cmd(ESPState *s, uint8_t *buf) |
95 | 2f275b8f | bellard | { |
96 | a917d384 | pbrook | uint32_t dmalen; |
97 | 2f275b8f | bellard | int target;
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98 | 2f275b8f | bellard | |
99 | 6787f5fa | pbrook | dmalen = s->rregs[0] | (s->rregs[1] << 8); |
100 | 4f6200f0 | bellard | target = s->wregs[4] & 7; |
101 | 9f149aa9 | pbrook | DPRINTF("get_cmd: len %d target %d\n", dmalen, target);
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102 | 4f6200f0 | bellard | if (s->dma) {
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103 | 67e999be | bellard | espdma_memory_read(s->dma_opaque, buf, dmalen); |
104 | 4f6200f0 | bellard | } else {
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105 | 4f6200f0 | bellard | buf[0] = 0; |
106 | 4f6200f0 | bellard | memcpy(&buf[1], s->ti_buf, dmalen);
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107 | 4f6200f0 | bellard | dmalen++; |
108 | 4f6200f0 | bellard | } |
109 | 2e5d83bb | pbrook | |
110 | 2f275b8f | bellard | s->ti_size = 0;
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111 | 4f6200f0 | bellard | s->ti_rptr = 0;
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112 | 4f6200f0 | bellard | s->ti_wptr = 0;
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113 | 2f275b8f | bellard | |
114 | a917d384 | pbrook | if (s->current_dev) {
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115 | a917d384 | pbrook | /* Started a new command before the old one finished. Cancel it. */
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116 | a917d384 | pbrook | scsi_cancel_io(s->current_dev, 0);
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117 | a917d384 | pbrook | s->async_len = 0;
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118 | a917d384 | pbrook | } |
119 | a917d384 | pbrook | |
120 | 67e999be | bellard | if (target >= MAX_DISKS || !s->scsi_dev[target]) {
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121 | 2e5d83bb | pbrook | // No such drive
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122 | 2f275b8f | bellard | s->rregs[4] = STAT_IN;
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123 | 2f275b8f | bellard | s->rregs[5] = INTR_DC;
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124 | 2f275b8f | bellard | s->rregs[6] = SEQ_0;
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125 | 67e999be | bellard | espdma_raise_irq(s->dma_opaque); |
126 | 9f149aa9 | pbrook | return 0; |
127 | 2f275b8f | bellard | } |
128 | 2e5d83bb | pbrook | s->current_dev = s->scsi_dev[target]; |
129 | 9f149aa9 | pbrook | return dmalen;
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130 | 9f149aa9 | pbrook | } |
131 | 9f149aa9 | pbrook | |
132 | 9f149aa9 | pbrook | static void do_cmd(ESPState *s, uint8_t *buf) |
133 | 9f149aa9 | pbrook | { |
134 | 9f149aa9 | pbrook | int32_t datalen; |
135 | 9f149aa9 | pbrook | int lun;
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136 | 9f149aa9 | pbrook | |
137 | 9f149aa9 | pbrook | DPRINTF("do_cmd: busid 0x%x\n", buf[0]); |
138 | 9f149aa9 | pbrook | lun = buf[0] & 7; |
139 | 0fc5c15a | pbrook | datalen = scsi_send_command(s->current_dev, 0, &buf[1], lun); |
140 | 67e999be | bellard | s->ti_size = datalen; |
141 | 67e999be | bellard | if (datalen != 0) { |
142 | 2e5d83bb | pbrook | s->rregs[4] = STAT_IN | STAT_TC;
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143 | a917d384 | pbrook | s->dma_left = 0;
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144 | 6787f5fa | pbrook | s->dma_counter = 0;
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145 | 2e5d83bb | pbrook | if (datalen > 0) { |
146 | 2e5d83bb | pbrook | s->rregs[4] |= STAT_DI;
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147 | a917d384 | pbrook | scsi_read_data(s->current_dev, 0);
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148 | 2e5d83bb | pbrook | } else {
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149 | 2e5d83bb | pbrook | s->rregs[4] |= STAT_DO;
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150 | a917d384 | pbrook | scsi_write_data(s->current_dev, 0);
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151 | b9788fc4 | bellard | } |
152 | 2f275b8f | bellard | } |
153 | 2f275b8f | bellard | s->rregs[5] = INTR_BS | INTR_FC;
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154 | 2f275b8f | bellard | s->rregs[6] = SEQ_CD;
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155 | 67e999be | bellard | espdma_raise_irq(s->dma_opaque); |
156 | 2f275b8f | bellard | } |
157 | 2f275b8f | bellard | |
158 | 9f149aa9 | pbrook | static void handle_satn(ESPState *s) |
159 | 9f149aa9 | pbrook | { |
160 | 9f149aa9 | pbrook | uint8_t buf[32];
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161 | 9f149aa9 | pbrook | int len;
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162 | 9f149aa9 | pbrook | |
163 | 9f149aa9 | pbrook | len = get_cmd(s, buf); |
164 | 9f149aa9 | pbrook | if (len)
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165 | 9f149aa9 | pbrook | do_cmd(s, buf); |
166 | 9f149aa9 | pbrook | } |
167 | 9f149aa9 | pbrook | |
168 | 9f149aa9 | pbrook | static void handle_satn_stop(ESPState *s) |
169 | 9f149aa9 | pbrook | { |
170 | 9f149aa9 | pbrook | s->cmdlen = get_cmd(s, s->cmdbuf); |
171 | 9f149aa9 | pbrook | if (s->cmdlen) {
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172 | 9f149aa9 | pbrook | DPRINTF("Set ATN & Stop: cmdlen %d\n", s->cmdlen);
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173 | 9f149aa9 | pbrook | s->do_cmd = 1;
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174 | 9f149aa9 | pbrook | s->rregs[4] = STAT_IN | STAT_TC | STAT_CD;
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175 | 9f149aa9 | pbrook | s->rregs[5] = INTR_BS | INTR_FC;
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176 | 9f149aa9 | pbrook | s->rregs[6] = SEQ_CD;
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177 | 67e999be | bellard | espdma_raise_irq(s->dma_opaque); |
178 | 9f149aa9 | pbrook | } |
179 | 9f149aa9 | pbrook | } |
180 | 9f149aa9 | pbrook | |
181 | 0fc5c15a | pbrook | static void write_response(ESPState *s) |
182 | 2f275b8f | bellard | { |
183 | 0fc5c15a | pbrook | DPRINTF("Transfer status (sense=%d)\n", s->sense);
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184 | 0fc5c15a | pbrook | s->ti_buf[0] = s->sense;
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185 | 0fc5c15a | pbrook | s->ti_buf[1] = 0; |
186 | 4f6200f0 | bellard | if (s->dma) {
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187 | 67e999be | bellard | espdma_memory_write(s->dma_opaque, s->ti_buf, 2);
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188 | 4f6200f0 | bellard | s->rregs[4] = STAT_IN | STAT_TC | STAT_ST;
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189 | 4f6200f0 | bellard | s->rregs[5] = INTR_BS | INTR_FC;
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190 | 4f6200f0 | bellard | s->rregs[6] = SEQ_CD;
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191 | 4f6200f0 | bellard | } else {
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192 | 0fc5c15a | pbrook | s->ti_size = 2;
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193 | 4f6200f0 | bellard | s->ti_rptr = 0;
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194 | 4f6200f0 | bellard | s->ti_wptr = 0;
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195 | 0fc5c15a | pbrook | s->rregs[7] = 2; |
196 | 4f6200f0 | bellard | } |
197 | 67e999be | bellard | espdma_raise_irq(s->dma_opaque); |
198 | 2f275b8f | bellard | } |
199 | 4f6200f0 | bellard | |
200 | a917d384 | pbrook | static void esp_dma_done(ESPState *s) |
201 | a917d384 | pbrook | { |
202 | a917d384 | pbrook | s->rregs[4] |= STAT_IN | STAT_TC;
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203 | a917d384 | pbrook | s->rregs[5] = INTR_BS;
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204 | a917d384 | pbrook | s->rregs[6] = 0; |
205 | a917d384 | pbrook | s->rregs[7] = 0; |
206 | 6787f5fa | pbrook | s->rregs[0] = 0; |
207 | 6787f5fa | pbrook | s->rregs[1] = 0; |
208 | 67e999be | bellard | espdma_raise_irq(s->dma_opaque); |
209 | a917d384 | pbrook | } |
210 | a917d384 | pbrook | |
211 | 4d611c9a | pbrook | static void esp_do_dma(ESPState *s) |
212 | 4d611c9a | pbrook | { |
213 | 67e999be | bellard | uint32_t len; |
214 | 4d611c9a | pbrook | int to_device;
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215 | a917d384 | pbrook | |
216 | 67e999be | bellard | to_device = (s->ti_size < 0);
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217 | a917d384 | pbrook | len = s->dma_left; |
218 | 4d611c9a | pbrook | if (s->do_cmd) {
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219 | 4d611c9a | pbrook | DPRINTF("command len %d + %d\n", s->cmdlen, len);
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220 | 67e999be | bellard | espdma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len); |
221 | 4d611c9a | pbrook | s->ti_size = 0;
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222 | 4d611c9a | pbrook | s->cmdlen = 0;
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223 | 4d611c9a | pbrook | s->do_cmd = 0;
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224 | 4d611c9a | pbrook | do_cmd(s, s->cmdbuf); |
225 | 4d611c9a | pbrook | return;
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226 | a917d384 | pbrook | } |
227 | a917d384 | pbrook | if (s->async_len == 0) { |
228 | a917d384 | pbrook | /* Defer until data is available. */
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229 | a917d384 | pbrook | return;
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230 | a917d384 | pbrook | } |
231 | a917d384 | pbrook | if (len > s->async_len) {
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232 | a917d384 | pbrook | len = s->async_len; |
233 | a917d384 | pbrook | } |
234 | a917d384 | pbrook | if (to_device) {
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235 | 67e999be | bellard | espdma_memory_read(s->dma_opaque, s->async_buf, len); |
236 | 4d611c9a | pbrook | } else {
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237 | 67e999be | bellard | espdma_memory_write(s->dma_opaque, s->async_buf, len); |
238 | a917d384 | pbrook | } |
239 | a917d384 | pbrook | s->dma_left -= len; |
240 | a917d384 | pbrook | s->async_buf += len; |
241 | a917d384 | pbrook | s->async_len -= len; |
242 | 6787f5fa | pbrook | if (to_device)
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243 | 6787f5fa | pbrook | s->ti_size += len; |
244 | 6787f5fa | pbrook | else
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245 | 6787f5fa | pbrook | s->ti_size -= len; |
246 | a917d384 | pbrook | if (s->async_len == 0) { |
247 | 4d611c9a | pbrook | if (to_device) {
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248 | 67e999be | bellard | // ti_size is negative
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249 | a917d384 | pbrook | scsi_write_data(s->current_dev, 0);
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250 | 4d611c9a | pbrook | } else {
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251 | a917d384 | pbrook | scsi_read_data(s->current_dev, 0);
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252 | 6787f5fa | pbrook | /* If there is still data to be read from the device then
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253 | 6787f5fa | pbrook | complete the DMA operation immeriately. Otherwise defer
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254 | 6787f5fa | pbrook | until the scsi layer has completed. */
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255 | 6787f5fa | pbrook | if (s->dma_left == 0 && s->ti_size > 0) { |
256 | 6787f5fa | pbrook | esp_dma_done(s); |
257 | 6787f5fa | pbrook | } |
258 | 4d611c9a | pbrook | } |
259 | 6787f5fa | pbrook | } else {
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260 | 6787f5fa | pbrook | /* Partially filled a scsi buffer. Complete immediately. */
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261 | a917d384 | pbrook | esp_dma_done(s); |
262 | a917d384 | pbrook | } |
263 | 4d611c9a | pbrook | } |
264 | 4d611c9a | pbrook | |
265 | a917d384 | pbrook | static void esp_command_complete(void *opaque, int reason, uint32_t tag, |
266 | a917d384 | pbrook | uint32_t arg) |
267 | 2e5d83bb | pbrook | { |
268 | 2e5d83bb | pbrook | ESPState *s = (ESPState *)opaque; |
269 | 2e5d83bb | pbrook | |
270 | 4d611c9a | pbrook | if (reason == SCSI_REASON_DONE) {
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271 | 4d611c9a | pbrook | DPRINTF("SCSI Command complete\n");
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272 | 4d611c9a | pbrook | if (s->ti_size != 0) |
273 | 4d611c9a | pbrook | DPRINTF("SCSI command completed unexpectedly\n");
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274 | 4d611c9a | pbrook | s->ti_size = 0;
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275 | a917d384 | pbrook | s->dma_left = 0;
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276 | a917d384 | pbrook | s->async_len = 0;
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277 | a917d384 | pbrook | if (arg)
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278 | 4d611c9a | pbrook | DPRINTF("Command failed\n");
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279 | a917d384 | pbrook | s->sense = arg; |
280 | a917d384 | pbrook | s->rregs[4] = STAT_ST;
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281 | a917d384 | pbrook | esp_dma_done(s); |
282 | a917d384 | pbrook | s->current_dev = NULL;
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283 | 4d611c9a | pbrook | } else {
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284 | 4d611c9a | pbrook | DPRINTF("transfer %d/%d\n", s->dma_left, s->ti_size);
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285 | a917d384 | pbrook | s->async_len = arg; |
286 | a917d384 | pbrook | s->async_buf = scsi_get_buf(s->current_dev, 0);
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287 | 6787f5fa | pbrook | if (s->dma_left) {
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288 | a917d384 | pbrook | esp_do_dma(s); |
289 | 6787f5fa | pbrook | } else if (s->dma_counter != 0 && s->ti_size <= 0) { |
290 | 6787f5fa | pbrook | /* If this was the last part of a DMA transfer then the
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291 | 6787f5fa | pbrook | completion interrupt is deferred to here. */
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292 | 6787f5fa | pbrook | esp_dma_done(s); |
293 | 6787f5fa | pbrook | } |
294 | 4d611c9a | pbrook | } |
295 | 2e5d83bb | pbrook | } |
296 | 2e5d83bb | pbrook | |
297 | 2f275b8f | bellard | static void handle_ti(ESPState *s) |
298 | 2f275b8f | bellard | { |
299 | 4d611c9a | pbrook | uint32_t dmalen, minlen; |
300 | 2f275b8f | bellard | |
301 | 6787f5fa | pbrook | dmalen = s->rregs[0] | (s->rregs[1] << 8); |
302 | db59203d | pbrook | if (dmalen==0) { |
303 | db59203d | pbrook | dmalen=0x10000;
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304 | db59203d | pbrook | } |
305 | 6787f5fa | pbrook | s->dma_counter = dmalen; |
306 | db59203d | pbrook | |
307 | 9f149aa9 | pbrook | if (s->do_cmd)
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308 | 9f149aa9 | pbrook | minlen = (dmalen < 32) ? dmalen : 32; |
309 | 67e999be | bellard | else if (s->ti_size < 0) |
310 | 67e999be | bellard | minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size; |
311 | 9f149aa9 | pbrook | else
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312 | 9f149aa9 | pbrook | minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size; |
313 | db59203d | pbrook | DPRINTF("Transfer Information len %d\n", minlen);
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314 | 4f6200f0 | bellard | if (s->dma) {
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315 | 4d611c9a | pbrook | s->dma_left = minlen; |
316 | 4d611c9a | pbrook | s->rregs[4] &= ~STAT_TC;
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317 | 4d611c9a | pbrook | esp_do_dma(s); |
318 | 9f149aa9 | pbrook | } else if (s->do_cmd) { |
319 | 9f149aa9 | pbrook | DPRINTF("command len %d\n", s->cmdlen);
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320 | 9f149aa9 | pbrook | s->ti_size = 0;
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321 | 9f149aa9 | pbrook | s->cmdlen = 0;
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322 | 9f149aa9 | pbrook | s->do_cmd = 0;
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323 | 9f149aa9 | pbrook | do_cmd(s, s->cmdbuf); |
324 | 9f149aa9 | pbrook | return;
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325 | 9f149aa9 | pbrook | } |
326 | 2f275b8f | bellard | } |
327 | 2f275b8f | bellard | |
328 | 67e999be | bellard | void esp_reset(void *opaque) |
329 | 6f7e9aec | bellard | { |
330 | 6f7e9aec | bellard | ESPState *s = opaque; |
331 | 67e999be | bellard | |
332 | 2f275b8f | bellard | memset(s->rregs, 0, ESP_MAXREG);
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333 | 4e9aec74 | pbrook | memset(s->wregs, 0, ESP_MAXREG);
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334 | 2f275b8f | bellard | s->rregs[0x0e] = 0x4; // Indicate fas100a |
335 | 4e9aec74 | pbrook | s->ti_size = 0;
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336 | 4e9aec74 | pbrook | s->ti_rptr = 0;
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337 | 4e9aec74 | pbrook | s->ti_wptr = 0;
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338 | 4e9aec74 | pbrook | s->dma = 0;
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339 | 9f149aa9 | pbrook | s->do_cmd = 0;
|
340 | 6f7e9aec | bellard | } |
341 | 6f7e9aec | bellard | |
342 | 6f7e9aec | bellard | static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr) |
343 | 6f7e9aec | bellard | { |
344 | 6f7e9aec | bellard | ESPState *s = opaque; |
345 | 6f7e9aec | bellard | uint32_t saddr; |
346 | 6f7e9aec | bellard | |
347 | 6f7e9aec | bellard | saddr = (addr & ESP_MAXREG) >> 2;
|
348 | 9e61bde5 | bellard | DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);
|
349 | 6f7e9aec | bellard | switch (saddr) {
|
350 | 4f6200f0 | bellard | case 2: |
351 | 4f6200f0 | bellard | // FIFO
|
352 | 4f6200f0 | bellard | if (s->ti_size > 0) { |
353 | 4f6200f0 | bellard | s->ti_size--; |
354 | 2e5d83bb | pbrook | if ((s->rregs[4] & 6) == 0) { |
355 | 2e5d83bb | pbrook | /* Data in/out. */
|
356 | a917d384 | pbrook | fprintf(stderr, "esp: PIO data read not implemented\n");
|
357 | a917d384 | pbrook | s->rregs[2] = 0; |
358 | 2e5d83bb | pbrook | } else {
|
359 | 2e5d83bb | pbrook | s->rregs[2] = s->ti_buf[s->ti_rptr++];
|
360 | 2e5d83bb | pbrook | } |
361 | 67e999be | bellard | espdma_raise_irq(s->dma_opaque); |
362 | 4f6200f0 | bellard | } |
363 | 4f6200f0 | bellard | if (s->ti_size == 0) { |
364 | 4f6200f0 | bellard | s->ti_rptr = 0;
|
365 | 4f6200f0 | bellard | s->ti_wptr = 0;
|
366 | 4f6200f0 | bellard | } |
367 | 4f6200f0 | bellard | break;
|
368 | 9e61bde5 | bellard | case 5: |
369 | 9e61bde5 | bellard | // interrupt
|
370 | 4d611c9a | pbrook | // Clear interrupt/error status bits
|
371 | 4d611c9a | pbrook | s->rregs[4] &= ~(STAT_IN | STAT_GE | STAT_PE);
|
372 | 67e999be | bellard | espdma_clear_irq(s->dma_opaque); |
373 | 9e61bde5 | bellard | break;
|
374 | 6f7e9aec | bellard | default:
|
375 | 6f7e9aec | bellard | break;
|
376 | 6f7e9aec | bellard | } |
377 | 2f275b8f | bellard | return s->rregs[saddr];
|
378 | 6f7e9aec | bellard | } |
379 | 6f7e9aec | bellard | |
380 | 6f7e9aec | bellard | static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
381 | 6f7e9aec | bellard | { |
382 | 6f7e9aec | bellard | ESPState *s = opaque; |
383 | 6f7e9aec | bellard | uint32_t saddr; |
384 | 6f7e9aec | bellard | |
385 | 6f7e9aec | bellard | saddr = (addr & ESP_MAXREG) >> 2;
|
386 | 2f275b8f | bellard | DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr], val);
|
387 | 6f7e9aec | bellard | switch (saddr) {
|
388 | 4f6200f0 | bellard | case 0: |
389 | 4f6200f0 | bellard | case 1: |
390 | 4d611c9a | pbrook | s->rregs[4] &= ~STAT_TC;
|
391 | 4f6200f0 | bellard | break;
|
392 | 4f6200f0 | bellard | case 2: |
393 | 4f6200f0 | bellard | // FIFO
|
394 | 9f149aa9 | pbrook | if (s->do_cmd) {
|
395 | 9f149aa9 | pbrook | s->cmdbuf[s->cmdlen++] = val & 0xff;
|
396 | 9f149aa9 | pbrook | } else if ((s->rregs[4] & 6) == 0) { |
397 | 2e5d83bb | pbrook | uint8_t buf; |
398 | 2e5d83bb | pbrook | buf = val & 0xff;
|
399 | 2e5d83bb | pbrook | s->ti_size--; |
400 | a917d384 | pbrook | fprintf(stderr, "esp: PIO data write not implemented\n");
|
401 | 2e5d83bb | pbrook | } else {
|
402 | 2e5d83bb | pbrook | s->ti_size++; |
403 | 2e5d83bb | pbrook | s->ti_buf[s->ti_wptr++] = val & 0xff;
|
404 | 2e5d83bb | pbrook | } |
405 | 4f6200f0 | bellard | break;
|
406 | 6f7e9aec | bellard | case 3: |
407 | 4f6200f0 | bellard | s->rregs[saddr] = val; |
408 | 6f7e9aec | bellard | // Command
|
409 | 4f6200f0 | bellard | if (val & 0x80) { |
410 | 4f6200f0 | bellard | s->dma = 1;
|
411 | 6787f5fa | pbrook | /* Reload DMA counter. */
|
412 | 6787f5fa | pbrook | s->rregs[0] = s->wregs[0]; |
413 | 6787f5fa | pbrook | s->rregs[1] = s->wregs[1]; |
414 | 4f6200f0 | bellard | } else {
|
415 | 4f6200f0 | bellard | s->dma = 0;
|
416 | 4f6200f0 | bellard | } |
417 | 6f7e9aec | bellard | switch(val & 0x7f) { |
418 | 6f7e9aec | bellard | case 0: |
419 | 2f275b8f | bellard | DPRINTF("NOP (%2.2x)\n", val);
|
420 | 2f275b8f | bellard | break;
|
421 | 2f275b8f | bellard | case 1: |
422 | 2f275b8f | bellard | DPRINTF("Flush FIFO (%2.2x)\n", val);
|
423 | 9e61bde5 | bellard | //s->ti_size = 0;
|
424 | 2f275b8f | bellard | s->rregs[5] = INTR_FC;
|
425 | 9e61bde5 | bellard | s->rregs[6] = 0; |
426 | 6f7e9aec | bellard | break;
|
427 | 6f7e9aec | bellard | case 2: |
428 | 2f275b8f | bellard | DPRINTF("Chip reset (%2.2x)\n", val);
|
429 | 6f7e9aec | bellard | esp_reset(s); |
430 | 6f7e9aec | bellard | break;
|
431 | 6f7e9aec | bellard | case 3: |
432 | 2f275b8f | bellard | DPRINTF("Bus reset (%2.2x)\n", val);
|
433 | 9e61bde5 | bellard | s->rregs[5] = INTR_RST;
|
434 | 9e61bde5 | bellard | if (!(s->wregs[8] & 0x40)) { |
435 | 67e999be | bellard | espdma_raise_irq(s->dma_opaque); |
436 | 9e61bde5 | bellard | } |
437 | 2f275b8f | bellard | break;
|
438 | 2f275b8f | bellard | case 0x10: |
439 | 2f275b8f | bellard | handle_ti(s); |
440 | 2f275b8f | bellard | break;
|
441 | 2f275b8f | bellard | case 0x11: |
442 | 2f275b8f | bellard | DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val);
|
443 | 0fc5c15a | pbrook | write_response(s); |
444 | 2f275b8f | bellard | break;
|
445 | 2f275b8f | bellard | case 0x12: |
446 | 2f275b8f | bellard | DPRINTF("Message Accepted (%2.2x)\n", val);
|
447 | 0fc5c15a | pbrook | write_response(s); |
448 | 2f275b8f | bellard | s->rregs[5] = INTR_DC;
|
449 | 2f275b8f | bellard | s->rregs[6] = 0; |
450 | 6f7e9aec | bellard | break;
|
451 | 6f7e9aec | bellard | case 0x1a: |
452 | 2f275b8f | bellard | DPRINTF("Set ATN (%2.2x)\n", val);
|
453 | 6f7e9aec | bellard | break;
|
454 | 6f7e9aec | bellard | case 0x42: |
455 | 9f149aa9 | pbrook | DPRINTF("Set ATN (%2.2x)\n", val);
|
456 | 2f275b8f | bellard | handle_satn(s); |
457 | 2f275b8f | bellard | break;
|
458 | 2f275b8f | bellard | case 0x43: |
459 | 2f275b8f | bellard | DPRINTF("Set ATN & stop (%2.2x)\n", val);
|
460 | 9f149aa9 | pbrook | handle_satn_stop(s); |
461 | 2f275b8f | bellard | break;
|
462 | 2f275b8f | bellard | default:
|
463 | 4f6200f0 | bellard | DPRINTF("Unhandled ESP command (%2.2x)\n", val);
|
464 | 6f7e9aec | bellard | break;
|
465 | 6f7e9aec | bellard | } |
466 | 6f7e9aec | bellard | break;
|
467 | 6f7e9aec | bellard | case 4 ... 7: |
468 | 6f7e9aec | bellard | break;
|
469 | 4f6200f0 | bellard | case 8: |
470 | 4f6200f0 | bellard | s->rregs[saddr] = val; |
471 | 4f6200f0 | bellard | break;
|
472 | 4f6200f0 | bellard | case 9 ... 10: |
473 | 4f6200f0 | bellard | break;
|
474 | 9e61bde5 | bellard | case 11: |
475 | 9e61bde5 | bellard | s->rregs[saddr] = val & 0x15;
|
476 | 9e61bde5 | bellard | break;
|
477 | 9e61bde5 | bellard | case 12 ... 15: |
478 | 4f6200f0 | bellard | s->rregs[saddr] = val; |
479 | 4f6200f0 | bellard | break;
|
480 | 6f7e9aec | bellard | default:
|
481 | 6f7e9aec | bellard | break;
|
482 | 6f7e9aec | bellard | } |
483 | 2f275b8f | bellard | s->wregs[saddr] = val; |
484 | 6f7e9aec | bellard | } |
485 | 6f7e9aec | bellard | |
486 | 6f7e9aec | bellard | static CPUReadMemoryFunc *esp_mem_read[3] = { |
487 | 6f7e9aec | bellard | esp_mem_readb, |
488 | 6f7e9aec | bellard | esp_mem_readb, |
489 | 6f7e9aec | bellard | esp_mem_readb, |
490 | 6f7e9aec | bellard | }; |
491 | 6f7e9aec | bellard | |
492 | 6f7e9aec | bellard | static CPUWriteMemoryFunc *esp_mem_write[3] = { |
493 | 6f7e9aec | bellard | esp_mem_writeb, |
494 | 6f7e9aec | bellard | esp_mem_writeb, |
495 | 6f7e9aec | bellard | esp_mem_writeb, |
496 | 6f7e9aec | bellard | }; |
497 | 6f7e9aec | bellard | |
498 | 6f7e9aec | bellard | static void esp_save(QEMUFile *f, void *opaque) |
499 | 6f7e9aec | bellard | { |
500 | 6f7e9aec | bellard | ESPState *s = opaque; |
501 | 2f275b8f | bellard | |
502 | 2f275b8f | bellard | qemu_put_buffer(f, s->rregs, ESP_MAXREG); |
503 | 2f275b8f | bellard | qemu_put_buffer(f, s->wregs, ESP_MAXREG); |
504 | 4f6200f0 | bellard | qemu_put_be32s(f, &s->ti_size); |
505 | 4f6200f0 | bellard | qemu_put_be32s(f, &s->ti_rptr); |
506 | 4f6200f0 | bellard | qemu_put_be32s(f, &s->ti_wptr); |
507 | 4f6200f0 | bellard | qemu_put_buffer(f, s->ti_buf, TI_BUFSZ); |
508 | 4f6200f0 | bellard | qemu_put_be32s(f, &s->dma); |
509 | 6f7e9aec | bellard | } |
510 | 6f7e9aec | bellard | |
511 | 6f7e9aec | bellard | static int esp_load(QEMUFile *f, void *opaque, int version_id) |
512 | 6f7e9aec | bellard | { |
513 | 6f7e9aec | bellard | ESPState *s = opaque; |
514 | 6f7e9aec | bellard | |
515 | 67e999be | bellard | if (version_id != 2) |
516 | 67e999be | bellard | return -EINVAL; // Cannot emulate 1 |
517 | 6f7e9aec | bellard | |
518 | 2f275b8f | bellard | qemu_get_buffer(f, s->rregs, ESP_MAXREG); |
519 | 2f275b8f | bellard | qemu_get_buffer(f, s->wregs, ESP_MAXREG); |
520 | 4f6200f0 | bellard | qemu_get_be32s(f, &s->ti_size); |
521 | 4f6200f0 | bellard | qemu_get_be32s(f, &s->ti_rptr); |
522 | 4f6200f0 | bellard | qemu_get_be32s(f, &s->ti_wptr); |
523 | 4f6200f0 | bellard | qemu_get_buffer(f, s->ti_buf, TI_BUFSZ); |
524 | 4f6200f0 | bellard | qemu_get_be32s(f, &s->dma); |
525 | 2f275b8f | bellard | |
526 | 6f7e9aec | bellard | return 0; |
527 | 6f7e9aec | bellard | } |
528 | 6f7e9aec | bellard | |
529 | 67e999be | bellard | void *esp_init(BlockDriverState **bd, uint32_t espaddr, void *dma_opaque) |
530 | 6f7e9aec | bellard | { |
531 | 6f7e9aec | bellard | ESPState *s; |
532 | 67e999be | bellard | int esp_io_memory;
|
533 | 2e5d83bb | pbrook | int i;
|
534 | 6f7e9aec | bellard | |
535 | 6f7e9aec | bellard | s = qemu_mallocz(sizeof(ESPState));
|
536 | 6f7e9aec | bellard | if (!s)
|
537 | 67e999be | bellard | return NULL; |
538 | 6f7e9aec | bellard | |
539 | 6f7e9aec | bellard | s->bd = bd; |
540 | 67e999be | bellard | s->dma_opaque = dma_opaque; |
541 | 6f7e9aec | bellard | |
542 | 6f7e9aec | bellard | esp_io_memory = cpu_register_io_memory(0, esp_mem_read, esp_mem_write, s);
|
543 | 6f7e9aec | bellard | cpu_register_physical_memory(espaddr, ESP_MAXREG*4, esp_io_memory);
|
544 | 6f7e9aec | bellard | |
545 | 6f7e9aec | bellard | esp_reset(s); |
546 | 6f7e9aec | bellard | |
547 | 67e999be | bellard | register_savevm("esp", espaddr, 2, esp_save, esp_load, s); |
548 | 6f7e9aec | bellard | qemu_register_reset(esp_reset, s); |
549 | 2e5d83bb | pbrook | for (i = 0; i < MAX_DISKS; i++) { |
550 | 2e5d83bb | pbrook | if (bs_table[i]) {
|
551 | a917d384 | pbrook | /* Command queueing is not implemented. */
|
552 | 2e5d83bb | pbrook | s->scsi_dev[i] = |
553 | a917d384 | pbrook | scsi_disk_init(bs_table[i], 0, esp_command_complete, s);
|
554 | 2e5d83bb | pbrook | } |
555 | 2e5d83bb | pbrook | } |
556 | 6f7e9aec | bellard | |
557 | 67e999be | bellard | return s;
|
558 | 67e999be | bellard | } |