root / hw / mips_r4k.c @ 6f15b608
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1 | 6af0bf9c | bellard | #include "vl.h" |
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2 | 6af0bf9c | bellard | |
3 | 6af0bf9c | bellard | #define BIOS_FILENAME "mips_bios.bin" |
4 | 6af0bf9c | bellard | //#define BIOS_FILENAME "system.bin"
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5 | 6af0bf9c | bellard | #define KERNEL_LOAD_ADDR 0x80010000 |
6 | 6af0bf9c | bellard | #define INITRD_LOAD_ADDR 0x80800000 |
7 | 6af0bf9c | bellard | |
8 | 66a93e0f | bellard | #define VIRT_TO_PHYS_ADDEND (-0x80000000LL) |
9 | 66a93e0f | bellard | |
10 | 6af0bf9c | bellard | extern FILE *logfile;
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11 | 6af0bf9c | bellard | |
12 | 697584ab | bellard | static PITState *pit;
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13 | 697584ab | bellard | |
14 | 73133662 | bellard | static void pic_irq_request(void *opaque, int level) |
15 | 6af0bf9c | bellard | { |
16 | c68ea704 | bellard | CPUState *env = first_cpu; |
17 | 73133662 | bellard | if (level) {
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18 | c68ea704 | bellard | env->CP0_Cause |= 0x00000400;
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19 | c68ea704 | bellard | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
20 | 6af0bf9c | bellard | } else {
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21 | c68ea704 | bellard | env->CP0_Cause &= ~0x00000400;
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22 | c68ea704 | bellard | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
23 | 6af0bf9c | bellard | } |
24 | 6af0bf9c | bellard | } |
25 | 6af0bf9c | bellard | |
26 | 6af0bf9c | bellard | void cpu_mips_irqctrl_init (void) |
27 | 6af0bf9c | bellard | { |
28 | 6af0bf9c | bellard | } |
29 | 6af0bf9c | bellard | |
30 | f5d2a381 | bellard | /* XXX: do not use a global */
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31 | 6af0bf9c | bellard | uint32_t cpu_mips_get_random (CPUState *env) |
32 | 6af0bf9c | bellard | { |
33 | f5d2a381 | bellard | static uint32_t seed = 0; |
34 | f5d2a381 | bellard | uint32_t idx; |
35 | f5d2a381 | bellard | seed = seed * 314159 + 1; |
36 | f5d2a381 | bellard | idx = (seed >> 16) % (MIPS_TLB_NB - env->CP0_Wired) + env->CP0_Wired;
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37 | f5d2a381 | bellard | return idx;
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38 | 6af0bf9c | bellard | } |
39 | 6af0bf9c | bellard | |
40 | 899abcf5 | bellard | /* MIPS R4K timer */
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41 | 6af0bf9c | bellard | uint32_t cpu_mips_get_count (CPUState *env) |
42 | 6af0bf9c | bellard | { |
43 | 6af0bf9c | bellard | return env->CP0_Count +
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44 | 6af0bf9c | bellard | (uint32_t)muldiv64(qemu_get_clock(vm_clock), |
45 | 6af0bf9c | bellard | 100 * 1000 * 1000, ticks_per_sec); |
46 | 6af0bf9c | bellard | } |
47 | 6af0bf9c | bellard | |
48 | 6af0bf9c | bellard | static void cpu_mips_update_count (CPUState *env, uint32_t count, |
49 | 6af0bf9c | bellard | uint32_t compare) |
50 | 6af0bf9c | bellard | { |
51 | 6af0bf9c | bellard | uint64_t now, next; |
52 | 6af0bf9c | bellard | uint32_t tmp; |
53 | 6af0bf9c | bellard | |
54 | 6af0bf9c | bellard | tmp = count; |
55 | 6af0bf9c | bellard | if (count == compare)
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56 | 6af0bf9c | bellard | tmp++; |
57 | 6af0bf9c | bellard | now = qemu_get_clock(vm_clock); |
58 | 6af0bf9c | bellard | next = now + muldiv64(compare - tmp, ticks_per_sec, 100 * 1000 * 1000); |
59 | 6af0bf9c | bellard | if (next == now)
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60 | 6af0bf9c | bellard | next++; |
61 | 2d7272a5 | bellard | #if 0
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62 | 6af0bf9c | bellard | if (logfile) {
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63 | 26a76461 | bellard | fprintf(logfile, "%s: 0x%08" PRIx64 " %08x %08x => 0x%08" PRIx64 "\n",
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64 | 6af0bf9c | bellard | __func__, now, count, compare, next - now);
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65 | 6af0bf9c | bellard | }
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66 | 6af0bf9c | bellard | #endif
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67 | 6af0bf9c | bellard | /* Store new count and compare registers */
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68 | 6af0bf9c | bellard | env->CP0_Compare = compare; |
69 | 6af0bf9c | bellard | env->CP0_Count = |
70 | 6af0bf9c | bellard | count - (uint32_t)muldiv64(now, 100 * 1000 * 1000, ticks_per_sec); |
71 | 6af0bf9c | bellard | /* Adjust timer */
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72 | 6af0bf9c | bellard | qemu_mod_timer(env->timer, next); |
73 | 6af0bf9c | bellard | } |
74 | 6af0bf9c | bellard | |
75 | 6af0bf9c | bellard | void cpu_mips_store_count (CPUState *env, uint32_t value)
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76 | 6af0bf9c | bellard | { |
77 | 6af0bf9c | bellard | cpu_mips_update_count(env, value, env->CP0_Compare); |
78 | 6af0bf9c | bellard | } |
79 | 6af0bf9c | bellard | |
80 | 6af0bf9c | bellard | void cpu_mips_store_compare (CPUState *env, uint32_t value)
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81 | 6af0bf9c | bellard | { |
82 | 6af0bf9c | bellard | cpu_mips_update_count(env, cpu_mips_get_count(env), value); |
83 | c68ea704 | bellard | env->CP0_Cause &= ~0x00008000;
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84 | c68ea704 | bellard | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
85 | 6af0bf9c | bellard | } |
86 | 6af0bf9c | bellard | |
87 | 6af0bf9c | bellard | static void mips_timer_cb (void *opaque) |
88 | 6af0bf9c | bellard | { |
89 | 6af0bf9c | bellard | CPUState *env; |
90 | 6af0bf9c | bellard | |
91 | 6af0bf9c | bellard | env = opaque; |
92 | 2d7272a5 | bellard | #if 0
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93 | 6af0bf9c | bellard | if (logfile) {
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94 | 6af0bf9c | bellard | fprintf(logfile, "%s\n", __func__);
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95 | 6af0bf9c | bellard | }
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96 | 6af0bf9c | bellard | #endif
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97 | 6af0bf9c | bellard | cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare); |
98 | c68ea704 | bellard | env->CP0_Cause |= 0x00008000;
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99 | c68ea704 | bellard | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
100 | 6af0bf9c | bellard | } |
101 | 6af0bf9c | bellard | |
102 | 6af0bf9c | bellard | void cpu_mips_clock_init (CPUState *env)
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103 | 6af0bf9c | bellard | { |
104 | 6af0bf9c | bellard | env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env); |
105 | 6af0bf9c | bellard | env->CP0_Compare = 0;
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106 | 6af0bf9c | bellard | cpu_mips_update_count(env, 1, 0); |
107 | 6af0bf9c | bellard | } |
108 | 6af0bf9c | bellard | |
109 | 66a93e0f | bellard | |
110 | 6af0bf9c | bellard | void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device, |
111 | 6af0bf9c | bellard | DisplayState *ds, const char **fd_filename, int snapshot, |
112 | 6af0bf9c | bellard | const char *kernel_filename, const char *kernel_cmdline, |
113 | 6af0bf9c | bellard | const char *initrd_filename) |
114 | 6af0bf9c | bellard | { |
115 | 6af0bf9c | bellard | char buf[1024]; |
116 | 66a93e0f | bellard | int64_t entry = 0;
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117 | 6af0bf9c | bellard | unsigned long bios_offset; |
118 | 6af0bf9c | bellard | int ret;
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119 | c68ea704 | bellard | CPUState *env; |
120 | 66a93e0f | bellard | long kernel_size;
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121 | c68ea704 | bellard | |
122 | c68ea704 | bellard | env = cpu_init(); |
123 | c68ea704 | bellard | register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); |
124 | c68ea704 | bellard | |
125 | 6af0bf9c | bellard | /* allocate RAM */
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126 | 6af0bf9c | bellard | cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
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127 | 66a93e0f | bellard | |
128 | 66a93e0f | bellard | /* Try to load a BIOS image. If this fails, we continue regardless,
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129 | 66a93e0f | bellard | but initialize the hardware ourselves. When a kernel gets
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130 | 66a93e0f | bellard | preloaded we also initialize the hardware, since the BIOS wasn't
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131 | 66a93e0f | bellard | run. */
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132 | 6af0bf9c | bellard | bios_offset = ram_size + vga_ram_size; |
133 | 6af0bf9c | bellard | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME); |
134 | 6af0bf9c | bellard | ret = load_image(buf, phys_ram_base + bios_offset); |
135 | 66a93e0f | bellard | if (ret == BIOS_SIZE) {
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136 | 66a93e0f | bellard | cpu_register_physical_memory((uint32_t)(0x1fc00000),
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137 | 66a93e0f | bellard | BIOS_SIZE, bios_offset | IO_MEM_ROM); |
138 | 66a93e0f | bellard | } else {
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139 | 66a93e0f | bellard | /* not fatal */
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140 | 66a93e0f | bellard | fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
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141 | 66a93e0f | bellard | buf); |
142 | 6af0bf9c | bellard | } |
143 | 66a93e0f | bellard | |
144 | 66a93e0f | bellard | kernel_size = 0;
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145 | 66a93e0f | bellard | if (kernel_filename) {
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146 | 66a93e0f | bellard | kernel_size = load_elf(kernel_filename, VIRT_TO_PHYS_ADDEND, &entry); |
147 | 66a93e0f | bellard | if (kernel_size >= 0) |
148 | 66a93e0f | bellard | env->PC = entry; |
149 | 66a93e0f | bellard | else {
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150 | 66a93e0f | bellard | kernel_size = load_image(kernel_filename, |
151 | 66a93e0f | bellard | phys_ram_base + KERNEL_LOAD_ADDR + VIRT_TO_PHYS_ADDEND); |
152 | 66a93e0f | bellard | if (kernel_size < 0) { |
153 | 66a93e0f | bellard | fprintf(stderr, "qemu: could not load kernel '%s'\n",
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154 | 66a93e0f | bellard | kernel_filename); |
155 | 66a93e0f | bellard | exit(1);
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156 | 66a93e0f | bellard | } |
157 | 66a93e0f | bellard | env->PC = KERNEL_LOAD_ADDR; |
158 | 66a93e0f | bellard | } |
159 | 66a93e0f | bellard | |
160 | 6af0bf9c | bellard | /* load initrd */
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161 | 6af0bf9c | bellard | if (initrd_filename) {
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162 | 66a93e0f | bellard | if (load_image(initrd_filename,
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163 | 66a93e0f | bellard | phys_ram_base + INITRD_LOAD_ADDR + VIRT_TO_PHYS_ADDEND) |
164 | 66a93e0f | bellard | == (target_ulong) -1) {
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165 | 6af0bf9c | bellard | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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166 | 6af0bf9c | bellard | initrd_filename); |
167 | 6af0bf9c | bellard | exit(1);
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168 | 6af0bf9c | bellard | } |
169 | 6af0bf9c | bellard | } |
170 | 66a93e0f | bellard | |
171 | 2d7272a5 | bellard | /* Store command line. */
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172 | 2d7272a5 | bellard | strcpy (phys_ram_base + (16 << 20) - 256, kernel_cmdline); |
173 | 2d7272a5 | bellard | /* FIXME: little endian support */
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174 | 2d7272a5 | bellard | *(int *)(phys_ram_base + (16 << 20) - 260) = tswap32 (0x12345678); |
175 | 2d7272a5 | bellard | *(int *)(phys_ram_base + (16 << 20) - 264) = tswap32 (ram_size); |
176 | 6af0bf9c | bellard | } |
177 | 6af0bf9c | bellard | |
178 | 6af0bf9c | bellard | /* Init internal devices */
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179 | c68ea704 | bellard | cpu_mips_clock_init(env); |
180 | 6af0bf9c | bellard | cpu_mips_irqctrl_init(); |
181 | 6af0bf9c | bellard | |
182 | 0699b548 | bellard | /* Register 64 KB of ISA IO space at 0x14000000 */
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183 | aef445bd | pbrook | isa_mmio_init(0x14000000, 0x00010000); |
184 | 0699b548 | bellard | isa_mem_base = 0x10000000;
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185 | 0699b548 | bellard | |
186 | c68ea704 | bellard | isa_pic = pic_init(pic_irq_request, env); |
187 | 697584ab | bellard | pit = pit_init(0x40, 0); |
188 | e5d13e2f | bellard | serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]); |
189 | 89b6b508 | bellard | isa_vga_init(ds, phys_ram_base + ram_size, ram_size, |
190 | 89b6b508 | bellard | vga_ram_size); |
191 | 9827e95c | bellard | |
192 | a41b2ff2 | pbrook | if (nd_table[0].vlan) { |
193 | a41b2ff2 | pbrook | if (nd_table[0].model == NULL |
194 | a41b2ff2 | pbrook | || strcmp(nd_table[0].model, "ne2k_isa") == 0) { |
195 | a41b2ff2 | pbrook | isa_ne2000_init(0x300, 9, &nd_table[0]); |
196 | a41b2ff2 | pbrook | } else {
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197 | a41b2ff2 | pbrook | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
198 | a41b2ff2 | pbrook | exit (1);
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199 | a41b2ff2 | pbrook | } |
200 | a41b2ff2 | pbrook | } |
201 | 6af0bf9c | bellard | } |
202 | 6af0bf9c | bellard | |
203 | 6af0bf9c | bellard | QEMUMachine mips_machine = { |
204 | 6af0bf9c | bellard | "mips",
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205 | 6af0bf9c | bellard | "mips r4k platform",
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206 | 6af0bf9c | bellard | mips_r4k_init, |
207 | 6af0bf9c | bellard | }; |